clk.c 2.9 KB
Newer Older
1 2 3 4 5 6 7 8 9
/*
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 *
 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 */
#include <linux/io.h>
10
#include <linux/export.h>
11 12 13 14
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/clk.h>
15
#include <linux/clkdev.h>
16 17 18 19 20 21 22 23 24 25
#include <linux/err.h>
#include <linux/list.h>

#include <asm/time.h>
#include <asm/irq.h>
#include <asm/div64.h>

#include <lantiq_soc.h>

#include "clk.h"
26
#include "prom.h"
27

28 29
/* lantiq socs have 3 static clocks */
static struct clk cpu_clk_generic[3];
30

31 32 33 34 35 36
void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io)
{
	cpu_clk_generic[0].rate = cpu;
	cpu_clk_generic[1].rate = fpi;
	cpu_clk_generic[2].rate = io;
}
37

38 39 40 41 42 43 44 45 46 47 48 49
struct clk *clk_get_cpu(void)
{
	return &cpu_clk_generic[0];
}

struct clk *clk_get_fpi(void)
{
	return &cpu_clk_generic[1];
}
EXPORT_SYMBOL_GPL(clk_get_fpi);

struct clk *clk_get_io(void)
50
{
51
	return &cpu_clk_generic[2];
52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73
}

static inline int clk_good(struct clk *clk)
{
	return clk && !IS_ERR(clk);
}

unsigned long clk_get_rate(struct clk *clk)
{
	if (unlikely(!clk_good(clk)))
		return 0;

	if (clk->rate != 0)
		return clk->rate;

	if (clk->get_rate != NULL)
		return clk->get_rate();

	return 0;
}
EXPORT_SYMBOL(clk_get_rate);

74
int clk_set_rate(struct clk *clk, unsigned long rate)
75
{
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
	if (unlikely(!clk_good(clk)))
		return 0;
	if (clk->rates && *clk->rates) {
		unsigned long *r = clk->rates;

		while (*r && (*r != rate))
			r++;
		if (!*r) {
			pr_err("clk %s.%s: trying to set invalid rate %ld\n",
				clk->cl.dev_id, clk->cl.con_id, rate);
			return -1;
		}
	}
	clk->rate = rate;
	return 0;
91
}
92
EXPORT_SYMBOL(clk_set_rate);
93

94 95
int clk_enable(struct clk *clk)
{
96 97 98 99 100 101 102
	if (unlikely(!clk_good(clk)))
		return -1;

	if (clk->enable)
		return clk->enable(clk);

	return -1;
103 104 105 106 107
}
EXPORT_SYMBOL(clk_enable);

void clk_disable(struct clk *clk)
{
108 109 110 111 112
	if (unlikely(!clk_good(clk)))
		return;

	if (clk->disable)
		clk->disable(clk);
113 114 115
}
EXPORT_SYMBOL(clk_disable);

116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138
int clk_activate(struct clk *clk)
{
	if (unlikely(!clk_good(clk)))
		return -1;

	if (clk->activate)
		return clk->activate(clk);

	return -1;
}
EXPORT_SYMBOL(clk_activate);

void clk_deactivate(struct clk *clk)
{
	if (unlikely(!clk_good(clk)))
		return;

	if (clk->deactivate)
		clk->deactivate(clk);
}
EXPORT_SYMBOL(clk_deactivate);

static inline u32 get_counter_resolution(void)
139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157
{
	u32 res;

	__asm__ __volatile__(
		".set   push\n"
		".set   mips32r2\n"
		"rdhwr  %0, $3\n"
		".set pop\n"
		: "=&r" (res)
		: /* no input */
		: "memory");

	return res;
}

void __init plat_time_init(void)
{
	struct clk *clk;

158
	ltq_soc_init();
159

160 161
	clk = clk_get_cpu();
	mips_hpt_frequency = clk_get_rate(clk) / get_counter_resolution();
162
	write_c0_compare(read_c0_count());
163
	pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
164 165
	clk_put(clk);
}