bcm7xxx.c 11.4 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14
/*
 * Broadcom BCM7xxx internal transceivers support.
 *
 * Copyright (C) 2014, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/phy.h>
#include <linux/delay.h>
15
#include "bcm-phy-lib.h"
16 17
#include <linux/bitops.h>
#include <linux/brcmphy.h>
18
#include <linux/mdio.h>
19 20 21 22 23 24 25 26 27 28 29 30

/* Broadcom BCM7xxx internal PHY registers */

/* 40nm only register definitions */
#define MII_BCM7XXX_100TX_AUX_CTL	0x10
#define MII_BCM7XXX_100TX_FALSE_CAR	0x13
#define MII_BCM7XXX_100TX_DISC		0x14
#define MII_BCM7XXX_AUX_MODE		0x1d
#define  MII_BCM7XX_64CLK_MDIO		BIT(12)
#define MII_BCM7XXX_TEST		0x1f
#define  MII_BCM7XXX_SHD_MODE_2		BIT(2)

31 32 33 34 35 36 37 38 39 40
/* 28nm only register definitions */
#define MISC_ADDR(base, channel)	base, channel

#define DSP_TAP10			MISC_ADDR(0x0a, 0)
#define PLL_PLLCTRL_1			MISC_ADDR(0x32, 1)
#define PLL_PLLCTRL_2			MISC_ADDR(0x32, 2)
#define PLL_PLLCTRL_4			MISC_ADDR(0x33, 0)

#define AFE_RXCONFIG_0			MISC_ADDR(0x38, 0)
#define AFE_RXCONFIG_1			MISC_ADDR(0x38, 1)
41
#define AFE_RXCONFIG_2			MISC_ADDR(0x38, 2)
42 43
#define AFE_RX_LP_COUNTER		MISC_ADDR(0x38, 3)
#define AFE_TX_CONFIG			MISC_ADDR(0x39, 0)
44 45
#define AFE_VDCA_ICTRL_0		MISC_ADDR(0x39, 1)
#define AFE_VDAC_OTHERS_0		MISC_ADDR(0x39, 3)
46 47
#define AFE_HPF_TRIM_OTHERS		MISC_ADDR(0x3a, 0)

48 49 50
static void r_rc_cal_reset(struct phy_device *phydev)
{
	/* Reset R_CAL/RC_CAL Engine */
51
	bcm_phy_write_exp(phydev, 0x00b0, 0x0010);
52 53

	/* Disable Reset R_AL/RC_CAL Engine */
54
	bcm_phy_write_exp(phydev, 0x00b0, 0x0000);
55 56
}

57
static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
58 59 60 61
{
	/* Increase VCO range to prevent unlocking problem of PLL at low
	 * temp
	 */
62
	bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
63 64

	/* Change Ki to 011 */
65
	bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
66 67 68 69

	/* Disable loading of TVCO buffer to bandgap, set bandgap trim
	 * to 111
	 */
70
	bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
71 72

	/* Adjust bias current trim by -3 */
73
	bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);
74 75

	/* Switch to CORE_BASE1E */
76
	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);
77

78
	r_rc_cal_reset(phydev);
79

80
	/* write AFE_RXCONFIG_0 */
81
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
82 83

	/* write AFE_RXCONFIG_1 */
84
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
85 86

	/* write AFE_RX_LP_COUNTER */
87
	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
88 89

	/* write AFE_HPF_TRIM_OTHERS */
90
	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
91 92

	/* write AFTE_TX_CONFIG */
93
	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
94

95 96 97
	return 0;
}

98 99 100
static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
{
	/* AFE_RXCONFIG_0 */
101
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);
102 103

	/* AFE_RXCONFIG_1 */
104
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
105 106

	/* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
107
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);
108 109

	/* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
110
	bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
111

112
	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
113
	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
114 115

	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
116
	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
117 118

	/* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
119
	bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);
120 121 122 123

	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
	 * offset for HT=0 code
	 */
124
	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
125 126

	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
127
	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
128 129

	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
130
	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
131 132 133 134 135 136 137

	/* Reset R_CAL/RC_CAL engine */
	r_rc_cal_reset(phydev);

	return 0;
}

138 139 140
static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
{
	/* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */
141
	bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
142

143
	/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
144
	bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
145

146
	/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
147
	bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
148 149 150 151

	/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
	 * offset for HT=0 code
	 */
152
	bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
153 154

	/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
155
	phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
156 157

	/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
158
	bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
159 160 161 162 163 164 165

	/* Reset R_CAL/RC_CAL engine */
	r_rc_cal_reset(phydev);

	return 0;
}

166 167
static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
{
168 169 170 171
	u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
	u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
	int ret = 0;

172
	pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
A
Andrew Lunn 已提交
173
		     phydev_name(phydev), phydev->drv->name, rev, patch);
174

175 176 177 178 179 180 181
	/* Dummy read to a register to workaround an issue upon reset where the
	 * internal inverter may not allow the first MDIO transaction to pass
	 * the MDIO management controller and make us return 0xffff for such
	 * reads.
	 */
	phy_read(phydev, MII_BMSR);

182 183
	switch (rev) {
	case 0xb0:
184
		ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
185
		break;
186 187 188
	case 0xd0:
		ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
		break;
189 190
	case 0xe0:
	case 0xf0:
191 192
	/* Rev G0 introduces a roll over */
	case 0x10:
193 194
		ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
		break;
195 196 197
	default:
		break;
	}
198

199 200 201
	if (ret)
		return ret;

202
	ret = bcm_phy_enable_eee(phydev);
203 204 205
	if (ret)
		return ret;

206
	return bcm_phy_enable_apd(phydev, true);
207 208
}

209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225
static int bcm7xxx_28nm_resume(struct phy_device *phydev)
{
	int ret;

	/* Re-apply workarounds coming out suspend/resume */
	ret = bcm7xxx_28nm_config_init(phydev);
	if (ret)
		return ret;

	/* 28nm Gigabit PHYs come out of reset without any half-duplex
	 * or "hub" compliant advertised mode, fix that. This does not
	 * cause any problems with the PHY library since genphy_config_aneg()
	 * gracefully handles auto-negotiated and forced modes.
	 */
	return genphy_config_aneg(phydev);
}

226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268
static int phy_set_clr_bits(struct phy_device *dev, int location,
					int set_mask, int clr_mask)
{
	int v, ret;

	v = phy_read(dev, location);
	if (v < 0)
		return v;

	v &= ~clr_mask;
	v |= set_mask;

	ret = phy_write(dev, location, v);
	if (ret < 0)
		return ret;

	return v;
}

static int bcm7xxx_config_init(struct phy_device *phydev)
{
	int ret;

	/* Enable 64 clock MDIO */
	phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO);
	phy_read(phydev, MII_BCM7XXX_AUX_MODE);

	/* set shadow mode 2 */
	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
			MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
	if (ret < 0)
		return ret;

	/* set iddq_clkbias */
	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
	udelay(10);

	/* reset iddq_clkbias */
	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);

	phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);

	/* reset shadow mode 2 */
269
	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, 0, MII_BCM7XXX_SHD_MODE_2);
270 271 272 273 274 275 276
	if (ret < 0)
		return ret;

	return 0;
}

/* Workaround for putting the PHY in IDDQ mode, required
277
 * for all BCM7XXX 40nm and 65nm PHYs
278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310
 */
static int bcm7xxx_suspend(struct phy_device *phydev)
{
	int ret;
	const struct bcm7xxx_regs {
		int reg;
		u16 value;
	} bcm7xxx_suspend_cfg[] = {
		{ MII_BCM7XXX_TEST, 0x008b },
		{ MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
		{ MII_BCM7XXX_100TX_DISC, 0x7000 },
		{ MII_BCM7XXX_TEST, 0x000f },
		{ MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
		{ MII_BCM7XXX_TEST, 0x000b },
	};
	unsigned int i;

	for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
		ret = phy_write(phydev,
				bcm7xxx_suspend_cfg[i].reg,
				bcm7xxx_suspend_cfg[i].value);
		if (ret)
			return ret;
	}

	return 0;
}

static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
{
	return 0;
}

311 312 313 314 315 316 317 318
#define BCM7XXX_28NM_GPHY(_oui, _name)					\
{									\
	.phy_id		= (_oui),					\
	.phy_id_mask	= 0xfffffff0,					\
	.name		= _name,					\
	.features	= PHY_GBIT_FEATURES |				\
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,	\
	.flags		= PHY_IS_INTERNAL,				\
319
	.config_init	= bcm7xxx_28nm_config_init,			\
320 321 322 323 324
	.config_aneg	= genphy_config_aneg,				\
	.read_status	= genphy_read_status,				\
	.resume		= bcm7xxx_28nm_resume,				\
}

325
static struct phy_driver bcm7xxx_driver[] = {
326 327
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
328 329
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
330
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
331
	BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
332
{
333 334 335
	.phy_id         = PHY_ID_BCM7425,
	.phy_id_mask    = 0xfffffff0,
	.name           = "Broadcom BCM7425",
336
	.features       = PHY_BASIC_FEATURES |
337
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
338
	.flags          = PHY_IS_INTERNAL,
339 340 341 342 343 344 345 346 347
	.config_init    = bcm7xxx_config_init,
	.config_aneg    = genphy_config_aneg,
	.read_status    = genphy_read_status,
	.suspend        = bcm7xxx_suspend,
	.resume         = bcm7xxx_config_init,
}, {
	.phy_id         = PHY_ID_BCM7429,
	.phy_id_mask    = 0xfffffff0,
	.name           = "Broadcom BCM7429",
348
	.features       = PHY_BASIC_FEATURES |
349 350 351 352 353 354 355
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags          = PHY_IS_INTERNAL,
	.config_init    = bcm7xxx_config_init,
	.config_aneg    = genphy_config_aneg,
	.read_status    = genphy_read_status,
	.suspend        = bcm7xxx_suspend,
	.resume         = bcm7xxx_config_init,
356 357 358 359
}, {
	.phy_id         = PHY_ID_BCM7435,
	.phy_id_mask    = 0xfffffff0,
	.name           = "Broadcom BCM7435",
360
	.features       = PHY_BASIC_FEATURES |
361 362 363 364 365 366 367
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags          = PHY_IS_INTERNAL,
	.config_init    = bcm7xxx_config_init,
	.config_aneg    = genphy_config_aneg,
	.read_status    = genphy_read_status,
	.suspend        = bcm7xxx_suspend,
	.resume         = bcm7xxx_config_init,
368
}, {
369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394
	.phy_id		= PHY_BCM_OUI_4,
	.phy_id_mask	= 0xffff0000,
	.name		= "Broadcom BCM7XXX 40nm",
	.features	= PHY_GBIT_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags		= PHY_IS_INTERNAL,
	.config_init	= bcm7xxx_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.suspend	= bcm7xxx_suspend,
	.resume		= bcm7xxx_config_init,
}, {
	.phy_id		= PHY_BCM_OUI_5,
	.phy_id_mask	= 0xffffff00,
	.name		= "Broadcom BCM7XXX 65nm",
	.features	= PHY_BASIC_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags		= PHY_IS_INTERNAL,
	.config_init	= bcm7xxx_dummy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.suspend	= bcm7xxx_suspend,
	.resume		= bcm7xxx_config_init,
} };

static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
395 396
	{ PHY_ID_BCM7250, 0xfffffff0, },
	{ PHY_ID_BCM7364, 0xfffffff0, },
397
	{ PHY_ID_BCM7366, 0xfffffff0, },
398 399
	{ PHY_ID_BCM7425, 0xfffffff0, },
	{ PHY_ID_BCM7429, 0xfffffff0, },
400
	{ PHY_ID_BCM7439, 0xfffffff0, },
401
	{ PHY_ID_BCM7435, 0xfffffff0, },
402 403 404 405 406 407
	{ PHY_ID_BCM7445, 0xfffffff0, },
	{ PHY_BCM_OUI_4, 0xffff0000 },
	{ PHY_BCM_OUI_5, 0xffffff00 },
	{ }
};

408
module_phy_driver(bcm7xxx_driver);
409 410 411 412 413 414

MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);

MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Broadcom Corporation");