kirkwood.dtsi 6.4 KB
Newer Older
1
/include/ "skeleton.dtsi"
2
#include <dt-bindings/input/input.h>
3

4 5
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

6
/ {
7
	compatible = "marvell,kirkwood";
8 9
	interrupt-parent = <&intc>;

10 11 12 13 14 15 16
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "marvell,feroceon";
17
			reg = <0>;
18 19 20 21 22
			clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
			clock-names = "cpu_clk", "ddrclk", "powersave";
		};
	};

23 24 25 26
	aliases {
	       gpio0 = &gpio0;
	       gpio1 = &gpio1;
	};
27

28 29
	mbus {
		compatible = "marvell,kirkwood-mbus", "simple-bus";
30 31
		#address-cells = <2>;
		#size-cells = <1>;
32 33 34 35 36
		/* If a board file needs to change this ranges it must replace it completely */
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000	/* internal-regs */
			  MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000	/* nand flash */
			  MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000	/* crypto sram */
			  >;
37
		controller = <&mbusc>;
38 39
		pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
		pcie-io-aperture  = <0xf2000000 0x100000>;   /*   1 MiB    I/O space */
40 41 42 43 44 45 46 47 48 49

		crypto@0301 {
			compatible = "marvell,orion-crypto";
			reg = <MBUS_ID(0xf0, 0x01) 0x30000 0x10000>,
			      <MBUS_ID(0x03, 0x01) 0 0x800>;
			reg-names = "regs", "sram";
			interrupts = <22>;
			clocks = <&gate_clk 17>;
			status = "okay";
		};
50 51 52 53 54 55 56 57 58 59 60 61 62 63

		nand: nand@012f {
			#address-cells = <1>;
			#size-cells = <1>;
			cle = <0>;
			ale = <1>;
			bank-width = <1>;
			compatible = "marvell,orion-nand";
			reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
			chip-delay = <25>;
			/* set partition map and/or chip-delay in board dts */
			clocks = <&gate_clk 7>;
			status = "disabled";
		};
64 65
	};

66 67
	ocp@f1000000 {
		compatible = "simple-bus";
68
		ranges = <0x00000000 0xf1000000 0x0100000>;
69 70 71
		#address-cells = <1>;
		#size-cells = <1>;

72 73 74 75 76
		mbusc: mbus-controller@20000 {
			compatible = "marvell,mbus-controller";
			reg = <0x20000 0x80>, <0x1500 0x20>;
		};

77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
		timer: timer@20300 {
			compatible = "marvell,orion-timer";
			reg = <0x20300 0x20>;
			interrupt-parent = <&bridge_intc>;
			interrupts = <1>, <2>;
			clocks = <&core_clk 0>;
		};

		intc: main-interrupt-ctrl@20200 {
			compatible = "marvell,orion-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x20200 0x10>, <0x20210 0x10>;
		};

		bridge_intc: bridge-interrupt-ctrl@20110 {
			compatible = "marvell,orion-bridge-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x20110 0x8>;
			interrupts = <1>;
			marvell,#interrupts = <6>;
		};

101 102 103 104 105 106
		core_clk: core-clocks@10030 {
			compatible = "marvell,kirkwood-core-clock";
			reg = <0x10030 0x4>;
	        	#clock-cells = <1>;
		};

107 108 109 110 111
		gpio0: gpio@10100 {
			compatible = "marvell,orion-gpio";
			#gpio-cells = <2>;
			gpio-controller;
			reg = <0x10100 0x40>;
112 113
			ngpios = <32>;
			interrupt-controller;
114
			#interrupt-cells = <2>;
115
			interrupts = <35>, <36>, <37>, <38>;
116
			clocks = <&gate_clk 7>;
117 118 119 120 121 122 123
		};

		gpio1: gpio@10140 {
			compatible = "marvell,orion-gpio";
			#gpio-cells = <2>;
			gpio-controller;
			reg = <0x10140 0x40>;
124 125
			ngpios = <18>;
			interrupt-controller;
126
			#interrupt-cells = <2>;
127
			interrupts = <39>, <40>, <41>;
128
			clocks = <&gate_clk 7>;
129 130
		};

131 132 133 134 135
		serial@12000 {
			compatible = "ns16550a";
			reg = <0x12000 0x100>;
			reg-shift = <2>;
			interrupts = <33>;
136
			clocks = <&gate_clk 7>;
137 138 139 140 141 142 143 144
			status = "disabled";
		};

		serial@12100 {
			compatible = "ns16550a";
			reg = <0x12100 0x100>;
			reg-shift = <2>;
			interrupts = <34>;
145
			clocks = <&gate_clk 7>;
146 147
			status = "disabled";
		};
148

149 150 151 152 153 154 155
		spi@10600 {
			compatible = "marvell,orion-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			interrupts = <23>;
			reg = <0x10600 0x28>;
156
			clocks = <&gate_clk 7>;
157 158 159
			status = "disabled";
		};

160 161 162 163 164 165 166
		gate_clk: clock-gating-control@2011c {
			compatible = "marvell,kirkwood-gating-clock";
			reg = <0x2011c 0x4>;
			clocks = <&core_clk 0>;
			#clock-cells = <1>;
		};

167
		wdt: watchdog-timer@20300 {
168 169
			compatible = "marvell,orion-wdt";
			reg = <0x20300 0x28>;
170 171
			interrupt-parent = <&bridge_intc>;
			interrupts = <3>;
172
			clocks = <&gate_clk 7>;
173 174 175
			status = "okay";
		};

176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198
		xor@60800 {
			compatible = "marvell,orion-xor";
			reg = <0x60800 0x100
			       0x60A00 0x100>;
			status = "okay";
			clocks = <&gate_clk 8>;

			xor00 {
			      interrupts = <5>;
			      dmacap,memcpy;
			      dmacap,xor;
			};
			xor01 {
			      interrupts = <6>;
			      dmacap,memcpy;
			      dmacap,xor;
			      dmacap,memset;
			};
		};

		xor@60900 {
			compatible = "marvell,orion-xor";
			reg = <0x60900 0x100
199
			       0x60B00 0x100>;
200
			status = "okay";
201 202 203 204 205 206 207 208 209 210 211 212 213
			clocks = <&gate_clk 16>;

			xor00 {
			      interrupts = <7>;
			      dmacap,memcpy;
			      dmacap,xor;
			};
			xor01 {
			      interrupts = <8>;
			      dmacap,memcpy;
			      dmacap,xor;
			      dmacap,memset;
			};
214 215
		};

216 217 218 219
		ehci@50000 {
			compatible = "marvell,orion-ehci";
			reg = <0x50000 0x1000>;
			interrupts = <19>;
220
			clocks = <&gate_clk 3>;
221 222 223
			status = "okay";
		};

224 225 226 227 228 229 230
		i2c@11000 {
			compatible = "marvell,mv64xxx-i2c";
			reg = <0x11000 0x20>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <29>;
			clock-frequency = <100000>;
231
			clocks = <&gate_clk 7>;
232 233
			status = "disabled";
		};
234

235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285
		mdio: mdio-bus@72004 {
			compatible = "marvell,orion-mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x72004 0x84>;
			interrupts = <46>;
			clocks = <&gate_clk 0>;
			status = "disabled";

			/* add phy nodes in board file */
		};

		eth0: ethernet-controller@72000 {
			compatible = "marvell,kirkwood-eth";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x72000 0x4000>;
			clocks = <&gate_clk 0>;
			marvell,tx-checksum-limit = <1600>;
			status = "disabled";

			ethernet0-port@0 {
				device_type = "network";
				compatible = "marvell,kirkwood-eth-port";
				reg = <0>;
				interrupts = <11>;
				/* overwrite MAC address in bootloader */
				local-mac-address = [00 00 00 00 00 00];
				/* set phy-handle property in board file */
			};
		};

		eth1: ethernet-controller@76000 {
			compatible = "marvell,kirkwood-eth";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x76000 0x4000>;
			clocks = <&gate_clk 19>;
			marvell,tx-checksum-limit = <1600>;
			status = "disabled";

			ethernet1-port@0 {
				device_type = "network";
				compatible = "marvell,kirkwood-eth-port";
				reg = <0>;
				interrupts = <15>;
				/* overwrite MAC address in bootloader */
				local-mac-address = [00 00 00 00 00 00];
				/* set phy-handle property in board file */
			};
		};
286 287
	};
};