traps.c 45.3 KB
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/*
 *  Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
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 *  Copyright 2007-2010 Freescale Semiconductor, Inc.
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 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 *  Modified by Cort Dougan (cort@cs.nmt.edu)
 *  and Paul Mackerras (paulus@samba.org)
 */

/*
 * This file handles the architecture-dependent parts of hardware exceptions
 */

#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
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#include <linux/ptrace.h>
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#include <linux/user.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/module.h>
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#include <linux/prctl.h>
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#include <linux/delay.h>
#include <linux/kprobes.h>
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#include <linux/kexec.h>
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#include <linux/backlight.h>
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#include <linux/bug.h>
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#include <linux/kdebug.h>
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#include <linux/debugfs.h>
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#include <linux/ratelimit.h>
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#include <asm/emulated_ops.h>
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#include <asm/pgtable.h>
#include <asm/uaccess.h>
#include <asm/io.h>
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#include <asm/machdep.h>
#include <asm/rtas.h>
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#include <asm/pmc.h>
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#ifdef CONFIG_PPC32
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#include <asm/reg.h>
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#endif
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#ifdef CONFIG_PMAC_BACKLIGHT
#include <asm/backlight.h>
#endif
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#ifdef CONFIG_PPC64
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#include <asm/firmware.h>
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#include <asm/processor.h>
#endif
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#include <asm/kexec.h>
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#include <asm/ppc-opcode.h>
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#include <asm/rio.h>
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#include <asm/fadump.h>
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#include <asm/switch_to.h>
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#include <asm/tm.h>
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#include <asm/debug.h>
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#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
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int (*__debugger)(struct pt_regs *regs) __read_mostly;
int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
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int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
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int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
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EXPORT_SYMBOL(__debugger);
EXPORT_SYMBOL(__debugger_ipi);
EXPORT_SYMBOL(__debugger_bpt);
EXPORT_SYMBOL(__debugger_sstep);
EXPORT_SYMBOL(__debugger_iabr_match);
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EXPORT_SYMBOL(__debugger_break_match);
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EXPORT_SYMBOL(__debugger_fault_handler);
#endif

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/* Transactional Memory trap debug */
#ifdef TM_DEBUG_SW
#define TM_DEBUG(x...) printk(KERN_INFO x)
#else
#define TM_DEBUG(x...) do { } while(0)
#endif

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/*
 * Trap & Exception support
 */

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#ifdef CONFIG_PMAC_BACKLIGHT
static void pmac_backlight_unblank(void)
{
	mutex_lock(&pmac_backlight_mutex);
	if (pmac_backlight) {
		struct backlight_properties *props;

		props = &pmac_backlight->props;
		props->brightness = props->max_brightness;
		props->power = FB_BLANK_UNBLANK;
		backlight_update_status(pmac_backlight);
	}
	mutex_unlock(&pmac_backlight_mutex);
}
#else
static inline void pmac_backlight_unblank(void) { }
#endif

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static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
static int die_owner = -1;
static unsigned int die_nest_count;
static int die_counter;

static unsigned __kprobes long oops_begin(struct pt_regs *regs)
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{
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	int cpu;
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	unsigned long flags;
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	if (debugger(regs))
		return 1;

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	oops_enter();

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	/* racy, but better than risking deadlock. */
	raw_local_irq_save(flags);
	cpu = smp_processor_id();
	if (!arch_spin_trylock(&die_lock)) {
		if (cpu == die_owner)
			/* nested oops. should stop eventually */;
		else
			arch_spin_lock(&die_lock);
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	}
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	die_nest_count++;
	die_owner = cpu;
	console_verbose();
	bust_spinlocks(1);
	if (machine_is(powermac))
		pmac_backlight_unblank();
	return flags;
}
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static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
			       int signr)
{
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	bust_spinlocks(0);
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	die_owner = -1;
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	add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
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	die_nest_count--;
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	oops_exit();
	printk("\n");
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	if (!die_nest_count)
		/* Nest count reaches zero, release the lock. */
		arch_spin_unlock(&die_lock);
	raw_local_irq_restore(flags);
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	crash_fadump(regs, "die oops");

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	/*
	 * A system reset (0x100) is a request to dump, so we always send
	 * it through the crashdump code.
	 */
	if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
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		crash_kexec(regs);
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		/*
		 * We aren't the primary crash CPU. We need to send it
		 * to a holding pattern to avoid it ending up in the panic
		 * code.
		 */
		crash_kexec_secondary(regs);
	}
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	if (!signr)
		return;

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	/*
	 * While our oops output is serialised by a spinlock, output
	 * from panic() called below can race and corrupt it. If we
	 * know we are going to panic, delay for 1 second so we have a
	 * chance to get clean backtraces from all CPUs that are oopsing.
	 */
	if (in_interrupt() || panic_on_oops || !current->pid ||
	    is_global_init(current)) {
		mdelay(MSEC_PER_SEC);
	}

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	if (in_interrupt())
		panic("Fatal exception in interrupt");
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	if (panic_on_oops)
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		panic("Fatal exception");
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	do_exit(signr);
}
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static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
{
	printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
#ifdef CONFIG_PREEMPT
	printk("PREEMPT ");
#endif
#ifdef CONFIG_SMP
	printk("SMP NR_CPUS=%d ", NR_CPUS);
#endif
#ifdef CONFIG_DEBUG_PAGEALLOC
	printk("DEBUG_PAGEALLOC ");
#endif
#ifdef CONFIG_NUMA
	printk("NUMA ");
#endif
	printk("%s\n", ppc_md.name ? ppc_md.name : "");

	if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
		return 1;

	print_modules();
	show_regs(regs);
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	return 0;
}

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void die(const char *str, struct pt_regs *regs, long err)
{
	unsigned long flags = oops_begin(regs);

	if (__die(str, regs, err))
		err = 0;
	oops_end(flags, regs, err);
}

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void user_single_step_siginfo(struct task_struct *tsk,
				struct pt_regs *regs, siginfo_t *info)
{
	memset(info, 0, sizeof(*info));
	info->si_signo = SIGTRAP;
	info->si_code = TRAP_TRACE;
	info->si_addr = (void __user *)regs->nip;
}

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void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
{
	siginfo_t info;
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	const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
			"at %08lx nip %08lx lr %08lx code %x\n";
	const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
			"at %016lx nip %016lx lr %016lx code %x\n";
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	if (!user_mode(regs)) {
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		die("Exception in kernel mode", regs, signr);
		return;
	}

	if (show_unhandled_signals && unhandled_signal(current, signr)) {
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		printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
				   current->comm, current->pid, signr,
				   addr, regs->nip, regs->link, code);
	}
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	if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
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		local_irq_enable();

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	current->thread.trap_nr = code;
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	memset(&info, 0, sizeof(info));
	info.si_signo = signr;
	info.si_code = code;
	info.si_addr = (void __user *) addr;
	force_sig_info(signr, &info, current);
}

#ifdef CONFIG_PPC64
void system_reset_exception(struct pt_regs *regs)
{
	/* See if any machine dependent calls */
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	if (ppc_md.system_reset_exception) {
		if (ppc_md.system_reset_exception(regs))
			return;
	}
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	die("System Reset", regs, SIGABRT);
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	/* Must die if the interrupt is not recoverable */
	if (!(regs->msr & MSR_RI))
		panic("Unrecoverable System Reset");

	/* What should we do here? We could issue a shutdown or hard reset. */
}
#endif

/*
 * I/O accesses can cause machine checks on powermacs.
 * Check if the NIP corresponds to the address of a sync
 * instruction for which there is an entry in the exception
 * table.
 * Note that the 601 only takes a machine check on TEA
 * (transfer error ack) signal assertion, and does not
 * set any of the top 16 bits of SRR1.
 *  -- paulus.
 */
static inline int check_io_access(struct pt_regs *regs)
{
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#ifdef CONFIG_PPC32
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	unsigned long msr = regs->msr;
	const struct exception_table_entry *entry;
	unsigned int *nip = (unsigned int *)regs->nip;

	if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
	    && (entry = search_exception_tables(regs->nip)) != NULL) {
		/*
		 * Check that it's a sync instruction, or somewhere
		 * in the twi; isync; nop sequence that inb/inw/inl uses.
		 * As the address is in the exception table
		 * we should be able to read the instr there.
		 * For the debug message, we look at the preceding
		 * load or store.
		 */
		if (*nip == 0x60000000)		/* nop */
			nip -= 2;
		else if (*nip == 0x4c00012c)	/* isync */
			--nip;
		if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
			/* sync or twi */
			unsigned int rb;

			--nip;
			rb = (*nip >> 11) & 0x1f;
			printk(KERN_DEBUG "%s bad port %lx at %p\n",
			       (*nip & 0x100)? "OUT to": "IN from",
			       regs->gpr[rb] - _IO_BASE, nip);
			regs->msr |= MSR_RI;
			regs->nip = entry->fixup;
			return 1;
		}
	}
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#endif /* CONFIG_PPC32 */
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	return 0;
}

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#ifdef CONFIG_PPC_ADV_DEBUG_REGS
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/* On 4xx, the reason for the machine check or program exception
   is in the ESR. */
#define get_reason(regs)	((regs)->dsisr)
#ifndef CONFIG_FSL_BOOKE
#define get_mc_reason(regs)	((regs)->dsisr)
#else
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#define get_mc_reason(regs)	(mfspr(SPRN_MCSR))
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#endif
#define REASON_FP		ESR_FP
#define REASON_ILLEGAL		(ESR_PIL | ESR_PUO)
#define REASON_PRIVILEGED	ESR_PPR
#define REASON_TRAP		ESR_PTR

/* single-step stuff */
#define single_stepping(regs)	(current->thread.dbcr0 & DBCR0_IC)
#define clear_single_step(regs)	(current->thread.dbcr0 &= ~DBCR0_IC)

#else
/* On non-4xx, the reason for the machine check or program
   exception is in the MSR. */
#define get_reason(regs)	((regs)->msr)
#define get_mc_reason(regs)	((regs)->msr)
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#define REASON_TM		0x200000
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#define REASON_FP		0x100000
#define REASON_ILLEGAL		0x80000
#define REASON_PRIVILEGED	0x40000
#define REASON_TRAP		0x20000

#define single_stepping(regs)	((regs)->msr & MSR_SE)
#define clear_single_step(regs)	((regs)->msr &= ~MSR_SE)
#endif

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#if defined(CONFIG_4xx)
int machine_check_4xx(struct pt_regs *regs)
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{
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	unsigned long reason = get_mc_reason(regs);
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	if (reason & ESR_IMCP) {
		printk("Instruction");
		mtspr(SPRN_ESR, reason & ~ESR_IMCP);
	} else
		printk("Data");
	printk(" machine check in kernel mode.\n");
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	return 0;
}

int machine_check_440A(struct pt_regs *regs)
{
	unsigned long reason = get_mc_reason(regs);

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	printk("Machine check in kernel mode.\n");
	if (reason & ESR_IMCP){
		printk("Instruction Synchronous Machine Check exception\n");
		mtspr(SPRN_ESR, reason & ~ESR_IMCP);
	}
	else {
		u32 mcsr = mfspr(SPRN_MCSR);
		if (mcsr & MCSR_IB)
			printk("Instruction Read PLB Error\n");
		if (mcsr & MCSR_DRB)
			printk("Data Read PLB Error\n");
		if (mcsr & MCSR_DWB)
			printk("Data Write PLB Error\n");
		if (mcsr & MCSR_TLBP)
			printk("TLB Parity Error\n");
		if (mcsr & MCSR_ICP){
			flush_instruction_cache();
			printk("I-Cache Parity Error\n");
		}
		if (mcsr & MCSR_DCSP)
			printk("D-Cache Search Parity Error\n");
		if (mcsr & MCSR_DCFP)
			printk("D-Cache Flush Parity Error\n");
		if (mcsr & MCSR_IMPE)
			printk("Machine Check exception is imprecise\n");

		/* Clear MCSR */
		mtspr(SPRN_MCSR, mcsr);
	}
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	return 0;
}
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int machine_check_47x(struct pt_regs *regs)
{
	unsigned long reason = get_mc_reason(regs);
	u32 mcsr;

	printk(KERN_ERR "Machine check in kernel mode.\n");
	if (reason & ESR_IMCP) {
		printk(KERN_ERR
		       "Instruction Synchronous Machine Check exception\n");
		mtspr(SPRN_ESR, reason & ~ESR_IMCP);
		return 0;
	}
	mcsr = mfspr(SPRN_MCSR);
	if (mcsr & MCSR_IB)
		printk(KERN_ERR "Instruction Read PLB Error\n");
	if (mcsr & MCSR_DRB)
		printk(KERN_ERR "Data Read PLB Error\n");
	if (mcsr & MCSR_DWB)
		printk(KERN_ERR "Data Write PLB Error\n");
	if (mcsr & MCSR_TLBP)
		printk(KERN_ERR "TLB Parity Error\n");
	if (mcsr & MCSR_ICP) {
		flush_instruction_cache();
		printk(KERN_ERR "I-Cache Parity Error\n");
	}
	if (mcsr & MCSR_DCSP)
		printk(KERN_ERR "D-Cache Search Parity Error\n");
	if (mcsr & PPC47x_MCSR_GPR)
		printk(KERN_ERR "GPR Parity Error\n");
	if (mcsr & PPC47x_MCSR_FPR)
		printk(KERN_ERR "FPR Parity Error\n");
	if (mcsr & PPC47x_MCSR_IPR)
		printk(KERN_ERR "Machine Check exception is imprecise\n");

	/* Clear MCSR */
	mtspr(SPRN_MCSR, mcsr);

	return 0;
}
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#elif defined(CONFIG_E500)
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int machine_check_e500mc(struct pt_regs *regs)
{
	unsigned long mcsr = mfspr(SPRN_MCSR);
	unsigned long reason = mcsr;
	int recoverable = 1;

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	if (reason & MCSR_LD) {
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		recoverable = fsl_rio_mcheck_exception(regs);
		if (recoverable == 1)
			goto silent_out;
	}

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	printk("Machine check in kernel mode.\n");
	printk("Caused by (from MCSR=%lx): ", reason);

	if (reason & MCSR_MCP)
		printk("Machine Check Signal\n");

	if (reason & MCSR_ICPERR) {
		printk("Instruction Cache Parity Error\n");

		/*
		 * This is recoverable by invalidating the i-cache.
		 */
		mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
		while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
			;

		/*
		 * This will generally be accompanied by an instruction
		 * fetch error report -- only treat MCSR_IF as fatal
		 * if it wasn't due to an L1 parity error.
		 */
		reason &= ~MCSR_IF;
	}

	if (reason & MCSR_DCPERR_MC) {
		printk("Data Cache Parity Error\n");
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		/*
		 * In write shadow mode we auto-recover from the error, but it
		 * may still get logged and cause a machine check.  We should
		 * only treat the non-write shadow case as non-recoverable.
		 */
		if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
			recoverable = 0;
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	}

	if (reason & MCSR_L2MMU_MHIT) {
		printk("Hit on multiple TLB entries\n");
		recoverable = 0;
	}

	if (reason & MCSR_NMI)
		printk("Non-maskable interrupt\n");

	if (reason & MCSR_IF) {
		printk("Instruction Fetch Error Report\n");
		recoverable = 0;
	}

	if (reason & MCSR_LD) {
		printk("Load Error Report\n");
		recoverable = 0;
	}

	if (reason & MCSR_ST) {
		printk("Store Error Report\n");
		recoverable = 0;
	}

	if (reason & MCSR_LDG) {
		printk("Guarded Load Error Report\n");
		recoverable = 0;
	}

	if (reason & MCSR_TLBSYNC)
		printk("Simultaneous tlbsync operations\n");

	if (reason & MCSR_BSL2_ERR) {
		printk("Level 2 Cache Error\n");
		recoverable = 0;
	}

	if (reason & MCSR_MAV) {
		u64 addr;

		addr = mfspr(SPRN_MCAR);
		addr |= (u64)mfspr(SPRN_MCARU) << 32;

		printk("Machine Check %s Address: %#llx\n",
		       reason & MCSR_MEA ? "Effective" : "Physical", addr);
	}

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silent_out:
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	mtspr(SPRN_MCSR, mcsr);
	return mfspr(SPRN_MCSR) == 0 && recoverable;
}

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int machine_check_e500(struct pt_regs *regs)
{
	unsigned long reason = get_mc_reason(regs);

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	if (reason & MCSR_BUS_RBERR) {
		if (fsl_rio_mcheck_exception(regs))
			return 1;
	}

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	printk("Machine check in kernel mode.\n");
	printk("Caused by (from MCSR=%lx): ", reason);

	if (reason & MCSR_MCP)
		printk("Machine Check Signal\n");
	if (reason & MCSR_ICPERR)
		printk("Instruction Cache Parity Error\n");
	if (reason & MCSR_DCP_PERR)
		printk("Data Cache Push Parity Error\n");
	if (reason & MCSR_DCPERR)
		printk("Data Cache Parity Error\n");
	if (reason & MCSR_BUS_IAERR)
		printk("Bus - Instruction Address Error\n");
	if (reason & MCSR_BUS_RAERR)
		printk("Bus - Read Address Error\n");
	if (reason & MCSR_BUS_WAERR)
		printk("Bus - Write Address Error\n");
	if (reason & MCSR_BUS_IBERR)
		printk("Bus - Instruction Data Error\n");
	if (reason & MCSR_BUS_RBERR)
		printk("Bus - Read Data Bus Error\n");
	if (reason & MCSR_BUS_WBERR)
		printk("Bus - Read Data Bus Error\n");
	if (reason & MCSR_BUS_IPERR)
		printk("Bus - Instruction Parity Error\n");
	if (reason & MCSR_BUS_RPERR)
		printk("Bus - Read Parity Error\n");
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	return 0;
}
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int machine_check_generic(struct pt_regs *regs)
{
	return 0;
}
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#elif defined(CONFIG_E200)
int machine_check_e200(struct pt_regs *regs)
{
	unsigned long reason = get_mc_reason(regs);

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	printk("Machine check in kernel mode.\n");
	printk("Caused by (from MCSR=%lx): ", reason);

	if (reason & MCSR_MCP)
		printk("Machine Check Signal\n");
	if (reason & MCSR_CP_PERR)
		printk("Cache Push Parity Error\n");
	if (reason & MCSR_CPERR)
		printk("Cache Parity Error\n");
	if (reason & MCSR_EXCP_ERR)
		printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
	if (reason & MCSR_BUS_IRERR)
		printk("Bus - Read Bus Error on instruction fetch\n");
	if (reason & MCSR_BUS_DRERR)
		printk("Bus - Read Bus Error on data load\n");
	if (reason & MCSR_BUS_WRERR)
		printk("Bus - Write Bus Error on buffered store or cache line push\n");
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	return 0;
}
#else
int machine_check_generic(struct pt_regs *regs)
{
	unsigned long reason = get_mc_reason(regs);

635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663
	printk("Machine check in kernel mode.\n");
	printk("Caused by (from SRR1=%lx): ", reason);
	switch (reason & 0x601F0000) {
	case 0x80000:
		printk("Machine check signal\n");
		break;
	case 0:		/* for 601 */
	case 0x40000:
	case 0x140000:	/* 7450 MSS error and TEA */
		printk("Transfer error ack signal\n");
		break;
	case 0x20000:
		printk("Data parity error signal\n");
		break;
	case 0x10000:
		printk("Address parity error signal\n");
		break;
	case 0x20000000:
		printk("L1 Data Cache error\n");
		break;
	case 0x40000000:
		printk("L1 Instruction Cache error\n");
		break;
	case 0x00100000:
		printk("L2 data cache parity error\n");
		break;
	default:
		printk("Unknown values in msr\n");
	}
664 665
	return 0;
}
666
#endif /* everything else */
667 668 669 670 671

void machine_check_exception(struct pt_regs *regs)
{
	int recover = 0;

672 673
	__get_cpu_var(irq_stat).mce_exceptions++;

674 675 676 677 678 679
	/* See if any machine dependent calls. In theory, we would want
	 * to call the CPU first, and call the ppc_md. one if the CPU
	 * one returns a positive number. However there is existing code
	 * that assumes the board gets a first chance, so let's keep it
	 * that way for now and fix things later. --BenH.
	 */
680 681
	if (ppc_md.machine_check_exception)
		recover = ppc_md.machine_check_exception(regs);
682 683
	else if (cur_cpu_spec->machine_check)
		recover = cur_cpu_spec->machine_check(regs);
684

685
	if (recover > 0)
686 687 688
		return;

#if defined(CONFIG_8xx) && defined(CONFIG_PCI)
689 690 691 692 693 694
	/* the qspan pci read routines can cause machine checks -- Cort
	 *
	 * yuck !!! that totally needs to go away ! There are better ways
	 * to deal with that than having a wart in the mcheck handler.
	 * -- BenH
	 */
695 696 697 698
	bad_page_fault(regs, regs->dar, SIGBUS);
	return;
#endif

699
	if (debugger_fault_handler(regs))
700 701 702 703 704
		return;

	if (check_io_access(regs))
		return;

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Paul Mackerras 已提交
705
	die("Machine check", regs, SIGBUS);
706 707 708 709 710 711 712 713 714 715 716

	/* Must die if the interrupt is not recoverable */
	if (!(regs->msr & MSR_RI))
		panic("Unrecoverable Machine check");
}

void SMIException(struct pt_regs *regs)
{
	die("System Management Interrupt", regs, SIGABRT);
}

717
void unknown_exception(struct pt_regs *regs)
718 719 720 721 722 723 724
{
	printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
	       regs->nip, regs->msr, regs->trap);

	_exception(SIGTRAP, regs, 0, 0);
}

725
void instruction_breakpoint_exception(struct pt_regs *regs)
726 727 728 729 730 731 732 733 734 735 736 737 738 739
{
	if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
					5, SIGTRAP) == NOTIFY_STOP)
		return;
	if (debugger_iabr_match(regs))
		return;
	_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
}

void RunModeException(struct pt_regs *regs)
{
	_exception(SIGTRAP, regs, 0, 0);
}

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Paul Mackerras 已提交
740
void __kprobes single_step_exception(struct pt_regs *regs)
741
{
742
	clear_single_step(regs);
743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758

	if (notify_die(DIE_SSTEP, "single_step", regs, 5,
					5, SIGTRAP) == NOTIFY_STOP)
		return;
	if (debugger_sstep(regs))
		return;

	_exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
}

/*
 * After we have successfully emulated an instruction, we have to
 * check if the instruction was being single-stepped, and if so,
 * pretend we got a single-step exception.  This was pointed out
 * by Kumar Gala.  -- paulus
 */
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759
static void emulate_single_step(struct pt_regs *regs)
760
{
761 762
	if (single_stepping(regs))
		single_step_exception(regs);
763 764
}

765
static inline int __parse_fpscr(unsigned long fpscr)
766
{
767
	int ret = 0;
768 769 770

	/* Invalid operation */
	if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
771
		ret = FPE_FLTINV;
772 773 774

	/* Overflow */
	else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
775
		ret = FPE_FLTOVF;
776 777 778

	/* Underflow */
	else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
779
		ret = FPE_FLTUND;
780 781 782

	/* Divide by zero */
	else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
783
		ret = FPE_FLTDIV;
784 785 786

	/* Inexact result */
	else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
787 788 789 790 791 792 793 794 795 796 797 798
		ret = FPE_FLTRES;

	return ret;
}

static void parse_fpe(struct pt_regs *regs)
{
	int code = 0;

	flush_fp_to_thread(current);

	code = __parse_fpscr(current->thread.fpscr.val);
799 800 801 802 803 804

	_exception(SIGFPE, regs, code, regs->nip);
}

/*
 * Illegal instruction emulation support.  Originally written to
805 806 807 808 809 810 811
 * provide the PVR to user applications using the mfspr rd, PVR.
 * Return non-zero if we can't emulate, or -EFAULT if the associated
 * memory access caused an access fault.  Return zero on success.
 *
 * There are a couple of ways to do this, either "decode" the instruction
 * or directly match lots of bits.  In this case, matching lots of
 * bits is faster and easier.
812
 *
813 814 815 816 817 818 819 820 821 822 823
 */
static int emulate_string_inst(struct pt_regs *regs, u32 instword)
{
	u8 rT = (instword >> 21) & 0x1f;
	u8 rA = (instword >> 16) & 0x1f;
	u8 NB_RB = (instword >> 11) & 0x1f;
	u32 num_bytes;
	unsigned long EA;
	int pos = 0;

	/* Early out if we are an invalid form of lswx */
824
	if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
825 826 827 828 829
		if ((rT == rA) || (rT == NB_RB))
			return -EINVAL;

	EA = (rA == 0) ? 0 : regs->gpr[rA];

830 831 832
	switch (instword & PPC_INST_STRING_MASK) {
		case PPC_INST_LSWX:
		case PPC_INST_STSWX:
833 834 835
			EA += NB_RB;
			num_bytes = regs->xer & 0x7f;
			break;
836 837
		case PPC_INST_LSWI:
		case PPC_INST_STSWI:
838 839 840 841 842 843 844 845 846 847 848
			num_bytes = (NB_RB == 0) ? 32 : NB_RB;
			break;
		default:
			return -EINVAL;
	}

	while (num_bytes != 0)
	{
		u8 val;
		u32 shift = 8 * (3 - (pos & 0x3));

849 850 851
		switch ((instword & PPC_INST_STRING_MASK)) {
			case PPC_INST_LSWX:
			case PPC_INST_LSWI:
852 853 854 855 856 857 858 859
				if (get_user(val, (u8 __user *)EA))
					return -EFAULT;
				/* first time updating this reg,
				 * zero it out */
				if (pos == 0)
					regs->gpr[rT] = 0;
				regs->gpr[rT] |= val << shift;
				break;
860 861
			case PPC_INST_STSWI:
			case PPC_INST_STSWX:
862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881
				val = regs->gpr[rT] >> shift;
				if (put_user(val, (u8 __user *)EA))
					return -EFAULT;
				break;
		}
		/* move EA to next address */
		EA += 1;
		num_bytes--;

		/* manage our position within the register */
		if (++pos == 4) {
			pos = 0;
			if (++rT == 32)
				rT = 0;
		}
	}

	return 0;
}

882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898
static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
{
	u32 ra,rs;
	unsigned long tmp;

	ra = (instword >> 16) & 0x1f;
	rs = (instword >> 21) & 0x1f;

	tmp = regs->gpr[rs];
	tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
	tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
	tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
	regs->gpr[ra] = tmp;

	return 0;
}

899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915
static int emulate_isel(struct pt_regs *regs, u32 instword)
{
	u8 rT = (instword >> 21) & 0x1f;
	u8 rA = (instword >> 16) & 0x1f;
	u8 rB = (instword >> 11) & 0x1f;
	u8 BC = (instword >> 6) & 0x1f;
	u8 bit;
	unsigned long tmp;

	tmp = (rA == 0) ? 0 : regs->gpr[rA];
	bit = (regs->ccr >> (31 - BC)) & 0x1;

	regs->gpr[rT] = bit ? tmp : regs->gpr[rB];

	return 0;
}

916 917 918 919 920
static int emulate_instruction(struct pt_regs *regs)
{
	u32 instword;
	u32 rd;

921
	if (!user_mode(regs) || (regs->msr & MSR_LE))
922 923 924 925 926 927 928
		return -EINVAL;
	CHECK_FULL_REGS(regs);

	if (get_user(instword, (u32 __user *)(regs->nip)))
		return -EFAULT;

	/* Emulate the mfspr rD, PVR. */
929
	if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
930
		PPC_WARN_EMULATED(mfpvr, regs);
931 932 933 934 935 936
		rd = (instword >> 21) & 0x1f;
		regs->gpr[rd] = mfspr(SPRN_PVR);
		return 0;
	}

	/* Emulating the dcba insn is just a no-op.  */
937
	if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
938
		PPC_WARN_EMULATED(dcba, regs);
939
		return 0;
940
	}
941 942

	/* Emulate the mcrxr insn.  */
943
	if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
944
		int shift = (instword >> 21) & 0x1c;
945 946
		unsigned long msk = 0xf0000000UL >> shift;

947
		PPC_WARN_EMULATED(mcrxr, regs);
948 949 950 951 952 953
		regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
		regs->xer &= ~0xf0000000UL;
		return 0;
	}

	/* Emulate load/store string insn. */
954
	if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
955
		PPC_WARN_EMULATED(string, regs);
956
		return emulate_string_inst(regs, instword);
957
	}
958

959
	/* Emulate the popcntb (Population Count Bytes) instruction. */
960
	if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
961
		PPC_WARN_EMULATED(popcntb, regs);
962 963 964
		return emulate_popcntb_inst(regs, instword);
	}

965
	/* Emulate isel (Integer Select) instruction */
966
	if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
967
		PPC_WARN_EMULATED(isel, regs);
968 969 970
		return emulate_isel(regs, instword);
	}

971 972
#ifdef CONFIG_PPC64
	/* Emulate the mfspr rD, DSCR. */
973 974 975 976
	if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
		PPC_INST_MFSPR_DSCR_USER) ||
	     ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
		PPC_INST_MFSPR_DSCR)) &&
977 978 979 980 981 982 983
			cpu_has_feature(CPU_FTR_DSCR)) {
		PPC_WARN_EMULATED(mfdscr, regs);
		rd = (instword >> 21) & 0x1f;
		regs->gpr[rd] = mfspr(SPRN_DSCR);
		return 0;
	}
	/* Emulate the mtspr DSCR, rD. */
984 985 986 987
	if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
		PPC_INST_MTSPR_DSCR_USER) ||
	     ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
		PPC_INST_MTSPR_DSCR)) &&
988 989 990
			cpu_has_feature(CPU_FTR_DSCR)) {
		PPC_WARN_EMULATED(mtdscr, regs);
		rd = (instword >> 21) & 0x1f;
991
		current->thread.dscr = regs->gpr[rd];
992
		current->thread.dscr_inherit = 1;
993
		mtspr(SPRN_DSCR, current->thread.dscr);
994 995 996 997
		return 0;
	}
#endif

998 999 1000
	return -EINVAL;
}

1001
int is_valid_bugaddr(unsigned long addr)
1002
{
1003
	return is_kernel_addr(addr);
1004 1005
}

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Paul Mackerras 已提交
1006
void __kprobes program_check_exception(struct pt_regs *regs)
1007 1008 1009 1010
{
	unsigned int reason = get_reason(regs);
	extern int do_mathemu(struct pt_regs *regs);

1011
	/* We can now get here via a FP Unavailable exception if the core
1012
	 * has no FPU, in that case the reason flags will be 0 */
1013

1014 1015 1016
	if (reason & REASON_FP) {
		/* IEEE FP exception */
		parse_fpe(regs);
P
Paul Mackerras 已提交
1017 1018 1019
		return;
	}
	if (reason & REASON_TRAP) {
1020 1021 1022 1023 1024
		/* Debugger is first in line to stop recursive faults in
		 * rcu_lock, notify_die, or atomic_notifier_call_chain */
		if (debugger_bpt(regs))
			return;

1025
		/* trap exception */
1026 1027 1028
		if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
				== NOTIFY_STOP)
			return;
1029 1030

		if (!(regs->msr & MSR_PR) &&  /* not user-mode */
1031
		    report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1032 1033 1034
			regs->nip += 4;
			return;
		}
P
Paul Mackerras 已提交
1035 1036 1037
		_exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
		return;
	}
1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
	if (reason & REASON_TM) {
		/* This is a TM "Bad Thing Exception" program check.
		 * This occurs when:
		 * -  An rfid/hrfid/mtmsrd attempts to cause an illegal
		 *    transition in TM states.
		 * -  A trechkpt is attempted when transactional.
		 * -  A treclaim is attempted when non transactional.
		 * -  A tend is illegally attempted.
		 * -  writing a TM SPR when transactional.
		 */
		if (!user_mode(regs) &&
		    report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
			regs->nip += 4;
			return;
		}
		/* If usermode caused this, it's done something illegal and
		 * gets a SIGILL slap on the wrist.  We call it an illegal
		 * operand to distinguish from the instruction just being bad
		 * (e.g. executing a 'tend' on a CPU without TM!); it's an
		 * illegal /placement/ of a valid instruction.
		 */
		if (user_mode(regs)) {
			_exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
			return;
		} else {
			printk(KERN_EMERG "Unexpected TM Bad Thing exception "
			       "at %lx (msr 0x%x)\n", regs->nip, reason);
			die("Unrecoverable exception", regs, SIGABRT);
		}
	}
#endif
P
Paul Mackerras 已提交
1070

1071 1072 1073
	/* We restore the interrupt state now */
	if (!arch_irq_disabled_regs(regs))
		local_irq_enable();
1074

1075 1076 1077 1078 1079 1080 1081
#ifdef CONFIG_MATH_EMULATION
	/* (reason & REASON_ILLEGAL) would be the obvious thing here,
	 * but there seems to be a hardware bug on the 405GP (RevD)
	 * that means ESR is sometimes set incorrectly - either to
	 * ESR_DST (!?) or 0.  In the process of chasing this with the
	 * hardware people - not sure if it can happen on any illegal
	 * instruction or only on FP instructions, whether there is a
L
Lucas De Marchi 已提交
1082
	 * pattern to occurrences etc. -dgibson 31/Mar/2003 */
1083 1084
	switch (do_mathemu(regs)) {
	case 0:
1085 1086
		emulate_single_step(regs);
		return;
1087 1088 1089 1090 1091 1092 1093 1094 1095
	case 1: {
			int code = 0;
			code = __parse_fpscr(current->thread.fpscr.val);
			_exception(SIGFPE, regs, code, regs->nip);
			return;
		}
	case -EFAULT:
		_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
		return;
1096
	}
1097
	/* fall through on any other errors */
1098 1099
#endif /* CONFIG_MATH_EMULATION */

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Paul Mackerras 已提交
1100 1101
	/* Try to emulate it if we should. */
	if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1102 1103 1104 1105
		switch (emulate_instruction(regs)) {
		case 0:
			regs->nip += 4;
			emulate_single_step(regs);
P
Paul Mackerras 已提交
1106
			return;
1107 1108
		case -EFAULT:
			_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
P
Paul Mackerras 已提交
1109
			return;
1110 1111
		}
	}
P
Paul Mackerras 已提交
1112 1113 1114 1115 1116

	if (reason & REASON_PRIVILEGED)
		_exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
	else
		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1117 1118
}

1119
void alignment_exception(struct pt_regs *regs)
1120
{
1121
	int sig, code, fixed = 0;
1122

1123 1124 1125 1126
	/* We restore the interrupt state now */
	if (!arch_irq_disabled_regs(regs))
		local_irq_enable();

1127 1128 1129
	/* we don't implement logging of alignment exceptions */
	if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
		fixed = fix_alignment(regs);
1130 1131 1132 1133 1134 1135 1136

	if (fixed == 1) {
		regs->nip += 4;	/* skip over emulated instruction */
		emulate_single_step(regs);
		return;
	}

1137
	/* Operand address was bad */
1138
	if (fixed == -EFAULT) {
1139 1140 1141 1142 1143
		sig = SIGSEGV;
		code = SEGV_ACCERR;
	} else {
		sig = SIGBUS;
		code = BUS_ADRALN;
1144
	}
1145 1146 1147 1148
	if (user_mode(regs))
		_exception(sig, regs, code, regs->dar);
	else
		bad_page_fault(regs, regs->dar, sig);
1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170
}

void StackOverflow(struct pt_regs *regs)
{
	printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
	       current, regs->gpr[1]);
	debugger(regs);
	show_regs(regs);
	panic("kernel stack overflow");
}

void nonrecoverable_exception(struct pt_regs *regs)
{
	printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
	       regs->nip, regs->msr);
	debugger(regs);
	die("nonrecoverable exception", regs, SIGKILL);
}

void trace_syscall(struct pt_regs *regs)
{
	printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld    %s\n",
1171
	       current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
1172 1173
	       regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
}
1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189

void kernel_fp_unavailable_exception(struct pt_regs *regs)
{
	printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
			  "%lx at %lx\n", regs->trap, regs->nip);
	die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
}

void altivec_unavailable_exception(struct pt_regs *regs)
{
	if (user_mode(regs)) {
		/* A user program has executed an altivec instruction,
		   but this kernel doesn't support altivec. */
		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
		return;
	}
1190

1191 1192 1193 1194 1195
	printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
			"%lx at %lx\n", regs->trap, regs->nip);
	die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
}

1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209
void vsx_unavailable_exception(struct pt_regs *regs)
{
	if (user_mode(regs)) {
		/* A user program has executed an vsx instruction,
		   but this kernel doesn't support vsx. */
		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
		return;
	}

	printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
			"%lx at %lx\n", regs->trap, regs->nip);
	die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
}

1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230
void tm_unavailable_exception(struct pt_regs *regs)
{
	/* We restore the interrupt state now */
	if (!arch_irq_disabled_regs(regs))
		local_irq_enable();

	/* Currently we never expect a TMU exception.  Catch
	 * this and kill the process!
	 */
	printk(KERN_EMERG "Unexpected TM unavailable exception at %lx "
	       "(msr %lx)\n",
	       regs->nip, regs->msr);

	if (user_mode(regs)) {
		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
		return;
	}

	die("Unexpected TM unavailable exception", regs, SIGABRT);
}

1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM

extern void do_load_up_fpu(struct pt_regs *regs);

void fp_unavailable_tm(struct pt_regs *regs)
{
	/* Note:  This does not handle any kind of FP laziness. */

	TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
		 regs->nip, regs->msr);
	tm_enable();

        /* We can only have got here if the task started using FP after
         * beginning the transaction.  So, the transactional regs are just a
         * copy of the checkpointed ones.  But, we still need to recheckpoint
         * as we're enabling FP for the process; it will return, abort the
         * transaction, and probably retry but now with FP enabled.  So the
         * checkpointed FP registers need to be loaded.
	 */
	tm_reclaim(&current->thread, current->thread.regs->msr,
		   TM_CAUSE_FAC_UNAV);
	/* Reclaim didn't save out any FPRs to transact_fprs. */

	/* Enable FP for the task: */
	regs->msr |= (MSR_FP | current->thread.fpexc_mode);

	/* This loads and recheckpoints the FP registers from
	 * thread.fpr[].  They will remain in registers after the
	 * checkpoint so we don't need to reload them after.
	 */
	tm_recheckpoint(&current->thread, regs->msr);
}

#ifdef CONFIG_ALTIVEC
extern void do_load_up_altivec(struct pt_regs *regs);

void altivec_unavailable_tm(struct pt_regs *regs)
{
	/* See the comments in fp_unavailable_tm().  This function operates
	 * the same way.
	 */

	TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
		 "MSR=%lx\n",
		 regs->nip, regs->msr);
	tm_enable();
	tm_reclaim(&current->thread, current->thread.regs->msr,
		   TM_CAUSE_FAC_UNAV);
	regs->msr |= MSR_VEC;
	tm_recheckpoint(&current->thread, regs->msr);
	current->thread.used_vr = 1;
}
#endif

#ifdef CONFIG_VSX
void vsx_unavailable_tm(struct pt_regs *regs)
{
	/* See the comments in fp_unavailable_tm().  This works similarly,
	 * though we're loading both FP and VEC registers in here.
	 *
	 * If FP isn't in use, load FP regs.  If VEC isn't in use, load VEC
	 * regs.  Either way, set MSR_VSX.
	 */

	TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
		 "MSR=%lx\n",
		 regs->nip, regs->msr);

	tm_enable();
	/* This reclaims FP and/or VR regs if they're already enabled */
	tm_reclaim(&current->thread, current->thread.regs->msr,
		   TM_CAUSE_FAC_UNAV);

	regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode |
		MSR_VSX;
	/* This loads & recheckpoints FP and VRs. */
	tm_recheckpoint(&current->thread, regs->msr);
	current->thread.used_vsr = 1;
}
#endif
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */

1313 1314
void performance_monitor_exception(struct pt_regs *regs)
{
1315 1316
	__get_cpu_var(irq_stat).pmu_irqs++;

1317 1318 1319
	perf_irq(regs);
}

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Paul Mackerras 已提交
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#ifdef CONFIG_8xx
1321 1322 1323 1324
void SoftwareEmulation(struct pt_regs *regs)
{
	extern int do_mathemu(struct pt_regs *);
	extern int Soft_emulate_8xx(struct pt_regs *);
1325
#if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU)
1326
	int errcode;
1327
#endif
1328 1329 1330 1331 1332 1333 1334 1335 1336 1337

	CHECK_FULL_REGS(regs);

	if (!user_mode(regs)) {
		debugger(regs);
		die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
	}

#ifdef CONFIG_MATH_EMULATION
	errcode = do_mathemu(regs);
1338
	if (errcode >= 0)
1339
		PPC_WARN_EMULATED(math, regs);
1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358

	switch (errcode) {
	case 0:
		emulate_single_step(regs);
		return;
	case 1: {
			int code = 0;
			code = __parse_fpscr(current->thread.fpscr.val);
			_exception(SIGFPE, regs, code, regs->nip);
			return;
		}
	case -EFAULT:
		_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
		return;
	default:
		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
		return;
	}

1359
#elif defined(CONFIG_8XX_MINIMAL_FPEMU)
1360
	errcode = Soft_emulate_8xx(regs);
1361
	if (errcode >= 0)
1362
		PPC_WARN_EMULATED(8xx, regs);
1363

1364 1365
	switch (errcode) {
	case 0:
1366
		emulate_single_step(regs);
1367 1368 1369 1370 1371 1372 1373 1374
		return;
	case 1:
		_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
		return;
	case -EFAULT:
		_exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
		return;
	}
1375 1376
#else
	_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1377
#endif
1378
}
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Paul Mackerras 已提交
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#endif /* CONFIG_8xx */
1380

1381
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438
static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
{
	int changed = 0;
	/*
	 * Determine the cause of the debug event, clear the
	 * event flags and send a trap to the handler. Torez
	 */
	if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
		dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
		current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
#endif
		do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
			     5);
		changed |= 0x01;
	}  else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
		dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
		do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
			     6);
		changed |= 0x01;
	}  else if (debug_status & DBSR_IAC1) {
		current->thread.dbcr0 &= ~DBCR0_IAC1;
		dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
		do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
			     1);
		changed |= 0x01;
	}  else if (debug_status & DBSR_IAC2) {
		current->thread.dbcr0 &= ~DBCR0_IAC2;
		do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
			     2);
		changed |= 0x01;
	}  else if (debug_status & DBSR_IAC3) {
		current->thread.dbcr0 &= ~DBCR0_IAC3;
		dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
		do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
			     3);
		changed |= 0x01;
	}  else if (debug_status & DBSR_IAC4) {
		current->thread.dbcr0 &= ~DBCR0_IAC4;
		do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
			     4);
		changed |= 0x01;
	}
	/*
	 * At the point this routine was called, the MSR(DE) was turned off.
	 * Check all other debug flags and see if that bit needs to be turned
	 * back on or not.
	 */
	if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
		regs->msr |= MSR_DE;
	else
		/* Make sure the IDM flag is off */
		current->thread.dbcr0 &= ~DBCR0_IDM;

	if (changed & 0x01)
		mtspr(SPRN_DBCR0, current->thread.dbcr0);
}
1439

1440
void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
1441
{
1442 1443
	current->thread.dbsr = debug_status;

1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471
	/* Hack alert: On BookE, Branch Taken stops on the branch itself, while
	 * on server, it stops on the target of the branch. In order to simulate
	 * the server behaviour, we thus restart right away with a single step
	 * instead of stopping here when hitting a BT
	 */
	if (debug_status & DBSR_BT) {
		regs->msr &= ~MSR_DE;

		/* Disable BT */
		mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
		/* Clear the BT event */
		mtspr(SPRN_DBSR, DBSR_BT);

		/* Do the single step trick only when coming from userspace */
		if (user_mode(regs)) {
			current->thread.dbcr0 &= ~DBCR0_BT;
			current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
			regs->msr |= MSR_DE;
			return;
		}

		if (notify_die(DIE_SSTEP, "block_step", regs, 5,
			       5, SIGTRAP) == NOTIFY_STOP) {
			return;
		}
		if (debugger_sstep(regs))
			return;
	} else if (debug_status & DBSR_IC) { 	/* Instruction complete */
1472
		regs->msr &= ~MSR_DE;
1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486

		/* Disable instruction completion */
		mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
		/* Clear the instruction completion event */
		mtspr(SPRN_DBSR, DBSR_IC);

		if (notify_die(DIE_SSTEP, "single_step", regs, 5,
			       5, SIGTRAP) == NOTIFY_STOP) {
			return;
		}

		if (debugger_sstep(regs))
			return;

1487
		if (user_mode(regs)) {
1488 1489 1490 1491 1492 1493 1494
			current->thread.dbcr0 &= ~DBCR0_IC;
			if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
					       current->thread.dbcr1))
				regs->msr |= MSR_DE;
			else
				/* Make sure the IDM bit is off */
				current->thread.dbcr0 &= ~DBCR0_IDM;
1495
		}
1496 1497 1498 1499

		_exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
	} else
		handle_debug(regs, debug_status);
1500
}
1501
#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1502 1503 1504 1505 1506 1507 1508 1509 1510 1511

#if !defined(CONFIG_TAU_INT)
void TAUException(struct pt_regs *regs)
{
	printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
	       regs->nip, regs->msr, regs->trap, print_tainted());
}
#endif /* CONFIG_INT_TAU */

#ifdef CONFIG_ALTIVEC
1512
void altivec_assist_exception(struct pt_regs *regs)
1513 1514 1515 1516 1517 1518
{
	int err;

	if (!user_mode(regs)) {
		printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
		       " at %lx\n", regs->nip);
P
Paul Mackerras 已提交
1519
		die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1520 1521
	}

1522 1523
	flush_altivec_to_thread(current);

1524
	PPC_WARN_EMULATED(altivec, regs);
1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537
	err = emulate_altivec(regs);
	if (err == 0) {
		regs->nip += 4;		/* skip emulated instruction */
		emulate_single_step(regs);
		return;
	}

	if (err == -EFAULT) {
		/* got an error reading the instruction */
		_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
	} else {
		/* didn't recognize the instruction */
		/* XXX quick hack for now: set the non-Java bit in the VSCR */
1538 1539
		printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
				   "in %s at %lx\n", current->comm, regs->nip);
1540 1541 1542 1543 1544
		current->thread.vscr.u[3] |= 0x10000;
	}
}
#endif /* CONFIG_ALTIVEC */

1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559
#ifdef CONFIG_VSX
void vsx_assist_exception(struct pt_regs *regs)
{
	if (!user_mode(regs)) {
		printk(KERN_EMERG "VSX assist exception in kernel mode"
		       " at %lx\n", regs->nip);
		die("Kernel VSX assist exception", regs, SIGILL);
	}

	flush_vsx_to_thread(current);
	printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip);
	_exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
}
#endif /* CONFIG_VSX */

1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576
#ifdef CONFIG_FSL_BOOKE
void CacheLockingException(struct pt_regs *regs, unsigned long address,
			   unsigned long error_code)
{
	/* We treat cache locking instructions from the user
	 * as priv ops, in the future we could try to do
	 * something smarter
	 */
	if (error_code & (ESR_DLK|ESR_ILK))
		_exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
	return;
}
#endif /* CONFIG_FSL_BOOKE */

#ifdef CONFIG_SPE
void SPEFloatingPointException(struct pt_regs *regs)
{
1577
	extern int do_spe_mathemu(struct pt_regs *regs);
1578 1579 1580
	unsigned long spefscr;
	int fpexc_mode;
	int code = 0;
1581 1582
	int err;

1583
	flush_spe_to_thread(current);
1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601

	spefscr = current->thread.spefscr;
	fpexc_mode = current->thread.fpexc_mode;

	if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
		code = FPE_FLTOVF;
	}
	else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
		code = FPE_FLTUND;
	}
	else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
		code = FPE_FLTDIV;
	else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
		code = FPE_FLTINV;
	}
	else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
		code = FPE_FLTRES;

1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618
	err = do_spe_mathemu(regs);
	if (err == 0) {
		regs->nip += 4;		/* skip emulated instruction */
		emulate_single_step(regs);
		return;
	}

	if (err == -EFAULT) {
		/* got an error reading the instruction */
		_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
	} else if (err == -EINVAL) {
		/* didn't recognize the instruction */
		printk(KERN_ERR "unrecognized spe instruction "
		       "in %s at %lx\n", current->comm, regs->nip);
	} else {
		_exception(SIGFPE, regs, code, regs->nip);
	}
1619 1620 1621

	return;
}
1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652

void SPEFloatingPointRoundException(struct pt_regs *regs)
{
	extern int speround_handler(struct pt_regs *regs);
	int err;

	preempt_disable();
	if (regs->msr & MSR_SPE)
		giveup_spe(current);
	preempt_enable();

	regs->nip -= 4;
	err = speround_handler(regs);
	if (err == 0) {
		regs->nip += 4;		/* skip emulated instruction */
		emulate_single_step(regs);
		return;
	}

	if (err == -EFAULT) {
		/* got an error reading the instruction */
		_exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
	} else if (err == -EINVAL) {
		/* didn't recognize the instruction */
		printk(KERN_ERR "unrecognized spe instruction "
		       "in %s at %lx\n", current->comm, regs->nip);
	} else {
		_exception(SIGFPE, regs, 0, regs->nip);
		return;
	}
}
1653 1654
#endif

1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667
/*
 * We enter here if we get an unrecoverable exception, that is, one
 * that happened at a point where the RI (recoverable interrupt) bit
 * in the MSR is 0.  This indicates that SRR0/1 are live, and that
 * we therefore lost state by taking this exception.
 */
void unrecoverable_exception(struct pt_regs *regs)
{
	printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
	       regs->trap, regs->nip);
	die("Unrecoverable exception", regs, SIGABRT);
}

1668
#if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685
/*
 * Default handler for a Watchdog exception,
 * spins until a reboot occurs
 */
void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
{
	/* Generic WatchdogHandler, implement your own */
	mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
	return;
}

void WatchdogException(struct pt_regs *regs)
{
	printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
	WatchdogHandler(regs);
}
#endif
1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696

/*
 * We enter here if we discover during exception entry that we are
 * running in supervisor mode with a userspace value in the stack pointer.
 */
void kernel_bad_stack(struct pt_regs *regs)
{
	printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
	       regs->gpr[1], regs->nip);
	die("Bad kernel stack pointer", regs, SIGABRT);
}
1697 1698 1699 1700

void __init trap_init(void)
{
}
1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729


#ifdef CONFIG_PPC_EMULATED_STATS

#define WARN_EMULATED_SETUP(type)	.type = { .name = #type }

struct ppc_emulated ppc_emulated = {
#ifdef CONFIG_ALTIVEC
	WARN_EMULATED_SETUP(altivec),
#endif
	WARN_EMULATED_SETUP(dcba),
	WARN_EMULATED_SETUP(dcbz),
	WARN_EMULATED_SETUP(fp_pair),
	WARN_EMULATED_SETUP(isel),
	WARN_EMULATED_SETUP(mcrxr),
	WARN_EMULATED_SETUP(mfpvr),
	WARN_EMULATED_SETUP(multiple),
	WARN_EMULATED_SETUP(popcntb),
	WARN_EMULATED_SETUP(spe),
	WARN_EMULATED_SETUP(string),
	WARN_EMULATED_SETUP(unaligned),
#ifdef CONFIG_MATH_EMULATION
	WARN_EMULATED_SETUP(math),
#elif defined(CONFIG_8XX_MINIMAL_FPEMU)
	WARN_EMULATED_SETUP(8xx),
#endif
#ifdef CONFIG_VSX
	WARN_EMULATED_SETUP(vsx),
#endif
1730 1731 1732 1733
#ifdef CONFIG_PPC64
	WARN_EMULATED_SETUP(mfdscr),
	WARN_EMULATED_SETUP(mtdscr),
#endif
1734 1735 1736 1737 1738 1739
};

u32 ppc_warn_emulated;

void ppc_warn_emulated_print(const char *type)
{
1740 1741
	pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
			    type);
1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779
}

static int __init ppc_warn_emulated_init(void)
{
	struct dentry *dir, *d;
	unsigned int i;
	struct ppc_emulated_entry *entries = (void *)&ppc_emulated;

	if (!powerpc_debugfs_root)
		return -ENODEV;

	dir = debugfs_create_dir("emulated_instructions",
				 powerpc_debugfs_root);
	if (!dir)
		return -ENOMEM;

	d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
			       &ppc_warn_emulated);
	if (!d)
		goto fail;

	for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
		d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
				       (u32 *)&entries[i].val.counter);
		if (!d)
			goto fail;
	}

	return 0;

fail:
	debugfs_remove_recursive(dir);
	return -ENOMEM;
}

device_initcall(ppc_warn_emulated_init);

#endif /* CONFIG_PPC_EMULATED_STATS */