nmi_int.c 15.5 KB
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/**
 * @file nmi_int.c
 *
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 * @remark Copyright 2002-2009 OProfile authors
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 * @remark Read the file COPYING
 *
 * @author John Levon <levon@movementarian.org>
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 * @author Robert Richter <robert.richter@amd.com>
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 * @author Barry Kasindorf <barry.kasindorf@amd.com>
 * @author Jason Yeh <jason.yeh@amd.com>
 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
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 */

#include <linux/init.h>
#include <linux/notifier.h>
#include <linux/smp.h>
#include <linux/oprofile.h>
#include <linux/sysdev.h>
#include <linux/slab.h>
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#include <linux/moduleparam.h>
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#include <linux/kdebug.h>
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#include <linux/cpu.h>
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#include <asm/nmi.h>
#include <asm/msr.h>
#include <asm/apic.h>
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#include "op_counter.h"
#include "op_x86_model.h"
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static struct op_x86_model_spec *model;
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static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
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/* 0 == registered but off, 1 == registered and on */
static int nmi_enabled = 0;

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struct op_counter_config counter_config[OP_MAX_COUNTER];

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/* common functions */

u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
		    struct op_counter_config *counter_config)
{
	u64 val = 0;
	u16 event = (u16)counter_config->event;

	val |= ARCH_PERFMON_EVENTSEL_INT;
	val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
	val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
	val |= (counter_config->unit_mask & 0xFF) << 8;
	event &= model->event_mask ? model->event_mask : 0xFF;
	val |= event & 0xFF;
	val |= (event & 0x0F00) << 24;

	return val;
}


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static int profile_exceptions_notify(struct notifier_block *self,
				     unsigned long val, void *data)
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{
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	struct die_args *args = (struct die_args *)data;
	int ret = NOTIFY_DONE;
	int cpu = smp_processor_id();

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	switch (val) {
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	case DIE_NMI:
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	case DIE_NMI_IPI:
		model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
		ret = NOTIFY_STOP;
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		break;
	default:
		break;
	}
	return ret;
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}
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static void nmi_cpu_save_registers(struct op_msrs *msrs)
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{
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	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
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	unsigned int i;

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	for (i = 0; i < model->num_counters; ++i) {
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		if (counters[i].addr)
			rdmsrl(counters[i].addr, counters[i].saved);
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	}
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	for (i = 0; i < model->num_controls; ++i) {
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		if (controls[i].addr)
			rdmsrl(controls[i].addr, controls[i].saved);
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	}
}

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static void nmi_cpu_start(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
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	if (!msrs->controls)
		WARN_ON_ONCE(1);
	else
		model->start(msrs);
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}

static int nmi_start(void)
{
	on_each_cpu(nmi_cpu_start, NULL, 1);
	return 0;
}

static void nmi_cpu_stop(void *dummy)
{
	struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
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	if (!msrs->controls)
		WARN_ON_ONCE(1);
	else
		model->stop(msrs);
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}

static void nmi_stop(void)
{
	on_each_cpu(nmi_cpu_stop, NULL, 1);
}

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#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX

static DEFINE_PER_CPU(int, switch_index);

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static inline int has_mux(void)
{
	return !!model->switch_ctrl;
}

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inline int op_x86_phys_to_virt(int phys)
{
	return __get_cpu_var(switch_index) + phys;
}

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inline int op_x86_virt_to_phys(int virt)
{
	return virt % model->num_counters;
}

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static void nmi_shutdown_mux(void)
{
	int i;
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	if (!has_mux())
		return;

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	for_each_possible_cpu(i) {
		kfree(per_cpu(cpu_msrs, i).multiplex);
		per_cpu(cpu_msrs, i).multiplex = NULL;
		per_cpu(switch_index, i) = 0;
	}
}

static int nmi_setup_mux(void)
{
	size_t multiplex_size =
		sizeof(struct op_msr) * model->num_virt_counters;
	int i;
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	if (!has_mux())
		return 1;

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	for_each_possible_cpu(i) {
		per_cpu(cpu_msrs, i).multiplex =
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			kzalloc(multiplex_size, GFP_KERNEL);
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		if (!per_cpu(cpu_msrs, i).multiplex)
			return 0;
	}
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	return 1;
}

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static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
{
	int i;
	struct op_msr *multiplex = msrs->multiplex;

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	if (!has_mux())
		return;

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	for (i = 0; i < model->num_virt_counters; ++i) {
		if (counter_config[i].enabled) {
			multiplex[i].saved = -(u64)counter_config[i].count;
		} else {
			multiplex[i].saved = 0;
		}
	}

	per_cpu(switch_index, cpu) = 0;
}

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static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
{
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	struct op_msr *counters = msrs->counters;
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	struct op_msr *multiplex = msrs->multiplex;
	int i;

	for (i = 0; i < model->num_counters; ++i) {
		int virt = op_x86_phys_to_virt(i);
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		if (counters[i].addr)
			rdmsrl(counters[i].addr, multiplex[virt].saved);
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	}
}

static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
{
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	struct op_msr *counters = msrs->counters;
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	struct op_msr *multiplex = msrs->multiplex;
	int i;

	for (i = 0; i < model->num_counters; ++i) {
		int virt = op_x86_phys_to_virt(i);
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		if (counters[i].addr)
			wrmsrl(counters[i].addr, multiplex[virt].saved);
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	}
}

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static void nmi_cpu_switch(void *dummy)
{
	int cpu = smp_processor_id();
	int si = per_cpu(switch_index, cpu);
	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);

	nmi_cpu_stop(NULL);
	nmi_cpu_save_mpx_registers(msrs);

	/* move to next set */
	si += model->num_counters;
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	if ((si >= model->num_virt_counters) || (counter_config[si].count == 0))
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		per_cpu(switch_index, cpu) = 0;
	else
		per_cpu(switch_index, cpu) = si;

	model->switch_ctrl(model, msrs);
	nmi_cpu_restore_mpx_registers(msrs);

	nmi_cpu_start(NULL);
}


/*
 * Quick check to see if multiplexing is necessary.
 * The check should be sufficient since counters are used
 * in ordre.
 */
static int nmi_multiplex_on(void)
{
	return counter_config[model->num_counters].count ? 0 : -EINVAL;
}

static int nmi_switch_event(void)
{
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	if (!has_mux())
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		return -ENOSYS;		/* not implemented */
	if (nmi_multiplex_on() < 0)
		return -EINVAL;		/* not necessary */

	on_each_cpu(nmi_cpu_switch, NULL, 1);

	return 0;
}

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static inline void mux_init(struct oprofile_operations *ops)
{
	if (has_mux())
		ops->switch_events = nmi_switch_event;
}

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static void mux_clone(int cpu)
{
	if (!has_mux())
		return;

	memcpy(per_cpu(cpu_msrs, cpu).multiplex,
	       per_cpu(cpu_msrs, 0).multiplex,
	       sizeof(struct op_msr) * model->num_virt_counters);
}

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#else

inline int op_x86_phys_to_virt(int phys) { return phys; }
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inline int op_x86_virt_to_phys(int virt) { return virt; }
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static inline void nmi_shutdown_mux(void) { }
static inline int nmi_setup_mux(void) { return 1; }
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static inline void
nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
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static inline void mux_init(struct oprofile_operations *ops) { }
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static void mux_clone(int cpu) { }
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#endif

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static void free_msrs(void)
{
	int i;
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	for_each_possible_cpu(i) {
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		kfree(per_cpu(cpu_msrs, i).counters);
		per_cpu(cpu_msrs, i).counters = NULL;
		kfree(per_cpu(cpu_msrs, i).controls);
		per_cpu(cpu_msrs, i).controls = NULL;
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	}
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	nmi_shutdown_mux();
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}

static int allocate_msrs(void)
{
	size_t controls_size = sizeof(struct op_msr) * model->num_controls;
	size_t counters_size = sizeof(struct op_msr) * model->num_counters;

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	int i;
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	for_each_possible_cpu(i) {
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		per_cpu(cpu_msrs, i).counters = kzalloc(counters_size,
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							GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).counters)
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			goto fail;
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		per_cpu(cpu_msrs, i).controls = kzalloc(controls_size,
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							GFP_KERNEL);
		if (!per_cpu(cpu_msrs, i).controls)
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			goto fail;
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	}

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	if (!nmi_setup_mux())
		goto fail;

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	return 1;
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fail:
	free_msrs();
	return 0;
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}

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static void nmi_cpu_setup(void *dummy)
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{
	int cpu = smp_processor_id();
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	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
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	nmi_cpu_save_registers(msrs);
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	spin_lock(&oprofilefs_lock);
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	model->setup_ctrs(model, msrs);
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	nmi_cpu_setup_mux(cpu, msrs);
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	spin_unlock(&oprofilefs_lock);
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	per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
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	apic_write(APIC_LVTPC, APIC_DM_NMI);
}

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static struct notifier_block profile_exceptions_nb = {
	.notifier_call = profile_exceptions_notify,
	.next = NULL,
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	.priority = 2
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};
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static int nmi_setup(void)
{
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	int err = 0;
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	int cpu;
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	if (!allocate_msrs())
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		return -ENOMEM;
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	/* We need to serialize save and setup for HT because the subset
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	 * of msrs are distinct for save and setup operations
	 */
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	/* Assume saved/restored counters are the same on all CPUs */
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	err = model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
	if (err)
		goto fail;

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	for_each_possible_cpu(cpu) {
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		if (!cpu)
			continue;

		memcpy(per_cpu(cpu_msrs, cpu).counters,
		       per_cpu(cpu_msrs, 0).counters,
		       sizeof(struct op_msr) * model->num_counters);

		memcpy(per_cpu(cpu_msrs, cpu).controls,
		       per_cpu(cpu_msrs, 0).controls,
		       sizeof(struct op_msr) * model->num_controls);

		mux_clone(cpu);
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	}
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	err = register_die_notifier(&profile_exceptions_nb);
	if (err)
		goto fail;

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	on_each_cpu(nmi_cpu_setup, NULL, 1);
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	nmi_enabled = 1;
	return 0;
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fail:
	free_msrs();
	return err;
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}

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static void nmi_cpu_restore_registers(struct op_msrs *msrs)
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{
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	struct op_msr *counters = msrs->counters;
	struct op_msr *controls = msrs->controls;
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	unsigned int i;

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	for (i = 0; i < model->num_controls; ++i) {
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		if (controls[i].addr)
			wrmsrl(controls[i].addr, controls[i].saved);
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	}
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	for (i = 0; i < model->num_counters; ++i) {
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		if (counters[i].addr)
			wrmsrl(counters[i].addr, counters[i].saved);
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	}
}

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static void nmi_cpu_shutdown(void *dummy)
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{
	unsigned int v;
	int cpu = smp_processor_id();
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	struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
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	/* restoring APIC_LVTPC can trigger an apic error because the delivery
	 * mode and vector nr combination can be illegal. That's by design: on
	 * power on apic lvt contain a zero vector nr which are legal only for
	 * NMI delivery mode. So inhibit apic err before restoring lvtpc
	 */
	v = apic_read(APIC_LVTERR);
	apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
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	apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
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	apic_write(APIC_LVTERR, v);
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	nmi_cpu_restore_registers(msrs);
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}

static void nmi_shutdown(void)
{
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	struct op_msrs *msrs;

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	nmi_enabled = 0;
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	on_each_cpu(nmi_cpu_shutdown, NULL, 1);
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	unregister_die_notifier(&profile_exceptions_nb);
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	msrs = &get_cpu_var(cpu_msrs);
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	model->shutdown(msrs);
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	free_msrs();
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	put_cpu_var(cpu_msrs);
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}

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static int nmi_create_files(struct super_block *sb, struct dentry *root)
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{
	unsigned int i;

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	for (i = 0; i < model->num_virt_counters; ++i) {
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		struct dentry *dir;
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		char buf[4];
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		/* quick little hack to _not_ expose a counter if it is not
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		 * available for use.  This should protect userspace app.
		 * NOTE:  assumes 1:1 mapping here (that counters are organized
		 *        sequentially in their struct assignment).
		 */
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		if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i)))
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			continue;

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		snprintf(buf,  sizeof(buf), "%d", i);
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		dir = oprofilefs_mkdir(sb, root, buf);
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		oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
		oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
		oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
		oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
		oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
		oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
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	}

	return 0;
}
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static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
				 void *data)
{
	int cpu = (unsigned long)data;
	switch (action) {
	case CPU_DOWN_FAILED:
	case CPU_ONLINE:
		smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
		break;
	case CPU_DOWN_PREPARE:
		smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
		break;
	}
	return NOTIFY_DONE;
}

static struct notifier_block oprofile_cpu_nb = {
	.notifier_call = oprofile_cpu_notifier
};

#ifdef CONFIG_PM

static int nmi_suspend(struct sys_device *dev, pm_message_t state)
{
	/* Only one CPU left, just stop that one */
	if (nmi_enabled == 1)
		nmi_cpu_stop(NULL);
	return 0;
}

static int nmi_resume(struct sys_device *dev)
{
	if (nmi_enabled == 1)
		nmi_cpu_start(NULL);
	return 0;
}

static struct sysdev_class oprofile_sysclass = {
	.name		= "oprofile",
	.resume		= nmi_resume,
	.suspend	= nmi_suspend,
};

static struct sys_device device_oprofile = {
	.id	= 0,
	.cls	= &oprofile_sysclass,
};

static int __init init_sysfs(void)
{
	int error;

	error = sysdev_class_register(&oprofile_sysclass);
	if (!error)
		error = sysdev_register(&device_oprofile);
	return error;
}

static void exit_sysfs(void)
{
	sysdev_unregister(&device_oprofile);
	sysdev_class_unregister(&oprofile_sysclass);
}

#else
#define init_sysfs() do { } while (0)
#define exit_sysfs() do { } while (0)
#endif /* CONFIG_PM */

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static int __init p4_init(char **cpu_type)
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{
	__u8 cpu_model = boot_cpu_data.x86_model;

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	if (cpu_model > 6 || cpu_model == 5)
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		return 0;

#ifndef CONFIG_SMP
	*cpu_type = "i386/p4";
	model = &op_p4_spec;
	return 1;
#else
	switch (smp_num_siblings) {
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	case 1:
		*cpu_type = "i386/p4";
		model = &op_p4_spec;
		return 1;

	case 2:
		*cpu_type = "i386/p4-ht";
		model = &op_p4_ht2_spec;
		return 1;
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	}
#endif

	printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
	printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
	return 0;
}

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static int force_arch_perfmon;
static int force_cpu_type(const char *str, struct kernel_param *kp)
{
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	if (!strcmp(str, "arch_perfmon")) {
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		force_arch_perfmon = 1;
		printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
	}

	return 0;
}
module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
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static int __init ppro_init(char **cpu_type)
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{
	__u8 cpu_model = boot_cpu_data.x86_model;
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	struct op_x86_model_spec *spec = &op_ppro_spec;	/* default */
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	if (force_arch_perfmon && cpu_has_arch_perfmon)
		return 0;

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	switch (cpu_model) {
	case 0 ... 2:
		*cpu_type = "i386/ppro";
		break;
	case 3 ... 5:
		*cpu_type = "i386/pii";
		break;
	case 6 ... 8:
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	case 10 ... 11:
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		*cpu_type = "i386/piii";
		break;
	case 9:
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	case 13:
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		*cpu_type = "i386/p6_mobile";
		break;
	case 14:
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		*cpu_type = "i386/core";
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		break;
	case 15: case 23:
		*cpu_type = "i386/core_2";
		break;
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	case 0x2e:
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	case 26:
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		spec = &op_arch_perfmon_spec;
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		*cpu_type = "i386/core_i7";
		break;
	case 28:
		*cpu_type = "i386/atom";
		break;
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	default:
		/* Unknown */
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		return 0;
	}

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	model = spec;
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	return 1;
}

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/* in order to get sysfs right */
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static int using_nmi;

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int __init op_nmi_init(struct oprofile_operations *ops)
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{
	__u8 vendor = boot_cpu_data.x86_vendor;
	__u8 family = boot_cpu_data.x86;
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	char *cpu_type = NULL;
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	int ret = 0;
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	if (!cpu_has_apic)
		return -ENODEV;
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	switch (vendor) {
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	case X86_VENDOR_AMD:
		/* Needs to be at least an Athlon (or hammer in 32bit mode) */
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		switch (family) {
		case 6:
			cpu_type = "i386/athlon";
			break;
		case 0xf:
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			/*
			 * Actually it could be i386/hammer too, but
			 * give user space an consistent name.
			 */
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			cpu_type = "x86-64/hammer";
			break;
		case 0x10:
			cpu_type = "x86-64/family10";
			break;
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		case 0x11:
			cpu_type = "x86-64/family11h";
			break;
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		default:
			return -ENODEV;
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		}
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		model = &op_amd_spec;
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		break;

	case X86_VENDOR_INTEL:
		switch (family) {
			/* Pentium IV */
		case 0xf:
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			p4_init(&cpu_type);
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			break;
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			/* A P6-class processor */
		case 6:
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			ppro_init(&cpu_type);
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			break;

		default:
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			break;
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		}
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		if (cpu_type)
			break;

		if (!cpu_has_arch_perfmon)
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			return -ENODEV;
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		/* use arch perfmon as fallback */
		cpu_type = "i386/arch_perfmon";
		model = &op_arch_perfmon_spec;
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		break;

	default:
		return -ENODEV;
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	}

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	register_cpu_notifier(&oprofile_cpu_nb);
703

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	/* default values, can be overwritten by model */
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	ops->create_files	= nmi_create_files;
	ops->setup		= nmi_setup;
	ops->shutdown		= nmi_shutdown;
	ops->start		= nmi_start;
	ops->stop		= nmi_stop;
	ops->cpu_type		= cpu_type;
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	if (model->init)
		ret = model->init(ops);
	if (ret)
		return ret;

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	if (!model->num_virt_counters)
		model->num_virt_counters = model->num_counters;

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	mux_init(ops);

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	init_sysfs();
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	using_nmi = 1;
	printk(KERN_INFO "oprofile: using NMI interrupt.\n");
	return 0;
}

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void op_nmi_exit(void)
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{
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	if (using_nmi) {
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		exit_sysfs();
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		unregister_cpu_notifier(&oprofile_cpu_nb);
	}
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	if (model->exit)
		model->exit();
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}