Skip to content

cloud-kernel
cloud-kernel

openanolis / cloud-kernel
1 年多 前同步成功

通知 160
Star 36
Fork 7
cloud-kernel
cloud-kernel
切换分支/标签
查找文件 普通视图历史永久链接Permalink
core.c 49.0 KB
Newer Older
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1 2 3 4 5 
/*
 *
 * arch/arm/mach-u300/core.c
 *
 *
L
ARM: 5895/2: Alter name of U300 watchdog resource  
Linus Walleij 已提交
6 
 * Copyright (C) 2007-2010 ST-Ericsson AB
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 
 * License terms: GNU General Public License (GPL) version 2
 * Core platform support, IRQ handling and device definitions.
 * Author: Linus Walleij <linus.walleij@stericsson.com>
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/mm.h>
#include <linux/termios.h>
#include <linux/amba/bus.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
L
ARM: 6296/1: clock U300 intcon and timer properly  
Linus Walleij 已提交
22 23 
#include <linux/clk.h>
#include <linux/err.h>
L
ARM: platform data to use the FSMC NAND with the U300  
Linus Walleij 已提交
24 25 
#include <linux/mtd/nand.h>
#include <linux/mtd/fsmc.h>
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
26 27 28 29 30 31 32 33 

#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/hardware/vic.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
L
ARM: platform data to use the FSMC NAND with the U300  
Linus Walleij 已提交
34 
#include <mach/coh901318.h>
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
35 36 
#include <mach/hardware.h>
#include <mach/syscon.h>
L
ARM: 5852/1: Add COH 901 318 DMA driver platform config for U300  
Linus Walleij 已提交
37 
#include <mach/dma_channels.h>
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
38 39 40 

#include "clock.h"
#include "mmc.h"
L
ARM: 5667/3: U300 SSP/SPI board setup and test  
Linus Walleij 已提交
41 
#include "spi.h"
L
ARM: 5668/2: U300 I2C board setup  
Linus Walleij 已提交
42 
#include "i2c.h"
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 

/*
 * Static I/O mappings that are needed for booting the U300 platforms. The
 * only things we need are the areas where we find the timer, syscon and
 * intcon, since the remaining device drivers will map their own memory
 * physical to virtual as the need arise.
 */
static struct map_desc u300_io_desc[] __initdata = {
	{
		.virtual	= U300_SLOW_PER_VIRT_BASE,
		.pfn		= __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
		.length		= SZ_64K,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= U300_AHB_PER_VIRT_BASE,
		.pfn		= __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
		.length		= SZ_32K,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= U300_FAST_PER_VIRT_BASE,
		.pfn		= __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
		.length		= SZ_32K,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= 0xffff2000, /* TCM memory */
		.pfn		= __phys_to_pfn(0xffff2000),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	},

	/*
	 * This overlaps with the IRQ vectors etc at 0xffff0000, so these
	 * may have to be moved to 0x00000000 in order to use the ROM.
	 */
	/*
	{
		.virtual	= U300_BOOTROM_VIRT_BASE,
		.pfn		= __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
		.length		= SZ_64K,
		.type		= MT_ROM,
	},
	*/
};

void __init u300_map_io(void)
{
	iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
}

/*
 * Declaration of devices found on the U300 board and
 * their respective memory locations.
 */
static struct amba_device uart0_device = {
	.dev = {
		.init_name = "uart0", /* Slow device at 0x3000 offset */
		.platform_data = NULL,
	},
	.res = {
		.start = U300_UART0_BASE,
		.end   = U300_UART0_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	.irq = { IRQ_U300_UART0, NO_IRQ },
};

/* The U335 have an additional UART1 on the APP CPU */
#ifdef CONFIG_MACH_U300_BS335
static struct amba_device uart1_device = {
	.dev = {
		.init_name = "uart1", /* Fast device at 0x7000 offset */
		.platform_data = NULL,
	},
	.res = {
		.start = U300_UART1_BASE,
		.end   = U300_UART1_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	.irq = { IRQ_U300_UART1, NO_IRQ },
};
#endif

static struct amba_device pl172_device = {
	.dev = {
		.init_name = "pl172", /* AHB device at 0x4000 offset */
		.platform_data = NULL,
	},
	.res = {
		.start = U300_EMIF_CFG_BASE,
		.end   = U300_EMIF_CFG_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};


/*
 * Everything within this next ifdef deals with external devices connected to
 * the APP SPI bus.
 */
static struct amba_device pl022_device = {
	.dev = {
		.coherent_dma_mask = ~0,
		.init_name = "pl022", /* Fast device at 0x6000 offset */
	},
	.res = {
		.start = U300_SPI_BASE,
		.end   = U300_SPI_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	.irq = {IRQ_U300_SPI, NO_IRQ },
	/*
	 * This device has a DMA channel but the Linux driver does not use
	 * it currently.
	 */
};

static struct amba_device mmcsd_device = {
	.dev = {
		.init_name = "mmci", /* Fast device at 0x1000 offset */
		.platform_data = NULL, /* Added later */
	},
	.res = {
		.start = U300_MMCSD_BASE,
		.end   = U300_MMCSD_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	.irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
	/*
	 * This device has a DMA channel but the Linux driver does not use
	 * it currently.
	 */
};

/*
 * The order of device declaration may be important, since some devices
 * have dependencies on other devices being initialized first.
 */
static struct amba_device *amba_devs[] __initdata = {
	&uart0_device,
#ifdef CONFIG_MACH_U300_BS335
	&uart1_device,
#endif
	&pl022_device,
	&pl172_device,
	&mmcsd_device,
};

/* Here follows a list of all hw resources that the platform devices
 * allocate. Note, clock dependencies are not included
 */

static struct resource gpio_resources[] = {
	{
		.start = U300_GPIO_BASE,
		.end   = (U300_GPIO_BASE + SZ_4K - 1),
		.flags = IORESOURCE_MEM,
	},
	{
		.name  = "gpio0",
		.start = IRQ_U300_GPIO_PORT0,
		.end   = IRQ_U300_GPIO_PORT0,
		.flags = IORESOURCE_IRQ,
	},
	{
		.name  = "gpio1",
		.start = IRQ_U300_GPIO_PORT1,
		.end   = IRQ_U300_GPIO_PORT1,
		.flags = IORESOURCE_IRQ,
	},
	{
		.name  = "gpio2",
		.start = IRQ_U300_GPIO_PORT2,
		.end   = IRQ_U300_GPIO_PORT2,
		.flags = IORESOURCE_IRQ,
	},
#ifdef U300_COH901571_3
	{
		.name  = "gpio3",
		.start = IRQ_U300_GPIO_PORT3,
		.end   = IRQ_U300_GPIO_PORT3,
		.flags = IORESOURCE_IRQ,
	},
	{
		.name  = "gpio4",
		.start = IRQ_U300_GPIO_PORT4,
		.end   = IRQ_U300_GPIO_PORT4,
		.flags = IORESOURCE_IRQ,
	},
#ifdef CONFIG_MACH_U300_BS335
	{
		.name  = "gpio5",
		.start = IRQ_U300_GPIO_PORT5,
		.end   = IRQ_U300_GPIO_PORT5,
		.flags = IORESOURCE_IRQ,
	},
	{
		.name  = "gpio6",
		.start = IRQ_U300_GPIO_PORT6,
		.end   = IRQ_U300_GPIO_PORT6,
		.flags = IORESOURCE_IRQ,
	},
#endif /* CONFIG_MACH_U300_BS335 */
#endif /* U300_COH901571_3 */
};

static struct resource keypad_resources[] = {
	{
		.start = U300_KEYPAD_BASE,
		.end   = U300_KEYPAD_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.name  = "coh901461-press",
		.start = IRQ_U300_KEYPAD_KEYBF,
		.end   = IRQ_U300_KEYPAD_KEYBF,
		.flags = IORESOURCE_IRQ,
	},
	{
		.name  = "coh901461-release",
		.start = IRQ_U300_KEYPAD_KEYBR,
		.end   = IRQ_U300_KEYPAD_KEYBR,
		.flags = IORESOURCE_IRQ,
	},
};

static struct resource rtc_resources[] = {
	{
		.start = U300_RTC_BASE,
		.end   = U300_RTC_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_U300_RTC,
		.end   = IRQ_U300_RTC,
		.flags = IORESOURCE_IRQ,
	},
};

/*
 * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
 * but these are not yet used by the driver.
 */
static struct resource fsmc_resources[] = {
	{
L
ARM: platform data to use the FSMC NAND with the U300  
Linus Walleij 已提交
290 291 292 293 294 295 296 
		.name  = "nand_data",
		.start = U300_NAND_CS0_PHYS_BASE,
		.end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.name  = "fsmc_regs",
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 
		.start = U300_NAND_IF_PHYS_BASE,
		.end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

static struct resource i2c0_resources[] = {
	{
		.start = U300_I2C0_BASE,
		.end   = U300_I2C0_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_U300_I2C0,
		.end   = IRQ_U300_I2C0,
		.flags = IORESOURCE_IRQ,
	},
};

static struct resource i2c1_resources[] = {
	{
		.start = U300_I2C1_BASE,
		.end   = U300_I2C1_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_U300_I2C1,
		.end   = IRQ_U300_I2C1,
		.flags = IORESOURCE_IRQ,
	},

};

static struct resource wdog_resources[] = {
	{
		.start = U300_WDOG_BASE,
		.end   = U300_WDOG_BASE + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = IRQ_U300_WDOG,
		.end   = IRQ_U300_WDOG,
		.flags = IORESOURCE_IRQ,
	}
};

/* TODO: These should be protected by suitable #ifdef's */
static struct resource ave_resources[] = {
	{
		.name  = "AVE3e I/O Area",
		.start = U300_VIDEOENC_BASE,
		.end   = U300_VIDEOENC_BASE + SZ_512K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.name  = "AVE3e IRQ0",
		.start = IRQ_U300_VIDEO_ENC_0,
		.end   = IRQ_U300_VIDEO_ENC_0,
		.flags = IORESOURCE_IRQ,
	},
	{
		.name  = "AVE3e IRQ1",
		.start = IRQ_U300_VIDEO_ENC_1,
		.end   = IRQ_U300_VIDEO_ENC_1,
		.flags = IORESOURCE_IRQ,
	},
	{
		.name  = "AVE3e Physmem Area",
		.start = 0, /* 0 will be remapped to reserved memory */
		.end   = SZ_1M - 1,
		.flags = IORESOURCE_MEM,
	},
	/*
	 * The AVE3e requires two regions of 256MB that it considers
	 * "invisible". The hardware will not be able to access these
D
tree-wide: Assorted spelling fixes  
Daniel Mack 已提交
372 
	 * addresses, so they should never point to system RAM.
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 
	 */
	{
		.name  = "AVE3e Reserved 0",
		.start = 0xd0000000,
		.end   = 0xd0000000 + SZ_256M - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.name  = "AVE3e Reserved 1",
		.start = 0xe0000000,
		.end   = 0xe0000000 + SZ_256M - 1,
		.flags = IORESOURCE_MEM,
	},
};
L
ARM: 5852/1: Add COH 901 318 DMA driver platform config for U300  
Linus Walleij 已提交
388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 
static struct resource dma_resource[] = {
	{
		.start = U300_DMAC_BASE,
		.end = U300_DMAC_BASE + PAGE_SIZE - 1,
		.flags =  IORESOURCE_MEM,
	},
	{
		.start = IRQ_U300_DMA,
		.end = IRQ_U300_DMA,
		.flags =  IORESOURCE_IRQ,
	}
};

#ifdef CONFIG_MACH_U300_BS335
/* points out all dma slave channels.
 * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 * Select all channels from A to B, end of list is marked with -1,-1
 */
static int dma_slave_channels[] = {
	U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
	U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};

/* points out all dma memcpy channels. */
static int dma_memcpy_channels[] = {
	U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};

#else /* CONFIG_MACH_U300_BS335 */

static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
static int dma_memcpy_channels[] = {
	U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};

#endif

/** register dma for memory access
 *
 * active  1 means dma intends to access memory
 *         0 means dma wont access memory
 */
static void coh901318_access_memory_state(struct device *dev, bool active)
{
}

#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
			COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
			COH901318_CX_CFG_LCR_DISABLE | \
			COH901318_CX_CFG_TC_IRQ_ENABLE | \
			COH901318_CX_CFG_BE_IRQ_ENABLE)
#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
			COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
			COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
			COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
			COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
			COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
			COH901318_CX_CTRL_MASTER_MODE_M1RW | \
			COH901318_CX_CTRL_TCP_DISABLE | \
			COH901318_CX_CTRL_TC_IRQ_DISABLE | \
			COH901318_CX_CTRL_HSP_DISABLE | \
			COH901318_CX_CTRL_HSS_DISABLE | \
			COH901318_CX_CTRL_DDMA_LEGACY | \
			COH901318_CX_CTRL_PRDD_SOURCE)
#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
			COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
			COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
			COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
			COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
			COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
			COH901318_CX_CTRL_MASTER_MODE_M1RW | \
			COH901318_CX_CTRL_TCP_DISABLE | \
			COH901318_CX_CTRL_TC_IRQ_DISABLE | \
			COH901318_CX_CTRL_HSP_DISABLE | \
			COH901318_CX_CTRL_HSS_DISABLE | \
			COH901318_CX_CTRL_DDMA_LEGACY | \
			COH901318_CX_CTRL_PRDD_SOURCE)
#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
			COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
			COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
			COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
			COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
			COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
			COH901318_CX_CTRL_MASTER_MODE_M1RW | \
			COH901318_CX_CTRL_TCP_DISABLE | \
			COH901318_CX_CTRL_TC_IRQ_ENABLE | \
			COH901318_CX_CTRL_HSP_DISABLE | \
			COH901318_CX_CTRL_HSS_DISABLE | \
			COH901318_CX_CTRL_DDMA_LEGACY | \
			COH901318_CX_CTRL_PRDD_SOURCE)

const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
	{
		.number = U300_DMA_MSL_TX_0,
		.name = "MSL TX 0",
		.priority_high = 0,
		.dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
	},
	{
		.number = U300_DMA_MSL_TX_1,
		.name = "MSL TX 1",
		.priority_high = 0,
		.dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
	},
	{
		.number = U300_DMA_MSL_TX_2,
		.name = "MSL TX 2",
		.priority_high = 0,
		.dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.desc_nbr_max = 10,
	},
	{
		.number = U300_DMA_MSL_TX_3,
		.name = "MSL TX 3",
		.priority_high = 0,
		.dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
	},
	{
		.number = U300_DMA_MSL_TX_4,
		.name = "MSL TX 4",
		.priority_high = 0,
		.dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
	},
	{
		.number = U300_DMA_MSL_TX_5,
		.name = "MSL TX 5",
		.priority_high = 0,
		.dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
	},
	{
		.number = U300_DMA_MSL_TX_6,
		.name = "MSL TX 6",
		.priority_high = 0,
		.dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
	},
	{
		.number = U300_DMA_MSL_RX_0,
		.name = "MSL RX 0",
		.priority_high = 0,
		.dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
	},
	{
		.number = U300_DMA_MSL_RX_1,
		.name = "MSL RX 1",
		.priority_high = 0,
		.dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli = 0,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
	},
	{
		.number = U300_DMA_MSL_RX_2,
		.name = "MSL RX 2",
		.priority_high = 0,
		.dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
	},
	{
		.number = U300_DMA_MSL_RX_3,
		.name = "MSL RX 3",
		.priority_high = 0,
		.dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
	},
	{
		.number = U300_DMA_MSL_RX_4,
		.name = "MSL RX 4",
		.priority_high = 0,
		.dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
	},
	{
		.number = U300_DMA_MSL_RX_5,
		.name = "MSL RX 5",
		.priority_high = 0,
		.dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
				COH901318_CX_CTRL_PRDD_DEST,
	},
	{
		.number = U300_DMA_MSL_RX_6,
		.name = "MSL RX 6",
		.priority_high = 0,
		.dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
	},
	{
		.number = U300_DMA_MMCSD_RX_TX,
		.name = "MMCSD RX TX",
		.priority_high = 0,
		.dev_addr =  U300_MMCSD_BASE + 0x080,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
L
ARM: 5935/1: [U300] Fix the DMA configuration  
Linus Walleij 已提交
978 979 
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
L
ARM: 5852/1: Add COH 901 318 DMA driver platform config for U300  
Linus Walleij 已提交
980 981 982 983 984 985 986 987 988 989 
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
L
ARM: 5935/1: [U300] Fix the DMA configuration  
Linus Walleij 已提交
990 
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
L
ARM: 5852/1: Add COH 901 318 DMA driver platform config for U300  
Linus Walleij 已提交
991 992 993 994 995 996 997 998 999 
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
L
ARM: 5935/1: [U300] Fix the DMA configuration  
Linus Walleij 已提交
1000 
				COH901318_CX_CTRL_TCP_DISABLE |
L
ARM: 5852/1: Add COH 901 318 DMA driver platform config for U300  
Linus Walleij 已提交
1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY,

	},
	{
		.number = U300_DMA_MSPRO_TX,
		.name = "MSPRO TX",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_MSPRO_RX,
		.name = "MSPRO RX",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_UART0_TX,
		.name = "UART0 TX",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_UART0_RX,
		.name = "UART0 RX",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_APEX_TX,
		.name = "APEX TX",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_APEX_RX,
		.name = "APEX RX",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_PCM_I2S0_TX,
		.name = "PCM I2S0 TX",
		.priority_high = 1,
		.dev_addr = U300_PCM_I2S0_BASE + 0x14,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
	},
	{
		.number = U300_DMA_PCM_I2S0_RX,
		.name = "PCM I2S0 RX",
		.priority_high = 1,
		.dev_addr = U300_PCM_I2S0_BASE + 0x10,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_DEST,
	},
	{
		.number = U300_DMA_PCM_I2S1_TX,
		.name = "PCM I2S1 TX",
		.priority_high = 1,
		.dev_addr =  U300_PCM_I2S1_BASE + 0x14,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_SOURCE,
	},
	{
		.number = U300_DMA_PCM_I2S1_RX,
		.name = "PCM I2S1 RX",
		.priority_high = 1,
		.dev_addr = U300_PCM_I2S1_BASE + 0x10,
		.param.config = COH901318_CX_CFG_CH_DISABLE |
				COH901318_CX_CFG_LCR_DISABLE |
				COH901318_CX_CFG_TC_IRQ_ENABLE |
				COH901318_CX_CFG_BE_IRQ_ENABLE,
		.param.ctrl_lli_chained = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_DISABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_DISABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_DEST,
		.param.ctrl_lli_last = 0 |
				COH901318_CX_CTRL_TC_ENABLE |
				COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
				COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
				COH901318_CX_CTRL_MASTER_MODE_M1RW |
				COH901318_CX_CTRL_TCP_ENABLE |
				COH901318_CX_CTRL_TC_IRQ_ENABLE |
				COH901318_CX_CTRL_HSP_ENABLE |
				COH901318_CX_CTRL_HSS_DISABLE |
				COH901318_CX_CTRL_DDMA_LEGACY |
				COH901318_CX_CTRL_PRDD_DEST,
	},
	{
		.number = U300_DMA_XGAM_CDI,
		.name = "XGAM CDI",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_XGAM_PDI,
		.name = "XGAM PDI",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_SPI_TX,
		.name = "SPI TX",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_SPI_RX,
		.name = "SPI RX",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_0,
		.name = "GENERAL 00",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_1,
		.name = "GENERAL 01",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_2,
		.name = "GENERAL 02",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_3,
		.name = "GENERAL 03",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_4,
		.name = "GENERAL 04",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_5,
		.name = "GENERAL 05",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_6,
		.name = "GENERAL 06",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_7,
		.name = "GENERAL 07",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_8,
		.name = "GENERAL 08",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
#ifdef CONFIG_MACH_U300_BS335
	{
		.number = U300_DMA_UART1_TX,
		.name = "UART1 TX",
		.priority_high = 0,
	},
	{
		.number = U300_DMA_UART1_RX,
		.name = "UART1 RX",
		.priority_high = 0,
	}
#else
	{
		.number = U300_DMA_GENERAL_PURPOSE_9,
		.name = "GENERAL 09",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	},
	{
		.number = U300_DMA_GENERAL_PURPOSE_10,
		.name = "GENERAL 10",
		.priority_high = 0,

		.param.config = flags_memcpy_config,
		.param.ctrl_lli_chained = flags_memcpy_lli_chained,
		.param.ctrl_lli = flags_memcpy_lli,
		.param.ctrl_lli_last = flags_memcpy_lli_last,
	}
#endif
};


static struct coh901318_platform coh901318_platform = {
	.chans_slave = dma_slave_channels,
	.chans_memcpy = dma_memcpy_channels,
	.access_memory_state = coh901318_access_memory_state,
	.chan_conf = chan_config,
	.max_channels = U300_DMA_CHANNELS,
};
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1399 
static struct platform_device wdog_device = {
L
ARM: 5895/2: Alter name of U300 watchdog resource  
Linus Walleij 已提交
1400 
	.name = "coh901327_wdog",
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1401 1402 1403 1404 1405 1406 
	.id = -1,
	.num_resources = ARRAY_SIZE(wdog_resources),
	.resource = wdog_resources,
};

static struct platform_device i2c0_device = {
L
ARM: 5668/2: U300 I2C board setup  
Linus Walleij 已提交
1407 
	.name = "stu300",
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1408 1409 1410 1411 1412 1413 
	.id = 0,
	.num_resources = ARRAY_SIZE(i2c0_resources),
	.resource = i2c0_resources,
};

static struct platform_device i2c1_device = {
L
ARM: 5668/2: U300 I2C board setup  
Linus Walleij 已提交
1414 
	.name = "stu300",
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 
	.id = 1,
	.num_resources = ARRAY_SIZE(i2c1_resources),
	.resource = i2c1_resources,
};

static struct platform_device gpio_device = {
	.name = "u300-gpio",
	.id = -1,
	.num_resources = ARRAY_SIZE(gpio_resources),
	.resource = gpio_resources,
};

static struct platform_device keypad_device = {
	.name = "keypad",
	.id = -1,
	.num_resources = ARRAY_SIZE(keypad_resources),
	.resource = keypad_resources,
};

static struct platform_device rtc_device = {
L
ARM: 5787/1: U300 COH 901 331 fixes  
Linus Walleij 已提交
1435 
	.name = "rtc-coh901331",
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1436 1437 1438 1439 1440 
	.id = -1,
	.num_resources = ARRAY_SIZE(rtc_resources),
	.resource = rtc_resources,
};
L
ARM: platform data to use the FSMC NAND with the U300  
Linus Walleij 已提交
1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 
static struct mtd_partition u300_partitions[] = {
	{
		.name = "bootrecords",
		.offset = 0,
		.size = SZ_128K,
	},
	{
		.name = "free",
		.offset = SZ_128K,
		.size = 8064 * SZ_1K,
	},
	{
		.name = "platform",
		.offset = 8192 * SZ_1K,
		.size = 253952 * SZ_1K,
	},
};

static struct fsmc_nand_platform_data nand_platform_data = {
	.partitions = u300_partitions,
	.nr_partitions = ARRAY_SIZE(u300_partitions),
	.options = NAND_SKIP_BBTSCAN,
	.width = FSMC_NAND_BW8,
};

static struct platform_device nand_device = {
	.name = "fsmc-nand",
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1468 1469 
	.id = -1,
	.resource = fsmc_resources,
L
ARM: platform data to use the FSMC NAND with the U300  
Linus Walleij 已提交
1470 1471 1472 1473 
	.num_resources = ARRAY_SIZE(fsmc_resources),
	.dev = {
		.platform_data = &nand_platform_data,
	},
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1474 1475 1476 1477 1478 1479 1480 1481 1482 
};

static struct platform_device ave_device = {
	.name = "video_enc",
	.id = -1,
	.num_resources = ARRAY_SIZE(ave_resources),
	.resource = ave_resources,
};
L
ARM: 5852/1: Add COH 901 318 DMA driver platform config for U300  
Linus Walleij 已提交
1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 
static struct platform_device dma_device = {
	.name		= "coh901318",
	.id		= -1,
	.resource	= dma_resource,
	.num_resources  = ARRAY_SIZE(dma_resource),
	.dev = {
		.platform_data = &coh901318_platform,
		.coherent_dma_mask = ~0,
	},
};
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1494 1495 1496 1497 1498 
/*
 * Notice that AMBA devices are initialized before platform devices.
 *
 */
static struct platform_device *platform_devs[] __initdata = {
L
ARM: 5852/1: Add COH 901 318 DMA driver platform config for U300  
Linus Walleij 已提交
1499 
	&dma_device,
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1500 1501 1502 1503 1504 
	&i2c0_device,
	&i2c1_device,
	&keypad_device,
	&rtc_device,
	&gpio_device,
L
ARM: platform data to use the FSMC NAND with the U300  
Linus Walleij 已提交
1505 
	&nand_device,
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 
	&wdog_device,
	&ave_device
};


/*
 * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
 * together so some interrupts are connected to the first one and some
 * to the second one.
 */
void __init u300_init_irq(void)
{
	u32 mask[2] = {0, 0};
L
ARM: 6296/1: clock U300 intcon and timer properly  
Linus Walleij 已提交
1519 
	struct clk *clk;
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1520 1521 
	int i;
L
ARM: 6295/1: fix U300 apb_pclk split  
Linus Walleij 已提交
1522 1523 1524 
	/* initialize clocking early, we want to clock the INTCON */
	u300_clock_init();
L
ARM: 6296/1: clock U300 intcon and timer properly  
Linus Walleij 已提交
1525 1526 1527 1528 1529 
	/* Clock the interrupt controller */
	clk = clk_get_sys("intcon", NULL);
	BUG_ON(IS_ERR(clk));
	clk_enable(clk);
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1530 1531 
	for (i = 0; i < NR_IRQS; i++)
		set_bit(i, (unsigned long *) &mask[0]);
L
[ARM] 5594/1: Correct U300 VIC init PM setting  
Linus Walleij 已提交
1532 1533 
	vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
	vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 
}


/*
 * U300 platforms peripheral handling
 */
struct db_chip {
	u16 chipid;
	const char *name;
};

/*
 * This is a list of the Digital Baseband chips used in the U300 platform.
 */
static struct db_chip db_chips[] __initdata = {
	{
		.chipid = 0xb800,
		.name = "DB3000",
	},
	{
		.chipid = 0xc000,
		.name = "DB3100",
	},
	{
		.chipid = 0xc800,
		.name = "DB3150",
	},
	{
		.chipid = 0xd800,
		.name = "DB3200",
	},
	{
		.chipid = 0xe000,
		.name = "DB3250",
	},
	{
		.chipid = 0xe800,
		.name = "DB3210",
	},
	{
		.chipid = 0xf000,
		.name = "DB3350 P1x",
	},
	{
		.chipid = 0xf100,
		.name = "DB3350 P2x",
	},
	{
		.chipid = 0x0000, /* List terminator */
		.name = NULL,
	}
};
L
ARM: 5673/1: U300 fix initsection compile warning  
Linus Walleij 已提交
1587 
static void __init u300_init_check_chip(void)
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 
{

	u16 val;
	struct db_chip *chip;
	const char *chipname;
	const char unknown[] = "UNKNOWN";

	/* Read out and print chip ID */
	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
	/* This is in funky bigendian order... */
	val = (val & 0xFFU) << 8 | (val >> 8);
	chip = db_chips;
	chipname = unknown;

	for ( ; chip->chipid; chip++) {
		if (chip->chipid == (val & 0xFF00U)) {
			chipname = chip->name;
			break;
		}
	}
	printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
	       "(chip ID 0x%04x)\n", chipname, val);

#ifdef CONFIG_MACH_U300_BS330
	if ((val & 0xFF00U) != 0xd800) {
		printk(KERN_ERR "Platform configured for BS330 " \
		       "with DB3200 but %s detected, expect problems!",
		       chipname);
	}
#endif
#ifdef CONFIG_MACH_U300_BS335
	if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
		printk(KERN_ERR "Platform configured for BS365 " \
		       " with DB3350 but %s detected, expect problems!",
		       chipname);
	}
#endif
#ifdef CONFIG_MACH_U300_BS365
	if ((val & 0xFF00U) != 0xe800) {
		printk(KERN_ERR "Platform configured for BS365 " \
		       "with DB3210 but %s detected, expect problems!",
		       chipname);
	}
#endif


}

/*
 * Some devices and their resources require reserved physical memory from
 * the end of the available RAM. This function traverses the list of devices
D
tree-wide: Assorted spelling fixes  
Daniel Mack 已提交
1639 
 * and assigns actual addresses to these.
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 
 */
static void __init u300_assign_physmem(void)
{
	unsigned long curr_start = __pa(high_memory);
	int i, j;

	for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
		for (j = 0; j < platform_devs[i]->num_resources; j++) {
			struct resource *const res =
			  &platform_devs[i]->resource[j];

			if (IORESOURCE_MEM == res->flags &&
				     0 == res->start) {
				res->start  = curr_start;
				res->end   += curr_start;
				curr_start += (res->end - res->start + 1);

				printk(KERN_INFO "core.c: Mapping RAM " \
				       "%#x-%#x to device %s:%s\n",
					res->start, res->end,
				       platform_devs[i]->name, res->name);
			}
		}
	}
}

void __init u300_init_devices(void)
{
	int i;
	u16 val;

	/* Check what platform we run and print some status information */
	u300_init_check_chip();

	/* Set system to run at PLL208, max performance, a known state. */
	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
	val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
	/* Wait for the PLL208 to lock if not locked in yet */
	while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
		 U300_SYSCON_CSR_PLL208_LOCK_IND));
L
ARM: 5667/3: U300 SSP/SPI board setup and test  
Linus Walleij 已提交
1681 1682 
	/* Initialize SPI device with some board specifics */
	u300_spi_init(&pl022_device);
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1683 1684 1685 1686 1687 1688 1689 1690 1691 

	/* Register the AMBA devices in the AMBA bus abstraction layer */
	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
		struct amba_device *d = amba_devs[i];
		amba_device_register(d, &iomem_resource);
	}

	u300_assign_physmem();
L
ARM: 5668/2: U300 I2C board setup  
Linus Walleij 已提交
1692 1693 1694 
	/* Register subdevices on the I2C buses */
	u300_i2c_register_board_devices();
L
ARM: 5667/3: U300 SSP/SPI board setup and test  
Linus Walleij 已提交
1695 1696 1697 
	/* Register subdevices on the SPI bus */
	u300_spi_register_board_devices();
L
[ARM] 5473/1: U300 core machine support  
Linus Walleij 已提交
1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 
	/* Register the platform devices */
	platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));

#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
	/*
	 * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
	 * both subsystems are requesting this mode.
	 * If we not share the Acc SDRAM, this is never the case. Therefore
	 * enable it here from the App side.
	 */
	val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
		U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
	writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
#endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
}

static int core_module_init(void)
{
	/*
	 * This needs to be initialized later: it needs the input framework
	 * to be initialized first.
	 */
	return mmc_init(&mmcsd_device);
}
module_init(core_module_init);