paging_tmpl.h 12.1 KB
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/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * This module enables machines with Intel VT-x extensions to run virtual
 * machines without emulation or binary translation.
 *
 * MMU support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

/*
 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
 * so the code in this file is compiled twice, once per pte size.
 */

#if PTTYPE == 64
	#define pt_element_t u64
	#define guest_walker guest_walker64
	#define FNAME(name) paging##64_##name
	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
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	#define PT_LEVEL_BITS PT64_LEVEL_BITS
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	#ifdef CONFIG_X86_64
	#define PT_MAX_FULL_LEVELS 4
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	#define CMPXCHG cmpxchg
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	#else
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	#define CMPXCHG cmpxchg64
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	#define PT_MAX_FULL_LEVELS 2
	#endif
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#elif PTTYPE == 32
	#define pt_element_t u32
	#define guest_walker guest_walker32
	#define FNAME(name) paging##32_##name
	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
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	#define PT_LEVEL_BITS PT32_LEVEL_BITS
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	#define PT_MAX_FULL_LEVELS 2
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	#define CMPXCHG cmpxchg
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#else
	#error Invalid PTTYPE value
#endif

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#define gpte_to_gfn FNAME(gpte_to_gfn)
#define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)

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/*
 * The guest_walker structure emulates the behavior of the hardware page
 * table walker.
 */
struct guest_walker {
	int level;
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	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
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	pt_element_t ptes[PT_MAX_FULL_LEVELS];
	gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
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	unsigned pt_access;
	unsigned pte_access;
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	gfn_t gfn;
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	u32 error_code;
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};

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static gfn_t gpte_to_gfn(pt_element_t gpte)
{
	return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
}

static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
{
	return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
}

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static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
			 gfn_t table_gfn, unsigned index,
			 pt_element_t orig_pte, pt_element_t new_pte)
{
	pt_element_t ret;
	pt_element_t *table;
	struct page *page;

	page = gfn_to_page(kvm, table_gfn);
	table = kmap_atomic(page, KM_USER0);

	ret = CMPXCHG(&table[index], orig_pte, new_pte);

	kunmap_atomic(table, KM_USER0);

	kvm_release_page_dirty(page);

	return (ret != orig_pte);
}

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static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
{
	unsigned access;

	access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
#if PTTYPE == 64
	if (is_nx(vcpu))
		access &= ~(gpte >> PT64_NX_SHIFT);
#endif
	return access;
}

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/*
 * Fetch a guest pte for a guest virtual address
 */
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static int FNAME(walk_addr)(struct guest_walker *walker,
			    struct kvm_vcpu *vcpu, gva_t addr,
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			    int write_fault, int user_fault, int fetch_fault)
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{
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	pt_element_t pte;
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	gfn_t table_gfn;
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	unsigned index, pt_access, pte_access;
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	gpa_t pte_gpa;
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	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
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walk:
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	walker->level = vcpu->arch.mmu.root_level;
	pte = vcpu->arch.cr3;
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#if PTTYPE == 64
	if (!is_long_mode(vcpu)) {
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		pte = vcpu->arch.pdptrs[(addr >> 30) & 3];
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		if (!is_present_pte(pte))
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			goto not_present;
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		--walker->level;
	}
#endif
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	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
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	       (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
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	pt_access = ACC_ALL;
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	for (;;) {
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		index = PT_INDEX(addr, walker->level);
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		table_gfn = gpte_to_gfn(pte);
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		pte_gpa = gfn_to_gpa(table_gfn);
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		pte_gpa += index * sizeof(pt_element_t);
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		walker->table_gfn[walker->level - 1] = table_gfn;
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		walker->pte_gpa[walker->level - 1] = pte_gpa;
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		pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
			 walker->level - 1, table_gfn);

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		kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
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		if (!is_present_pte(pte))
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			goto not_present;

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		if (write_fault && !is_writeble_pte(pte))
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			if (user_fault || is_write_protection(vcpu))
				goto access_error;

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		if (user_fault && !(pte & PT_USER_MASK))
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			goto access_error;

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#if PTTYPE == 64
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		if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
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			goto access_error;
#endif

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		if (!(pte & PT_ACCESSED_MASK)) {
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			mark_page_dirty(vcpu->kvm, table_gfn);
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			if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
			    index, pte, pte|PT_ACCESSED_MASK))
				goto walk;
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			pte |= PT_ACCESSED_MASK;
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		}
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		pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
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		walker->ptes[walker->level - 1] = pte;

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		if (walker->level == PT_PAGE_TABLE_LEVEL) {
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			walker->gfn = gpte_to_gfn(pte);
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			break;
		}

		if (walker->level == PT_DIRECTORY_LEVEL
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		    && (pte & PT_PAGE_SIZE_MASK)
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		    && (PTTYPE == 64 || is_pse(vcpu))) {
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			walker->gfn = gpte_to_gfn_pde(pte);
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			walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
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			if (PTTYPE == 32 && is_cpuid_PSE36())
				walker->gfn += pse36_gfn_delta(pte);
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			break;
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		}
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		pt_access = pte_access;
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		--walker->level;
	}
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	if (write_fault && !is_dirty_pte(pte)) {
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		bool ret;

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		mark_page_dirty(vcpu->kvm, table_gfn);
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		ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
			    pte|PT_DIRTY_MASK);
		if (ret)
			goto walk;
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		pte |= PT_DIRTY_MASK;
		kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
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		walker->ptes[walker->level - 1] = pte;
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	}

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	walker->pt_access = pt_access;
	walker->pte_access = pte_access;
	pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
		 __FUNCTION__, (u64)pte, pt_access, pte_access);
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	return 1;

not_present:
	walker->error_code = 0;
	goto err;

access_error:
	walker->error_code = PFERR_PRESENT_MASK;

err:
	if (write_fault)
		walker->error_code |= PFERR_WRITE_MASK;
	if (user_fault)
		walker->error_code |= PFERR_USER_MASK;
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	if (fetch_fault)
		walker->error_code |= PFERR_FETCH_MASK;
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	return 0;
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}

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static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
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			      u64 *spte, const void *pte, int bytes,
			      int offset_in_pte)
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{
	pt_element_t gpte;
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	unsigned pte_access;
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	gpte = *(const pt_element_t *)pte;
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	if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
		if (!offset_in_pte && !is_present_pte(gpte))
			set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
		return;
	}
	if (bytes < sizeof(pt_element_t))
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		return;
	pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
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	pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
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	mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
		     gpte & PT_DIRTY_MASK, NULL, gpte_to_gfn(gpte));
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}

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/*
 * Fetch a shadow pte for a specific level in the paging hierarchy.
 */
static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
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			 struct guest_walker *walker,
			 int user_fault, int write_fault, int *ptwrite)
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{
	hpa_t shadow_addr;
	int level;
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	u64 *shadow_ent;
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	unsigned access = walker->pt_access;
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	if (!is_present_pte(walker->ptes[walker->level - 1]))
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		return NULL;
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	shadow_addr = vcpu->arch.mmu.root_hpa;
	level = vcpu->arch.mmu.shadow_root_level;
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	if (level == PT32E_ROOT_LEVEL) {
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		shadow_addr = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
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		shadow_addr &= PT64_BASE_ADDR_MASK;
		--level;
	}
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	for (; ; level--) {
		u32 index = SHADOW_PT_INDEX(addr, level);
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		struct kvm_mmu_page *shadow_page;
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		u64 shadow_pte;
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		int metaphysical;
		gfn_t table_gfn;
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		bool new_page = 0;
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		shadow_ent = ((u64 *)__va(shadow_addr)) + index;
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		if (is_shadow_present_pte(*shadow_ent)) {
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			if (level == PT_PAGE_TABLE_LEVEL)
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				break;
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			shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
			continue;
		}

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		if (level == PT_PAGE_TABLE_LEVEL)
			break;
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		if (level - 1 == PT_PAGE_TABLE_LEVEL
		    && walker->level == PT_DIRECTORY_LEVEL) {
			metaphysical = 1;
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			if (!is_dirty_pte(walker->ptes[level - 1]))
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				access &= ~ACC_WRITE_MASK;
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			table_gfn = gpte_to_gfn(walker->ptes[level - 1]);
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		} else {
			metaphysical = 0;
			table_gfn = walker->table_gfn[level - 2];
		}
		shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
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					       metaphysical, access,
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					       shadow_ent, &new_page);
		if (new_page && !metaphysical) {
			pt_element_t curr_pte;
			kvm_read_guest(vcpu->kvm, walker->pte_gpa[level - 2],
				       &curr_pte, sizeof(curr_pte));
			if (curr_pte != walker->ptes[level - 2])
				return NULL;
		}
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		shadow_addr = __pa(shadow_page->spt);
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		shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
			| PT_WRITABLE_MASK | PT_USER_MASK;
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		*shadow_ent = shadow_pte;
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	}
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	mmu_set_spte(vcpu, shadow_ent, access, walker->pte_access & access,
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		     user_fault, write_fault,
		     walker->ptes[walker->level-1] & PT_DIRTY_MASK,
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		     ptwrite, walker->gfn);
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	return shadow_ent;
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}

/*
 * Page fault handler.  There are several causes for a page fault:
 *   - there is no shadow pte for the guest pte
 *   - write access through a shadow pte marked read only so that we can set
 *     the dirty bit
 *   - write access to a shadow pte marked read only so we can update the page
 *     dirty bitmap, when userspace requests it
 *   - mmio access; in this case we will never install a present shadow pte
 *   - normal guest page fault due to the guest pte marked not present, not
 *     writable, or not executable
 *
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 *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 *           a negative value on error.
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 */
static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
			       u32 error_code)
{
	int write_fault = error_code & PFERR_WRITE_MASK;
	int user_fault = error_code & PFERR_USER_MASK;
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	int fetch_fault = error_code & PFERR_FETCH_MASK;
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	struct guest_walker walker;
	u64 *shadow_pte;
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	int write_pt = 0;
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	int r;
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	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
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	kvm_mmu_audit(vcpu, "pre page fault");
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	r = mmu_topup_memory_caches(vcpu);
	if (r)
		return r;
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	down_read(&current->mm->mmap_sem);
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	/*
	 * Look up the shadow pte for the faulting address.
	 */
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	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
			     fetch_fault);
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	up_read(&current->mm->mmap_sem);
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	/*
	 * The page is not mapped by the guest.  Let the guest handle it.
	 */
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	if (!r) {
		pgprintk("%s: guest page fault\n", __FUNCTION__);
		inject_page_fault(vcpu, addr, walker.error_code);
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		vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
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		return 0;
	}

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	mutex_lock(&vcpu->kvm->lock);
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	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
				  &write_pt);
	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
		 shadow_pte, *shadow_pte, write_pt);
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	if (!write_pt)
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		vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
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	/*
	 * mmio: emulate if accessible, otherwise its a guest fault.
	 */
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	if (shadow_pte && is_io_pte(*shadow_pte)) {
		mutex_unlock(&vcpu->kvm->lock);
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		return 1;
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	}
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	++vcpu->stat.pf_fixed;
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	kvm_mmu_audit(vcpu, "post page fault (fixed)");
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	mutex_unlock(&vcpu->kvm->lock);
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	return write_pt;
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}

static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
{
	struct guest_walker walker;
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	gpa_t gpa = UNMAPPED_GVA;
	int r;
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	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
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	if (r) {
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		gpa = gfn_to_gpa(walker.gfn);
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		gpa |= vaddr & ~PAGE_MASK;
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	}

	return gpa;
}

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static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
				 struct kvm_mmu_page *sp)
{
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	int i, offset = 0;
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	pt_element_t *gpt;
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	struct page *page;
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	if (sp->role.metaphysical
	    || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
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		nonpaging_prefetch_page(vcpu, sp);
		return;
	}

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	if (PTTYPE == 32)
		offset = sp->role.quadrant << PT64_LEVEL_BITS;
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	page = gfn_to_page(vcpu->kvm, sp->gfn);
	gpt = kmap_atomic(page, KM_USER0);
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	for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
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		if (is_present_pte(gpt[offset + i]))
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			sp->spt[i] = shadow_trap_nonpresent_pte;
		else
			sp->spt[i] = shadow_notrap_nonpresent_pte;
	kunmap_atomic(gpt, KM_USER0);
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	kvm_release_page_clean(page);
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}

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#undef pt_element_t
#undef guest_walker
#undef FNAME
#undef PT_BASE_ADDR_MASK
#undef PT_INDEX
#undef SHADOW_PT_INDEX
#undef PT_LEVEL_MASK
#undef PT_DIR_BASE_ADDR_MASK
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#undef PT_LEVEL_BITS
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#undef PT_MAX_FULL_LEVELS
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#undef gpte_to_gfn
#undef gpte_to_gfn_pde
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#undef CMPXCHG