core.c 13.7 KB
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/*
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 * SuperH Pin Function Controller support.
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 *
 * Copyright (C) 2008 Magnus Damm
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 * Copyright (C) 2009 - 2012 Paul Mundt
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 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
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#define DRV_NAME "sh-pfc"
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
#include <linux/module.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "core.h"

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static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
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{
	struct resource *res;
	int k;

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	if (pdev->num_resources == 0) {
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		pfc->num_windows = 0;
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		return 0;
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	}
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	pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
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				   sizeof(*pfc->window), GFP_NOWAIT);
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	if (!pfc->window)
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		return -ENOMEM;
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	pfc->num_windows = pdev->num_resources;
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	for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
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		WARN_ON(resource_type(res) != IORESOURCE_MEM);
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		pfc->window[k].phys = res->start;
		pfc->window[k].size = resource_size(res);
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		pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
							   resource_size(res));
		if (!pfc->window[k].virt)
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			return -ENOMEM;
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	}

	return 0;
}

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static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
					 unsigned long address)
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{
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	struct sh_pfc_window *window;
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	int k;

	/* scan through physical windows and convert address */
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	for (k = 0; k < pfc->num_windows; k++) {
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		window = pfc->window + k;
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		if (address < window->phys)
			continue;

		if (address >= (window->phys + window->size))
			continue;

		return window->virt + (address - window->phys);
	}

	/* no windows defined, register must be 1:1 mapped virt:phys */
	return (void __iomem *)address;
}
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static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
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{
	if (enum_id < r->begin)
		return 0;

	if (enum_id > r->end)
		return 0;

	return 1;
}

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static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
					 unsigned long reg_width)
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{
	switch (reg_width) {
	case 8:
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		return ioread8(mapped_reg);
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	case 16:
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		return ioread16(mapped_reg);
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	case 32:
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		return ioread32(mapped_reg);
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	}

	BUG();
	return 0;
}

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static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
				 unsigned long reg_width, unsigned long data)
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{
	switch (reg_width) {
	case 8:
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		iowrite8(data, mapped_reg);
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		return;
	case 16:
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		iowrite16(data, mapped_reg);
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		return;
	case 32:
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		iowrite32(data, mapped_reg);
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		return;
	}

	BUG();
}

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int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
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{
	unsigned long pos;

	pos = dr->reg_width - (in_pos + 1);

	pr_debug("read_bit: addr = %lx, pos = %ld, "
		 "r_width = %ld\n", dr->reg, pos, dr->reg_width);

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	return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
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}

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void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
		      unsigned long value)
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{
	unsigned long pos;

	pos = dr->reg_width - (in_pos + 1);

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	pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
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		 "r_width = %ld\n",
		 dr->reg, !!value, pos, dr->reg_width);
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	if (value)
		set_bit(pos, &dr->reg_shadow);
	else
		clear_bit(pos, &dr->reg_shadow);

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	sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
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}

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static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
				     struct pinmux_cfg_reg *crp,
				     unsigned long in_pos,
				     void __iomem **mapped_regp,
				     unsigned long *maskp,
				     unsigned long *posp)
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{
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	int k;

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	*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
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	if (crp->field_width) {
		*maskp = (1 << crp->field_width) - 1;
		*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
	} else {
		*maskp = (1 << crp->var_field_width[in_pos]) - 1;
		*posp = crp->reg_width;
		for (k = 0; k <= in_pos; k++)
			*posp -= crp->var_field_width[k];
	}
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}

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static int sh_pfc_read_config_reg(struct sh_pfc *pfc,
				  struct pinmux_cfg_reg *crp,
				  unsigned long field)
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{
	void __iomem *mapped_reg;
	unsigned long mask, pos;

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	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
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	pr_debug("read_reg: addr = %lx, field = %ld, "
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		 "r_width = %ld, f_width = %ld\n",
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		 crp->reg, field, crp->reg_width, crp->field_width);
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	return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
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}

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static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
				    struct pinmux_cfg_reg *crp,
				    unsigned long field, unsigned long value)
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{
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	void __iomem *mapped_reg;
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	unsigned long mask, pos, data;
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	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
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	pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
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		 "r_width = %ld, f_width = %ld\n",
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		 crp->reg, value, field, crp->reg_width, crp->field_width);
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	mask = ~(mask << pos);
	value = value << pos;
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	data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
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	data &= mask;
	data |= value;

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	if (pfc->info->unlock_reg)
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		sh_pfc_write_raw_reg(
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			sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
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			~data);
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	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
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}

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static void sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
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{
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	struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
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	struct pinmux_data_reg *data_reg;
	int k, n;

	k = 0;
	while (1) {
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		data_reg = pfc->info->data_regs + k;
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		if (!data_reg->reg_width)
			break;

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		data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);
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		for (n = 0; n < data_reg->reg_width; n++) {
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			if (data_reg->enum_ids[n] == gpiop->enum_id) {
				gpiop->flags &= ~PINMUX_FLAG_DREG;
				gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
				gpiop->flags &= ~PINMUX_FLAG_DBIT;
				gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
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				return;
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			}
		}
		k++;
	}

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	BUG();
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}

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static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
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{
	struct pinmux_data_reg *drp;
	int k;

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	for (k = 0; k < pfc->info->nr_pins; k++) {
		if (pfc->info->pins[k].enum_id == 0)
			continue;

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		sh_pfc_setup_data_reg(pfc, k);
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	}
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	k = 0;
	while (1) {
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		drp = pfc->info->data_regs + k;
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		if (!drp->reg_width)
			break;

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		drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
						      drp->reg_width);
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		k++;
	}
}

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void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
			 struct pinmux_data_reg **drp, int *bitp)
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{
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	struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio];
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	int k, n;

	k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
	n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
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	*drp = pfc->info->data_regs + k;
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	*bitp = n;
}

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static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
				 struct pinmux_cfg_reg **crp, int *fieldp,
				 int *valuep, unsigned long **cntp)
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{
	struct pinmux_cfg_reg *config_reg;
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	unsigned long r_width, f_width, curr_width, ncomb;
	int k, m, n, pos, bit_pos;
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	k = 0;
	while (1) {
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		config_reg = pfc->info->cfg_regs + k;
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		r_width = config_reg->reg_width;
		f_width = config_reg->field_width;

		if (!r_width)
			break;
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		pos = 0;
		m = 0;
		for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
			if (f_width)
				curr_width = f_width;
			else
				curr_width = config_reg->var_field_width[m];

			ncomb = 1 << curr_width;
			for (n = 0; n < ncomb; n++) {
				if (config_reg->enum_ids[pos + n] == enum_id) {
					*crp = config_reg;
					*fieldp = m;
					*valuep = n;
					*cntp = &config_reg->cnt[m];
					return 0;
				}
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			}
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			pos += ncomb;
			m++;
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		}
		k++;
	}

	return -1;
}

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static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
			      pinmux_enum_t *enum_idp)
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{
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	pinmux_enum_t *data = pfc->info->gpio_data;
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	int k;

	if (pos) {
		*enum_idp = data[pos + 1];
		return pos + 1;
	}

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	for (k = 0; k < pfc->info->gpio_data_size; k++) {
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		if (data[k] == mark) {
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			*enum_idp = data[k + 1];
			return k + 1;
		}
	}

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	pr_err("cannot locate data/mark enum_id for mark %d\n", mark);
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	return -1;
}

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int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type,
		      int cfg_mode)
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{
	struct pinmux_cfg_reg *cr = NULL;
	pinmux_enum_t enum_id;
	struct pinmux_range *range;
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	int in_range, pos, field, value;
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	unsigned long *cntp;

	switch (pinmux_type) {

	case PINMUX_TYPE_FUNCTION:
		range = NULL;
		break;

	case PINMUX_TYPE_OUTPUT:
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		range = &pfc->info->output;
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		break;

	case PINMUX_TYPE_INPUT:
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		range = &pfc->info->input;
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		break;

	case PINMUX_TYPE_INPUT_PULLUP:
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		range = &pfc->info->input_pu;
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		break;

	case PINMUX_TYPE_INPUT_PULLDOWN:
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		range = &pfc->info->input_pd;
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		break;

	default:
		goto out_err;
	}

	pos = 0;
	enum_id = 0;
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	field = 0;
	value = 0;
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	while (1) {
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		pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
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		if (pos <= 0)
			goto out_err;

		if (!enum_id)
			break;

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		/* first check if this is a function enum */
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		in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
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		if (!in_range) {
			/* not a function enum */
			if (range) {
				/*
				 * other range exists, so this pin is
				 * a regular GPIO pin that now is being
				 * bound to a specific direction.
				 *
				 * for this case we only allow function enums
				 * and the enums that match the other range.
				 */
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				in_range = sh_pfc_enum_in_range(enum_id, range);
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				/*
				 * special case pass through for fixed
				 * input-only or output-only pins without
				 * function enum register association.
				 */
				if (in_range && enum_id == range->force)
					continue;
			} else {
				/*
				 * no other range exists, so this pin
				 * must then be of the function type.
				 *
				 * allow function type pins to select
				 * any combination of function/in/out
				 * in their MARK lists.
				 */
				in_range = 1;
			}
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		}

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		if (!in_range)
			continue;

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		if (sh_pfc_get_config_reg(pfc, enum_id, &cr,
					  &field, &value, &cntp) != 0)
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			goto out_err;

		switch (cfg_mode) {
		case GPIO_CFG_DRYRUN:
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			if (!*cntp ||
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			    (sh_pfc_read_config_reg(pfc, cr, field) != value))
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				continue;
			break;

		case GPIO_CFG_REQ:
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			sh_pfc_write_config_reg(pfc, cr, field, value);
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			*cntp = *cntp + 1;
			break;

		case GPIO_CFG_FREE:
			*cntp = *cntp - 1;
			break;
		}
	}

	return 0;
 out_err:
	return -1;
}

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static int sh_pfc_probe(struct platform_device *pdev)
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{
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	struct sh_pfc_soc_info *info;
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	struct sh_pfc *pfc;
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	int ret;
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	/*
	 * Ensure that the type encoding fits
	 */
	BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));

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	info = pdev->id_entry->driver_data
	      ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
	if (info == NULL)
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		return -ENODEV;
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	pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
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	if (pfc == NULL)
		return -ENOMEM;
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	pfc->info = info;
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	pfc->dev = &pdev->dev;

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	ret = sh_pfc_ioremap(pfc, pdev);
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	if (unlikely(ret < 0))
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		return ret;

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	spin_lock_init(&pfc->lock);
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	pinctrl_provide_dummies();
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	sh_pfc_setup_data_regs(pfc);
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	/*
	 * Initialize pinctrl bindings first
	 */
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	ret = sh_pfc_register_pinctrl(pfc);
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	if (unlikely(ret != 0))
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		return ret;
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#ifdef CONFIG_GPIO_SH_PFC
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	/*
	 * Then the GPIO chip
	 */
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	ret = sh_pfc_register_gpiochip(pfc);
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	if (unlikely(ret != 0)) {
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		/*
		 * If the GPIO chip fails to come up we still leave the
		 * PFC state as it is, given that there are already
		 * extant users of it that have succeeded by this point.
		 */
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		pr_notice("failed to init GPIO chip, ignoring...\n");
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	}
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#endif
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	platform_set_drvdata(pdev, pfc);

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	pr_info("%s support registered\n", info->name);
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	return 0;
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}
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static int sh_pfc_remove(struct platform_device *pdev)
{
	struct sh_pfc *pfc = platform_get_drvdata(pdev);

#ifdef CONFIG_GPIO_SH_PFC
	sh_pfc_unregister_gpiochip(pfc);
#endif
	sh_pfc_unregister_pinctrl(pfc);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

static const struct platform_device_id sh_pfc_id_table[] = {
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#ifdef CONFIG_PINCTRL_PFC_R8A7740
	{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
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#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7779
	{ "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
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#endif
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#ifdef CONFIG_PINCTRL_PFC_SH7203
	{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
#endif
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#ifdef CONFIG_PINCTRL_PFC_SH7264
	{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
#endif
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#ifdef CONFIG_PINCTRL_PFC_SH7269
	{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
#endif
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#ifdef CONFIG_PINCTRL_PFC_SH7372
	{ "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
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#endif
#ifdef CONFIG_PINCTRL_PFC_SH73A0
	{ "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
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#endif
#ifdef CONFIG_PINCTRL_PFC_SH7720
	{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
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#endif
#ifdef CONFIG_PINCTRL_PFC_SH7722
	{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
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#endif
#ifdef CONFIG_PINCTRL_PFC_SH7723
	{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
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#endif
#ifdef CONFIG_PINCTRL_PFC_SH7724
	{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
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#endif
#ifdef CONFIG_PINCTRL_PFC_SH7734
	{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
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#endif
#ifdef CONFIG_PINCTRL_PFC_SH7757
	{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
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#endif
#ifdef CONFIG_PINCTRL_PFC_SH7785
	{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
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#endif
#ifdef CONFIG_PINCTRL_PFC_SH7786
	{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
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#endif
#ifdef CONFIG_PINCTRL_PFC_SHX3
	{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
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#endif
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	{ "sh-pfc", 0 },
	{ },
};
MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);

static struct platform_driver sh_pfc_driver = {
	.probe		= sh_pfc_probe,
	.remove		= sh_pfc_remove,
	.id_table	= sh_pfc_id_table,
	.driver		= {
		.name	= DRV_NAME,
		.owner	= THIS_MODULE,
	},
};

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static int __init sh_pfc_init(void)
{
	return platform_driver_register(&sh_pfc_driver);
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}
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postcore_initcall(sh_pfc_init);
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static void __exit sh_pfc_exit(void)
{
	platform_driver_unregister(&sh_pfc_driver);
}
module_exit(sh_pfc_exit);

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MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
MODULE_LICENSE("GPL v2");