radeon_device.c 39.2 KB
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/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include <linux/console.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/radeon_drm.h>
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#include <linux/vgaarb.h>
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#include <linux/vga_switcheroo.h>
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#include <linux/efi.h>
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#include "radeon_reg.h"
#include "radeon.h"
#include "atom.h"

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static const char radeon_family_name[][16] = {
	"R100",
	"RV100",
	"RS100",
	"RV200",
	"RS200",
	"R200",
	"RV250",
	"RS300",
	"RV280",
	"R300",
	"R350",
	"RV350",
	"RV380",
	"R420",
	"R423",
	"RV410",
	"RS400",
	"RS480",
	"RS600",
	"RS690",
	"RS740",
	"RV515",
	"R520",
	"RV530",
	"RV560",
	"RV570",
	"R580",
	"R600",
	"RV610",
	"RV630",
	"RV670",
	"RV620",
	"RV635",
	"RS780",
	"RS880",
	"RV770",
	"RV730",
	"RV710",
	"RV740",
	"CEDAR",
	"REDWOOD",
	"JUNIPER",
	"CYPRESS",
	"HEMLOCK",
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	"PALM",
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	"SUMO",
	"SUMO2",
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	"BARTS",
	"TURKS",
	"CAICOS",
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	"CAYMAN",
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	"ARUBA",
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	"TAHITI",
	"PITCAIRN",
	"VERDE",
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	"OLAND",
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	"HAINAN",
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	"LAST",
};

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/**
 * radeon_program_register_sequence - program an array of registers.
 *
 * @rdev: radeon_device pointer
 * @registers: pointer to the register array
 * @array_size: size of the register array
 *
 * Programs an array or registers with and and or masks.
 * This is a helper for setting golden registers.
 */
void radeon_program_register_sequence(struct radeon_device *rdev,
				      const u32 *registers,
				      const u32 array_size)
{
	u32 tmp, reg, and_mask, or_mask;
	int i;

	if (array_size % 3)
		return;

	for (i = 0; i < array_size; i +=3) {
		reg = registers[i + 0];
		and_mask = registers[i + 1];
		or_mask = registers[i + 2];

		if (and_mask == 0xffffffff) {
			tmp = or_mask;
		} else {
			tmp = RREG32(reg);
			tmp &= ~and_mask;
			tmp |= or_mask;
		}
		WREG32(reg, tmp);
	}
}

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/**
 * radeon_surface_init - Clear GPU surface registers.
 *
 * @rdev: radeon_device pointer
 *
 * Clear GPU surface registers (r1xx-r5xx).
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 */
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void radeon_surface_init(struct radeon_device *rdev)
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{
	/* FIXME: check this out */
	if (rdev->family < CHIP_R600) {
		int i;

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		for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
			if (rdev->surface_regs[i].bo)
				radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
			else
				radeon_clear_surface_reg(rdev, i);
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		}
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		/* enable surfaces */
		WREG32(RADEON_SURFACE_CNTL, 0);
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	}
}

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/*
 * GPU scratch registers helpers function.
 */
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/**
 * radeon_scratch_init - Init scratch register driver information.
 *
 * @rdev: radeon_device pointer
 *
 * Init CP scratch register driver information (r1xx-r5xx)
 */
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void radeon_scratch_init(struct radeon_device *rdev)
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{
	int i;

	/* FIXME: check this out */
	if (rdev->family < CHIP_R300) {
		rdev->scratch.num_reg = 5;
	} else {
		rdev->scratch.num_reg = 7;
	}
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	rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
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	for (i = 0; i < rdev->scratch.num_reg; i++) {
		rdev->scratch.free[i] = true;
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		rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
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	}
}

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/**
 * radeon_scratch_get - Allocate a scratch register
 *
 * @rdev: radeon_device pointer
 * @reg: scratch register mmio offset
 *
 * Allocate a CP scratch register for use by the driver (all asics).
 * Returns 0 on success or -EINVAL on failure.
 */
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int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
{
	int i;

	for (i = 0; i < rdev->scratch.num_reg; i++) {
		if (rdev->scratch.free[i]) {
			rdev->scratch.free[i] = false;
			*reg = rdev->scratch.reg[i];
			return 0;
		}
	}
	return -EINVAL;
}

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/**
 * radeon_scratch_free - Free a scratch register
 *
 * @rdev: radeon_device pointer
 * @reg: scratch register mmio offset
 *
 * Free a CP scratch register allocated for use by the driver (all asics)
 */
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void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
{
	int i;

	for (i = 0; i < rdev->scratch.num_reg; i++) {
		if (rdev->scratch.reg[i] == reg) {
			rdev->scratch.free[i] = true;
			return;
		}
	}
}

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/*
 * radeon_wb_*()
 * Writeback is the the method by which the the GPU updates special pages
 * in memory with the status of certain GPU events (fences, ring pointers,
 * etc.).
 */

/**
 * radeon_wb_disable - Disable Writeback
 *
 * @rdev: radeon_device pointer
 *
 * Disables Writeback (all asics).  Used for suspend.
 */
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void radeon_wb_disable(struct radeon_device *rdev)
{
	int r;

	if (rdev->wb.wb_obj) {
		r = radeon_bo_reserve(rdev->wb.wb_obj, false);
		if (unlikely(r != 0))
			return;
		radeon_bo_kunmap(rdev->wb.wb_obj);
		radeon_bo_unpin(rdev->wb.wb_obj);
		radeon_bo_unreserve(rdev->wb.wb_obj);
	}
	rdev->wb.enabled = false;
}

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/**
 * radeon_wb_fini - Disable Writeback and free memory
 *
 * @rdev: radeon_device pointer
 *
 * Disables Writeback and frees the Writeback memory (all asics).
 * Used at driver shutdown.
 */
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void radeon_wb_fini(struct radeon_device *rdev)
{
	radeon_wb_disable(rdev);
	if (rdev->wb.wb_obj) {
		radeon_bo_unref(&rdev->wb.wb_obj);
		rdev->wb.wb = NULL;
		rdev->wb.wb_obj = NULL;
	}
}

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/**
 * radeon_wb_init- Init Writeback driver info and allocate memory
 *
 * @rdev: radeon_device pointer
 *
 * Disables Writeback and frees the Writeback memory (all asics).
 * Used at driver startup.
 * Returns 0 on success or an -error on failure.
 */
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int radeon_wb_init(struct radeon_device *rdev)
{
	int r;

	if (rdev->wb.wb_obj == NULL) {
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		r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
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				     RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
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		if (r) {
			dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
			return r;
		}
	}
	r = radeon_bo_reserve(rdev->wb.wb_obj, false);
	if (unlikely(r != 0)) {
		radeon_wb_fini(rdev);
		return r;
	}
	r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
			  &rdev->wb.gpu_addr);
	if (r) {
		radeon_bo_unreserve(rdev->wb.wb_obj);
		dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
		radeon_wb_fini(rdev);
		return r;
	}
	r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
	radeon_bo_unreserve(rdev->wb.wb_obj);
	if (r) {
		dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
		radeon_wb_fini(rdev);
		return r;
	}

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	/* clear wb memory */
	memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
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	/* disable event_write fences */
	rdev->wb.use_event = false;
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	/* disabled via module param */
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	if (radeon_no_wb == 1) {
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		rdev->wb.enabled = false;
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	} else {
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		if (rdev->flags & RADEON_IS_AGP) {
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			/* often unreliable on AGP */
			rdev->wb.enabled = false;
		} else if (rdev->family < CHIP_R300) {
			/* often unreliable on pre-r300 */
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			rdev->wb.enabled = false;
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		} else {
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			rdev->wb.enabled = true;
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			/* event_write fences are only available on r600+ */
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			if (rdev->family >= CHIP_R600) {
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				rdev->wb.use_event = true;
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			}
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		}
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	}
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	/* always use writeback/events on NI, APUs */
	if (rdev->family >= CHIP_PALM) {
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		rdev->wb.enabled = true;
		rdev->wb.use_event = true;
	}
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	dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");

	return 0;
}

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/**
 * radeon_vram_location - try to find VRAM location
 * @rdev: radeon device structure holding all necessary informations
 * @mc: memory controller structure holding memory informations
 * @base: base address at which to put VRAM
 *
 * Function will place try to place VRAM at base address provided
 * as parameter (which is so far either PCI aperture address or
 * for IGP TOM base address).
 *
 * If there is not enough space to fit the unvisible VRAM in the 32bits
 * address space then we limit the VRAM size to the aperture.
 *
 * If we are using AGP and if the AGP aperture doesn't allow us to have
 * room for all the VRAM than we restrict the VRAM to the PCI aperture
 * size and print a warning.
 *
 * This function will never fails, worst case are limiting VRAM.
 *
 * Note: GTT start, end, size should be initialized before calling this
 * function on AGP platform.
 *
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 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
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 * this shouldn't be a problem as we are using the PCI aperture as a reference.
 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 * not IGP.
 *
 * Note: we use mc_vram_size as on some board we need to program the mc to
 * cover the whole aperture even if VRAM size is inferior to aperture size
 * Novell bug 204882 + along with lots of ubuntu ones
 *
 * Note: when limiting vram it's safe to overwritte real_vram_size because
 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 * ones)
 *
 * Note: IGP TOM addr should be the same as the aperture addr, we don't
 * explicitly check for that thought.
 *
 * FIXME: when reducing VRAM size align new size on power of 2.
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 */
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void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
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{
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	uint64_t limit = (uint64_t)radeon_vram_limit << 20;

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	mc->vram_start = base;
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	if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
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		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
		mc->real_vram_size = mc->aper_size;
		mc->mc_vram_size = mc->aper_size;
	}
	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
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	if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
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		dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
		mc->real_vram_size = mc->aper_size;
		mc->mc_vram_size = mc->aper_size;
	}
	mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
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	if (limit && limit < mc->real_vram_size)
		mc->real_vram_size = limit;
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	dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
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			mc->mc_vram_size >> 20, mc->vram_start,
			mc->vram_end, mc->real_vram_size >> 20);
}
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/**
 * radeon_gtt_location - try to find GTT location
 * @rdev: radeon device structure holding all necessary informations
 * @mc: memory controller structure holding memory informations
 *
 * Function will place try to place GTT before or after VRAM.
 *
 * If GTT size is bigger than space left then we ajust GTT size.
 * Thus function will never fails.
 *
 * FIXME: when reducing GTT size align new size on power of 2.
 */
void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
{
	u64 size_af, size_bf;

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	size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
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	size_bf = mc->vram_start & ~mc->gtt_base_align;
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	if (size_bf > size_af) {
		if (mc->gtt_size > size_bf) {
			dev_warn(rdev->dev, "limiting GTT\n");
			mc->gtt_size = size_bf;
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		}
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		mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
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	} else {
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		if (mc->gtt_size > size_af) {
			dev_warn(rdev->dev, "limiting GTT\n");
			mc->gtt_size = size_af;
		}
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		mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
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	}
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	mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
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	dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
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			mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
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}

/*
 * GPU helpers function.
 */
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/**
 * radeon_card_posted - check if the hw has already been initialized
 *
 * @rdev: radeon_device pointer
 *
 * Check if the asic has been initialized (all asics).
 * Used at driver startup.
 * Returns true if initialized or false if not.
 */
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bool radeon_card_posted(struct radeon_device *rdev)
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{
	uint32_t reg;

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	if (efi_enabled(EFI_BOOT) &&
	    rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE)
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		return false;

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	/* first check CRTCs */
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	if (ASIC_IS_DCE4(rdev)) {
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		reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
			RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
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			if (rdev->num_crtc >= 4) {
				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
			}
			if (rdev->num_crtc >= 6) {
				reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
					RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
			}
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		if (reg & EVERGREEN_CRTC_MASTER_EN)
			return true;
	} else if (ASIC_IS_AVIVO(rdev)) {
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		reg = RREG32(AVIVO_D1CRTC_CONTROL) |
		      RREG32(AVIVO_D2CRTC_CONTROL);
		if (reg & AVIVO_CRTC_EN) {
			return true;
		}
	} else {
		reg = RREG32(RADEON_CRTC_GEN_CNTL) |
		      RREG32(RADEON_CRTC2_GEN_CNTL);
		if (reg & RADEON_CRTC_EN) {
			return true;
		}
	}

	/* then check MEM_SIZE, in case the crtcs are off */
	if (rdev->family >= CHIP_R600)
		reg = RREG32(R600_CONFIG_MEMSIZE);
	else
		reg = RREG32(RADEON_CONFIG_MEMSIZE);

	if (reg)
		return true;

	return false;

}

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/**
 * radeon_update_bandwidth_info - update display bandwidth params
 *
 * @rdev: radeon_device pointer
 *
 * Used when sclk/mclk are switched or display modes are set.
 * params are used to calculate display watermarks (all asics)
 */
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void radeon_update_bandwidth_info(struct radeon_device *rdev)
{
	fixed20_12 a;
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	u32 sclk = rdev->pm.current_sclk;
	u32 mclk = rdev->pm.current_mclk;
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	/* sclk/mclk in Mhz */
	a.full = dfixed_const(100);
	rdev->pm.sclk.full = dfixed_const(sclk);
	rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
	rdev->pm.mclk.full = dfixed_const(mclk);
	rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
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	if (rdev->flags & RADEON_IS_IGP) {
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		a.full = dfixed_const(16);
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		/* core_bandwidth = sclk(Mhz) * 16 */
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		rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
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	}
}

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/**
 * radeon_boot_test_post_card - check and possibly initialize the hw
 *
 * @rdev: radeon_device pointer
 *
 * Check if the asic is initialized and if not, attempt to initialize
 * it (all asics).
 * Returns true if initialized or false if not.
 */
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bool radeon_boot_test_post_card(struct radeon_device *rdev)
{
	if (radeon_card_posted(rdev))
		return true;

	if (rdev->bios) {
		DRM_INFO("GPU not posted. posting now...\n");
		if (rdev->is_atom_bios)
			atom_asic_init(rdev->mode_info.atom_context);
		else
			radeon_combios_asic_init(rdev->ddev);
		return true;
	} else {
		dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
		return false;
	}
}

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/**
 * radeon_dummy_page_init - init dummy page used by the driver
 *
 * @rdev: radeon_device pointer
 *
 * Allocate the dummy page used by the driver (all asics).
 * This dummy page is used by the driver as a filler for gart entries
 * when pages are taken out of the GART
 * Returns 0 on sucess, -ENOMEM on failure.
 */
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int radeon_dummy_page_init(struct radeon_device *rdev)
{
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	if (rdev->dummy_page.page)
		return 0;
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	rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
	if (rdev->dummy_page.page == NULL)
		return -ENOMEM;
	rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
					0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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	if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
		dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
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		__free_page(rdev->dummy_page.page);
		rdev->dummy_page.page = NULL;
		return -ENOMEM;
	}
	return 0;
}

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/**
 * radeon_dummy_page_fini - free dummy page used by the driver
 *
 * @rdev: radeon_device pointer
 *
 * Frees the dummy page used by the driver (all asics).
 */
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void radeon_dummy_page_fini(struct radeon_device *rdev)
{
	if (rdev->dummy_page.page == NULL)
		return;
	pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
			PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
	__free_page(rdev->dummy_page.page);
	rdev->dummy_page.page = NULL;
}

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/* ATOM accessor methods */
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/*
 * ATOM is an interpreted byte code stored in tables in the vbios.  The
 * driver registers callbacks to access registers and the interpreter
 * in the driver parses the tables and executes then to program specific
 * actions (set display modes, asic init, etc.).  See radeon_atombios.c,
 * atombios.h, and atom.c
 */

/**
 * cail_pll_read - read PLL register
 *
 * @info: atom card_info pointer
 * @reg: PLL register offset
 *
 * Provides a PLL register accessor for the atom interpreter (r4xx+).
 * Returns the value of the PLL register.
 */
634 635 636 637 638 639 640 641 642
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
{
	struct radeon_device *rdev = info->dev->dev_private;
	uint32_t r;

	r = rdev->pll_rreg(rdev, reg);
	return r;
}

643 644 645 646 647 648 649 650 651
/**
 * cail_pll_write - write PLL register
 *
 * @info: atom card_info pointer
 * @reg: PLL register offset
 * @val: value to write to the pll register
 *
 * Provides a PLL register accessor for the atom interpreter (r4xx+).
 */
652 653 654 655 656 657 658
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
{
	struct radeon_device *rdev = info->dev->dev_private;

	rdev->pll_wreg(rdev, reg, val);
}

659 660 661 662 663 664 665 666 667
/**
 * cail_mc_read - read MC (Memory Controller) register
 *
 * @info: atom card_info pointer
 * @reg: MC register offset
 *
 * Provides an MC register accessor for the atom interpreter (r4xx+).
 * Returns the value of the MC register.
 */
668 669 670 671 672 673 674 675 676
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
{
	struct radeon_device *rdev = info->dev->dev_private;
	uint32_t r;

	r = rdev->mc_rreg(rdev, reg);
	return r;
}

677 678 679 680 681 682 683 684 685
/**
 * cail_mc_write - write MC (Memory Controller) register
 *
 * @info: atom card_info pointer
 * @reg: MC register offset
 * @val: value to write to the pll register
 *
 * Provides a MC register accessor for the atom interpreter (r4xx+).
 */
686 687 688 689 690 691 692
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
{
	struct radeon_device *rdev = info->dev->dev_private;

	rdev->mc_wreg(rdev, reg, val);
}

693 694 695 696 697 698 699 700 701
/**
 * cail_reg_write - write MMIO register
 *
 * @info: atom card_info pointer
 * @reg: MMIO register offset
 * @val: value to write to the pll register
 *
 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 */
702 703 704 705 706 707 708
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
{
	struct radeon_device *rdev = info->dev->dev_private;

	WREG32(reg*4, val);
}

709 710 711 712 713 714 715 716 717
/**
 * cail_reg_read - read MMIO register
 *
 * @info: atom card_info pointer
 * @reg: MMIO register offset
 *
 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 * Returns the value of the MMIO register.
 */
718 719 720 721 722 723 724 725 726
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
{
	struct radeon_device *rdev = info->dev->dev_private;
	uint32_t r;

	r = RREG32(reg*4);
	return r;
}

727 728 729 730 731 732 733 734 735
/**
 * cail_ioreg_write - write IO register
 *
 * @info: atom card_info pointer
 * @reg: IO register offset
 * @val: value to write to the pll register
 *
 * Provides a IO register accessor for the atom interpreter (r4xx+).
 */
736 737 738 739 740 741 742
static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
{
	struct radeon_device *rdev = info->dev->dev_private;

	WREG32_IO(reg*4, val);
}

743 744 745 746 747 748 749 750 751
/**
 * cail_ioreg_read - read IO register
 *
 * @info: atom card_info pointer
 * @reg: IO register offset
 *
 * Provides an IO register accessor for the atom interpreter (r4xx+).
 * Returns the value of the IO register.
 */
752 753 754 755 756 757 758 759 760
static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
{
	struct radeon_device *rdev = info->dev->dev_private;
	uint32_t r;

	r = RREG32_IO(reg*4);
	return r;
}

761 762 763 764 765 766 767 768 769 770
/**
 * radeon_atombios_init - init the driver info and callbacks for atombios
 *
 * @rdev: radeon_device pointer
 *
 * Initializes the driver info and register access callbacks for the
 * ATOM interpreter (r4xx+).
 * Returns 0 on sucess, -ENOMEM on failure.
 * Called at driver startup.
 */
771 772
int radeon_atombios_init(struct radeon_device *rdev)
{
773 774 775 776 777 778 779 780 781 782
	struct card_info *atom_card_info =
	    kzalloc(sizeof(struct card_info), GFP_KERNEL);

	if (!atom_card_info)
		return -ENOMEM;

	rdev->mode_info.atom_card_info = atom_card_info;
	atom_card_info->dev = rdev->ddev;
	atom_card_info->reg_read = cail_reg_read;
	atom_card_info->reg_write = cail_reg_write;
783 784 785 786 787 788 789 790 791
	/* needed for iio ops */
	if (rdev->rio_mem) {
		atom_card_info->ioreg_read = cail_ioreg_read;
		atom_card_info->ioreg_write = cail_ioreg_write;
	} else {
		DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
		atom_card_info->ioreg_read = cail_reg_read;
		atom_card_info->ioreg_write = cail_reg_write;
	}
792 793 794 795 796 797
	atom_card_info->mc_read = cail_mc_read;
	atom_card_info->mc_write = cail_mc_write;
	atom_card_info->pll_read = cail_pll_read;
	atom_card_info->pll_write = cail_pll_write;

	rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
798 799 800 801 802
	if (!rdev->mode_info.atom_context) {
		radeon_atombios_fini(rdev);
		return -ENOMEM;
	}

803
	mutex_init(&rdev->mode_info.atom_context->mutex);
804
	radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
805
	atom_allocate_fb_scratch(rdev->mode_info.atom_context);
806 807 808
	return 0;
}

809 810 811 812 813 814 815 816 817
/**
 * radeon_atombios_fini - free the driver info and callbacks for atombios
 *
 * @rdev: radeon_device pointer
 *
 * Frees the driver info and register access callbacks for the ATOM
 * interpreter (r4xx+).
 * Called at driver shutdown.
 */
818 819
void radeon_atombios_fini(struct radeon_device *rdev)
{
820 821 822
	if (rdev->mode_info.atom_context) {
		kfree(rdev->mode_info.atom_context->scratch);
	}
823 824
	kfree(rdev->mode_info.atom_context);
	rdev->mode_info.atom_context = NULL;
825
	kfree(rdev->mode_info.atom_card_info);
826
	rdev->mode_info.atom_card_info = NULL;
827 828
}

829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844
/* COMBIOS */
/*
 * COMBIOS is the bios format prior to ATOM. It provides
 * command tables similar to ATOM, but doesn't have a unified
 * parser.  See radeon_combios.c
 */

/**
 * radeon_combios_init - init the driver info for combios
 *
 * @rdev: radeon_device pointer
 *
 * Initializes the driver info for combios (r1xx-r3xx).
 * Returns 0 on sucess.
 * Called at driver startup.
 */
845 846 847 848 849 850
int radeon_combios_init(struct radeon_device *rdev)
{
	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
	return 0;
}

851 852 853 854 855 856 857 858
/**
 * radeon_combios_fini - free the driver info for combios
 *
 * @rdev: radeon_device pointer
 *
 * Frees the driver info for combios (r1xx-r3xx).
 * Called at driver shutdown.
 */
859 860 861 862
void radeon_combios_fini(struct radeon_device *rdev)
{
}

863 864 865 866 867 868 869 870 871 872
/* if we get transitioned to only one device, take VGA back */
/**
 * radeon_vga_set_decode - enable/disable vga decode
 *
 * @cookie: radeon_device pointer
 * @state: enable/disable vga decode
 *
 * Enable/disable vga decode (all asics).
 * Returns VGA resource flags.
 */
873 874 875 876 877 878 879 880 881 882
static unsigned int radeon_vga_set_decode(void *cookie, bool state)
{
	struct radeon_device *rdev = cookie;
	radeon_vga_set_state(rdev, state);
	if (state)
		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
	else
		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
}
883

884 885 886 887 888 889 890 891 892 893 894 895 896
/**
 * radeon_check_pot_argument - check that argument is a power of two
 *
 * @arg: value to check
 *
 * Validates that a certain argument is a power of two (all asics).
 * Returns true if argument is valid.
 */
static bool radeon_check_pot_argument(int arg)
{
	return (arg & (arg - 1)) == 0;
}

897 898 899 900 901 902 903 904
/**
 * radeon_check_arguments - validate module params
 *
 * @rdev: radeon_device pointer
 *
 * Validates certain module parameters and updates
 * the associated values used by the driver (all asics).
 */
905
static void radeon_check_arguments(struct radeon_device *rdev)
906 907
{
	/* vramlimit must be a power of two */
908
	if (!radeon_check_pot_argument(radeon_vram_limit)) {
909 910 911 912
		dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
				radeon_vram_limit);
		radeon_vram_limit = 0;
	}
913

914
	/* gtt size must be power of two and greater or equal to 32M */
915
	if (radeon_gart_size < 32) {
916 917 918
		dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
				radeon_gart_size);
		radeon_gart_size = 512;
919 920

	} else if (!radeon_check_pot_argument(radeon_gart_size)) {
921 922 923 924
		dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
				radeon_gart_size);
		radeon_gart_size = 512;
	}
925 926
	rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;

927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943
	/* AGP mode can only be -1, 1, 2, 4, 8 */
	switch (radeon_agpmode) {
	case -1:
	case 0:
	case 1:
	case 2:
	case 4:
	case 8:
		break;
	default:
		dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
				"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
		radeon_agpmode = 0;
		break;
	}
}

944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962
/**
 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
 * needed for waking up.
 *
 * @pdev: pci dev pointer
 */
static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
{

	/* 6600m in a macbook pro */
	if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
	    pdev->subsystem_device == 0x00e2) {
		printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
		return true;
	}

	return false;
}

963 964 965 966 967 968 969 970 971
/**
 * radeon_switcheroo_set_state - set switcheroo state
 *
 * @pdev: pci dev pointer
 * @state: vga switcheroo state
 *
 * Callback for the switcheroo driver.  Suspends or resumes the
 * the asics before or after it is powered up using ACPI methods.
 */
972 973 974 975 976
static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
	if (state == VGA_SWITCHEROO_ON) {
977 978
		unsigned d3_delay = dev->pdev->d3_delay;

979 980
		printk(KERN_INFO "radeon: switched on\n");
		/* don't suspend or resume card normally */
981
		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
982 983 984 985

		if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
			dev->pdev->d3_delay = 20;

986
		radeon_resume_kms(dev);
987 988 989

		dev->pdev->d3_delay = d3_delay;

990
		dev->switch_power_state = DRM_SWITCH_POWER_ON;
991
		drm_kms_helper_poll_enable(dev);
992 993
	} else {
		printk(KERN_INFO "radeon: switched off\n");
994
		drm_kms_helper_poll_disable(dev);
995
		dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
996
		radeon_suspend_kms(dev, pmm);
997
		dev->switch_power_state = DRM_SWITCH_POWER_OFF;
998 999 1000
	}
}

1001 1002 1003 1004 1005 1006 1007 1008 1009
/**
 * radeon_switcheroo_can_switch - see if switcheroo state can change
 *
 * @pdev: pci dev pointer
 *
 * Callback for the switcheroo driver.  Check of the switcheroo
 * state can be changed.
 * Returns true if the state can be changed, false if not.
 */
1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020
static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	bool can_switch;

	spin_lock(&dev->count_lock);
	can_switch = (dev->open_count == 0);
	spin_unlock(&dev->count_lock);
	return can_switch;
}

1021 1022 1023 1024 1025
static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
	.set_gpu_state = radeon_switcheroo_set_state,
	.reprobe = NULL,
	.can_switch = radeon_switcheroo_can_switch,
};
1026

1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038
/**
 * radeon_device_init - initialize the driver
 *
 * @rdev: radeon_device pointer
 * @pdev: drm dev pointer
 * @pdev: pci dev pointer
 * @flags: driver flags
 *
 * Initializes the driver info and hw (all asics).
 * Returns 0 for success or an error on failure.
 * Called at driver startup.
 */
1039 1040 1041 1042 1043
int radeon_device_init(struct radeon_device *rdev,
		       struct drm_device *ddev,
		       struct pci_dev *pdev,
		       uint32_t flags)
{
1044
	int r, i;
D
Dave Airlie 已提交
1045
	int dma_bits;
1046 1047

	rdev->shutdown = false;
1048
	rdev->dev = &pdev->dev;
1049 1050 1051 1052 1053 1054 1055
	rdev->ddev = ddev;
	rdev->pdev = pdev;
	rdev->flags = flags;
	rdev->family = flags & RADEON_FAMILY_MASK;
	rdev->is_atom_bios = false;
	rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
1056
	rdev->accel_working = false;
1057 1058 1059 1060
	/* set up ring ids */
	for (i = 0; i < RADEON_NUM_RINGS; i++) {
		rdev->ring[i].idx = i;
	}
1061

1062 1063 1064
	DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
		radeon_family_name[rdev->family], pdev->vendor, pdev->device,
		pdev->subsystem_vendor, pdev->subsystem_device);
1065

1066 1067
	/* mutex initialization are all done here so we
	 * can recall function without having locking issues */
1068
	mutex_init(&rdev->ring_lock);
1069
	mutex_init(&rdev->dc_hw_i2c_mutex);
1070
	atomic_set(&rdev->ih.lock, 0);
1071
	mutex_init(&rdev->gem.mutex);
1072
	mutex_init(&rdev->pm.mutex);
1073
	mutex_init(&rdev->gpu_clock_mutex);
1074
	init_rwsem(&rdev->pm.mclk_lock);
1075
	init_rwsem(&rdev->exclusive_lock);
1076
	init_waitqueue_head(&rdev->irq.vblank_queue);
1077 1078 1079
	r = radeon_gem_init(rdev);
	if (r)
		return r;
1080
	/* initialize vm here */
1081
	mutex_init(&rdev->vm_manager.lock);
1082 1083 1084 1085
	/* Adjust VM size here.
	 * Currently set to 4GB ((1 << 20) 4k pages).
	 * Max GPUVM size for cayman and SI is 40 bits.
	 */
1086 1087
	rdev->vm_manager.max_pfn = 1 << 20;
	INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
1088

1089 1090
	/* Set asic functions */
	r = radeon_asic_init(rdev);
1091
	if (r)
1092
		return r;
1093
	radeon_check_arguments(rdev);
1094

1095 1096 1097 1098 1099 1100 1101 1102
	/* all of the newer IGP chips have an internal gart
	 * However some rs4xx report as AGP, so remove that here.
	 */
	if ((rdev->family >= CHIP_RS400) &&
	    (rdev->flags & RADEON_IS_IGP)) {
		rdev->flags &= ~RADEON_IS_AGP;
	}

1103
	if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1104
		radeon_agp_disable(rdev);
1105 1106
	}

1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117
	/* Set the internal MC address mask
	 * This is the max address of the GPU's
	 * internal address space.
	 */
	if (rdev->family >= CHIP_CAYMAN)
		rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
	else if (rdev->family >= CHIP_CEDAR)
		rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
	else
		rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */

D
Dave Airlie 已提交
1118 1119
	/* set DMA mask + need_dma32 flags.
	 * PCIE - can handle 40-bits.
1120
	 * IGP - can handle 40-bits
D
Dave Airlie 已提交
1121
	 * AGP - generally dma32 is safest
1122
	 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
D
Dave Airlie 已提交
1123 1124 1125 1126
	 */
	rdev->need_dma32 = false;
	if (rdev->flags & RADEON_IS_AGP)
		rdev->need_dma32 = true;
1127
	if ((rdev->flags & RADEON_IS_PCI) &&
1128
	    (rdev->family <= CHIP_RS740))
D
Dave Airlie 已提交
1129 1130 1131 1132
		rdev->need_dma32 = true;

	dma_bits = rdev->need_dma32 ? 32 : 40;
	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1133
	if (r) {
1134
		rdev->need_dma32 = true;
1135
		dma_bits = 32;
1136 1137
		printk(KERN_WARNING "radeon: No suitable DMA available.\n");
	}
1138 1139 1140 1141 1142
	r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
	if (r) {
		pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
		printk(KERN_WARNING "radeon: No coherent DMA available.\n");
	}
1143 1144 1145

	/* Registers mapping */
	/* TODO: block userspace mapping of io register */
1146
	spin_lock_init(&rdev->mmio_idx_lock);
1147 1148
	rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
	rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1149 1150 1151 1152 1153 1154 1155
	rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
	if (rdev->rmmio == NULL) {
		return -ENOMEM;
	}
	DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
	DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);

1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166
	/* io port mapping */
	for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
		if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
			rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
			rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
			break;
		}
	}
	if (rdev->rio_mem == NULL)
		DRM_ERROR("Unable to find PCI I/O BAR\n");

1167
	/* if we have > 1 VGA cards, then disable the radeon VGA resources */
1168 1169 1170
	/* this will fail for cards that aren't VGA class devices, just
	 * ignore it */
	vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1171
	vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops);
1172

1173
	r = radeon_init(rdev);
1174
	if (r)
1175 1176
		return r;

1177 1178 1179 1180
	r = radeon_ib_ring_tests(rdev);
	if (r)
		DRM_ERROR("ib ring test failed (%d).\n", r);

J
Jerome Glisse 已提交
1181 1182 1183 1184 1185
	r = radeon_gem_debugfs_init(rdev);
	if (r) {
		DRM_ERROR("registering gem debugfs failed (%d).\n", r);
	}

1186 1187 1188 1189
	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
		/* Acceleration not working on AGP card try again
		 * with fallback to PCI or PCIE GART
		 */
1190
		radeon_asic_reset(rdev);
1191 1192 1193
		radeon_fini(rdev);
		radeon_agp_disable(rdev);
		r = radeon_init(rdev);
1194 1195
		if (r)
			return r;
1196
	}
1197
	if ((radeon_testing & 1)) {
1198 1199
		radeon_test_moves(rdev);
	}
1200 1201 1202
	if ((radeon_testing & 2)) {
		radeon_test_syncing(rdev);
	}
1203
	if (radeon_benchmarking) {
1204
		radeon_benchmark(rdev, radeon_benchmarking);
1205
	}
1206
	return 0;
1207 1208
}

1209 1210
static void radeon_debugfs_remove_files(struct radeon_device *rdev);

1211 1212 1213 1214 1215 1216 1217 1218
/**
 * radeon_device_fini - tear down the driver
 *
 * @rdev: radeon_device pointer
 *
 * Tear down the driver info (all asics).
 * Called at driver shutdown.
 */
1219 1220 1221 1222
void radeon_device_fini(struct radeon_device *rdev)
{
	DRM_INFO("radeon: finishing device.\n");
	rdev->shutdown = true;
1223 1224
	/* evict vram memory */
	radeon_bo_evict_vram(rdev);
1225
	radeon_fini(rdev);
1226
	vga_switcheroo_unregister_client(rdev->pdev);
1227
	vga_client_register(rdev->pdev, NULL, NULL, NULL);
1228 1229
	if (rdev->rio_mem)
		pci_iounmap(rdev->pdev, rdev->rio_mem);
1230
	rdev->rio_mem = NULL;
1231 1232
	iounmap(rdev->rmmio);
	rdev->rmmio = NULL;
1233
	radeon_debugfs_remove_files(rdev);
1234 1235 1236 1237 1238 1239
}


/*
 * Suspend & resume.
 */
1240 1241 1242 1243 1244 1245 1246 1247 1248 1249
/**
 * radeon_suspend_kms - initiate device suspend
 *
 * @pdev: drm dev pointer
 * @state: suspend state
 *
 * Puts the hw in the suspend state (all asics).
 * Returns 0 for success or an error on failure.
 * Called at driver suspend.
 */
1250 1251
int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
{
1252
	struct radeon_device *rdev;
1253
	struct drm_crtc *crtc;
1254
	struct drm_connector *connector;
1255
	int i, r;
1256
	bool force_completion = false;
1257

1258
	if (dev == NULL || dev->dev_private == NULL) {
1259 1260 1261 1262 1263
		return -ENODEV;
	}
	if (state.event == PM_EVENT_PRETHAW) {
		return 0;
	}
1264 1265
	rdev = dev->dev_private;

1266
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1267
		return 0;
1268

1269 1270
	drm_kms_helper_poll_disable(dev);

1271 1272 1273 1274 1275
	/* turn off display hw */
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
	}

1276 1277 1278
	/* unpin the front buffers */
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
1279
		struct radeon_bo *robj;
1280 1281 1282 1283

		if (rfb == NULL || rfb->obj == NULL) {
			continue;
		}
1284
		robj = gem_to_radeon_bo(rfb->obj);
1285 1286
		/* don't unpin kernel fb objects */
		if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1287
			r = radeon_bo_reserve(robj, false);
1288
			if (r == 0) {
1289 1290 1291
				radeon_bo_unpin(robj);
				radeon_bo_unreserve(robj);
			}
1292 1293 1294
		}
	}
	/* evict vram memory */
1295
	radeon_bo_evict_vram(rdev);
1296 1297

	mutex_lock(&rdev->ring_lock);
1298
	/* wait for gpu to finish processing current batch */
1299 1300 1301 1302 1303 1304 1305 1306 1307 1308
	for (i = 0; i < RADEON_NUM_RINGS; i++) {
		r = radeon_fence_wait_empty_locked(rdev, i);
		if (r) {
			/* delay GPU reset to resume */
			force_completion = true;
		}
	}
	if (force_completion) {
		radeon_fence_driver_force_completion(rdev);
	}
1309
	mutex_unlock(&rdev->ring_lock);
1310

1311 1312
	radeon_save_bios_scratch_regs(rdev);

1313
	radeon_pm_suspend(rdev);
1314
	radeon_suspend(rdev);
A
Alex Deucher 已提交
1315
	radeon_hpd_fini(rdev);
1316
	/* evict remaining vram memory */
1317
	radeon_bo_evict_vram(rdev);
1318

1319 1320
	radeon_agp_suspend(rdev);

1321 1322 1323 1324 1325 1326
	pci_save_state(dev->pdev);
	if (state.event == PM_EVENT_SUSPEND) {
		/* Shut down the device */
		pci_disable_device(dev->pdev);
		pci_set_power_state(dev->pdev, PCI_D3hot);
	}
1327
	console_lock();
1328
	radeon_fbdev_set_suspend(rdev, 1);
1329
	console_unlock();
1330 1331 1332
	return 0;
}

1333 1334 1335 1336 1337 1338 1339 1340 1341
/**
 * radeon_resume_kms - initiate device resume
 *
 * @pdev: drm dev pointer
 *
 * Bring the hw back to operating state (all asics).
 * Returns 0 for success or an error on failure.
 * Called at driver resume.
 */
1342 1343
int radeon_resume_kms(struct drm_device *dev)
{
1344
	struct drm_connector *connector;
1345
	struct radeon_device *rdev = dev->dev_private;
1346
	int r;
1347

1348
	if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1349 1350
		return 0;

1351
	console_lock();
1352 1353 1354
	pci_set_power_state(dev->pdev, PCI_D0);
	pci_restore_state(dev->pdev);
	if (pci_enable_device(dev->pdev)) {
1355
		console_unlock();
1356 1357
		return -1;
	}
1358 1359
	/* resume AGP if in use */
	radeon_agp_resume(rdev);
1360
	radeon_resume(rdev);
1361 1362 1363 1364 1365

	r = radeon_ib_ring_tests(rdev);
	if (r)
		DRM_ERROR("ib ring test failed (%d).\n", r);

1366
	radeon_pm_resume(rdev);
1367
	radeon_restore_bios_scratch_regs(rdev);
1368

1369
	radeon_fbdev_set_suspend(rdev, 0);
1370
	console_unlock();
1371

1372 1373
	/* init dig PHYs, disp eng pll */
	if (rdev->is_atom_bios) {
1374
		radeon_atom_encoder_init(rdev);
1375
		radeon_atom_disp_eng_pll_init(rdev);
1376 1377 1378 1379 1380 1381 1382
		/* turn on the BL */
		if (rdev->mode_info.bl_encoder) {
			u8 bl_level = radeon_get_backlight_level(rdev,
								 rdev->mode_info.bl_encoder);
			radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
						   bl_level);
		}
1383
	}
A
Alex Deucher 已提交
1384 1385
	/* reset hpd state */
	radeon_hpd_init(rdev);
1386 1387
	/* blat the mode back in */
	drm_helper_resume_force_mode(dev);
1388 1389 1390 1391
	/* turn on display hw */
	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
		drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
	}
1392 1393

	drm_kms_helper_poll_enable(dev);
1394 1395 1396
	return 0;
}

1397 1398 1399 1400 1401 1402 1403 1404
/**
 * radeon_gpu_reset - reset the asic
 *
 * @rdev: radeon device pointer
 *
 * Attempt the reset the GPU if it has hung (all asics).
 * Returns 0 for success or an error on failure.
 */
1405 1406
int radeon_gpu_reset(struct radeon_device *rdev)
{
1407 1408 1409 1410 1411 1412
	unsigned ring_sizes[RADEON_NUM_RINGS];
	uint32_t *ring_data[RADEON_NUM_RINGS];

	bool saved = false;

	int i, r;
1413
	int resched;
1414

1415
	down_write(&rdev->exclusive_lock);
1416
	radeon_save_bios_scratch_regs(rdev);
1417 1418
	/* block TTM */
	resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1419 1420
	radeon_suspend(rdev);

1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431
	for (i = 0; i < RADEON_NUM_RINGS; ++i) {
		ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
						   &ring_data[i]);
		if (ring_sizes[i]) {
			saved = true;
			dev_info(rdev->dev, "Saved %d dwords of commands "
				 "on ring %d.\n", ring_sizes[i], i);
		}
	}

retry:
1432 1433
	r = radeon_asic_reset(rdev);
	if (!r) {
1434
		dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1435
		radeon_resume(rdev);
1436
	}
1437

1438
	radeon_restore_bios_scratch_regs(rdev);
1439

1440 1441 1442 1443
	if (!r) {
		for (i = 0; i < RADEON_NUM_RINGS; ++i) {
			radeon_ring_restore(rdev, &rdev->ring[i],
					    ring_sizes[i], ring_data[i]);
1444 1445
			ring_sizes[i] = 0;
			ring_data[i] = NULL;
1446 1447 1448 1449 1450 1451
		}

		r = radeon_ib_ring_tests(rdev);
		if (r) {
			dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
			if (saved) {
1452
				saved = false;
1453 1454 1455 1456 1457
				radeon_suspend(rdev);
				goto retry;
			}
		}
	} else {
1458
		radeon_fence_driver_force_completion(rdev);
1459 1460 1461
		for (i = 0; i < RADEON_NUM_RINGS; ++i) {
			kfree(ring_data[i]);
		}
1462
	}
1463

1464 1465
	drm_helper_resume_force_mode(rdev->ddev);

1466
	ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1467 1468 1469 1470 1471
	if (r) {
		/* bad news, how to tell it to userspace ? */
		dev_info(rdev->dev, "GPU reset failed\n");
	}

1472
	up_write(&rdev->exclusive_lock);
1473 1474 1475
	return r;
}

1476 1477 1478 1479 1480 1481 1482 1483 1484 1485

/*
 * Debugfs
 */
int radeon_debugfs_add_files(struct radeon_device *rdev,
			     struct drm_info_list *files,
			     unsigned nfiles)
{
	unsigned i;

1486 1487
	for (i = 0; i < rdev->debugfs_count; i++) {
		if (rdev->debugfs[i].files == files) {
1488 1489 1490 1491
			/* Already registered */
			return 0;
		}
	}
1492

1493
	i = rdev->debugfs_count + 1;
1494 1495 1496 1497
	if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
		DRM_ERROR("Reached maximum number of debugfs components.\n");
		DRM_ERROR("Report so we increase "
		          "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1498 1499
		return -EINVAL;
	}
1500 1501 1502
	rdev->debugfs[rdev->debugfs_count].files = files;
	rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
	rdev->debugfs_count = i;
1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513
#if defined(CONFIG_DEBUG_FS)
	drm_debugfs_create_files(files, nfiles,
				 rdev->ddev->control->debugfs_root,
				 rdev->ddev->control);
	drm_debugfs_create_files(files, nfiles,
				 rdev->ddev->primary->debugfs_root,
				 rdev->ddev->primary);
#endif
	return 0;
}

1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529
static void radeon_debugfs_remove_files(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
	unsigned i;

	for (i = 0; i < rdev->debugfs_count; i++) {
		drm_debugfs_remove_files(rdev->debugfs[i].files,
					 rdev->debugfs[i].num_files,
					 rdev->ddev->control);
		drm_debugfs_remove_files(rdev->debugfs[i].files,
					 rdev->debugfs[i].num_files,
					 rdev->ddev->primary);
	}
#endif
}

1530 1531 1532 1533 1534 1535 1536 1537 1538 1539
#if defined(CONFIG_DEBUG_FS)
int radeon_debugfs_init(struct drm_minor *minor)
{
	return 0;
}

void radeon_debugfs_cleanup(struct drm_minor *minor)
{
}
#endif