davinci_emac.c 57.9 KB
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/*
 * DaVinci Ethernet Medium Access Controller
 *
 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
 *
 * Copyright (C) 2009 Texas Instruments.
 *
 * ---------------------------------------------------------------------------
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 * ---------------------------------------------------------------------------
 * History:
 * 0-5 A number of folks worked on this driver in bits and pieces but the major
 *     contribution came from Suraj Iyer and Anant Gole
 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
 *     PHY layer usage
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/errno.h>
#include <linux/in.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/ethtool.h>
#include <linux/highmem.h>
#include <linux/proc_fs.h>
#include <linux/ctype.h>
#include <linux/spinlock.h>
#include <linux/dma-mapping.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/semaphore.h>
#include <linux/phy.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/uaccess.h>
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#include <linux/pm_runtime.h>
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#include <linux/davinci_emac.h>
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#include <linux/of.h>
#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_mdio.h>
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#include <linux/of_irq.h>
#include <linux/of_net.h>
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#include <linux/mfd/syscon.h>
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#include <asm/irq.h>
#include <asm/page.h>

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#include "cpsw.h"
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#include "davinci_cpdma.h"

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static int debug_level;
module_param(debug_level, int, 0);
MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");

/* Netif debug messages possible */
#define DAVINCI_EMAC_DEBUG	(NETIF_MSG_DRV | \
				NETIF_MSG_PROBE | \
				NETIF_MSG_LINK | \
				NETIF_MSG_TIMER | \
				NETIF_MSG_IFDOWN | \
				NETIF_MSG_IFUP | \
				NETIF_MSG_RX_ERR | \
				NETIF_MSG_TX_ERR | \
				NETIF_MSG_TX_QUEUED | \
				NETIF_MSG_INTR | \
				NETIF_MSG_TX_DONE | \
				NETIF_MSG_RX_STATUS | \
				NETIF_MSG_PKTDATA | \
				NETIF_MSG_HW | \
				NETIF_MSG_WOL)

/* version info */
#define EMAC_MAJOR_VERSION	6
#define EMAC_MINOR_VERSION	1
#define EMAC_MODULE_VERSION	"6.1"
MODULE_VERSION(EMAC_MODULE_VERSION);
static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";

/* Configuration items */
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#define EMAC_DEF_PASS_CRC		(0) /* Do not pass CRC up to frames */
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#define EMAC_DEF_QOS_EN			(0) /* EMAC proprietary QoS disabled */
#define EMAC_DEF_NO_BUFF_CHAIN		(0) /* No buffer chain */
#define EMAC_DEF_MACCTRL_FRAME_EN	(0) /* Discard Maccontrol frames */
#define EMAC_DEF_SHORT_FRAME_EN		(0) /* Discard short frames */
#define EMAC_DEF_ERROR_FRAME_EN		(0) /* Discard error frames */
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#define EMAC_DEF_PROM_EN		(0) /* Promiscuous disabled */
#define EMAC_DEF_PROM_CH		(0) /* Promiscuous channel is 0 */
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#define EMAC_DEF_BCAST_EN		(1) /* Broadcast enabled */
#define EMAC_DEF_BCAST_CH		(0) /* Broadcast channel is 0 */
#define EMAC_DEF_MCAST_EN		(1) /* Multicast enabled */
#define EMAC_DEF_MCAST_CH		(0) /* Multicast channel is 0 */

#define EMAC_DEF_TXPRIO_FIXED		(1) /* TX Priority is fixed */
#define EMAC_DEF_TXPACING_EN		(0) /* TX pacing NOT supported*/

#define EMAC_DEF_BUFFER_OFFSET		(0) /* Buffer offset to DMA (future) */
#define EMAC_DEF_MIN_ETHPKTSIZE		(60) /* Minimum ethernet pkt size */
#define EMAC_DEF_MAX_FRAME_SIZE		(1500 + 14 + 4 + 4)
#define EMAC_DEF_TX_CH			(0) /* Default 0th channel */
#define EMAC_DEF_RX_CH			(0) /* Default 0th channel */
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#define EMAC_DEF_RX_NUM_DESC		(128)
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#define EMAC_DEF_MAX_TX_CH		(1) /* Max TX channels configured */
#define EMAC_DEF_MAX_RX_CH		(1) /* Max RX channels configured */
#define EMAC_POLL_WEIGHT		(64) /* Default NAPI poll weight */

/* Buffer descriptor parameters */
#define EMAC_DEF_TX_MAX_SERVICE		(32) /* TX max service BD's */
#define EMAC_DEF_RX_MAX_SERVICE		(64) /* should = netdev->weight */

/* EMAC register related defines */
#define EMAC_ALL_MULTI_REG_VALUE	(0xFFFFFFFF)
#define EMAC_NUM_MULTICAST_BITS		(64)
#define EMAC_TX_CONTROL_TX_ENABLE_VAL	(0x1)
#define EMAC_RX_CONTROL_RX_ENABLE_VAL	(0x1)
#define EMAC_MAC_HOST_ERR_INTMASK_VAL	(0x2)
#define EMAC_RX_UNICAST_CLEAR_ALL	(0xFF)
#define EMAC_INT_MASK_CLEAR		(0xFF)

/* RX MBP register bit positions */
#define EMAC_RXMBP_PASSCRC_MASK		BIT(30)
#define EMAC_RXMBP_QOSEN_MASK		BIT(29)
#define EMAC_RXMBP_NOCHAIN_MASK		BIT(28)
#define EMAC_RXMBP_CMFEN_MASK		BIT(24)
#define EMAC_RXMBP_CSFEN_MASK		BIT(23)
#define EMAC_RXMBP_CEFEN_MASK		BIT(22)
#define EMAC_RXMBP_CAFEN_MASK		BIT(21)
#define EMAC_RXMBP_PROMCH_SHIFT		(16)
#define EMAC_RXMBP_PROMCH_MASK		(0x7 << 16)
#define EMAC_RXMBP_BROADEN_MASK		BIT(13)
#define EMAC_RXMBP_BROADCH_SHIFT	(8)
#define EMAC_RXMBP_BROADCH_MASK		(0x7 << 8)
#define EMAC_RXMBP_MULTIEN_MASK		BIT(5)
#define EMAC_RXMBP_MULTICH_SHIFT	(0)
#define EMAC_RXMBP_MULTICH_MASK		(0x7)
#define EMAC_RXMBP_CHMASK		(0x7)

/* EMAC register definitions/bit maps used */
# define EMAC_MBP_RXPROMISC		(0x00200000)
# define EMAC_MBP_PROMISCCH(ch)		(((ch) & 0x7) << 16)
# define EMAC_MBP_RXBCAST		(0x00002000)
# define EMAC_MBP_BCASTCHAN(ch)		(((ch) & 0x7) << 8)
# define EMAC_MBP_RXMCAST		(0x00000020)
# define EMAC_MBP_MCASTCHAN(ch)		((ch) & 0x7)

/* EMAC mac_control register */
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#define EMAC_MACCONTROL_TXPTYPE		BIT(9)
#define EMAC_MACCONTROL_TXPACEEN	BIT(6)
#define EMAC_MACCONTROL_GMIIEN		BIT(5)
#define EMAC_MACCONTROL_GIGABITEN	BIT(7)
#define EMAC_MACCONTROL_FULLDUPLEXEN	BIT(0)
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#define EMAC_MACCONTROL_RMIISPEED_MASK	BIT(15)

/* GIGABIT MODE related bits */
#define EMAC_DM646X_MACCONTORL_GIG	BIT(7)
#define EMAC_DM646X_MACCONTORL_GIGFORCE	BIT(17)

/* EMAC mac_status register */
#define EMAC_MACSTATUS_TXERRCODE_MASK	(0xF00000)
#define EMAC_MACSTATUS_TXERRCODE_SHIFT	(20)
#define EMAC_MACSTATUS_TXERRCH_MASK	(0x7)
#define EMAC_MACSTATUS_TXERRCH_SHIFT	(16)
#define EMAC_MACSTATUS_RXERRCODE_MASK	(0xF000)
#define EMAC_MACSTATUS_RXERRCODE_SHIFT	(12)
#define EMAC_MACSTATUS_RXERRCH_MASK	(0x7)
#define EMAC_MACSTATUS_RXERRCH_SHIFT	(8)

/* EMAC RX register masks */
#define EMAC_RX_MAX_LEN_MASK		(0xFFFF)
#define EMAC_RX_BUFFER_OFFSET_MASK	(0xFFFF)

/* MAC_IN_VECTOR (0x180) register bit fields */
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#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT	BIT(17)
#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT	BIT(16)
#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC	BIT(8)
#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC	BIT(0)
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/** NOTE:: For DM646x the IN_VECTOR has changed */
#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC	BIT(EMAC_DEF_RX_CH)
#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC	BIT(16 + EMAC_DEF_TX_CH)
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#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT	BIT(26)
#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT	BIT(27)

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/* CPPI bit positions */
#define EMAC_CPPI_SOP_BIT		BIT(31)
#define EMAC_CPPI_EOP_BIT		BIT(30)
#define EMAC_CPPI_OWNERSHIP_BIT		BIT(29)
#define EMAC_CPPI_EOQ_BIT		BIT(28)
#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
#define EMAC_CPPI_PASS_CRC_BIT		BIT(26)
#define EMAC_RX_BD_BUF_SIZE		(0xFFFF)
#define EMAC_BD_LENGTH_FOR_CACHE	(16) /* only CPPI bytes */
#define EMAC_RX_BD_PKT_LENGTH_MASK	(0xFFFF)

/* Max hardware defines */
#define EMAC_MAX_TXRX_CHANNELS		 (8)  /* Max hardware channels */
#define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */

/* EMAC Peripheral Device Register Memory Layout structure */
#define EMAC_MACINVECTOR	0x90

#define EMAC_DM646X_MACEOIVECTOR	0x94

#define EMAC_MACINTSTATRAW	0xB0
#define EMAC_MACINTSTATMASKED	0xB4
#define EMAC_MACINTMASKSET	0xB8
#define EMAC_MACINTMASKCLEAR	0xBC

#define EMAC_RXMBPENABLE	0x100
#define EMAC_RXUNICASTSET	0x104
#define EMAC_RXUNICASTCLEAR	0x108
#define EMAC_RXMAXLEN		0x10C
#define EMAC_RXBUFFEROFFSET	0x110
#define EMAC_RXFILTERLOWTHRESH	0x114

#define EMAC_MACCONTROL		0x160
#define EMAC_MACSTATUS		0x164
#define EMAC_EMCONTROL		0x168
#define EMAC_FIFOCONTROL	0x16C
#define EMAC_MACCONFIG		0x170
#define EMAC_SOFTRESET		0x174
#define EMAC_MACSRCADDRLO	0x1D0
#define EMAC_MACSRCADDRHI	0x1D4
#define EMAC_MACHASH1		0x1D8
#define EMAC_MACHASH2		0x1DC
#define EMAC_MACADDRLO		0x500
#define EMAC_MACADDRHI		0x504
#define EMAC_MACINDEX		0x508

/* EMAC statistics registers */
#define EMAC_RXGOODFRAMES	0x200
#define EMAC_RXBCASTFRAMES	0x204
#define EMAC_RXMCASTFRAMES	0x208
#define EMAC_RXPAUSEFRAMES	0x20C
#define EMAC_RXCRCERRORS	0x210
#define EMAC_RXALIGNCODEERRORS	0x214
#define EMAC_RXOVERSIZED	0x218
#define EMAC_RXJABBER		0x21C
#define EMAC_RXUNDERSIZED	0x220
#define EMAC_RXFRAGMENTS	0x224
#define EMAC_RXFILTERED		0x228
#define EMAC_RXQOSFILTERED	0x22C
#define EMAC_RXOCTETS		0x230
#define EMAC_TXGOODFRAMES	0x234
#define EMAC_TXBCASTFRAMES	0x238
#define EMAC_TXMCASTFRAMES	0x23C
#define EMAC_TXPAUSEFRAMES	0x240
#define EMAC_TXDEFERRED		0x244
#define EMAC_TXCOLLISION	0x248
#define EMAC_TXSINGLECOLL	0x24C
#define EMAC_TXMULTICOLL	0x250
#define EMAC_TXEXCESSIVECOLL	0x254
#define EMAC_TXLATECOLL		0x258
#define EMAC_TXUNDERRUN		0x25C
#define EMAC_TXCARRIERSENSE	0x260
#define EMAC_TXOCTETS		0x264
#define EMAC_NETOCTETS		0x280
#define EMAC_RXSOFOVERRUNS	0x284
#define EMAC_RXMOFOVERRUNS	0x288
#define EMAC_RXDMAOVERRUNS	0x28C

/* EMAC DM644x control registers */
#define EMAC_CTRL_EWCTL		(0x4)
#define EMAC_CTRL_EWINTTCNT	(0x8)

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/* EMAC DM644x control module masks */
#define EMAC_DM644X_EWINTCNT_MASK	0x1FFFF
#define EMAC_DM644X_INTMIN_INTVL	0x1
#define EMAC_DM644X_INTMAX_INTVL	(EMAC_DM644X_EWINTCNT_MASK)

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/* EMAC DM646X control module registers */
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#define EMAC_DM646X_CMINTCTRL	0x0C
#define EMAC_DM646X_CMRXINTEN	0x14
#define EMAC_DM646X_CMTXINTEN	0x18
#define EMAC_DM646X_CMRXINTMAX	0x70
#define EMAC_DM646X_CMTXINTMAX	0x74

/* EMAC DM646X control module masks */
#define EMAC_DM646X_INTPACEEN		(0x3 << 16)
#define EMAC_DM646X_INTPRESCALE_MASK	(0x7FF << 0)
#define EMAC_DM646X_CMINTMAX_CNT	63
#define EMAC_DM646X_CMINTMIN_CNT	2
#define EMAC_DM646X_CMINTMAX_INTVL	(1000 / EMAC_DM646X_CMINTMIN_CNT)
#define EMAC_DM646X_CMINTMIN_INTVL	((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)

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/* EMAC EOI codes for C0 */
#define EMAC_DM646X_MAC_EOI_C0_RXEN	(0x01)
#define EMAC_DM646X_MAC_EOI_C0_TXEN	(0x02)

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/* EMAC Stats Clear Mask */
#define EMAC_STATS_CLR_MASK    (0xFFFFFFFF)

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/* emac_priv: EMAC private data structure
 *
 * EMAC adapter private data structure
 */
struct emac_priv {
	u32 msg_enable;
	struct net_device *ndev;
	struct platform_device *pdev;
	struct napi_struct napi;
	char mac_addr[6];
	void __iomem *remap_addr;
	u32 emac_base_phys;
	void __iomem *emac_base;
	void __iomem *ctrl_base;
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	struct cpdma_ctlr *dma;
	struct cpdma_chan *txchan;
	struct cpdma_chan *rxchan;
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	u32 link; /* 1=link on, 0=link off */
	u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
	u32 duplex; /* Link duplex: 0=Half, 1=Full */
	u32 rx_buf_size;
	u32 isr_count;
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	u32 coal_intvl;
	u32 bus_freq_mhz;
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	u8 rmii_en;
	u8 version;
	u32 mac_hash1;
	u32 mac_hash2;
	u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
	u32 rx_addr_type;
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	const char *phy_id;
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	struct device_node *phy_node;
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	spinlock_t lock;
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	/*platform specific members*/
	void (*int_enable) (void);
	void (*int_disable) (void);
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};

/* EMAC TX Host Error description strings */
static char *emac_txhost_errcodes[16] = {
	"No error", "SOP error", "Ownership bit not set in SOP buffer",
	"Zero Next Buffer Descriptor Pointer Without EOP",
	"Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
	"Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
	"Reserved", "Reserved", "Reserved", "Reserved"
};

/* EMAC RX Host Error description strings */
static char *emac_rxhost_errcodes[16] = {
	"No error", "Reserved", "Ownership bit not set in input buffer",
	"Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
	"Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
	"Reserved", "Reserved", "Reserved", "Reserved"
};

/* Helper macros */
#define emac_read(reg)		  ioread32(priv->emac_base + (reg))
#define emac_write(reg, val)      iowrite32(val, priv->emac_base + (reg))

#define emac_ctrl_read(reg)	  ioread32((priv->ctrl_base + (reg)))
#define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))

/**
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 * emac_get_drvinfo - Get EMAC driver information
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 * @ndev: The DaVinci EMAC network adapter
 * @info: ethtool info structure containing name and version
 *
 * Returns EMAC driver information (name and version)
 *
 */
static void emac_get_drvinfo(struct net_device *ndev,
			     struct ethtool_drvinfo *info)
{
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	strlcpy(info->driver, emac_version_string, sizeof(info->driver));
	strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version));
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}

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/**
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 * emac_get_coalesce - Get interrupt coalesce settings for this device
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 * @ndev : The DaVinci EMAC network adapter
 * @coal : ethtool coalesce settings structure
 *
 * Fetch the current interrupt coalesce settings
 *
 */
static int emac_get_coalesce(struct net_device *ndev,
				struct ethtool_coalesce *coal)
{
	struct emac_priv *priv = netdev_priv(ndev);

	coal->rx_coalesce_usecs = priv->coal_intvl;
	return 0;

}

/**
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 * emac_set_coalesce - Set interrupt coalesce settings for this device
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 * @ndev : The DaVinci EMAC network adapter
 * @coal : ethtool coalesce settings structure
 *
 * Set interrupt coalesce parameters
 *
 */
static int emac_set_coalesce(struct net_device *ndev,
				struct ethtool_coalesce *coal)
{
	struct emac_priv *priv = netdev_priv(ndev);
	u32 int_ctrl, num_interrupts = 0;
	u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;

	if (!coal->rx_coalesce_usecs)
		return -EINVAL;

	coal_intvl = coal->rx_coalesce_usecs;

	switch (priv->version) {
	case EMAC_VERSION_2:
		int_ctrl =  emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
		prescale = priv->bus_freq_mhz * 4;

		if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
			coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;

		if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
			/*
			 * Interrupt pacer works with 4us Pulse, we can
			 * throttle further by dilating the 4us pulse.
			 */
			addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;

			if (addnl_dvdr > 1) {
				prescale *= addnl_dvdr;
				if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
							* addnl_dvdr))
					coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
							* addnl_dvdr);
			} else {
				addnl_dvdr = 1;
				coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
			}
		}

		num_interrupts = (1000 * addnl_dvdr) / coal_intvl;

		int_ctrl |= EMAC_DM646X_INTPACEEN;
		int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
		int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
		emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);

		emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
		emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);

		break;
	default:
		int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
		int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
		prescale = coal_intvl * priv->bus_freq_mhz;
		if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
			prescale = EMAC_DM644X_EWINTCNT_MASK;
			coal_intvl = prescale / priv->bus_freq_mhz;
		}
		emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));

		break;
	}

	printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
	priv->coal_intvl = coal_intvl;

	return 0;

}


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/* ethtool_ops: DaVinci EMAC Ethtool structure
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 *
 * Ethtool support for EMAC adapter
 */
static const struct ethtool_ops ethtool_ops = {
	.get_drvinfo = emac_get_drvinfo,
	.get_link = ethtool_op_get_link,
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	.get_coalesce = emac_get_coalesce,
	.set_coalesce =  emac_set_coalesce,
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	.get_ts_info = ethtool_op_get_ts_info,
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	.get_link_ksettings = phy_ethtool_get_link_ksettings,
	.set_link_ksettings = phy_ethtool_set_link_ksettings,
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};

/**
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 * emac_update_phystatus - Update Phy status
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 * @priv: The DaVinci EMAC private adapter structure
 *
 * Updates phy status and takes action for network queue if required
 * based upon link status
 *
 */
static void emac_update_phystatus(struct emac_priv *priv)
{
	u32 mac_control;
	u32 new_duplex;
	u32 cur_duplex;
	struct net_device *ndev = priv->ndev;

	mac_control = emac_read(EMAC_MACCONTROL);
	cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
			DUPLEX_FULL : DUPLEX_HALF;
525 526
	if (ndev->phydev)
		new_duplex = ndev->phydev->duplex;
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	else
		new_duplex = DUPLEX_FULL;

	/* We get called only if link has changed (speed/duplex/status) */
	if ((priv->link) && (new_duplex != cur_duplex)) {
		priv->duplex = new_duplex;
		if (DUPLEX_FULL == priv->duplex)
			mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
		else
			mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
	}

	if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
		mac_control = emac_read(EMAC_MACCONTROL);
541
		mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
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				EMAC_DM646X_MACCONTORL_GIGFORCE);
	} else {
		/* Clear the GIG bit and GIGFORCE bit */
		mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
					EMAC_DM646X_MACCONTORL_GIG);

		if (priv->rmii_en && (priv->speed == SPEED_100))
			mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
		else
			mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
	}

	/* Update mac_control if changed */
	emac_write(EMAC_MACCONTROL, mac_control);

	if (priv->link) {
		/* link ON */
		if (!netif_carrier_ok(ndev))
			netif_carrier_on(ndev);
	/* reactivate the transmit queue if it is stopped */
		if (netif_running(ndev) && netif_queue_stopped(ndev))
			netif_wake_queue(ndev);
	} else {
		/* link OFF */
		if (netif_carrier_ok(ndev))
			netif_carrier_off(ndev);
		if (!netif_queue_stopped(ndev))
			netif_stop_queue(ndev);
	}
}

/**
574
 * hash_get - Calculate hash value from mac address
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 * @addr: mac address to delete from hash table
 *
 * Calculates hash value from mac address
 *
 */
static u32 hash_get(u8 *addr)
{
	u32 hash;
	u8 tmpval;
	int cnt;
	hash = 0;

	for (cnt = 0; cnt < 2; cnt++) {
		tmpval = *addr++;
		hash ^= (tmpval >> 2) ^ (tmpval << 4);
		tmpval = *addr++;
		hash ^= (tmpval >> 4) ^ (tmpval << 2);
		tmpval = *addr++;
		hash ^= (tmpval >> 6) ^ (tmpval);
	}

	return hash & 0x3F;
}

/**
600
 * emac_hash_add - Hash function to add mac addr from hash table
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 * @priv: The DaVinci EMAC private adapter structure
602
 * @mac_addr: mac address to delete from hash table
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 *
 * Adds mac address to the internal hash table
 *
 */
607
static int emac_hash_add(struct emac_priv *priv, u8 *mac_addr)
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{
	struct device *emac_dev = &priv->ndev->dev;
	u32 rc = 0;
	u32 hash_bit;
	u32 hash_value = hash_get(mac_addr);

	if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
		if (netif_msg_drv(priv)) {
616
			dev_err(emac_dev, "DaVinci EMAC: emac_hash_add(): Invalid "\
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				"Hash %08x, should not be greater than %08x",
				hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
		}
		return -1;
	}

	/* set the hash bit only if not previously set */
	if (priv->multicast_hash_cnt[hash_value] == 0) {
		rc = 1; /* hash value changed */
		if (hash_value < 32) {
			hash_bit = BIT(hash_value);
			priv->mac_hash1 |= hash_bit;
		} else {
			hash_bit = BIT((hash_value - 32));
			priv->mac_hash2 |= hash_bit;
		}
	}

	/* incr counter for num of mcast addr's mapped to "this" hash bit */
	++priv->multicast_hash_cnt[hash_value];

	return rc;
}

/**
642
 * emac_hash_del - Hash function to delete mac addr from hash table
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 * @priv: The DaVinci EMAC private adapter structure
644
 * @mac_addr: mac address to delete from hash table
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 *
 * Removes mac address from the internal hash table
 *
 */
649
static int emac_hash_del(struct emac_priv *priv, u8 *mac_addr)
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{
	u32 hash_value;
	u32 hash_bit;

	hash_value = hash_get(mac_addr);
	if (priv->multicast_hash_cnt[hash_value] > 0) {
		/* dec cntr for num of mcast addr's mapped to this hash bit */
		--priv->multicast_hash_cnt[hash_value];
	}

	/* if counter still > 0, at least one multicast address refers
	 * to this hash bit. so return 0 */
	if (priv->multicast_hash_cnt[hash_value] > 0)
		return 0;

	if (hash_value < 32) {
		hash_bit = BIT(hash_value);
		priv->mac_hash1 &= ~hash_bit;
	} else {
		hash_bit = BIT((hash_value - 32));
		priv->mac_hash2 &= ~hash_bit;
	}

	/* return 1 to indicate change in mac_hash registers reqd */
	return 1;
}

/* EMAC multicast operation */
#define EMAC_MULTICAST_ADD	0
#define EMAC_MULTICAST_DEL	1
#define EMAC_ALL_MULTI_SET	2
#define EMAC_ALL_MULTI_CLR	3

/**
684
 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal)
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 * @priv: The DaVinci EMAC private adapter structure
 * @action: multicast operation to perform
 * mac_addr: mac address to set
 *
 * Set multicast addresses in EMAC adapter - internal function
 *
 */
static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
{
	struct device *emac_dev = &priv->ndev->dev;
	int update = -1;

	switch (action) {
	case EMAC_MULTICAST_ADD:
699
		update = emac_hash_add(priv, mac_addr);
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		break;
	case EMAC_MULTICAST_DEL:
702
		update = emac_hash_del(priv, mac_addr);
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		break;
	case EMAC_ALL_MULTI_SET:
		update = 1;
		priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
		priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
		break;
	case EMAC_ALL_MULTI_CLR:
		update = 1;
		priv->mac_hash1 = 0;
		priv->mac_hash2 = 0;
		memset(&(priv->multicast_hash_cnt[0]), 0,
		sizeof(priv->multicast_hash_cnt[0]) *
		       EMAC_NUM_MULTICAST_BITS);
		break;
	default:
		if (netif_msg_drv(priv))
			dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
				": bad operation %d", action);
		break;
	}

	/* write to the hardware only if the register status chances */
	if (update > 0) {
		emac_write(EMAC_MACHASH1, priv->mac_hash1);
		emac_write(EMAC_MACHASH2, priv->mac_hash2);
	}
}

/**
732
 * emac_dev_mcast_set - Set multicast address in the EMAC adapter
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 * @ndev: The DaVinci EMAC network adapter
 *
 * Set multicast addresses in EMAC adapter
 *
 */
static void emac_dev_mcast_set(struct net_device *ndev)
{
	u32 mbp_enable;
	struct emac_priv *priv = netdev_priv(ndev);

	mbp_enable = emac_read(EMAC_RXMBPENABLE);
	if (ndev->flags & IFF_PROMISC) {
		mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
		mbp_enable |= (EMAC_MBP_RXPROMISC);
	} else {
		mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
		if ((ndev->flags & IFF_ALLMULTI) ||
750
		    netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
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			mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
			emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
753
		} else if (!netdev_mc_empty(ndev)) {
754 755
			struct netdev_hw_addr *ha;

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			mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
			emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
			/* program multicast address list into EMAC hardware */
759
			netdev_for_each_mc_addr(ha, ndev) {
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				emac_add_mcast(priv, EMAC_MULTICAST_ADD,
761
					       (u8 *) ha->addr);
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			}
		} else {
			mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
			emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
		}
	}
	/* Set mbp config register */
	emac_write(EMAC_RXMBPENABLE, mbp_enable);
}

/*************************************************************************
 *  EMAC Hardware manipulation
 *************************************************************************/

/**
777
 * emac_int_disable - Disable EMAC module interrupt (from adapter)
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 * @priv: The DaVinci EMAC private adapter structure
 *
 * Disable EMAC interrupt on the adapter
 *
 */
static void emac_int_disable(struct emac_priv *priv)
{
	if (priv->version == EMAC_VERSION_2) {
		unsigned long flags;

		local_irq_save(flags);

		/* Program C0_Int_En to zero to turn off
		* interrupts to the CPU */
		emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
		emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
		/* NOTE: Rx Threshold and Misc interrupts are not disabled */
795 796
		if (priv->int_disable)
			priv->int_disable();
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798 799 800 801 802 803 804 805 806 807
		/* NOTE: Rx Threshold and Misc interrupts are not enabled */

		/* ack rxen only then a new pulse will be generated */
		emac_write(EMAC_DM646X_MACEOIVECTOR,
			EMAC_DM646X_MAC_EOI_C0_RXEN);

		/* ack txen- only then a new pulse will be generated */
		emac_write(EMAC_DM646X_MACEOIVECTOR,
			EMAC_DM646X_MAC_EOI_C0_TXEN);

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		local_irq_restore(flags);

	} else {
		/* Set DM644x control registers for interrupt control */
		emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
	}
}

/**
817
 * emac_int_enable - Enable EMAC module interrupt (from adapter)
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 * @priv: The DaVinci EMAC private adapter structure
 *
 * Enable EMAC interrupt on the adapter
 *
 */
static void emac_int_enable(struct emac_priv *priv)
{
	if (priv->version == EMAC_VERSION_2) {
826 827 828
		if (priv->int_enable)
			priv->int_enable();

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		emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
		emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);

		/* In addition to turning on interrupt Enable, we need
		 * ack by writing appropriate values to the EOI
		 * register */

		/* NOTE: Rx Threshold and Misc interrupts are not enabled */
	} else {
		/* Set DM644x control registers for interrupt control */
		emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
	}
}

/**
844
 * emac_irq - EMAC interrupt handler
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 * @irq: interrupt number
 * @dev_id: EMAC network adapter data structure ptr
 *
 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
 *
 * Returns interrupt handled condition
 */
static irqreturn_t emac_irq(int irq, void *dev_id)
{
	struct net_device *ndev = (struct net_device *)dev_id;
	struct emac_priv *priv = netdev_priv(ndev);

	++priv->isr_count;
	if (likely(netif_running(priv->ndev))) {
		emac_int_disable(priv);
		napi_schedule(&priv->napi);
	} else {
		/* we are closing down, so dont process anything */
	}
	return IRQ_HANDLED;
}

868 869
static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
{
870
	struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size);
871 872 873 874 875 876 877 878 879 880 881 882 883 884 885
	if (WARN_ON(!skb))
		return NULL;
	skb_reserve(skb, NET_IP_ALIGN);
	return skb;
}

static void emac_rx_handler(void *token, int len, int status)
{
	struct sk_buff		*skb = token;
	struct net_device	*ndev = skb->dev;
	struct emac_priv	*priv = netdev_priv(ndev);
	struct device		*emac_dev = &ndev->dev;
	int			ret;

	/* free and bail if we are shutting down */
886
	if (unlikely(!netif_running(ndev))) {
887 888 889 890
		dev_kfree_skb_any(skb);
		return;
	}

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	/* recycle on receive error */
892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913
	if (status < 0) {
		ndev->stats.rx_errors++;
		goto recycle;
	}

	/* feed received packet up the stack */
	skb_put(skb, len);
	skb->protocol = eth_type_trans(skb, ndev);
	netif_receive_skb(skb);
	ndev->stats.rx_bytes += len;
	ndev->stats.rx_packets++;

	/* alloc a new packet for receive */
	skb = emac_rx_alloc(priv);
	if (!skb) {
		if (netif_msg_rx_err(priv) && net_ratelimit())
			dev_err(emac_dev, "failed rx buffer alloc\n");
		return;
	}

recycle:
	ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
914
			skb_tailroom(skb), 0);
915 916 917

	WARN_ON(ret == -ENOMEM);
	if (unlikely(ret < 0))
918 919 920 921 922 923 924 925
		dev_kfree_skb_any(skb);
}

static void emac_tx_handler(void *token, int len, int status)
{
	struct sk_buff		*skb = token;
	struct net_device	*ndev = skb->dev;

926 927 928
	/* Check whether the queue is stopped due to stalled tx dma, if the
	 * queue is stopped then start the queue as we have free desc for tx
	 */
929
	if (unlikely(netif_queue_stopped(ndev)))
930
		netif_wake_queue(ndev);
931 932 933 934 935
	ndev->stats.tx_packets++;
	ndev->stats.tx_bytes += len;
	dev_kfree_skb_any(skb);
}

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/**
937
 * emac_dev_xmit - EMAC Transmit function
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 * @skb: SKB pointer
 * @ndev: The DaVinci EMAC network adapter
 *
 * Called by the system to transmit a packet  - we queue the packet in
 * EMAC hardware transmit queue
 *
 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
 */
static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
{
	struct device *emac_dev = &ndev->dev;
	int ret_code;
	struct emac_priv *priv = netdev_priv(ndev);

	/* If no link, return */
	if (unlikely(!priv->link)) {
		if (netif_msg_tx_err(priv) && net_ratelimit())
			dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
956
		goto fail_tx;
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	}

959 960 961 962 963 964 965
	ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
	if (unlikely(ret_code < 0)) {
		if (netif_msg_tx_err(priv) && net_ratelimit())
			dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
		goto fail_tx;
	}

966 967
	skb_tx_timestamp(skb);

968
	ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
969
				     0);
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	if (unlikely(ret_code != 0)) {
971 972 973
		if (netif_msg_tx_err(priv) && net_ratelimit())
			dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
		goto fail_tx;
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	}

976 977 978
	/* If there is no more tx desc left free then we need to
	 * tell the kernel to stop sending us tx frames.
	 */
979
	if (unlikely(!cpdma_check_free_tx_desc(priv->txchan)))
980 981
		netif_stop_queue(ndev);

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	return NETDEV_TX_OK;
983 984 985 986 987

fail_tx:
	ndev->stats.tx_dropped++;
	netif_stop_queue(ndev);
	return NETDEV_TX_BUSY;
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}

/**
991
 * emac_dev_tx_timeout - EMAC Transmit timeout function
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 * @ndev: The DaVinci EMAC network adapter
 *
 * Called when system detects that a skb timeout period has expired
 * potentially due to a fault in the adapter in not being able to send
 * it out on the wire. We teardown the TX channel assuming a hardware
 * error and re-initialize the TX channel for hardware operation
 *
 */
static void emac_dev_tx_timeout(struct net_device *ndev)
{
	struct emac_priv *priv = netdev_priv(ndev);
	struct device *emac_dev = &ndev->dev;

	if (netif_msg_tx_err(priv))
		dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");

1008
	ndev->stats.tx_errors++;
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	emac_int_disable(priv);
1010 1011
	cpdma_chan_stop(priv->txchan);
	cpdma_chan_start(priv->txchan);
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	emac_int_enable(priv);
}

/**
1016
 * emac_set_type0addr - Set EMAC Type0 mac address
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 * @priv: The DaVinci EMAC private adapter structure
 * @ch: RX channel number
 * @mac_addr: MAC address to set in device
 *
 * Called internally to set Type0 mac address of the adapter (Device)
 *
 * Returns success (0) or appropriate error code (none as of now)
 */
static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
{
	u32 val;
	val = ((mac_addr[5] << 8) | (mac_addr[4]));
	emac_write(EMAC_MACSRCADDRLO, val);

	val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
	       (mac_addr[1] << 8) | (mac_addr[0]));
	emac_write(EMAC_MACSRCADDRHI, val);
	val = emac_read(EMAC_RXUNICASTSET);
	val |= BIT(ch);
	emac_write(EMAC_RXUNICASTSET, val);
	val = emac_read(EMAC_RXUNICASTCLEAR);
	val &= ~BIT(ch);
	emac_write(EMAC_RXUNICASTCLEAR, val);
}

/**
1043
 * emac_set_type1addr - Set EMAC Type1 mac address
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 * @priv: The DaVinci EMAC private adapter structure
 * @ch: RX channel number
 * @mac_addr: MAC address to set in device
 *
 * Called internally to set Type1 mac address of the adapter (Device)
 *
 * Returns success (0) or appropriate error code (none as of now)
 */
static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
{
	u32 val;
	emac_write(EMAC_MACINDEX, ch);
	val = ((mac_addr[5] << 8) | mac_addr[4]);
	emac_write(EMAC_MACADDRLO, val);
	val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
	       (mac_addr[1] << 8) | (mac_addr[0]));
	emac_write(EMAC_MACADDRHI, val);
	emac_set_type0addr(priv, ch, mac_addr);
}

/**
1065
 * emac_set_type2addr - Set EMAC Type2 mac address
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 * @priv: The DaVinci EMAC private adapter structure
 * @ch: RX channel number
 * @mac_addr: MAC address to set in device
 * @index: index into RX address entries
 * @match: match parameter for RX address matching logic
 *
 * Called internally to set Type2 mac address of the adapter (Device)
 *
 * Returns success (0) or appropriate error code (none as of now)
 */
static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
			       char *mac_addr, int index, int match)
{
	u32 val;
	emac_write(EMAC_MACINDEX, index);
	val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
	       (mac_addr[1] << 8) | (mac_addr[0]));
	emac_write(EMAC_MACADDRHI, val);
	val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
	       (match << 19) | BIT(20));
	emac_write(EMAC_MACADDRLO, val);
	emac_set_type0addr(priv, ch, mac_addr);
}

/**
1091
 * emac_setmac - Set mac address in the adapter (internal function)
A
Anant Gole 已提交
1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119
 * @priv: The DaVinci EMAC private adapter structure
 * @ch: RX channel number
 * @mac_addr: MAC address to set in device
 *
 * Called internally to set the mac address of the adapter (Device)
 *
 * Returns success (0) or appropriate error code (none as of now)
 */
static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
{
	struct device *emac_dev = &priv->ndev->dev;

	if (priv->rx_addr_type == 0) {
		emac_set_type0addr(priv, ch, mac_addr);
	} else if (priv->rx_addr_type == 1) {
		u32 cnt;
		for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
			emac_set_type1addr(priv, ch, mac_addr);
	} else if (priv->rx_addr_type == 2) {
		emac_set_type2addr(priv, ch, mac_addr, ch, 1);
		emac_set_type0addr(priv, ch, mac_addr);
	} else {
		if (netif_msg_drv(priv))
			dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
	}
}

/**
1120
 * emac_dev_setmac_addr - Set mac address in the adapter
A
Anant Gole 已提交
1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133
 * @ndev: The DaVinci EMAC network adapter
 * @addr: MAC address to set in device
 *
 * Called by the system to set the mac address of the adapter (Device)
 *
 * Returns success (0) or appropriate error code (none as of now)
 */
static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
{
	struct emac_priv *priv = netdev_priv(ndev);
	struct device *emac_dev = &priv->ndev->dev;
	struct sockaddr *sa = addr;

1134
	if (!is_valid_ether_addr(sa->sa_data))
1135
		return -EADDRNOTAVAIL;
1136

A
Anant Gole 已提交
1137 1138 1139
	/* Store mac addr in priv and rx channel and set it in EMAC hw */
	memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
	memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1140 1141 1142

	/* MAC address is configured only after the interface is enabled. */
	if (netif_running(ndev)) {
1143
		emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1144
	}
A
Anant Gole 已提交
1145 1146

	if (netif_msg_drv(priv))
1147 1148
		dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
					priv->mac_addr);
A
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1149 1150 1151 1152 1153

	return 0;
}

/**
1154
 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception
A
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1155 1156 1157 1158 1159 1160 1161 1162 1163
 * @priv: The DaVinci EMAC private adapter structure
 *
 * Enables EMAC hardware for packet processing - enables PHY, enables RX
 * for packet reception and enables device interrupts and then NAPI
 *
 * Returns success (0) or appropriate error code (none right now)
 */
static int emac_hw_enable(struct emac_priv *priv)
{
1164
	u32 val, mbp_enable, mac_control;
A
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1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208

	/* Soft reset */
	emac_write(EMAC_SOFTRESET, 1);
	while (emac_read(EMAC_SOFTRESET))
		cpu_relax();

	/* Disable interrupt & Set pacing for more interrupts initially */
	emac_int_disable(priv);

	/* Full duplex enable bit set when auto negotiation happens */
	mac_control =
		(((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
		((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
		((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
		((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
	emac_write(EMAC_MACCONTROL, mac_control);

	mbp_enable =
		(((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
		((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
		 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
		 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
		 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
		 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
		 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
		 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
			EMAC_RXMBP_PROMCH_SHIFT) |
		 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
		 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
			EMAC_RXMBP_BROADCH_SHIFT) |
		 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
		 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
			EMAC_RXMBP_MULTICH_SHIFT));
	emac_write(EMAC_RXMBPENABLE, mbp_enable);
	emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
				   EMAC_RX_MAX_LEN_MASK));
	emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
					 EMAC_RX_BUFFER_OFFSET_MASK));
	emac_write(EMAC_RXFILTERLOWTHRESH, 0);
	emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
	priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;

	emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);

1209
	emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
A
Anant Gole 已提交
1210 1211 1212

	/* Enable MII */
	val = emac_read(EMAC_MACCONTROL);
1213
	val |= (EMAC_MACCONTROL_GMIIEN);
A
Anant Gole 已提交
1214 1215 1216 1217 1218 1219 1220 1221 1222 1223
	emac_write(EMAC_MACCONTROL, val);

	/* Enable NAPI and interrupts */
	napi_enable(&priv->napi);
	emac_int_enable(priv);
	return 0;

}

/**
1224
 * emac_poll - EMAC NAPI Poll function
A
Anant Gole 已提交
1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242
 * @ndev: The DaVinci EMAC network adapter
 * @budget: Number of receive packets to process (as told by NAPI layer)
 *
 * NAPI Poll function implemented to process packets as per budget. We check
 * the type of interrupt on the device and accordingly call the TX or RX
 * packet processing functions. We follow the budget for RX processing and
 * also put a cap on number of TX pkts processed through config param. The
 * NAPI schedule function is called if more packets pending.
 *
 * Returns number of packets received (in most cases; else TX pkts - rarely)
 */
static int emac_poll(struct napi_struct *napi, int budget)
{
	unsigned int mask;
	struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
	struct net_device *ndev = priv->ndev;
	struct device *emac_dev = &ndev->dev;
	u32 status = 0;
1243
	u32 num_tx_pkts = 0, num_rx_pkts = 0;
A
Anant Gole 已提交
1244 1245 1246 1247 1248 1249 1250 1251 1252 1253

	/* Check interrupt vectors and call packet processing */
	status = emac_read(EMAC_MACINVECTOR);

	mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;

	if (priv->version == EMAC_VERSION_2)
		mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;

	if (status & mask) {
1254 1255
		num_tx_pkts = cpdma_chan_process(priv->txchan,
					      EMAC_DEF_TX_MAX_SERVICE);
A
Anant Gole 已提交
1256 1257 1258 1259 1260 1261 1262 1263
	} /* TX processing */

	mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;

	if (priv->version == EMAC_VERSION_2)
		mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;

	if (status & mask) {
1264
		num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
A
Anant Gole 已提交
1265 1266
	} /* RX processing */

1267 1268 1269 1270 1271
	mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
	if (priv->version == EMAC_VERSION_2)
		mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;

	if (unlikely(status & mask)) {
A
Anant Gole 已提交
1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296
		u32 ch, cause;
		dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
		netif_stop_queue(ndev);
		napi_disable(&priv->napi);

		status = emac_read(EMAC_MACSTATUS);
		cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
			 EMAC_MACSTATUS_TXERRCODE_SHIFT);
		if (cause) {
			ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
			      EMAC_MACSTATUS_TXERRCH_SHIFT);
			if (net_ratelimit()) {
				dev_err(emac_dev, "TX Host error %s on ch=%d\n",
					&emac_txhost_errcodes[cause][0], ch);
			}
		}
		cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
			 EMAC_MACSTATUS_RXERRCODE_SHIFT);
		if (cause) {
			ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
			      EMAC_MACSTATUS_RXERRCH_SHIFT);
			if (netif_msg_hw(priv) && net_ratelimit())
				dev_err(emac_dev, "RX Host error %s on ch=%d\n",
					&emac_rxhost_errcodes[cause][0], ch);
		}
1297 1298 1299 1300
	} else if (num_rx_pkts < budget) {
		napi_complete(napi);
		emac_int_enable(priv);
	}
A
Anant Gole 已提交
1301

1302
	return num_rx_pkts;
A
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1303 1304 1305 1306
}

#ifdef CONFIG_NET_POLL_CONTROLLER
/**
1307
 * emac_poll_controller - EMAC Poll controller function
A
Anant Gole 已提交
1308 1309 1310 1311 1312
 * @ndev: The DaVinci EMAC network adapter
 *
 * Polled functionality used by netconsole and others in non interrupt mode
 *
 */
1313
static void emac_poll_controller(struct net_device *ndev)
A
Anant Gole 已提交
1314 1315 1316 1317
{
	struct emac_priv *priv = netdev_priv(ndev);

	emac_int_disable(priv);
T
Tonyliu 已提交
1318
	emac_irq(ndev->irq, ndev);
A
Anant Gole 已提交
1319 1320 1321 1322 1323 1324 1325
	emac_int_enable(priv);
}
#endif

static void emac_adjust_link(struct net_device *ndev)
{
	struct emac_priv *priv = netdev_priv(ndev);
1326
	struct phy_device *phydev = ndev->phydev;
A
Anant Gole 已提交
1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354
	unsigned long flags;
	int new_state = 0;

	spin_lock_irqsave(&priv->lock, flags);

	if (phydev->link) {
		/* check the mode of operation - full/half duplex */
		if (phydev->duplex != priv->duplex) {
			new_state = 1;
			priv->duplex = phydev->duplex;
		}
		if (phydev->speed != priv->speed) {
			new_state = 1;
			priv->speed = phydev->speed;
		}
		if (!priv->link) {
			new_state = 1;
			priv->link = 1;
		}

	} else if (priv->link) {
		new_state = 1;
		priv->link = 0;
		priv->speed = 0;
		priv->duplex = ~0;
	}
	if (new_state) {
		emac_update_phystatus(priv);
1355
		phy_print_status(ndev->phydev);
A
Anant Gole 已提交
1356 1357 1358 1359 1360 1361 1362 1363 1364 1365
	}

	spin_unlock_irqrestore(&priv->lock, flags);
}

/*************************************************************************
 *  Linux Driver Model
 *************************************************************************/

/**
1366
 * emac_devioctl - EMAC adapter ioctl
A
Anant Gole 已提交
1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381
 * @ndev: The DaVinci EMAC network adapter
 * @ifrq: request parameter
 * @cmd: command parameter
 *
 * EMAC driver ioctl function
 *
 * Returns success(0) or appropriate error code
 */
static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
{
	if (!(netif_running(ndev)))
		return -EINVAL;

	/* TODO: Add phy read and write and private statistics get feature */

1382 1383
	if (ndev->phydev)
		return phy_mii_ioctl(ndev->phydev, ifrq, cmd);
1384 1385
	else
		return -EOPNOTSUPP;
A
Anant Gole 已提交
1386 1387
}

1388 1389
static int match_first_device(struct device *dev, void *data)
{
1390
	return !strncmp(dev_name(dev), "davinci_mdio", 12);
1391 1392
}

A
Anant Gole 已提交
1393
/**
1394
 * emac_dev_open - EMAC device open
A
Anant Gole 已提交
1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405
 * @ndev: The DaVinci EMAC network adapter
 *
 * Called when system wants to start the interface. We init TX/RX channels
 * and enable the hardware for packet reception/transmission and start the
 * network queue.
 *
 * Returns 0 for a successful open, or appropriate error code
 */
static int emac_dev_open(struct net_device *ndev)
{
	struct device *emac_dev = &ndev->dev;
1406
	u32 cnt;
A
Anant Gole 已提交
1407
	struct resource *res;
1408
	int q, m, ret;
1409
	int res_num = 0, irq_num = 0;
A
Anant Gole 已提交
1410 1411
	int i = 0;
	struct emac_priv *priv = netdev_priv(ndev);
1412
	struct phy_device *phydev = NULL;
A
Anant Gole 已提交
1413

1414 1415 1416 1417 1418 1419 1420
	ret = pm_runtime_get_sync(&priv->pdev->dev);
	if (ret < 0) {
		pm_runtime_put_noidle(&priv->pdev->dev);
		dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
			__func__, ret);
		return ret;
	}
1421

A
Anant Gole 已提交
1422
	netif_carrier_off(ndev);
D
Dan Carpenter 已提交
1423
	for (cnt = 0; cnt < ETH_ALEN; cnt++)
A
Anant Gole 已提交
1424 1425 1426 1427 1428 1429 1430 1431 1432 1433
		ndev->dev_addr[cnt] = priv->mac_addr[cnt];

	/* Configuration items */
	priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;

	priv->mac_hash1 = 0;
	priv->mac_hash2 = 0;
	emac_write(EMAC_MACHASH1, 0);
	emac_write(EMAC_MACHASH2, 0);

1434 1435 1436 1437 1438 1439 1440
	for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
		struct sk_buff *skb = emac_rx_alloc(priv);

		if (!skb)
			break;

		ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1441
					skb_tailroom(skb), 0);
1442 1443
		if (WARN_ON(ret < 0))
			break;
A
Anant Gole 已提交
1444 1445 1446
	}

	/* Request IRQ */
1447 1448 1449 1450 1451 1452 1453 1454
	while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ,
					    res_num))) {
		for (irq_num = res->start; irq_num <= res->end; irq_num++) {
			if (request_irq(irq_num, emac_irq, 0, ndev->name,
					ndev)) {
				dev_err(emac_dev,
					"DaVinci EMAC: request_irq() failed\n");
				ret = -EBUSY;
A
Anant Gole 已提交
1455 1456

				goto rollback;
1457
			}
A
Anant Gole 已提交
1458
		}
1459
		res_num++;
A
Anant Gole 已提交
1460
	}
1461 1462 1463
	/* prepare counters for rollback in case of an error */
	res_num--;
	irq_num--;
A
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1464 1465 1466 1467

	/* Start/Enable EMAC hardware */
	emac_hw_enable(priv);

1468 1469 1470 1471 1472 1473 1474 1475
	/* Enable Interrupt pacing if configured */
	if (priv->coal_intvl != 0) {
		struct ethtool_coalesce coal;

		coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
		emac_set_coalesce(ndev, &coal);
	}

1476 1477
	cpdma_ctlr_start(priv->dma);

1478
	if (priv->phy_node) {
1479 1480 1481
		phydev = of_phy_connect(ndev, priv->phy_node,
					&emac_adjust_link, 0, 0);
		if (!phydev) {
1482 1483 1484 1485 1486 1487 1488
			dev_err(emac_dev, "could not connect to phy %s\n",
				priv->phy_node->full_name);
			ret = -ENODEV;
			goto err;
		}
	}

1489
	/* use the first phy on the bus if pdata did not give us a phy id */
1490
	if (!phydev && !priv->phy_id) {
1491
		struct device *phy;
A
Anant Gole 已提交
1492

1493 1494 1495 1496 1497
		phy = bus_find_device(&mdio_bus_type, NULL, NULL,
				      match_first_device);
		if (phy)
			priv->phy_id = dev_name(phy);
	}
A
Anant Gole 已提交
1498

1499 1500 1501 1502
	if (!phydev && priv->phy_id && *priv->phy_id) {
		phydev = phy_connect(ndev, priv->phy_id,
				     &emac_adjust_link,
				     PHY_INTERFACE_MODE_MII);
A
Anant Gole 已提交
1503

1504
		if (IS_ERR(phydev)) {
1505 1506
			dev_err(emac_dev, "could not connect to phy %s\n",
				priv->phy_id);
1507
			ret = PTR_ERR(phydev);
1508
			goto err;
A
Anant Gole 已提交
1509 1510 1511 1512 1513 1514
		}

		priv->link = 0;
		priv->speed = 0;
		priv->duplex = ~0;

1515
		phy_attached_info(phydev);
1516 1517
	}

1518
	if (!phydev) {
A
Anant Gole 已提交
1519
		/* No PHY , fix the link, speed and duplex settings */
1520
		dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
A
Anant Gole 已提交
1521 1522 1523 1524 1525 1526 1527 1528 1529
		priv->link = 1;
		priv->speed = SPEED_100;
		priv->duplex = DUPLEX_FULL;
		emac_update_phystatus(priv);
	}

	if (netif_msg_drv(priv))
		dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);

1530 1531
	if (phydev)
		phy_start(phydev);
A
Anant Gole 已提交
1532 1533 1534

	return 0;

1535 1536 1537
err:
	emac_int_disable(priv);
	napi_disable(&priv->napi);
1538

1539 1540 1541 1542 1543 1544 1545 1546 1547 1548
rollback:
	for (q = res_num; q >= 0; q--) {
		res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q);
		/* at the first iteration, irq_num is already set to the
		 * right value
		 */
		if (q != res_num)
			irq_num = res->end;

		for (m = irq_num; m >= res->start; m--)
1549 1550
			free_irq(m, ndev);
	}
1551
	cpdma_ctlr_stop(priv->dma);
1552 1553
	pm_runtime_put(&priv->pdev->dev);
	return ret;
A
Anant Gole 已提交
1554 1555 1556
}

/**
1557
 * emac_dev_stop - EMAC device stop
A
Anant Gole 已提交
1558 1559 1560 1561 1562 1563 1564 1565 1566
 * @ndev: The DaVinci EMAC network adapter
 *
 * Called when system wants to stop or down the interface. We stop the network
 * queue, disable interrupts and cleanup TX/RX channels.
 *
 * We return the statistics in net_device_stats structure pulled from emac
 */
static int emac_dev_stop(struct net_device *ndev)
{
1567 1568 1569
	struct resource *res;
	int i = 0;
	int irq_num;
A
Anant Gole 已提交
1570 1571 1572 1573 1574 1575 1576 1577 1578
	struct emac_priv *priv = netdev_priv(ndev);
	struct device *emac_dev = &ndev->dev;

	/* inform the upper layers. */
	netif_stop_queue(ndev);
	napi_disable(&priv->napi);

	netif_carrier_off(ndev);
	emac_int_disable(priv);
1579
	cpdma_ctlr_stop(priv->dma);
A
Anant Gole 已提交
1580 1581
	emac_write(EMAC_SOFTRESET, 1);

1582 1583
	if (ndev->phydev)
		phy_disconnect(ndev->phydev);
A
Anant Gole 已提交
1584

1585 1586 1587 1588 1589 1590 1591
	/* Free IRQ */
	while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
		for (irq_num = res->start; irq_num <= res->end; irq_num++)
			free_irq(irq_num, priv->ndev);
		i++;
	}

A
Anant Gole 已提交
1592 1593 1594
	if (netif_msg_drv(priv))
		dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);

1595
	pm_runtime_put(&priv->pdev->dev);
A
Anant Gole 已提交
1596 1597 1598 1599
	return 0;
}

/**
1600
 * emac_dev_getnetstats - EMAC get statistics function
A
Anant Gole 已提交
1601 1602 1603 1604 1605 1606 1607 1608 1609
 * @ndev: The DaVinci EMAC network adapter
 *
 * Called when system wants to get statistics from the device.
 *
 * We return the statistics in net_device_stats structure pulled from emac
 */
static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
{
	struct emac_priv *priv = netdev_priv(ndev);
1610 1611
	u32 mac_control;
	u32 stats_clear_mask;
1612 1613 1614 1615 1616 1617 1618 1619 1620
	int err;

	err = pm_runtime_get_sync(&priv->pdev->dev);
	if (err < 0) {
		pm_runtime_put_noidle(&priv->pdev->dev);
		dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
			__func__, err);
		return &ndev->stats;
	}
A
Anant Gole 已提交
1621 1622 1623

	/* update emac hardware stats and reset the registers*/

1624 1625 1626 1627 1628 1629 1630
	mac_control = emac_read(EMAC_MACCONTROL);

	if (mac_control & EMAC_MACCONTROL_GMIIEN)
		stats_clear_mask = EMAC_STATS_CLR_MASK;
	else
		stats_clear_mask = 0;

1631
	ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1632
	emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
A
Anant Gole 已提交
1633

1634
	ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
A
Anant Gole 已提交
1635 1636
					   emac_read(EMAC_TXSINGLECOLL) +
					   emac_read(EMAC_TXMULTICOLL));
1637 1638 1639
	emac_write(EMAC_TXCOLLISION, stats_clear_mask);
	emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
	emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
A
Anant Gole 已提交
1640

1641
	ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
A
Anant Gole 已提交
1642 1643
						emac_read(EMAC_RXJABBER) +
						emac_read(EMAC_RXUNDERSIZED));
1644 1645 1646
	emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
	emac_write(EMAC_RXJABBER, stats_clear_mask);
	emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
A
Anant Gole 已提交
1647

1648
	ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
A
Anant Gole 已提交
1649
					       emac_read(EMAC_RXMOFOVERRUNS));
1650 1651
	emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
	emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
A
Anant Gole 已提交
1652

1653
	ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1654
	emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
A
Anant Gole 已提交
1655

1656
	ndev->stats.tx_carrier_errors +=
A
Anant Gole 已提交
1657
		emac_read(EMAC_TXCARRIERSENSE);
1658
	emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
A
Anant Gole 已提交
1659

1660
	ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1661
	emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
A
Anant Gole 已提交
1662

1663 1664
	pm_runtime_put(&priv->pdev->dev);

1665
	return &ndev->stats;
A
Anant Gole 已提交
1666 1667 1668 1669 1670 1671
}

static const struct net_device_ops emac_netdev_ops = {
	.ndo_open		= emac_dev_open,
	.ndo_stop		= emac_dev_stop,
	.ndo_start_xmit		= emac_dev_xmit,
1672
	.ndo_set_rx_mode	= emac_dev_mcast_set,
A
Anant Gole 已提交
1673 1674 1675 1676 1677 1678 1679 1680 1681
	.ndo_set_mac_address	= emac_dev_setmac_addr,
	.ndo_do_ioctl		= emac_devioctl,
	.ndo_tx_timeout		= emac_dev_tx_timeout,
	.ndo_get_stats		= emac_dev_getnetstats,
#ifdef CONFIG_NET_POLL_CONTROLLER
	.ndo_poll_controller	= emac_poll_controller,
#endif
};

1682 1683
static const struct of_device_id davinci_emac_of_match[];

1684 1685
static struct emac_platform_data *
davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv)
1686 1687
{
	struct device_node *np;
1688 1689
	const struct of_device_id *match;
	const struct emac_platform_data *auxdata;
1690 1691 1692
	struct emac_platform_data *pdata = NULL;
	const u8 *mac_addr;

1693
	if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
1694
		return dev_get_platdata(&pdev->dev);
1695 1696 1697 1698

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return NULL;
1699 1700

	np = pdev->dev.of_node;
1701
	pdata->version = EMAC_VERSION_2;
1702 1703 1704 1705

	if (!is_valid_ether_addr(pdata->mac_addr)) {
		mac_addr = of_get_mac_address(np);
		if (mac_addr)
1706
			ether_addr_copy(pdata->mac_addr, mac_addr);
1707 1708
	}

1709 1710
	of_property_read_u32(np, "ti,davinci-ctrl-reg-offset",
			     &pdata->ctrl_reg_offset);
1711

1712 1713
	of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
			     &pdata->ctrl_mod_reg_offset);
1714

1715 1716
	of_property_read_u32(np, "ti,davinci-ctrl-ram-offset",
			     &pdata->ctrl_ram_offset);
1717

1718 1719
	of_property_read_u32(np, "ti,davinci-ctrl-ram-size",
			     &pdata->ctrl_ram_size);
1720

1721
	of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en);
1722

1723
	pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram");
1724 1725

	priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
1726 1727 1728 1729 1730 1731
	if (!priv->phy_node) {
		if (!of_phy_is_fixed_link(np))
			pdata->phy_id = NULL;
		else if (of_phy_register_fixed_link(np) >= 0)
			priv->phy_node = of_node_get(np);
	}
1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744

	auxdata = pdev->dev.platform_data;
	if (auxdata) {
		pdata->interrupt_enable = auxdata->interrupt_enable;
		pdata->interrupt_disable = auxdata->interrupt_disable;
	}

	match = of_match_device(davinci_emac_of_match, &pdev->dev);
	if (match && match->data) {
		auxdata = match->data;
		pdata->version = auxdata->version;
		pdata->hw_ram_addr = auxdata->hw_ram_addr;
	}
1745 1746 1747

	return  pdata;
}
1748

1749 1750 1751 1752
static int davinci_emac_try_get_mac(struct platform_device *pdev,
				    int instance, u8 *mac_addr)
{
	if (!pdev->dev.of_node)
1753 1754 1755
		return -EINVAL;

	return ti_cm_get_macid(&pdev->dev, instance, mac_addr);
1756 1757
}

A
Anant Gole 已提交
1758
/**
1759
 * davinci_emac_probe - EMAC device probe
A
Anant Gole 已提交
1760 1761 1762 1763 1764 1765
 * @pdev: The DaVinci EMAC device that we are removing
 *
 * Called when probing for emac devicesr. We get details of instances and
 * resource information from platform init and register a network device
 * and allocate resources necessary for driver to perform
 */
1766
static int davinci_emac_probe(struct platform_device *pdev)
A
Anant Gole 已提交
1767 1768
{
	int rc = 0;
1769
	struct resource *res, *res_ctrl;
A
Anant Gole 已提交
1770 1771
	struct net_device *ndev;
	struct emac_priv *priv;
1772
	unsigned long hw_ram_addr;
A
Anant Gole 已提交
1773
	struct emac_platform_data *pdata;
1774
	struct cpdma_params dma_params;
1775 1776 1777
	struct clk *emac_clk;
	unsigned long emac_bus_frequency;

A
Anant Gole 已提交
1778 1779

	/* obtain emac clock from kernel */
S
Sekhar Nori 已提交
1780
	emac_clk = devm_clk_get(&pdev->dev, NULL);
A
Anant Gole 已提交
1781
	if (IS_ERR(emac_clk)) {
1782
		dev_err(&pdev->dev, "failed to get EMAC clock\n");
A
Anant Gole 已提交
1783 1784 1785
		return -EBUSY;
	}
	emac_bus_frequency = clk_get_rate(emac_clk);
1786
	devm_clk_put(&pdev->dev, emac_clk);
1787

A
Anant Gole 已提交
1788 1789 1790
	/* TODO: Probe PHY here if possible */

	ndev = alloc_etherdev(sizeof(struct emac_priv));
S
Sekhar Nori 已提交
1791 1792
	if (!ndev)
		return -ENOMEM;
A
Anant Gole 已提交
1793 1794 1795 1796 1797 1798 1799 1800 1801

	platform_set_drvdata(pdev, ndev);
	priv = netdev_priv(ndev);
	priv->pdev = pdev;
	priv->ndev = ndev;
	priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);

	spin_lock_init(&priv->lock);

1802
	pdata = davinci_emac_of_get_pdata(pdev, priv);
A
Anant Gole 已提交
1803
	if (!pdata) {
1804
		dev_err(&pdev->dev, "no platform data\n");
1805
		rc = -ENODEV;
S
Sekhar Nori 已提交
1806
		goto no_pdata;
A
Anant Gole 已提交
1807 1808 1809
	}

	/* MAC addr and PHY mask , RMII enable info from platform_data */
1810
	memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN);
1811
	priv->phy_id = pdata->phy_id;
A
Anant Gole 已提交
1812 1813
	priv->rmii_en = pdata->rmii_en;
	priv->version = pdata->version;
1814 1815 1816
	priv->int_enable = pdata->interrupt_enable;
	priv->int_disable = pdata->interrupt_disable;

1817 1818 1819
	priv->coal_intvl = 0;
	priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);

A
Anant Gole 已提交
1820 1821 1822
	/* Get EMAC platform data */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1823 1824 1825
	priv->remap_addr = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(priv->remap_addr)) {
		rc = PTR_ERR(priv->remap_addr);
S
Sekhar Nori 已提交
1826
		goto no_pdata;
A
Anant Gole 已提交
1827
	}
1828 1829 1830 1831 1832

	res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (res_ctrl) {
		priv->ctrl_base =
			devm_ioremap_resource(&pdev->dev, res_ctrl);
1833 1834
		if (IS_ERR(priv->ctrl_base)) {
			rc = PTR_ERR(priv->ctrl_base);
1835
			goto no_pdata;
1836
		}
1837 1838 1839 1840
	} else {
		priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
	}

A
Anant Gole 已提交
1841 1842 1843
	priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
	ndev->base_addr = (unsigned long)priv->remap_addr;

1844 1845 1846 1847 1848
	hw_ram_addr = pdata->hw_ram_addr;
	if (!hw_ram_addr)
		hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;

	memset(&dma_params, 0, sizeof(dma_params));
1849
	dma_params.dev			= &pdev->dev;
1850 1851 1852 1853 1854 1855 1856 1857 1858
	dma_params.dmaregs		= priv->emac_base;
	dma_params.rxthresh		= priv->emac_base + 0x120;
	dma_params.rxfree		= priv->emac_base + 0x140;
	dma_params.txhdp		= priv->emac_base + 0x600;
	dma_params.rxhdp		= priv->emac_base + 0x620;
	dma_params.txcp			= priv->emac_base + 0x640;
	dma_params.rxcp			= priv->emac_base + 0x660;
	dma_params.num_chan		= EMAC_MAX_TXRX_CHANNELS;
	dma_params.min_packet_size	= EMAC_DEF_MIN_ETHPKTSIZE;
1859
	dma_params.desc_hw_addr		= hw_ram_addr;
1860 1861 1862
	dma_params.desc_mem_size	= pdata->ctrl_ram_size;
	dma_params.desc_align		= 16;

1863 1864 1865
	dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
			(u32 __force)res->start + pdata->ctrl_ram_offset;

1866 1867
	priv->dma = cpdma_ctlr_create(&dma_params);
	if (!priv->dma) {
1868
		dev_err(&pdev->dev, "error initializing DMA\n");
1869
		rc = -ENOMEM;
S
Sekhar Nori 已提交
1870
		goto no_pdata;
1871 1872 1873 1874 1875 1876 1877 1878
	}

	priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
				       emac_tx_handler);
	priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
				       emac_rx_handler);
	if (WARN_ON(!priv->txchan || !priv->rxchan)) {
		rc = -ENOMEM;
S
Sekhar Nori 已提交
1879
		goto no_cpdma_chan;
1880
	}
1881

A
Anant Gole 已提交
1882 1883
	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!res) {
1884
		dev_err(&pdev->dev, "error getting irq res\n");
A
Anant Gole 已提交
1885
		rc = -ENOENT;
S
Sekhar Nori 已提交
1886
		goto no_cpdma_chan;
A
Anant Gole 已提交
1887 1888 1889
	}
	ndev->irq = res->start;

1890 1891 1892 1893
	rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr);
	if (!rc)
		ether_addr_copy(ndev->dev_addr, priv->mac_addr);

A
Anant Gole 已提交
1894 1895
	if (!is_valid_ether_addr(priv->mac_addr)) {
		/* Use random MAC if none passed */
1896 1897
		eth_hw_addr_random(ndev);
		memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len);
1898 1899
		dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
							priv->mac_addr);
A
Anant Gole 已提交
1900 1901 1902
	}

	ndev->netdev_ops = &emac_netdev_ops;
1903
	ndev->ethtool_ops = &ethtool_ops;
A
Anant Gole 已提交
1904 1905
	netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);

1906 1907 1908 1909 1910 1911 1912 1913 1914
	pm_runtime_enable(&pdev->dev);
	rc = pm_runtime_get_sync(&pdev->dev);
	if (rc < 0) {
		pm_runtime_put_noidle(&pdev->dev);
		dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n",
			__func__, rc);
		goto no_cpdma_chan;
	}

A
Anant Gole 已提交
1915 1916 1917 1918
	/* register the network device */
	SET_NETDEV_DEV(ndev, &pdev->dev);
	rc = register_netdev(ndev);
	if (rc) {
1919
		dev_err(&pdev->dev, "error in register_netdev\n");
A
Anant Gole 已提交
1920
		rc = -ENODEV;
1921
		pm_runtime_put(&pdev->dev);
S
Sekhar Nori 已提交
1922
		goto no_cpdma_chan;
A
Anant Gole 已提交
1923 1924 1925 1926
	}


	if (netif_msg_probe(priv)) {
1927
		dev_notice(&pdev->dev, "DaVinci EMAC Probe found device "
A
Anant Gole 已提交
1928 1929 1930
			   "(regs: %p, irq: %d)\n",
			   (void *)priv->emac_base_phys, ndev->irq);
	}
1931
	pm_runtime_put(&pdev->dev);
1932

A
Anant Gole 已提交
1933 1934
	return 0;

S
Sekhar Nori 已提交
1935
no_cpdma_chan:
1936 1937 1938 1939 1940
	if (priv->txchan)
		cpdma_chan_destroy(priv->txchan);
	if (priv->rxchan)
		cpdma_chan_destroy(priv->rxchan);
	cpdma_ctlr_destroy(priv->dma);
S
Sekhar Nori 已提交
1941
no_pdata:
A
Anant Gole 已提交
1942 1943 1944 1945 1946
	free_netdev(ndev);
	return rc;
}

/**
1947
 * davinci_emac_remove - EMAC device remove
A
Anant Gole 已提交
1948 1949 1950 1951 1952
 * @pdev: The DaVinci EMAC device that we are removing
 *
 * Called when removing the device driver. We disable clock usage and release
 * the resources taken up by the driver and unregister network device
 */
1953
static int davinci_emac_remove(struct platform_device *pdev)
A
Anant Gole 已提交
1954 1955 1956 1957 1958 1959
{
	struct net_device *ndev = platform_get_drvdata(pdev);
	struct emac_priv *priv = netdev_priv(ndev);

	dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");

1960 1961 1962 1963 1964 1965
	if (priv->txchan)
		cpdma_chan_destroy(priv->txchan);
	if (priv->rxchan)
		cpdma_chan_destroy(priv->rxchan);
	cpdma_ctlr_destroy(priv->dma);

A
Anant Gole 已提交
1966
	unregister_netdev(ndev);
1967
	of_node_put(priv->phy_node);
1968
	pm_runtime_disable(&pdev->dev);
1969
	free_netdev(ndev);
A
Anant Gole 已提交
1970 1971 1972 1973

	return 0;
}

1974
static int davinci_emac_suspend(struct device *dev)
1975
{
1976 1977
	struct platform_device *pdev = to_platform_device(dev);
	struct net_device *ndev = platform_get_drvdata(pdev);
1978

1979 1980
	if (netif_running(ndev))
		emac_dev_stop(ndev);
1981 1982 1983 1984

	return 0;
}

1985
static int davinci_emac_resume(struct device *dev)
1986
{
1987 1988
	struct platform_device *pdev = to_platform_device(dev);
	struct net_device *ndev = platform_get_drvdata(pdev);
1989

1990 1991
	if (netif_running(ndev))
		emac_dev_open(ndev);
1992 1993 1994 1995

	return 0;
}

1996 1997 1998 1999 2000
static const struct dev_pm_ops davinci_emac_pm_ops = {
	.suspend	= davinci_emac_suspend,
	.resume		= davinci_emac_resume,
};

2001
#if IS_ENABLED(CONFIG_OF)
2002 2003 2004 2005 2006
static const struct emac_platform_data am3517_emac_data = {
	.version		= EMAC_VERSION_2,
	.hw_ram_addr		= 0x01e20000,
};

2007 2008 2009 2010
static const struct emac_platform_data dm816_emac_data = {
	.version		= EMAC_VERSION_2,
};

2011 2012
static const struct of_device_id davinci_emac_of_match[] = {
	{.compatible = "ti,davinci-dm6467-emac", },
2013
	{.compatible = "ti,am3517-emac", .data = &am3517_emac_data, },
2014
	{.compatible = "ti,dm816-emac", .data = &dm816_emac_data, },
2015 2016 2017
	{},
};
MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
2018
#endif
2019

2020
/* davinci_emac_driver: EMAC platform driver structure */
A
Anant Gole 已提交
2021 2022 2023
static struct platform_driver davinci_emac_driver = {
	.driver = {
		.name	 = "davinci_emac",
2024
		.pm	 = &davinci_emac_pm_ops,
2025
		.of_match_table = of_match_ptr(davinci_emac_of_match),
A
Anant Gole 已提交
2026 2027
	},
	.probe = davinci_emac_probe,
2028
	.remove = davinci_emac_remove,
A
Anant Gole 已提交
2029 2030 2031
};

/**
2032
 * davinci_emac_init - EMAC driver module init
A
Anant Gole 已提交
2033 2034 2035 2036 2037 2038 2039 2040
 *
 * Called when initializing the driver. We register the driver with
 * the platform.
 */
static int __init davinci_emac_init(void)
{
	return platform_driver_register(&davinci_emac_driver);
}
2041
late_initcall(davinci_emac_init);
A
Anant Gole 已提交
2042 2043

/**
2044
 * davinci_emac_exit - EMAC driver module exit
A
Anant Gole 已提交
2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058
 *
 * Called when exiting the driver completely. We unregister the driver with
 * the platform and exit
 */
static void __exit davinci_emac_exit(void)
{
	platform_driver_unregister(&davinci_emac_driver);
}
module_exit(davinci_emac_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");