amdgpu_object.c 26.2 KB
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/*
 * Copyright 2009 Jerome Glisse.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
 *    Dave Airlie
 */
#include <linux/list.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include <drm/amdgpu_drm.h>
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#include <drm/drm_cache.h>
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#include "amdgpu.h"
#include "amdgpu_trace.h"



static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev,
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						struct ttm_mem_reg *mem)
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{
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	if (mem->start << PAGE_SHIFT >= adev->mc.visible_vram_size)
		return 0;

	return ((mem->start << PAGE_SHIFT) + mem->size) >
		adev->mc.visible_vram_size ?
		adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) :
		mem->size;
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}

static void amdgpu_update_memory_usage(struct amdgpu_device *adev,
		       struct ttm_mem_reg *old_mem,
		       struct ttm_mem_reg *new_mem)
{
	u64 vis_size;
	if (!adev)
		return;

	if (new_mem) {
		switch (new_mem->mem_type) {
		case TTM_PL_TT:
			atomic64_add(new_mem->size, &adev->gtt_usage);
			break;
		case TTM_PL_VRAM:
			atomic64_add(new_mem->size, &adev->vram_usage);
			vis_size = amdgpu_get_vis_part_size(adev, new_mem);
			atomic64_add(vis_size, &adev->vram_vis_usage);
			break;
		}
	}

	if (old_mem) {
		switch (old_mem->mem_type) {
		case TTM_PL_TT:
			atomic64_sub(old_mem->size, &adev->gtt_usage);
			break;
		case TTM_PL_VRAM:
			atomic64_sub(old_mem->size, &adev->vram_usage);
			vis_size = amdgpu_get_vis_part_size(adev, old_mem);
			atomic64_sub(vis_size, &adev->vram_vis_usage);
			break;
		}
	}
}

static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
{
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	struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
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	struct amdgpu_bo *bo;

	bo = container_of(tbo, struct amdgpu_bo, tbo);

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	amdgpu_bo_kunmap(bo);
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	amdgpu_update_memory_usage(adev, &bo->tbo.mem, NULL);
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	drm_gem_object_release(&bo->gem_base);
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	amdgpu_bo_unref(&bo->parent);
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	if (!list_empty(&bo->shadow_list)) {
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		mutex_lock(&adev->shadow_list_lock);
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		list_del_init(&bo->shadow_list);
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		mutex_unlock(&adev->shadow_list_lock);
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	}
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	kfree(bo->metadata);
	kfree(bo);
}

bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
{
	if (bo->destroy == &amdgpu_ttm_bo_destroy)
		return true;
	return false;
}

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static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
				      struct ttm_placement *placement,
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				      struct ttm_place *places,
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				      u32 domain, u64 flags)
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{
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	u32 c = 0;
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	if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
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		unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT;

		places[c].fpfn = 0;
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		places[c].lpfn = 0;
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		places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
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			TTM_PL_FLAG_VRAM;
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		if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
			places[c].lpfn = visible_pfn;
		else
			places[c].flags |= TTM_PL_FLAG_TOPDOWN;
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		if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
			places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
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		c++;
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	}

	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
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		places[c].fpfn = 0;
		places[c].lpfn = 0;
		places[c].flags = TTM_PL_FLAG_TT;
		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
			places[c].flags |= TTM_PL_FLAG_WC |
				TTM_PL_FLAG_UNCACHED;
		else
			places[c].flags |= TTM_PL_FLAG_CACHED;
		c++;
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	}

	if (domain & AMDGPU_GEM_DOMAIN_CPU) {
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		places[c].fpfn = 0;
		places[c].lpfn = 0;
		places[c].flags = TTM_PL_FLAG_SYSTEM;
		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
			places[c].flags |= TTM_PL_FLAG_WC |
				TTM_PL_FLAG_UNCACHED;
		else
			places[c].flags |= TTM_PL_FLAG_CACHED;
		c++;
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	}

	if (domain & AMDGPU_GEM_DOMAIN_GDS) {
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		places[c].fpfn = 0;
		places[c].lpfn = 0;
		places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
		c++;
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	}
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	if (domain & AMDGPU_GEM_DOMAIN_GWS) {
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		places[c].fpfn = 0;
		places[c].lpfn = 0;
		places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
		c++;
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	}
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	if (domain & AMDGPU_GEM_DOMAIN_OA) {
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		places[c].fpfn = 0;
		places[c].lpfn = 0;
		places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
		c++;
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	}

	if (!c) {
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		places[c].fpfn = 0;
		places[c].lpfn = 0;
		places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
		c++;
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	}
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	placement->num_placement = c;
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	placement->placement = places;
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	placement->num_busy_placement = c;
	placement->busy_placement = places;
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}

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void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
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{
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	struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);

	amdgpu_ttm_placement_init(adev, &abo->placement, abo->placements,
				  domain, abo->flags);
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}

static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
					struct ttm_placement *placement)
{
	BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1));

	memcpy(bo->placements, placement->placement,
	       placement->num_placement * sizeof(struct ttm_place));
	bo->placement.num_placement = placement->num_placement;
	bo->placement.num_busy_placement = placement->num_busy_placement;
	bo->placement.placement = bo->placements;
	bo->placement.busy_placement = bo->placements;
}

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/**
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 * amdgpu_bo_create_reserved - create reserved BO for kernel use
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 *
 * @adev: amdgpu device object
 * @size: size for the new BO
 * @align: alignment for the new BO
 * @domain: where to place it
 * @bo_ptr: resulting BO
 * @gpu_addr: GPU addr of the pinned BO
 * @cpu_addr: optional CPU address mapping
 *
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 * Allocates and pins a BO for kernel internal use, and returns it still
 * reserved.
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 *
 * Returns 0 on success, negative error code otherwise.
 */
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int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
			      unsigned long size, int align,
			      u32 domain, struct amdgpu_bo **bo_ptr,
			      u64 *gpu_addr, void **cpu_addr)
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{
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	bool free = false;
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	int r;

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	if (!*bo_ptr) {
		r = amdgpu_bo_create(adev, size, align, true, domain,
				     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
				     AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
				     NULL, NULL, bo_ptr);
		if (r) {
			dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
				r);
			return r;
		}
		free = true;
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	}

	r = amdgpu_bo_reserve(*bo_ptr, false);
	if (r) {
		dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
		goto error_free;
	}

	r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
	if (r) {
		dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
		goto error_unreserve;
	}

	if (cpu_addr) {
		r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
		if (r) {
			dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
			goto error_unreserve;
		}
	}

	return 0;

error_unreserve:
	amdgpu_bo_unreserve(*bo_ptr);

error_free:
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	if (free)
		amdgpu_bo_unref(bo_ptr);
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	return r;
}

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/**
 * amdgpu_bo_create_kernel - create BO for kernel use
 *
 * @adev: amdgpu device object
 * @size: size for the new BO
 * @align: alignment for the new BO
 * @domain: where to place it
 * @bo_ptr: resulting BO
 * @gpu_addr: GPU addr of the pinned BO
 * @cpu_addr: optional CPU address mapping
 *
 * Allocates and pins a BO for kernel internal use.
 *
 * Returns 0 on success, negative error code otherwise.
 */
int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
			    unsigned long size, int align,
			    u32 domain, struct amdgpu_bo **bo_ptr,
			    u64 *gpu_addr, void **cpu_addr)
{
	int r;

	r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
				      gpu_addr, cpu_addr);

	if (r)
		return r;

	amdgpu_bo_unreserve(*bo_ptr);

	return 0;
}

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/**
 * amdgpu_bo_free_kernel - free BO for kernel use
 *
 * @bo: amdgpu BO to free
 *
 * unmaps and unpin a BO for kernel internal use.
 */
void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
			   void **cpu_addr)
{
	if (*bo == NULL)
		return;

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	if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
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		if (cpu_addr)
			amdgpu_bo_kunmap(*bo);

		amdgpu_bo_unpin(*bo);
		amdgpu_bo_unreserve(*bo);
	}
	amdgpu_bo_unref(bo);

	if (gpu_addr)
		*gpu_addr = 0;

	if (cpu_addr)
		*cpu_addr = NULL;
}

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int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
				unsigned long size, int byte_align,
				bool kernel, u32 domain, u64 flags,
				struct sg_table *sg,
				struct ttm_placement *placement,
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				struct reservation_object *resv,
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				struct amdgpu_bo **bo_ptr)
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{
	struct amdgpu_bo *bo;
	enum ttm_bo_type type;
	unsigned long page_align;
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	u64 initial_bytes_moved, bytes_moved;
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	size_t acc_size;
	int r;

	page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
	size = ALIGN(size, PAGE_SIZE);

	if (kernel) {
		type = ttm_bo_type_kernel;
	} else if (sg) {
		type = ttm_bo_type_sg;
	} else {
		type = ttm_bo_type_device;
	}
	*bo_ptr = NULL;

	acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
				       sizeof(struct amdgpu_bo));

	bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
	if (bo == NULL)
		return -ENOMEM;
	r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
	if (unlikely(r)) {
		kfree(bo);
		return r;
	}
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	INIT_LIST_HEAD(&bo->shadow_list);
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	INIT_LIST_HEAD(&bo->va);
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	bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
					 AMDGPU_GEM_DOMAIN_GTT |
					 AMDGPU_GEM_DOMAIN_CPU |
					 AMDGPU_GEM_DOMAIN_GDS |
					 AMDGPU_GEM_DOMAIN_GWS |
					 AMDGPU_GEM_DOMAIN_OA);
	bo->allowed_domains = bo->prefered_domains;
	if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
		bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
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	bo->flags = flags;
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#ifdef CONFIG_X86_32
	/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
	 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
	 */
	bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
	/* Don't try to enable write-combining when it can't work, or things
	 * may be slow
	 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
	 */

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#ifndef CONFIG_COMPILE_TEST
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#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
	 thanks to write-combining
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#endif
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	if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
		DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
			      "better performance thanks to write-combining\n");
	bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
#else
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	/* For architectures that don't support WC memory,
	 * mask out the WC flag from the BO
	 */
	if (!drm_arch_can_wc_memory())
		bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
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#endif
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	amdgpu_fill_placement_to_bo(bo, placement);
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	/* Kernel allocation are uninterruptible */
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	initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
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	r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
				 &bo->placement, page_align, !kernel, NULL,
				 acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
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	bytes_moved = atomic64_read(&adev->num_bytes_moved) -
		      initial_bytes_moved;
	if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
	    bo->tbo.mem.mem_type == TTM_PL_VRAM &&
	    bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT)
		amdgpu_cs_report_moved_bytes(adev, bytes_moved, bytes_moved);
	else
		amdgpu_cs_report_moved_bytes(adev, bytes_moved, 0);
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	if (unlikely(r != 0))
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		return r;
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	if (kernel)
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		bo->tbo.priority = 1;
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	if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
	    bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
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		struct dma_fence *fence;
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		r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
		if (unlikely(r))
			goto fail_unreserve;

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		amdgpu_bo_fence(bo, fence, false);
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		dma_fence_put(bo->tbo.moving);
		bo->tbo.moving = dma_fence_get(fence);
		dma_fence_put(fence);
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	}
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	if (!resv)
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		amdgpu_bo_unreserve(bo);
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	*bo_ptr = bo;

	trace_amdgpu_bo_create(bo);

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	/* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
	if (type == ttm_bo_type_device)
		bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;

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	return 0;
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fail_unreserve:
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	if (!resv)
		ww_mutex_unlock(&bo->tbo.resv->lock);
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	amdgpu_bo_unref(&bo);
	return r;
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}

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static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
				   unsigned long size, int byte_align,
				   struct amdgpu_bo *bo)
{
	struct ttm_placement placement = {0};
	struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
	int r;

	if (bo->shadow)
		return 0;

	bo->flags |= AMDGPU_GEM_CREATE_SHADOW;
	memset(&placements, 0,
	       (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));

	amdgpu_ttm_placement_init(adev, &placement,
				  placements, AMDGPU_GEM_DOMAIN_GTT,
				  AMDGPU_GEM_CREATE_CPU_GTT_USWC);

	r = amdgpu_bo_create_restricted(adev, size, byte_align, true,
					AMDGPU_GEM_DOMAIN_GTT,
					AMDGPU_GEM_CREATE_CPU_GTT_USWC,
					NULL, &placement,
					bo->tbo.resv,
					&bo->shadow);
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	if (!r) {
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		bo->shadow->parent = amdgpu_bo_ref(bo);
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		mutex_lock(&adev->shadow_list_lock);
		list_add_tail(&bo->shadow_list, &adev->shadow_list);
		mutex_unlock(&adev->shadow_list_lock);
	}
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	return r;
}

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int amdgpu_bo_create(struct amdgpu_device *adev,
		     unsigned long size, int byte_align,
		     bool kernel, u32 domain, u64 flags,
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		     struct sg_table *sg,
		     struct reservation_object *resv,
		     struct amdgpu_bo **bo_ptr)
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{
	struct ttm_placement placement = {0};
	struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
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	int r;
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	memset(&placements, 0,
	       (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));

	amdgpu_ttm_placement_init(adev, &placement,
				  placements, domain, flags);

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	r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel,
					domain, flags, sg, &placement,
					resv, bo_ptr);
	if (r)
		return r;

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	if (amdgpu_need_backup(adev) && (flags & AMDGPU_GEM_CREATE_SHADOW)) {
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		if (!resv) {
			r = ww_mutex_lock(&(*bo_ptr)->tbo.resv->lock, NULL);
			WARN_ON(r != 0);
		}

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		r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
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		if (!resv)
			ww_mutex_unlock(&(*bo_ptr)->tbo.resv->lock);

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		if (r)
			amdgpu_bo_unref(bo_ptr);
	}

	return r;
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}

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int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
			       struct amdgpu_ring *ring,
			       struct amdgpu_bo *bo,
			       struct reservation_object *resv,
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			       struct dma_fence **fence,
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			       bool direct)

{
	struct amdgpu_bo *shadow = bo->shadow;
	uint64_t bo_addr, shadow_addr;
	int r;

	if (!shadow)
		return -EINVAL;

	bo_addr = amdgpu_bo_gpu_offset(bo);
	shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);

	r = reservation_object_reserve_shared(bo->tbo.resv);
	if (r)
		goto err;

	r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
			       amdgpu_bo_size(bo), resv, fence,
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			       direct, false);
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	if (!r)
		amdgpu_bo_fence(bo, *fence, true);

err:
	return r;
}

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int amdgpu_bo_validate(struct amdgpu_bo *bo)
{
	uint32_t domain;
	int r;

	if (bo->pin_count)
		return 0;

	domain = bo->prefered_domains;

retry:
	amdgpu_ttm_placement_from_domain(bo, domain);
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
	if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
		domain = bo->allowed_domains;
		goto retry;
	}

	return r;
}

616 617 618 619
int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
				  struct amdgpu_ring *ring,
				  struct amdgpu_bo *bo,
				  struct reservation_object *resv,
620
				  struct dma_fence **fence,
621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639
				  bool direct)

{
	struct amdgpu_bo *shadow = bo->shadow;
	uint64_t bo_addr, shadow_addr;
	int r;

	if (!shadow)
		return -EINVAL;

	bo_addr = amdgpu_bo_gpu_offset(bo);
	shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);

	r = reservation_object_reserve_shared(bo->tbo.resv);
	if (r)
		goto err;

	r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
			       amdgpu_bo_size(bo), resv, fence,
640
			       direct, false);
641 642 643 644 645 646 647
	if (!r)
		amdgpu_bo_fence(bo, *fence, true);

err:
	return r;
}

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648 649
int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
{
650
	void *kptr;
651
	long r;
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Alex Deucher 已提交
652

653 654 655
	if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
		return -EPERM;

656 657 658 659
	kptr = amdgpu_bo_kptr(bo);
	if (kptr) {
		if (ptr)
			*ptr = kptr;
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Alex Deucher 已提交
660 661
		return 0;
	}
662 663 664 665 666 667

	r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
						MAX_SCHEDULE_TIMEOUT);
	if (r < 0)
		return r;

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668
	r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
669
	if (r)
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670
		return r;
671 672

	if (ptr)
673
		*ptr = amdgpu_bo_kptr(bo);
674

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675 676 677
	return 0;
}

678 679 680 681 682 683 684
void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
{
	bool is_iomem;

	return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
}

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685 686
void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
{
687 688
	if (bo->kmap.bo)
		ttm_bo_kunmap(&bo->kmap);
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}

struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
{
	if (bo == NULL)
		return NULL;

	ttm_bo_reference(&bo->tbo);
	return bo;
}

void amdgpu_bo_unref(struct amdgpu_bo **bo)
{
	struct ttm_buffer_object *tbo;

	if ((*bo) == NULL)
		return;

	tbo = &((*bo)->tbo);
	ttm_bo_unref(&tbo);
	if (tbo == NULL)
		*bo = NULL;
}

713 714
int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
			     u64 min_offset, u64 max_offset,
A
Alex Deucher 已提交
715 716
			     u64 *gpu_addr)
{
717
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
A
Alex Deucher 已提交
718
	int r, i;
719
	unsigned fpfn, lpfn;
A
Alex Deucher 已提交
720

721
	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
A
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		return -EPERM;

724 725 726
	if (WARN_ON_ONCE(min_offset > max_offset))
		return -EINVAL;

727 728 729 730
	/* A shared bo cannot be migrated to VRAM */
	if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
		return -EINVAL;

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731
	if (bo->pin_count) {
732 733 734 735 736
		uint32_t mem_type = bo->tbo.mem.mem_type;

		if (domain != amdgpu_mem_type_to_domain(mem_type))
			return -EINVAL;

A
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737 738 739 740 741
		bo->pin_count++;
		if (gpu_addr)
			*gpu_addr = amdgpu_bo_gpu_offset(bo);

		if (max_offset != 0) {
742
			u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
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Alex Deucher 已提交
743 744 745 746 747 748
			WARN_ON_ONCE(max_offset <
				     (amdgpu_bo_gpu_offset(bo) - domain_start));
		}

		return 0;
	}
749 750

	bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
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	amdgpu_ttm_placement_from_domain(bo, domain);
	for (i = 0; i < bo->placement.num_placement; i++) {
		/* force to pin into visible video ram */
		if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
755
		    !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
756
		    (!max_offset || max_offset >
757
		     adev->mc.visible_vram_size)) {
758
			if (WARN_ON_ONCE(min_offset >
759
					 adev->mc.visible_vram_size))
760 761
				return -EINVAL;
			fpfn = min_offset >> PAGE_SHIFT;
762
			lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
763 764 765 766 767 768
		} else {
			fpfn = min_offset >> PAGE_SHIFT;
			lpfn = max_offset >> PAGE_SHIFT;
		}
		if (fpfn > bo->placements[i].fpfn)
			bo->placements[i].fpfn = fpfn;
769 770
		if (!bo->placements[i].lpfn ||
		    (lpfn && lpfn < bo->placements[i].lpfn))
771
			bo->placements[i].lpfn = lpfn;
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		bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
	}

	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
776
	if (unlikely(r)) {
777
		dev_err(adev->dev, "%p pin failed\n", bo);
778 779 780 781
		goto error;
	}

	bo->pin_count = 1;
782 783 784 785 786 787
	if (gpu_addr != NULL) {
		r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
		if (unlikely(r)) {
			dev_err(adev->dev, "%p bind failed\n", bo);
			goto error;
		}
788
		*gpu_addr = amdgpu_bo_gpu_offset(bo);
789
	}
790
	if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
791
		adev->vram_pin_size += amdgpu_bo_size(bo);
792
		if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
793
			adev->invisible_pin_size += amdgpu_bo_size(bo);
794
	} else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
795
		adev->gart_pin_size += amdgpu_bo_size(bo);
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	}
797 798

error:
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	return r;
}

int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
{
804
	return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
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}

int amdgpu_bo_unpin(struct amdgpu_bo *bo)
{
809
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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	int r, i;

	if (!bo->pin_count) {
813
		dev_warn(adev->dev, "%p unpin not necessary\n", bo);
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		return 0;
	}
	bo->pin_count--;
	if (bo->pin_count)
		return 0;
	for (i = 0; i < bo->placement.num_placement; i++) {
		bo->placements[i].lpfn = 0;
		bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
	}
	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
824
	if (unlikely(r)) {
825
		dev_err(adev->dev, "%p validate failed for unpin\n", bo);
826
		goto error;
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Alex Deucher 已提交
827
	}
828 829

	if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
830
		adev->vram_pin_size -= amdgpu_bo_size(bo);
831
		if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
832
			adev->invisible_pin_size -= amdgpu_bo_size(bo);
833
	} else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
834
		adev->gart_pin_size -= amdgpu_bo_size(bo);
835 836 837
	}

error:
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	return r;
}

int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
{
	/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
844
	if (0 && (adev->flags & AMD_IS_APU)) {
A
Alex Deucher 已提交
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		/* Useless to evict on IGP chips */
		return 0;
	}
	return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
}

851 852 853 854 855 856 857 858 859 860 861
static const char *amdgpu_vram_names[] = {
	"UNKNOWN",
	"GDDR1",
	"DDR2",
	"GDDR3",
	"GDDR4",
	"GDDR5",
	"HBM",
	"DDR3"
};

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Alex Deucher 已提交
862 863
int amdgpu_bo_init(struct amdgpu_device *adev)
{
864 865 866 867
	/* reserve PAT memory space to WC for VRAM */
	arch_io_reserve_memtype_wc(adev->mc.aper_base,
				   adev->mc.aper_size);

A
Alex Deucher 已提交
868 869 870 871 872 873
	/* Add an MTRR for the VRAM */
	adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
					      adev->mc.aper_size);
	DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
		adev->mc.mc_vram_size >> 20,
		(unsigned long long)adev->mc.aper_size >> 20);
874 875
	DRM_INFO("RAM width %dbits %s\n",
		 adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
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Alex Deucher 已提交
876 877 878 879 880 881 882
	return amdgpu_ttm_init(adev);
}

void amdgpu_bo_fini(struct amdgpu_device *adev)
{
	amdgpu_ttm_fini(adev);
	arch_phys_wc_del(adev->mc.vram_mtrr);
883
	arch_io_free_memtype_wc(adev->mc.aper_base, adev->mc.aper_size);
A
Alex Deucher 已提交
884 885 886 887 888 889 890 891 892 893
}

int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
			     struct vm_area_struct *vma)
{
	return ttm_fbdev_mmap(vma, &bo->tbo);
}

int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
{
894 895 896 897
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);

	if (adev->family <= AMDGPU_FAMILY_CZ &&
	    AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
A
Alex Deucher 已提交
898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919
		return -EINVAL;

	bo->tiling_flags = tiling_flags;
	return 0;
}

void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
{
	lockdep_assert_held(&bo->tbo.resv->lock.base);

	if (tiling_flags)
		*tiling_flags = bo->tiling_flags;
}

int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
			    uint32_t metadata_size, uint64_t flags)
{
	void *buffer;

	if (!metadata_size) {
		if (bo->metadata_size) {
			kfree(bo->metadata);
920
			bo->metadata = NULL;
A
Alex Deucher 已提交
921 922 923 924 925 926 927 928
			bo->metadata_size = 0;
		}
		return 0;
	}

	if (metadata == NULL)
		return -EINVAL;

929
	buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
A
Alex Deucher 已提交
930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964
	if (buffer == NULL)
		return -ENOMEM;

	kfree(bo->metadata);
	bo->metadata_flags = flags;
	bo->metadata = buffer;
	bo->metadata_size = metadata_size;

	return 0;
}

int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
			   size_t buffer_size, uint32_t *metadata_size,
			   uint64_t *flags)
{
	if (!buffer && !metadata_size)
		return -EINVAL;

	if (buffer) {
		if (buffer_size < bo->metadata_size)
			return -EINVAL;

		if (bo->metadata_size)
			memcpy(buffer, bo->metadata, bo->metadata_size);
	}

	if (metadata_size)
		*metadata_size = bo->metadata_size;
	if (flags)
		*flags = bo->metadata_flags;

	return 0;
}

void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
965
			   bool evict,
A
Alex Deucher 已提交
966 967
			   struct ttm_mem_reg *new_mem)
{
968
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
969
	struct amdgpu_bo *abo;
970
	struct ttm_mem_reg *old_mem = &bo->mem;
A
Alex Deucher 已提交
971 972 973 974

	if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
		return;

975
	abo = container_of(bo, struct amdgpu_bo, tbo);
976
	amdgpu_vm_bo_invalidate(adev, abo);
A
Alex Deucher 已提交
977

978 979
	amdgpu_bo_kunmap(abo);

980 981 982 983
	/* remember the eviction */
	if (evict)
		atomic64_inc(&adev->num_evictions);

A
Alex Deucher 已提交
984 985 986 987 988
	/* update statistics */
	if (!new_mem)
		return;

	/* move_notify is called before move happens */
989
	amdgpu_update_memory_usage(adev, &bo->mem, new_mem);
990

991
	trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
A
Alex Deucher 已提交
992 993 994 995
}

int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
{
996
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
997
	struct amdgpu_bo *abo;
998 999
	unsigned long offset, size;
	int r;
A
Alex Deucher 已提交
1000 1001 1002

	if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
		return 0;
1003 1004

	abo = container_of(bo, struct amdgpu_bo, tbo);
1005 1006 1007 1008

	/* Remember that this BO was accessed by the CPU */
	abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;

1009 1010 1011 1012 1013
	if (bo->mem.mem_type != TTM_PL_VRAM)
		return 0;

	size = bo->mem.num_pages << PAGE_SHIFT;
	offset = bo->mem.start << PAGE_SHIFT;
1014
	if ((offset + size) <= adev->mc.visible_vram_size)
1015 1016
		return 0;

1017 1018 1019 1020
	/* Can't move a pinned BO to visible VRAM */
	if (abo->pin_count > 0)
		return -EINVAL;

1021
	/* hurrah the memory is not visible ! */
1022
	atomic64_inc(&adev->num_vram_cpu_page_faults);
1023 1024 1025 1026 1027 1028 1029
	amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
					 AMDGPU_GEM_DOMAIN_GTT);

	/* Avoid costly evictions; only set GTT as a busy placement */
	abo->placement.num_busy_placement = 1;
	abo->placement.busy_placement = &abo->placements[1];

1030
	r = ttm_bo_validate(bo, &abo->placement, false, false);
1031
	if (unlikely(r != 0))
1032 1033 1034 1035
		return r;

	offset = bo->mem.start << PAGE_SHIFT;
	/* this should never happen */
1036 1037
	if (bo->mem.mem_type == TTM_PL_VRAM &&
	    (offset + size) > adev->mc.visible_vram_size)
1038 1039
		return -EINVAL;

A
Alex Deucher 已提交
1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050
	return 0;
}

/**
 * amdgpu_bo_fence - add fence to buffer object
 *
 * @bo: buffer object in question
 * @fence: fence to add
 * @shared: true if fence should be added shared
 *
 */
1051
void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
A
Alex Deucher 已提交
1052 1053 1054 1055 1056
		     bool shared)
{
	struct reservation_object *resv = bo->tbo.resv;

	if (shared)
1057
		reservation_object_add_shared_fence(resv, fence);
A
Alex Deucher 已提交
1058
	else
1059
		reservation_object_add_excl_fence(resv, fence);
A
Alex Deucher 已提交
1060
}
1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073

/**
 * amdgpu_bo_gpu_offset - return GPU offset of bo
 * @bo:	amdgpu object for which we query the offset
 *
 * Returns current GPU offset of the object.
 *
 * Note: object should either be pinned or reserved when calling this
 * function, it might be useful to add check for this for debugging.
 */
u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
{
	WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1074 1075
	WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
		     !amdgpu_ttm_is_bound(bo->tbo.ttm));
1076 1077
	WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
		     !bo->pin_count);
1078
	WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1079 1080
	WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
		     !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1081 1082 1083

	return bo->tbo.offset;
}