Merge pull request #833 from geniusgogo/samd21

[BSP] add atmel SAM D21 bsp support

bsp/samd21/README.txt

+使用SAMD21-Xplained-Pro开发板
+scons:
+  scons
+  scons --target=mdk5
+demo代码演示了串口、外部中断、RTC低功耗唤醒

bsp/samd21/SAM_D2X_RTT.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00008000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

bsp/samd21/SConscript

+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/samd21/SConstruct

+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'SAM_D2X_RTT.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/samd21/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+#remove other no use files
+#SrcRemove(src, '*.c')
+
+group = DefineGroup('Application', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
\ No newline at end of file

bsp/samd21/applications/application.c

+#include <rtthread.h>
+#include <rthw.h>
+
+#include "board.h"
+
+#include "port.h"
+#include "extint.h"
+
+#include "sleep_timer.h"
+
+void LED_Init(void)
+{
+    struct port_config config_port_pin;
+
+    port_get_config_defaults(&config_port_pin);
+    config_port_pin.direction  = PORT_PIN_DIR_INPUT;
+    config_port_pin.input_pull = PORT_PIN_PULL_UP;
+    port_pin_set_config(PIN_PA15, &config_port_pin);
+
+    config_port_pin.direction  = PORT_PIN_DIR_OUTPUT;
+    port_pin_set_config(PIN_PB30, &config_port_pin);
+}
+
+void LED_ON(void)
+{
+    port_pin_set_output_level(PIN_PB30, false);
+}
+
+void LED_OFF(void)
+{
+    port_pin_set_output_level(PIN_PB30, true);
+}
+
+void extint_detection_callback(void);
+
+void configure_extint_channel(void)
+{
+//! [setup_1]
+    struct extint_chan_conf config_extint_chan;
+//! [setup_1]
+//! [setup_2]
+    extint_chan_get_config_defaults(&config_extint_chan);
+//! [setup_2]
+
+//! [setup_3]
+    config_extint_chan.gpio_pin           = PIN_PA15A_EIC_EXTINT15;
+    config_extint_chan.gpio_pin_mux       = MUX_PA15A_EIC_EXTINT15;
+    config_extint_chan.gpio_pin_pull      = EXTINT_PULL_UP;
+    config_extint_chan.detection_criteria = EXTINT_DETECT_BOTH;
+//! [setup_3]
+//! [setup_4]
+    extint_chan_set_config(15, &config_extint_chan);
+//! [setup_4]
+}
+
+void configure_extint_callbacks(void)
+{
+//! [setup_5]
+    extint_register_callback(extint_detection_callback, 15, EXTINT_CALLBACK_TYPE_DETECT);
+//! [setup_5]
+//! [setup_6]
+    extint_chan_enable_callback(15, EXTINT_CALLBACK_TYPE_DETECT);
+//! [setup_6]
+}
+
+//! [setup_7]
+void extint_detection_callback(void)
+{
+    bool pin_state = port_pin_get_input_level(PIN_PA15);
+    port_pin_set_output_level(PIN_PB30, pin_state);
+}
+
+static struct rt_semaphore _rx_sem;
+
+static rt_err_t _rx_ind(rt_device_t dev, rt_size_t size)
+{
+    return rt_sem_release(&_rx_sem);
+}
+
+void rt_init_thread_entry(void* parameter)
+{
+    rt_thread_t thread;
+    rt_device_t dev;
+
+    rt_kprintf("SYSTEM running at %uhz\n", SystemCoreClock);
+
+#ifdef RT_USING_FINSH
+    /* init finsh */
+    finsh_system_init();
+    finsh_set_device("uart1");
+#endif
+
+    LED_Init();
+    configure_extint_channel();
+    configure_extint_callbacks();
+
+    sleep_timer_init();
+    // sleep_timer_start(1500);
+
+    while (1)
+    {
+        rt_kprintf("init thread running tick:%u\n", rt_tick_get());
+        rt_thread_delay(2*RT_TICK_PER_SECOND);
+    }
+}
+
+int rt_application_init(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL,
+                            512, RT_THREAD_PRIORITY_MAX / 3, 20);
+
+    if (tid != RT_NULL)
+        rt_thread_startup(tid);
+
+    return 0;
+}
+

bsp/samd21/applications/startup.c

+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-08-31     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+/**
+ * @addtogroup STM32
+ */
+
+/*@{*/
+
+extern int  rt_application_init(void);
+#ifdef RT_USING_FINSH
+extern void finsh_system_init(void);
+extern void finsh_set_device(const char* device);
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+#pragma section="HEAP"
+#else
+extern int __bss_end;
+#endif
+
+#ifdef  DEBUG
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(uint8_t* file, uint32_t line)
+{
+    rt_kprintf("\n\r Wrong parameter value detected on\r\n");
+    rt_kprintf("       file  %s\r\n", file);
+    rt_kprintf("       line  %d\r\n", line);
+
+    while (1) ;
+}
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* init board */
+    rt_board_init();
+
+    /* show version */
+    rt_show_version();
+
+    /* init tick */
+    rt_system_tick_init();
+
+    /* init kernel object */
+    rt_system_object_init();
+
+    /* init timer system */
+    rt_system_timer_init();
+
+#ifdef RT_USING_HEAP
+    #ifdef __CC_ARM
+        rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)CHIP_SRAM_END);
+    #elif __ICCARM__
+        rt_system_heap_init(__segment_end("HEAP"), (void*)CHIP_SRAM_END);
+    #else
+        /* init memory system */
+        rt_system_heap_init((void*)&__bss_end, (void*)CHIP_SRAM_END);
+    #endif
+#endif
+
+    /* init scheduler system */
+    rt_system_scheduler_init();
+
+    /* init application */
+    rt_application_init();
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
+}
+
+/*@}*/

bsp/samd21/asflib_config/clock_samd20/conf_clocks.h

+/**
+ * \file
+ *
+ * \brief SAM D20 Clock configuration
+ *
+ * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <clock.h>
+
+#ifndef CONF_CLOCKS_H_INCLUDED
+#  define CONF_CLOCKS_H_INCLUDED
+
+/* System clock bus configuration */
+#  define CONF_CLOCK_FLASH_WAIT_STATES            0
+#  define CONF_CLOCK_CPU_DIVIDER                  SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBA_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBB_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBC_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+
+/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
+#  define CONF_CLOCK_OSC8M_PRESCALER              SYSTEM_OSC8M_DIV_1
+#  define CONF_CLOCK_OSC8M_ON_DEMAND              true
+#  define CONF_CLOCK_OSC8M_RUN_IN_STANDBY         false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
+#  define CONF_CLOCK_XOSC_ENABLE                  false
+#  define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL        SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY      12000000UL
+#  define CONF_CLOCK_XOSC_STARTUP_TIME            SYSTEM_XOSC_STARTUP_32768
+#  define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL       true
+#  define CONF_CLOCK_XOSC_ON_DEMAND               true
+#  define CONF_CLOCK_XOSC_RUN_IN_STANDBY          false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
+#  define CONF_CLOCK_XOSC32K_ENABLE               false
+#  define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL     SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC32K_STARTUP_TIME         SYSTEM_XOSC32K_STARTUP_65536
+#  define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL  false
+#  define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT    false
+#  define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT  true
+#  define CONF_CLOCK_XOSC32K_ON_DEMAND            true
+#  define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY       false
+
+/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
+#  define CONF_CLOCK_OSC32K_ENABLE                false
+#  define CONF_CLOCK_OSC32K_STARTUP_TIME          SYSTEM_OSC32K_STARTUP_130
+#  define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT    true
+#  define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT   true
+#  define CONF_CLOCK_OSC32K_ON_DEMAND             true
+#  define CONF_CLOCK_OSC32K_RUN_IN_STANDBY        false
+
+/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
+#  define CONF_CLOCK_DFLL_ENABLE                  false
+#  define CONF_CLOCK_DFLL_LOOP_MODE               SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
+#  define CONF_CLOCK_DFLL_ON_DEMAND               false
+
+/* DFLL open loop mode configuration */
+#  define CONF_CLOCK_DFLL_FINE_VALUE              (512)
+
+/* DFLL closed loop mode configuration */
+#  define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR   GCLK_GENERATOR_1
+#  define CONF_CLOCK_DFLL_MULTIPLY_FACTOR         1465 /* (48000000 / 32768) */
+#  define CONF_CLOCK_DFLL_QUICK_LOCK              true
+#  define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK   true
+#  define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP     true
+#  define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE      true
+#  define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE    (0x1f / 4)
+#  define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE      (0xff / 4)
+
+
+/* Set this to true to configure the GCLK when running clocks_init. If set to
+ * false, none of the GCLK generators will be configured in clocks_init(). */
+#  define CONF_CLOCK_CONFIGURE_GCLK               true
+
+/* Configure GCLK generator 0 (Main Clock) */
+#  define CONF_CLOCK_GCLK_0_ENABLE                true
+#  define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_0_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_0_PRESCALER             1
+#  define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 1 */
+#  define CONF_CLOCK_GCLK_1_ENABLE                false
+#  define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_1_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_XOSC32K
+#  define CONF_CLOCK_GCLK_1_PRESCALER             1
+#  define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 2 (RTC) */
+#  define CONF_CLOCK_GCLK_2_ENABLE                false
+#  define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_2_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC32K
+#  define CONF_CLOCK_GCLK_2_PRESCALER             32
+#  define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 3 */
+#  define CONF_CLOCK_GCLK_3_ENABLE                false
+#  define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_3_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_3_PRESCALER             1
+#  define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 4 */
+#  define CONF_CLOCK_GCLK_4_ENABLE                false
+#  define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_4_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_4_PRESCALER             1
+#  define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 5 */
+#  define CONF_CLOCK_GCLK_5_ENABLE                false
+#  define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_5_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_5_PRESCALER             1
+#  define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 6 */
+#  define CONF_CLOCK_GCLK_6_ENABLE                false
+#  define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_6_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_6_PRESCALER             1
+#  define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 7 */
+#  define CONF_CLOCK_GCLK_7_ENABLE                false
+#  define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_7_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_7_PRESCALER             1
+#  define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE         false
+
+#endif /* CONF_CLOCKS_H_INCLUDED */
+

bsp/samd21/asflib_config/clock_samd21_r21_da_ha1/conf_clocks.h

+/**
+ * \file
+ *
+ * \brief SAM D21/R21/DA/HA Clock configuration
+ *
+ * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#include <clock.h>
+
+#ifndef CONF_CLOCKS_H_INCLUDED
+#  define CONF_CLOCKS_H_INCLUDED
+
+/* System clock bus configuration */
+#  define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT     false
+#  define CONF_CLOCK_FLASH_WAIT_STATES            1
+#  define CONF_CLOCK_CPU_DIVIDER                  SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBA_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBB_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+#  define CONF_CLOCK_APBC_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
+
+/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
+#  define CONF_CLOCK_OSC8M_PRESCALER              SYSTEM_OSC8M_DIV_1
+#  define CONF_CLOCK_OSC8M_ON_DEMAND              true
+#  define CONF_CLOCK_OSC8M_RUN_IN_STANDBY         false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
+#  define CONF_CLOCK_XOSC_ENABLE                  false
+#  define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL        SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY      12000000UL
+#  define CONF_CLOCK_XOSC_STARTUP_TIME            SYSTEM_XOSC_STARTUP_32768
+#  define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL       true
+#  define CONF_CLOCK_XOSC_ON_DEMAND               true
+#  define CONF_CLOCK_XOSC_RUN_IN_STANDBY          false
+
+/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
+#  define CONF_CLOCK_XOSC32K_ENABLE               true
+#  define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL     SYSTEM_CLOCK_EXTERNAL_CRYSTAL
+#  define CONF_CLOCK_XOSC32K_STARTUP_TIME         SYSTEM_XOSC32K_STARTUP_2048
+#  define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL  true
+#  define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT    false
+#  define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT  true
+#  define CONF_CLOCK_XOSC32K_ON_DEMAND            false
+#  define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY       true
+
+/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
+#  define CONF_CLOCK_OSC32K_ENABLE                false
+#  define CONF_CLOCK_OSC32K_STARTUP_TIME          SYSTEM_OSC32K_STARTUP_130
+#  define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT    true
+#  define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT   true
+#  define CONF_CLOCK_OSC32K_ON_DEMAND             true
+#  define CONF_CLOCK_OSC32K_RUN_IN_STANDBY        false
+
+/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
+#  define CONF_CLOCK_DFLL_ENABLE                  true
+#  define CONF_CLOCK_DFLL_LOOP_MODE               SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
+#  define CONF_CLOCK_DFLL_ON_DEMAND               true
+
+/* DFLL open loop mode configuration */
+#  define CONF_CLOCK_DFLL_FINE_VALUE              ((*((uint32_t*)(0x806020 + 8))) & 0x3FF)/*(512)*/
+
+/* DFLL closed loop mode configuration */
+#  define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR   GCLK_GENERATOR_2
+#  define CONF_CLOCK_DFLL_MULTIPLY_FACTOR         (48000000 / 32768)
+#  define CONF_CLOCK_DFLL_QUICK_LOCK              true
+#  define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK   true
+#  define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP     true
+#  define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE      true
+#  define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE    ((*((uint8_t*)(0x806020 + 7))) >> 2)/*(0x1f / 4)*/
+#  define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE      ((*((uint32_t*)(0x806020 + 8))) & 0x3FF)/*(0xff / 4)*/
+
+/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */
+#  define CONF_CLOCK_DPLL_ENABLE                  false
+#  define CONF_CLOCK_DPLL_ON_DEMAND               true
+#  define CONF_CLOCK_DPLL_RUN_IN_STANDBY          false
+#  define CONF_CLOCK_DPLL_LOCK_BYPASS             false
+#  define CONF_CLOCK_DPLL_WAKE_UP_FAST            false
+#  define CONF_CLOCK_DPLL_LOW_POWER_ENABLE        false
+
+#  define CONF_CLOCK_DPLL_LOCK_TIME               SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT
+#  define CONF_CLOCK_DPLL_REFERENCE_CLOCK         SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K
+#  define CONF_CLOCK_DPLL_FILTER                  SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT
+
+#  define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY     32768
+#  define CONF_CLOCK_DPLL_REFERENCE_DIVIDER       1
+#  define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY        48000000
+
+/* DPLL GCLK reference configuration */
+#  define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR  GCLK_GENERATOR_1
+/* DPLL GCLK lock timer configuration */
+#  define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR     GCLK_GENERATOR_1
+
+/* Set this to true to configure the GCLK when running clocks_init. If set to
+ * false, none of the GCLK generators will be configured in clocks_init(). */
+#  define CONF_CLOCK_CONFIGURE_GCLK               true
+
+/* Configure GCLK generator 0 (Main Clock) */
+#  define CONF_CLOCK_GCLK_0_ENABLE                true
+#  define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_0_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_DFLL
+#  define CONF_CLOCK_GCLK_0_PRESCALER             1
+#  define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 1 */
+#  define CONF_CLOCK_GCLK_1_ENABLE                false
+#  define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY        true
+#  define CONF_CLOCK_GCLK_1_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_XOSC32K
+#  define CONF_CLOCK_GCLK_1_PRESCALER             1
+#  define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 2 (RTC) */
+#  define CONF_CLOCK_GCLK_2_ENABLE                true
+#  define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY        true
+#  define CONF_CLOCK_GCLK_2_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_XOSC32K
+#  define CONF_CLOCK_GCLK_2_PRESCALER             1
+#  define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 3 */
+#  define CONF_CLOCK_GCLK_3_ENABLE                false
+#  define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_3_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_3_PRESCALER             1
+#  define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 4 */
+#  define CONF_CLOCK_GCLK_4_ENABLE                false
+#  define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_4_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_4_PRESCALER             1
+#  define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 5 */
+#  define CONF_CLOCK_GCLK_5_ENABLE                false
+#  define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_5_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_5_PRESCALER             1
+#  define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 6 */
+#  define CONF_CLOCK_GCLK_6_ENABLE                false
+#  define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_6_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_6_PRESCALER             1
+#  define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 7 */
+#  define CONF_CLOCK_GCLK_7_ENABLE                false
+#  define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_7_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_7_PRESCALER             1
+#  define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE         false
+
+/* Configure GCLK generator 8 */
+#  define CONF_CLOCK_GCLK_8_ENABLE                false
+#  define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY        false
+#  define CONF_CLOCK_GCLK_8_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
+#  define CONF_CLOCK_GCLK_8_PRESCALER             1
+#  define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE         false
+
+#endif /* CONF_CLOCKS_H_INCLUDED */
+

bsp/samd21/asflib_config/conf_extint.h

+/**
+ * \file
+ *
+ * \brief SAM D21 External Interrupt Driver Configuration Header
+ *
+ * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CONF_EXTINT_H_INCLUDED
+#define CONF_EXTINT_H_INCLUDED
+
+#  define EXTINT_CLOCK_SOURCE      GCLK_GENERATOR_2
+
+#endif

bsp/samd21/board/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+path = [cwd]
+
+#remove other no use files
+#SrcRemove(src, 'i2c_iomaster.c')
+#SrcRemove(src, 'delay.c')
+
+if rtconfig.DEVICE_SERIES == 'SAMD20':
+	path += [cwd + '/../asflib_config', cwd + '/../asflib_config/clock_samd20']
+elif rtconfig.DEVICE_SERIES == 'SAMD21':
+	path += [cwd + '/../asflib_config', cwd + '/../asflib_config/clock_samd21_r21_da_ha1']
+
+group = DefineGroup('Board', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/samd21/board/board.c

+#include "board.h"
+#include <clock.h>
+#include <gclk.h>
+#include <system.h>
+#include <rtthread.h>
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+	rt_interrupt_enter();
+
+	rt_tick_increase();
+
+	/* leave interrupt */
+	rt_interrupt_leave();
+}
+
+void configure_extosc32k(void);
+void configure_dfll_open_loop(void);
+
+//! [setup]
+//! [config_extosc32k]
+void configure_extosc32k(void)
+{
+//! [config_extosc32k_config]
+	struct system_clock_source_xosc32k_config config_ext32k;
+//! [config_extosc32k_config]
+//! [config_extosc32k_get_defaults]
+	system_clock_source_xosc32k_get_config_defaults(&config_ext32k);
+//! [config_extosc32k_get_defaults]
+
+//! [config_extosc32k_change_defaults]
+	config_ext32k.startup_time = SYSTEM_XOSC32K_STARTUP_4096;
+    config_ext32k.on_demand = false;
+//! [config_extosc32k_change_defaults]
+
+//! [config_extosc32k_set_config]
+	system_clock_source_xosc32k_set_config(&config_ext32k);
+//! [config_extosc32k_set_config]
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K);
+	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K));
+}
+//! [config_extosc32k]
+
+#if (!SAMC21)
+//! [config_dfll]
+void configure_dfll_open_loop(void)
+{
+//! [config_dfll_config]
+	struct system_clock_source_dfll_config config_dfll;
+//! [config_dfll_config]
+//! [config_dfll_get_defaults]
+	system_clock_source_dfll_get_config_defaults(&config_dfll);
+//! [config_dfll_get_defaults]
+	config_dfll.coarse_value    = (*((uint8_t*)(0x806020 + 7))) >> 2;// 0x1f / 4; /* Midpoint */
+	config_dfll.fine_value      = (*((uint32_t*)(0x806020 + 8))) & 0x3FF;//0xff / 4; /* Midpoint */
+//! [config_dfll_set_config]
+	system_clock_source_dfll_set_config(&config_dfll);
+//! [config_dfll_set_config]
+
+//! [enable_dfll_main]
+	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
+	// while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
+
+//! [enable_dfll_main]
+	/* Configure flash wait states before switching to high frequency clock */
+//! [set_sys_wait_states]
+	system_flash_set_waitstates(2);
+//! [set_sys_wait_states]
+
+	/* Change system clock to DFLL */
+//! [set_sys_clk_src]
+	struct system_gclk_gen_config config_gclock_gen;
+	system_gclk_gen_get_config_defaults(&config_gclock_gen);
+	config_gclock_gen.source_clock    = SYSTEM_CLOCK_SOURCE_DFLL;
+	config_gclock_gen.division_factor = 1;
+	system_gclk_gen_set_config(GCLK_GENERATOR_0, &config_gclock_gen);
+//! [set_sys_clk_src]
+}
+//! [config_dfll]
+#endif
+
+void rt_board_init(void)
+{
+    extern void uart_init(void);
+
+    // configure_extosc32k();
+
+    // configure_dfll_open_loop();
+	system_init();
+
+	/* initialize systick */
+	SystemCoreClock = system_gclk_gen_get_hz(0);
+	SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+
+    uart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+

bsp/samd21/board/board.h

+/* This is a template file for board configuration created by MCUXpresso Project Generator. Enjoy! */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#include <stdint.h>
+#include "samd21.h"
+#include "system_samd21.h"
+#include "core_cm0plus.h"              /* Core Peripheral Access Layer */
+
+/* The board name */
+#define BOARD_NAME "###-not-specified-###"
+
+#define CHIP_SRAM_END   (0x20000000 + 32*1024)
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief initialize debug console to enable printf for this demo/example
+ */
+void rt_board_init(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */

bsp/samd21/board/sleep_timer.c

+// From module: RTC - Real Time Counter in Count Mode (Polled APIs)
+#include <rtc_count.h>
+#include <rtc_count_interrupt.h>
+// #include <rtc_tamper.h>
+#include <power.h>
+#include <port.h>
+
+#include <rtthread.h>
+
+/* RTC module instance */
+static struct rtc_module rtc_instance;
+
+static void _rtc_timer_int_cb(void)
+{
+	port_pin_toggle_output_level(PIN_PB30);
+}
+
+/* Init RTC as ADC sample timer */
+static void _rtc_timer_init(void)
+{
+	struct rtc_count_config conf;
+
+	rtc_count_get_config_defaults(&conf);
+
+	conf.prescaler         = RTC_COUNT_PRESCALER_DIV_1;
+	conf.mode              = RTC_COUNT_MODE_32BIT;
+	conf.clear_on_match    = false;
+	conf.compare_values[0] = 0;
+
+	// struct rtc_count_events evconfig;
+	// evconfig.generate_event_on_compare[0] = true;
+
+	rtc_count_init(&rtc_instance, RTC, &conf);
+	// rtc_count_enable_events(&rtc_instance, &evconfig);
+    // rtc_count_enable(&rtc_instance);
+	rtc_count_set_count(&rtc_instance, 0);
+	rtc_count_register_callback(&rtc_instance, _rtc_timer_int_cb, RTC_COUNT_CALLBACK_COMPARE_0);
+	// rtc_count_enable_callback(&rtc_instance, RTC_COUNT_CALLBACK_COMPARE_0);
+}
+
+static void _rtc_timer_start(uint32_t ms)
+{
+	uint32_t compare = 0;
+
+	compare = (uint32_t)(32.768 * ms);
+
+	// rtc_count_register_callback(&rtc_instance, _rtc_timer_int_cb, RTC_COUNT_CALLBACK_COMPARE_0);
+	rtc_count_enable_callback(&rtc_instance, RTC_COUNT_CALLBACK_COMPARE_0);
+
+	rtc_count_set_count(&rtc_instance, 0);
+	rtc_count_set_compare(&rtc_instance, compare, RTC_COUNT_COMPARE_0);
+	rtc_count_enable(&rtc_instance);
+}
+
+static void sleep_tick_adjust(uint32_t ms)
+{
+	uint32_t diff;
+
+	diff = rt_tick_from_millisecond(ms);
+
+	rt_tick_set(rt_tick_get() + diff);
+	{
+		struct rt_thread *thread;
+
+		/* check time slice */
+		thread = rt_thread_self();
+
+		if (thread->remaining_tick <= diff)
+		{
+			/* change to initialized tick */
+			thread->remaining_tick = thread->init_tick;
+
+			/* yield */
+			rt_thread_yield();
+		}
+		else
+		{
+			thread->remaining_tick -= diff;
+		}
+
+		/* check timer */
+		rt_timer_check();
+	}
+}
+
+static void _sleep_entry(void)
+{
+	rt_tick_t timeout;
+	rt_uint32_t ms;
+	rt_uint32_t count;
+
+	system_set_sleepmode(SYSTEM_SLEEPMODE_STANDBY);
+	timeout = rt_timer_next_timeout_tick() - rt_tick_get();
+
+	ms = timeout * (1000 / RT_TICK_PER_SECOND);
+	rt_kprintf("os tick:%u entry sleep:%u tick\r\n", rt_tick_get(), timeout);
+
+	_rtc_timer_start(ms);
+
+	system_sleep();
+
+	rt_enter_critical();
+	count = rtc_count_get_count(&rtc_instance);
+	ms = (count + 32) / 32.768;
+	rtc_count_disable(&rtc_instance);
+	sleep_tick_adjust(ms);
+	timeout = rt_tick_get();
+	rt_exit_critical();
+	rt_kprintf("sleep exited, os tick:%u\n", timeout);
+}
+
+void sleep_timer_init(void)
+{
+	_rtc_timer_init();
+	rt_thread_idle_sethook(_sleep_entry);
+}
+
+void sleep_timer_start(uint32_t ms)
+{
+	_rtc_timer_start(ms);
+}
+
+void sleep_timer_stop(void)
+{
+	rtc_count_disable(&rtc_instance);
+}

bsp/samd21/board/sleep_timer.h

+#ifndef _SLEEP_TIMER_H_
+#define _SLEEP_TIMER_H_
+
+void sleep_timer_init(void);
+
+void sleep_timer_start(uint32_t ms);
+
+#endif

bsp/samd21/board/uart.c

+// From module: SERCOM Callback API
+#include <samd21.h>
+#include <sercom.h>
+// #include <sercom_interrupt.h>
+
+// From module: SERCOM USART - Serial Communications (Callback APIs)
+#include <usart.h>
+// #include <usart_interrupt.h>
+
+#include <rtdevice.h>
+
+typedef struct _samd2x_uart_t
+{
+    struct rt_serial_device *serial;
+    struct usart_module *instance;
+    Sercom *com;
+    enum usart_signal_mux_settings mux_setting;
+    uint32_t pinmux_pad0;
+    uint32_t pinmux_pad1;
+    uint32_t pinmux_pad2;
+    uint32_t pinmux_pad3;
+    enum system_interrupt_vector vector;
+} SAMD2x_UART_T;
+
+static struct rt_serial_device _serial3;
+static struct usart_module _uart3_instance;
+static SAMD2x_UART_T _uart3 = {
+    &_serial3,
+    &_uart3_instance,
+    SERCOM3,
+    USART_RX_1_TX_0_XCK_1,
+    PINMUX_PA22C_SERCOM3_PAD0,
+    PINMUX_PA23C_SERCOM3_PAD1,
+    PINMUX_UNUSED,
+    PINMUX_UNUSED,
+    SYSTEM_INTERRUPT_MODULE_SERCOM3
+};
+
+// static struct rt_serial_device _serial2;
+// static struct rt_serial_device _serial3;
+// static struct rt_serial_device _serial4;
+
+static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    SAMD2x_UART_T *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart = (SAMD2x_UART_T *)serial->parent.user_data;
+    //! [setup_config]
+	struct usart_config config_usart;
+    //! [setup_config]
+    //! [setup_config_defaults]
+    usart_get_config_defaults(&config_usart);
+    //! [setup_config_defaults]
+    config_usart.baudrate = cfg->baud_rate;
+
+    switch (cfg->data_bits )
+    {
+    case DATA_BITS_8:
+        config_usart.character_size = USART_CHARACTER_SIZE_8BIT;
+        break;
+
+    case DATA_BITS_5:
+        config_usart.character_size = USART_CHARACTER_SIZE_5BIT;
+        break;
+
+    case DATA_BITS_6:
+        config_usart.character_size = USART_CHARACTER_SIZE_6BIT;
+        break;
+
+    case DATA_BITS_7:
+        config_usart.character_size = USART_CHARACTER_SIZE_7BIT;
+        break;
+
+    case DATA_BITS_9:
+        config_usart.character_size = USART_CHARACTER_SIZE_9BIT;
+        break;
+
+    default:
+        config_usart.character_size = USART_CHARACTER_SIZE_8BIT;
+        break;
+    }
+
+    switch (cfg->parity)
+    {
+    case PARITY_NONE:
+        config_usart.parity = USART_PARITY_NONE;
+        break;
+
+    case PARITY_EVEN:
+        config_usart.parity = USART_PARITY_EVEN;
+        break;
+
+    case PARITY_ODD:
+        config_usart.parity = USART_PARITY_ODD;
+        break;
+
+    default:
+        config_usart.parity = USART_PARITY_NONE;
+        break;
+    }
+
+    config_usart.stopbits = USART_STOPBITS_1;
+    if (cfg->stop_bits != USART_STOPBITS_1)
+    {
+        config_usart.stopbits = USART_STOPBITS_2;
+    }
+
+    config_usart.data_order = USART_DATAORDER_LSB;
+    if (cfg->bit_order != BIT_ORDER_LSB)
+    {
+        config_usart.data_order = USART_DATAORDER_MSB;
+    }
+
+    config_usart.mux_setting = uart->mux_setting;
+    config_usart.pinmux_pad0 = uart->pinmux_pad0;
+    config_usart.pinmux_pad1 = uart->pinmux_pad1;
+    config_usart.pinmux_pad2 = uart->pinmux_pad2;
+    config_usart.pinmux_pad3 = uart->pinmux_pad3;
+    config_usart.receiver_enable = false;
+    config_usart.transmitter_enable = true;
+
+    while (usart_init(uart->instance, uart->com, &config_usart) != STATUS_OK) {
+    }
+
+    usart_enable(uart->instance);
+    /* Wait for the synchronization to complete */
+    _usart_wait_for_sync(uart->instance);
+
+    return RT_EOK;
+}
+
+static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    SAMD2x_UART_T *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (SAMD2x_UART_T *)(serial->parent.user_data);
+
+    switch (cmd)
+    {
+        /* disable interrupt */
+    case RT_DEVICE_CTRL_CLR_INT:
+        uart->com->USART.INTENCLR.reg = SERCOM_USART_INTFLAG_RXC;
+        usart_disable_transceiver(uart->instance, USART_TRANSCEIVER_RX);
+        system_interrupt_disable(uart->vector);
+        /* Wait for the synchronization to complete */
+	    _usart_wait_for_sync(uart->instance);
+        break;
+        /* enable interrupt */
+    case RT_DEVICE_CTRL_SET_INT:
+        /* Enable RX interrupt. */
+        /* Enable the RX Complete Interrupt */
+        uart->com->USART.INTENSET.reg = SERCOM_USART_INTFLAG_RXC;
+        usart_enable_transceiver(uart->instance, USART_TRANSCEIVER_RX);
+        system_interrupt_enable(uart->vector);
+        /* Wait for the synchronization to complete */
+	    _usart_wait_for_sync(uart->instance);
+        break;
+
+    default:
+        return RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static int _uart_putc(struct rt_serial_device *serial, char c)
+{
+    SAMD2x_UART_T *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    // while (!(uart->com->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) {
+    // }
+
+    uart = (SAMD2x_UART_T *)(serial->parent.user_data);
+
+	/* Write data to USART module */
+	uart->com->USART.DATA.reg = c;
+
+	while (!(uart->com->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) {
+		/* Wait until data is sent */
+    }
+
+    return 1;
+}
+
+static int _uart_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    SAMD2x_UART_T *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (SAMD2x_UART_T *)(serial->parent.user_data);
+
+    /* Check if USART has new data */
+	if (!(uart->com->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) {
+		/* Return error code */
+		return -1;
+    }
+
+    ch = uart->com->USART.DATA.reg & 0x1FF;
+
+    return ch;
+}
+
+static struct rt_uart_ops _uart_ops = {
+    _uart_cfg,
+    _uart_ctrl,
+    _uart_putc,
+    _uart_getc
+};
+
+static void uart_int_cb(SAMD2x_UART_T *uart_handle)
+{
+    /* Temporary variables */
+	uint16_t interrupt_status;
+	uint8_t error_code;
+    struct usart_module *module = uart_handle->instance;
+	/* Pointer to the hardware module instance */
+	SercomUsart *const usart_hw = &(module->hw->USART);
+
+	/* Read and mask interrupt flag register */
+	interrupt_status = usart_hw->INTFLAG.reg;
+	interrupt_status &= usart_hw->INTENSET.reg;
+
+	/* Check if the Receive Complete interrupt has occurred, and that
+	 * there's more data to receive */
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXC) {
+        /* Read out the status code and mask away all but the 4 LSBs*/
+        error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK);
+#if !SAMD20
+        /* CTS status should not be considered as an error */
+        if(error_code & SERCOM_USART_STATUS_CTS) {
+            error_code &= ~SERCOM_USART_STATUS_CTS;
+        }
+#endif
+#ifdef FEATURE_USART_LIN_MASTER
+        /* TXE status should not be considered as an error */
+        if(error_code & SERCOM_USART_STATUS_TXE) {
+            error_code &= ~SERCOM_USART_STATUS_TXE;
+        }
+#endif
+        /* Check if an error has occurred during the receiving */
+        if (error_code) {
+            /* Check which error occurred */
+            if (error_code & SERCOM_USART_STATUS_FERR) {
+                /* clear flag by writing 1 to it */
+                usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR;
+            } else if (error_code & SERCOM_USART_STATUS_BUFOVF) {
+                /* clear flag by writing 1 to it */
+                usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF;
+            } else if (error_code & SERCOM_USART_STATUS_PERR) {
+                /* clear flag by writing 1 to it */
+                usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR;
+            }
+#ifdef FEATURE_USART_LIN_SLAVE
+            else if (error_code & SERCOM_USART_STATUS_ISF) {
+                /* clear flag by writing 1 to it */
+                usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF;
+            }
+#endif
+#ifdef FEATURE_USART_COLLISION_DECTION
+            else if (error_code & SERCOM_USART_STATUS_COLL) {
+                /* clear flag by writing 1 to it */
+                usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL;
+            }
+#endif
+        } else {
+            rt_hw_serial_isr(uart_handle->serial, RT_SERIAL_EVENT_RX_IND);
+        }
+	}
+
+#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL
+	if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC;
+	}
+#endif
+
+#ifdef FEATURE_USART_LIN_SLAVE
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK;
+	}
+#endif
+
+#ifdef FEATURE_USART_START_FRAME_DECTION
+	if (interrupt_status & SERCOM_USART_INTFLAG_RXS) {
+		/* Disable interrupts */
+		usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS;
+		/* Clear interrupt flag */
+		usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS;
+	}
+#endif
+}
+
+void SERCOM3_Handler(void)
+{
+    uart_int_cb(&_uart3);
+}
+
+void uart_init(void)
+{
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    config.bufsz = 512;
+    _serial3.config = config;
+    _serial3.ops = &_uart_ops;
+
+    rt_hw_serial_register(&_serial3, "uart3", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_uart3);
+}

bsp/samd21/rtconfig.h

+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX	   6
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE	4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	8
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND	200
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+#define RT_DEBUG
+//#define RT_DEBUG_INIT 1
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+#define RT_USING_HOOK
+
+#define IDLE_THREAD_STACK_SIZE	512
+
+/* Using Software Timer */
+/* #define RT_USING_TIMER_SOFT */
+#define RT_TIMER_THREAD_PRIO		4
+#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_TICK_PER_SECOND	100
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+/* #define RT_USING_MAILBOX */
+
+/* Using Message Queue */
+/* #define RT_USING_MESSAGEQUEUE */
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+/* #define RT_USING_MEMPOOL */
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+#define RT_USING_TINY_SIZE
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+//#define RT_USING_COMPONENTS_INIT
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+// <bool name="RT_USING_DEVICE_IPC" description="Using device communication" default="true" />
+#define RT_USING_DEVICE_IPC
+// <bool name="RT_USING_SERIAL" description="Using Serial" default="true" />
+#define RT_USING_SERIAL
+
+/* SECTION: Console options */
+#define RT_USING_CONSOLE
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE	128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
+#define RT_CONSOLE_DEVICE_NAME	    "uart3"
+
+// #define RT_USING_SPI
+
+/* SECTION: finsh, a C-Express shell */
+// #define RT_USING_FINSH
+/* configure finsh parameters */
+#define FINSH_THREAD_PRIORITY 6
+#define FINSH_THREAD_STACK_SIZE	512
+#define FINSH_HISTORY_LINES	1
+/* Using symbol table */
+// #define FINSH_USING_SYMTAB
+// #define FINSH_USING_DESCRIPTION
+
+// #define FINSH_USING_MSH
+// #define FINSH_USING_MSH_ONLY
+
+#endif

bsp/samd21/rtconfig.py

+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m0'
+CROSS_TOOL='keil'
+
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+#DEVICE_SERIES = 'SAMD20'
+DEVICE_SERIES = 'SAMD21'
+#DEVICE_TYPE = '__SAMD20G18A__'
+DEVICE_TYPE = '__SAMD21J18A__'
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH 	= 'C:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= 'C:/Keil'
+elif CROSS_TOOL == 'iar':
+    print '================ERROR============================'
+    print 'Not support iar yet!'
+    print '================================================='
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'axf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m0+ -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-MKL15Z128.map,-cref,-u,Reset_Handler -T MKL15Z128_FLASH.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-SAM_D2x.map --strict --scatter SAM_D2X_RTT.sct'
+
+    CFLAGS += ' --c99'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'

bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_common_tables.h

+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+//extern const q31_t realCoefAQ31[1024];
+//extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */

bsp/samd21/sam_d2x_asflib/CMSIS/Include/arm_const_structs.h

+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        31. July 2014
+* $Revision: 	V1.4.4
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif

bsp/samd21/sam_d2x_asflib/CMSIS/Include/core_cmFunc.h

+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.00
+ * @date     28. August 2014
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

bsp/samd21/sam_d2x_asflib/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+#var defined
+CPPDEFINES = []
+src = []
+path = []
+
+#common lib define
+CPPDEFINES += [rtconfig.DEVICE_TYPE, 'DEBUG']
+
+#CMSIS/Include/ common/ common2/service/delay 
+path += [cwd + '/CMSIS/Include/']
+path += [cwd + '/common/utils/', cwd + '/common/utils/interrupt/']
+path += [cwd + '/common/boards/']
+path += [cwd + '/common2/services/delay/', cwd + '/common2/services/delay/sam0/']
+src += Glob('./common/utils/interrupt/interrupt_sam_nvic.c')
+
+#sam0/ sam0/utils/
+path += [cwd + '/sam0/', cwd + '/sam0/utils/']
+path += [cwd + '/sam0/utils/preprocessor']
+path += [cwd + '/sam0/utils/header_files']
+
+#sam0/utils/cmsis/
+if rtconfig.DEVICE_SERIES == 'SAMD20':
+	#D20
+	path += [cwd + '/sam0/', cwd + '/sam0/utils/cmsis/samd20/include/']
+	path += [cwd + '/sam0/utils/cmsis/samd20/source/']
+	src	+= Glob('./sam0/utils/cmsis/samd20/source/*.c')
+	src += Glob('./sam0/utils/cmsis/samd20/source/arm/*.s')
+elif rtconfig.DEVICE_SERIES == 'SAMD21':
+	#D21
+	path += [cwd + '/sam0/utils/cmsis/samd21/include/']
+	path += [cwd + '/sam0/utils/cmsis/samd21/source/']
+	src	+= Glob('./sam0/utils/cmsis/samd21/source/*.c')
+	src += Glob('./sam0/utils/cmsis/samd21/source/arm/*.s')
+
+#sam0/drivers/system
+path += [cwd + '/sam0/drivers/system/']
+src += Glob('./sam0/drivers/system/system.c')
+path += [cwd + '/sam0/drivers/system/pinmux']
+src += Glob('./sam0/drivers/system/pinmux/*.c')
+path += [cwd + '/sam0/drivers/system/power/power_sam_d_r_h']
+path += [cwd + '/sam0/drivers/system/reset/reset_sam_d_r_h']
+path += [cwd + '/sam0/drivers/system/clock']
+path += [cwd + '/sam0/drivers/system/interrupt/']
+src += Glob('./sam0/drivers/system/interrupt/*.c')
+if rtconfig.DEVICE_SERIES == 'SAMD20':
+	path += [cwd + '/sam0/drivers/system/interrupt/system_interrupt_samd20/']
+elif rtconfig.DEVICE_SERIES == 'SAMD21':
+	path += [cwd + '/sam0/drivers/system/interrupt/system_interrupt_samd21/']
+
+#sam0/drivers/system/clock
+if rtconfig.DEVICE_SERIES == 'SAMD20':
+	path += [cwd + '/sam0/drivers/system/clock/clock_samd20']
+	#path += [cwd + '/sam0/drivers/system/clock/clock_samd20/module_config']
+	src += Glob('./sam0/drivers/system/clock/clock_samd20/*.c')
+elif rtconfig.DEVICE_SERIES == 'SAMD21':
+	#path += [cwd + '/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/module_config']
+	path += [cwd + '/sam0/drivers/system/clock/clock_samd21_r21_da_ha1']
+	src += Glob('./sam0/drivers/system/clock/clock_samd21_r21_da_ha1/*.c')
+
+#sam0/drivers/sercom
+path += [cwd + '/sam0/drivers/sercom', cwd + '/sam0/drivers/sercom/usart']
+src += Glob('./sam0/drivers/sercom/*.c')
+src += Glob('./sam0/drivers/sercom/usart/*.c')
+SrcRemove(src, 'sercom_interrupt.c')
+SrcRemove(src, 'usart_interrupt.c')
+CPPDEFINES += ['USART_CALLBACK_MODE=false']
+
+#sam0/drivers/port
+path += [cwd + '/sam0/drivers/port']
+src += Glob('./sam0/drivers/port/port.c')
+
+#sam0/drivers/rtc
+path += [cwd + '/sam0/drivers/rtc']
+src += Glob('./sam0/drivers/rtc/rtc_sam_d_r_h/rtc_count*.c')
+CPPDEFINES += ['RTC_COUNT_ASYNC=true']
+
+#sam0/drivers/extint
+path += [cwd + '/sam0/drivers/extint', cwd + '/sam0/drivers/extint/extint_sam_d_r_h']
+src += Glob('./sam0/drivers/extint/extint_callback.c')
+src += Glob('./sam0/drivers/extint/extint_sam_d_r_h/extint.c')
+CPPDEFINES += ['EXTINT_CALLBACK_MODE=true']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
\ No newline at end of file

bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.c

+/**
+ * \file
+ *
+ * \brief SECURITY_XPLAINED extension board adaptation.
+ *
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+
+#include "security_xplained.h"
+#include "sha204_physical.h"
+#include "conf_atsha204.h"
+
+
+//! TWI address used at SHA204 library startup
+#define SHA204_I2C_DEFAULT_ADDRESS  (0xCA)
+
+
+/** \brief This function initializes peripherals needed to communicate with
+ *         the I2C security devices (ATSHA204 and ATAES132).
+ */
+void security_board_init(void)
+{
+	sha204p_init();
+}
+
+
+/** \brief This function returns the I2C address of a chosen SHA204 device.
+ *  \param[in] index the selected device on the Security Xplained board
+ *  \return I2C address of chosen device
+ */
+uint8_t sha204_i2c_address(uint8_t index)
+{
+	static uint8_t i2c_addresses[SHA204_DEVICE_COUNT] = {SHA204_I2C_DEFAULT_ADDRESS, 0xCC, 0xCE, 0xF8};
+	return i2c_addresses[index % SHA204_DEVICE_COUNT];
+}
+

bsp/samd21/sam_d2x_asflib/common/boards/security_xplained/security_xplained.h

+/**
+ * \file
+ *
+ * \brief SECURITY_XPLAINED_BOARD board header file.
+ *
+ * This file contains definitions and services related to the features of the
+ * SECURITY_XPLAINED Xplained board.
+ *
+ * To use the board, define EXT_BOARD=SECURITY_XPLAINED.
+ *
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef SECURITY_XPLAINED_H_
+#   define SECURITY_XPLAINED_H_
+
+#include <compiler.h>
+
+//! number of ATSHA204 I2C devices on Security Xplained extension board
+#define SHA204_DEVICE_COUNT          (4)
+
+void security_board_init(void);
+uint8_t sha204_i2c_address(uint8_t index);
+
+#endif /* SECURITY_XPLAINED_H_ */

bsp/samd21/sam_d2x_asflib/common/boards/user_board/board_config/conf_board.h

+/**
+ * \file
+ *
+ * \brief User board configuration template
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CONF_BOARD_H
+#define CONF_BOARD_H
+
+#endif // CONF_BOARD_H

bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/flash.gdb

+# This file needs to be customized to your MCU and is intentionally left blank

bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/flash.mac

+// This file needs to be customized to your MCU and is intentionally left blank /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */

bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/ram.gdb

+# This file needs to be customized to your MCU and is intentionally left blank

bsp/samd21/sam_d2x_asflib/common/boards/user_board/debug_config/ram.mac

+// This file needs to be customized to your MCU and is intentionally left blank /**
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */

bsp/samd21/sam_d2x_asflib/common/boards/user_board/init.c

+/**
+ * \file
+ *
+ * \brief User board initialization template
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include <asf.h>
+#include <board.h>
+#include <conf_board.h>
+
+void board_init(void)
+{
+	/* This function is meant to contain board-specific initialization code
+	 * for, e.g., the I/O pins. The initialization can rely on application-
+	 * specific board configuration, found in conf_board.h.
+	 */
+}

bsp/samd21/sam_d2x_asflib/common/boards/user_board/user_board.h

+/**
+ * \file
+ *
+ * \brief User board definition template
+ *
+ */
+
+ /* This file is intended to contain definitions and configuration details for
+ * features and devices that are available on the board, e.g., frequency and
+ * startup time for an external crystal, external memory devices, LED and USART
+ * pins.
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef USER_BOARD_H
+#define USER_BOARD_H
+
+#include <conf_board.h>
+
+// External oscillator settings.
+// Uncomment and set correct values if external oscillator is used.
+
+// External oscillator frequency
+//#define BOARD_XOSC_HZ          8000000
+
+// External oscillator type.
+//!< External clock signal
+//#define BOARD_XOSC_TYPE        XOSC_TYPE_EXTERNAL
+//!< 32.768 kHz resonator on TOSC
+//#define BOARD_XOSC_TYPE        XOSC_TYPE_32KHZ
+//!< 0.4 to 16 MHz resonator on XTALS
+//#define BOARD_XOSC_TYPE        XOSC_TYPE_XTAL
+
+// External oscillator startup time
+//#define BOARD_XOSC_STARTUP_US  500000
+
+
+#endif // USER_BOARD_H

bsp/samd21/sam_d2x_asflib/common/components/crypto/sha204/module_config/conf_atsha204.h

+/**
+ * \file
+ *
+ * \brief ATSHA204 CryptoAuth driver configuration file
+ *
+ *
+ * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+#ifndef CONF_ATSHA204_H_INCLUDED
+#define CONF_ATSHA204_H_INCLUDED
+
+#include <board.h>
+
+#if BOARD == XMEGA_A1_XPLAINED
+// Interface configuration for XMEGA-A1 Xplained
+#  define ATSHA204_TWI_PORT         (&TWIC)
+
+#else
+// Interface configuration for other boards
+#  warning ATSHA204 TWI port is not set for your board. Please see conf_atsha204.h.
+#  define ATSHA204_TWI_PORT         (&TWIC)
+#endif // BOARD
+
+// Xplain board independent configuration
+#define ATSHA204_TWI_SPEED      	(400000)
+
+//! TWI address used at SHA204 library startup
+#define SHA204_I2C_DEFAULT_ADDRESS  (0xCA)
+
+#endif /* CONF_ATSHA204_H_INCLUDED */

bsp/samd21/sam_d2x_asflib/common/drivers/nvm/sam/module_config/conf_nvm.h

+/**
+ * \file
+ *
+ * \brief Non volatile memories management for SAM devices
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#ifndef CONF_NVM_H_INCLUDED
+#define CONF_NVM_H_INCLUDED
+
+#endif /* CONF_NVM_H_INCLUDED */