未验证 提交 298ddc60 编写于 作者: B Bernard Xiong 提交者: GitHub

Merge pull request #2433 from lymzzyh/master

[BSP][K210]Add LCD Camera driver
......@@ -65,7 +65,7 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uarths"
CONFIG_RT_VER_NUM=0x40000
CONFIG_RT_VER_NUM=0x40001
CONFIG_ARCH_CPU_64BIT=y
CONFIG_ARCH_RISCV=y
CONFIG_ARCH_RISCV64=y
......@@ -126,6 +126,7 @@ CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
......@@ -142,6 +143,7 @@ CONFIG_RT_SERIAL_USING_DMA=y
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
#
# Using WiFi
......@@ -233,6 +235,7 @@ CONFIG_RT_USING_POSIX=y
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
......@@ -247,6 +250,8 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
#
# security packages
......@@ -278,6 +283,7 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ADBD is not set
#
# system packages
......@@ -298,6 +304,18 @@ CONFIG_RT_USING_POSIX=y
#
# peripheral libraries and drivers
#
#
# sensors drivers
#
# CONFIG_PKG_USING_LSM6DSL is not set
# CONFIG_PKG_USING_LPS22HB is not set
# CONFIG_PKG_USING_HTS221 is not set
# CONFIG_PKG_USING_LSM303AGR is not set
# CONFIG_PKG_USING_BME280 is not set
# CONFIG_PKG_USING_BMA400 is not set
# CONFIG_PKG_USING_BMI160_BMX160 is not set
# CONFIG_PKG_USING_SPL0601 is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AHT10 is not set
......@@ -308,6 +326,7 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
CONFIG_PKG_USING_KENDRYTE_SDK=y
CONFIG_PKG_KENDRYTE_SDK_PATH="/packages/peripherals/kendryte-sdk"
CONFIG_PKG_USING_KENDRYTE_SDK_V052=y
......@@ -337,12 +356,14 @@ CONFIG_PKG_KENDRYTE_SDK_VER="v0.5.2"
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
#
# Privated Packages of RealThread
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_MPLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
# CONFIG_PKG_USING_JS_PERSIMMON is not set
# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
......@@ -359,6 +380,44 @@ CONFIG_PKG_KENDRYTE_SDK_VER="v0.5.2"
# CONFIG_PKG_USING_RTINSIGHT is not set
# CONFIG_PKG_USING_SMARTCONFIG is not set
# CONFIG_PKG_USING_RTX is not set
# CONFIG_RT_USING_TESTCASE is not set
# CONFIG_PKG_USING_NGHTTP2 is not set
# CONFIG_PKG_USING_AVS is not set
# CONFIG_PKG_USING_STS is not set
# CONFIG_PKG_USING_DLMS is not set
#
# Test Packages of RealThread
#
#
# RT-Thread Senior Membership Packages
#
#
# system packages
#
# CONFIG_PKG_USING_FTL_SRC is not set
#
# IoT - internet of things
#
#
# Webnet: A web server package for rt-thread
#
#
# rtpkgs online packages
#
# CONFIG_PKG_USING_CSTRING is not set
# CONFIG_PKG_USING_ARGPARSE is not set
# CONFIG_PKG_USING_LIBBMPREAD is not set
# CONFIG_PKG_USING_LIBUTILS is not set
# CONFIG_PKG_USING_SAM is not set
# CONFIG_PKG_USING_LIBCALLBACK is not set
# CONFIG_PKG_USING_Z_EVENT is not set
# CONFIG_PKG_USING_LIBSTM32HAL is not set
CONFIG_BOARD_K210_EVB=y
CONFIG_BSP_USING_UART_HS=y
# CONFIG_BSP_USING_UART1 is not set
......@@ -366,4 +425,18 @@ CONFIG_BSP_USING_UART_HS=y
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_SPI1 is not set
CONFIG_BSP_USING_LCD=y
CONFIG_BSP_LCD_CS_PIN=6
CONFIG_BSP_LCD_WR_PIN=7
CONFIG_BSP_LCD_DC_PIN=8
CONFIG_BSP_LCD_X_MAX=240
CONFIG_BSP_LCD_Y_MAX=320
CONFIG_BSP_USING_CAMERA=y
CONFIG_BSP_CAMERA_SCCB_SDA_PIN=9
CONFIG_BSP_CAMERA_SCCB_SCLK_PIN=10
CONFIG_BSP_CAMERA_CMOS_RST_PIN=11
CONFIG_BSP_CAMERA_CMOS_VSYNC_PIN=12
CONFIG_BSP_CAMERA_CMOS_PWDN_PIN=13
CONFIG_BSP_CAMERA_CMOS_XCLK_PIN=14
CONFIG_BSP_CAMERA_CMOS_PCLK_PIN=15
CONFIG___STACKSIZE__=4096
......@@ -23,3 +23,55 @@ config BSP_USING_SPI1
bool "Enable SPI1 (GPIO0/1)"
select RT_USING_SPI
default n
menuconfig BSP_USING_LCD
bool "Enable LCD on SPI0"
default n
if BSP_USING_LCD
config BSP_LCD_CS_PIN
int "CS pin number of 8080 interface"
default 6
config BSP_LCD_WR_PIN
int "DC pin number of 8080 interface"
default 7
config BSP_LCD_DC_PIN
int "DC pin number of 8080 interface"
default 8
config BSP_LCD_X_MAX
int "LCD Height"
default 240
config BSP_LCD_Y_MAX
int "LCD Width"
default 320
endif
menuconfig BSP_USING_CAMERA
bool "Enable Camera"
default n
if BSP_USING_CAMERA
config BSP_CAMERA_SCCB_SDA_PIN
int "SCCB SDA pin number for camera"
default 9
config BSP_CAMERA_SCCB_SCLK_PIN
int "SCCB SCLK pin number for camera"
default 10
config BSP_CAMERA_CMOS_RST_PIN
int "CMOS RST pin number for camera"
default 11
config BSP_CAMERA_CMOS_VSYNC_PIN
int "CMOS VSYNC pin number for camera"
default 12
config BSP_CAMERA_CMOS_PWDN_PIN
int "CMOS PWDN pin number for camera"
default 13
config BSP_CAMERA_CMOS_XCLK_PIN
int "CMOS XCLK pin number for camera"
default 14
config BSP_CAMERA_CMOS_PCLK_PIN
int "CMOS PCLK pin number for camera"
default 15
endif
......@@ -10,6 +10,9 @@ drv_uart.c
''')
CPPPATH = [cwd]
if GetDepend('BSP_USING_LCD'):
src += ['drv_lcd.c']
if GetDepend('RT_USING_PIN'):
src += ['drv_gpio.c']
......
from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd]
group = DefineGroup('camera', src, depend = ['BSP_USING_CAMERA'], CPPPATH = CPPPATH)
Return('group')
/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
#include <unistd.h>
#include "drv_ov5640.h"
#include "ov5640cfg.h"
#include "ov5640af.h"
#include "dvp.h"
static void hal_delay(uint32_t delay)
{
usleep(delay * 1000);
}
static void ov5640_wr_reg(uint16_t reg,uint8_t data)
{
dvp_sccb_send_data(OV5640_ADDR, reg, data);
}
static uint8_t ov5640_rd_reg(uint16_t reg)
{
return dvp_sccb_receive_data(OV5640_ADDR, reg);
}
uint8_t ov5640_init(void)
{
uint16_t i = 0;
uint16_t reg = 0;
reg = ov5640_rd_reg(OV5640_CHIPIDH);
reg <<= 8;
reg |= ov5640_rd_reg(OV5640_CHIPIDL);
if(reg != OV5640_ID)
{
printf("ID: %d \r\n", reg);
return 1;
}
ov5640_wr_reg(0x3103,0X11); /*system clock from pad, bit[1]*/
ov5640_wr_reg(0X3008,0X82);
hal_delay(10);
for(i = 0; i<sizeof(ov5640_init_reg_tbl) / 4; i++)
{
ov5640_wr_reg(ov5640_init_reg_tbl[i][0], ov5640_init_reg_tbl[i][1]);
}
hal_delay(50);
/* Test for flash light*/
ov5640_flash_lamp(1);
hal_delay(50);
ov5640_flash_lamp(0);
return 0x00;
}
void ov5640_flash_lamp(uint8_t sw)
{
ov5640_wr_reg(0x3016, 0X02);
ov5640_wr_reg(0x301C, 0X02);
if(sw)
ov5640_wr_reg(0X3019, 0X02);
else
ov5640_wr_reg(0X3019, 0X00);
}
const static uint8_t OV5640_EXPOSURE_TBL[7][6]=
{
0x10,0x08,0x10,0x08,0x20,0x10,//-3
0x20,0x18,0x41,0x20,0x18,0x10,//-2
0x30,0x28,0x61,0x30,0x28,0x10,//-1
0x38,0x30,0x61,0x38,0x30,0x10,//0
0x40,0x38,0x71,0x40,0x38,0x10,//+1
0x50,0x48,0x90,0x50,0x48,0x20,//+2
0x60,0x58,0xa0,0x60,0x58,0x20,//+3
};
//exposure: 0 - 6,
void OV5640_Exposure(uint8_t exposure)
{
ov5640_wr_reg(0x3212,0x03); //start group 3
ov5640_wr_reg(0x3a0f,OV5640_EXPOSURE_TBL[exposure][0]);
ov5640_wr_reg(0x3a10,OV5640_EXPOSURE_TBL[exposure][1]);
ov5640_wr_reg(0x3a1b,OV5640_EXPOSURE_TBL[exposure][2]);
ov5640_wr_reg(0x3a1e,OV5640_EXPOSURE_TBL[exposure][3]);
ov5640_wr_reg(0x3a11,OV5640_EXPOSURE_TBL[exposure][4]);
ov5640_wr_reg(0x3a1f,OV5640_EXPOSURE_TBL[exposure][5]);
ov5640_wr_reg(0x3212,0x13); //end group 3
ov5640_wr_reg(0x3212,0xa3); //launch group 3
}
const static uint8_t OV5640_LIGHTMODE_TBL[5][7]=
{
0x04,0X00,0X04,0X00,0X04,0X00,0X00,//Auto
0x06,0X1C,0X04,0X00,0X04,0XF3,0X01,//Sunny
0x05,0X48,0X04,0X00,0X07,0XCF,0X01,//Office
0x06,0X48,0X04,0X00,0X04,0XD3,0X01,//Cloudy
0x04,0X10,0X04,0X00,0X08,0X40,0X01,//Home
};
// light mode:
// 0: auto
// 1: sunny
// 2: office
// 3: cloudy
// 4: home
void OV5640_Light_Mode(uint8_t mode)
{
uint8_t i;
ov5640_wr_reg(0x3212,0x03); //start group 3
for(i=0;i<7;i++)ov5640_wr_reg(0x3400+i,OV5640_LIGHTMODE_TBL[mode][i]);
ov5640_wr_reg(0x3212,0x13); //end group 3
ov5640_wr_reg(0x3212,0xa3); //launch group 3
}
const static uint8_t OV5640_SATURATION_TBL[7][6]=
{
0X0C,0x30,0X3D,0X3E,0X3D,0X01,//-3
0X10,0x3D,0X4D,0X4E,0X4D,0X01,//-2
0X15,0x52,0X66,0X68,0X66,0X02,//-1
0X1A,0x66,0X80,0X82,0X80,0X02,//+0
0X1F,0x7A,0X9A,0X9C,0X9A,0X02,//+1
0X24,0x8F,0XB3,0XB6,0XB3,0X03,//+2
0X2B,0xAB,0XD6,0XDA,0XD6,0X04,//+3
};
// Color Saturation:
// sat: 0 - 6
void OV5640_Color_Saturation(uint8_t sat)
{
uint8_t i;
ov5640_wr_reg(0x3212,0x03); //start group 3
ov5640_wr_reg(0x5381,0x1c);
ov5640_wr_reg(0x5382,0x5a);
ov5640_wr_reg(0x5383,0x06);
for(i=0;i<6;i++) ov5640_wr_reg(0x5384+i,OV5640_SATURATION_TBL[sat][i]);
ov5640_wr_reg(0x538b, 0x98);
ov5640_wr_reg(0x538a, 0x01);
ov5640_wr_reg(0x3212, 0x13); //end group 3
ov5640_wr_reg(0x3212, 0xa3); //launch group 3
}
//Brightness
// bright: 0 - 8
void OV5640_Brightness(uint8_t bright)
{
uint8_t brtval;
if(bright<4)brtval=4-bright;
else brtval=bright-4;
ov5640_wr_reg(0x3212,0x03); //start group 3
ov5640_wr_reg(0x5587,brtval<<4);
if(bright<4)ov5640_wr_reg(0x5588,0x09);
else ov5640_wr_reg(0x5588,0x01);
ov5640_wr_reg(0x3212,0x13); //end group 3
ov5640_wr_reg(0x3212,0xa3); //launch group 3
}
//Contrast:
// contrast: 0 - 6
void OV5640_Contrast(uint8_t contrast)
{
uint8_t reg0val=0X00;
uint8_t reg1val=0X20;
switch(contrast)
{
case 0://-3
reg1val=reg0val=0X14;
break;
case 1://-2
reg1val=reg0val=0X18;
break;
case 2://-1
reg1val=reg0val=0X1C;
break;
case 4://1
reg0val=0X10;
reg1val=0X24;
break;
case 5://2
reg0val=0X18;
reg1val=0X28;
break;
case 6://3
reg0val=0X1C;
reg1val=0X2C;
break;
}
ov5640_wr_reg(0x3212,0x03); //start group 3
ov5640_wr_reg(0x5585,reg0val);
ov5640_wr_reg(0x5586,reg1val);
ov5640_wr_reg(0x3212,0x13); //end group 3
ov5640_wr_reg(0x3212,0xa3); //launch group 3
}
// Sharpness:
// sharp: 0 - 33 (0: close , 33: auto , other: Sharpness)
void OV5640_Sharpness(uint8_t sharp)
{
if(sharp<33)
{
ov5640_wr_reg(0x5308,0x65);
ov5640_wr_reg(0x5302,sharp);
}else // auto
{
ov5640_wr_reg(0x5308,0x25);
ov5640_wr_reg(0x5300,0x08);
ov5640_wr_reg(0x5301,0x30);
ov5640_wr_reg(0x5302,0x10);
ov5640_wr_reg(0x5303,0x00);
ov5640_wr_reg(0x5309,0x08);
ov5640_wr_reg(0x530a,0x30);
ov5640_wr_reg(0x530b,0x04);
ov5640_wr_reg(0x530c,0x06);
}
}
const static uint8_t OV5640_EFFECTS_TBL[7][3]=
{
0X06,0x40,0X10, // normal
0X1E,0xA0,0X40,
0X1E,0x80,0XC0,
0X1E,0x80,0X80,
0X1E,0x40,0XA0,
0X40,0x40,0X10,
0X1E,0x60,0X60,
};
void OV5640_Special_Effects(uint8_t eft)
{
ov5640_wr_reg(0x3212,0x03); //start group 3
ov5640_wr_reg(0x5580,OV5640_EFFECTS_TBL[eft][0]);
ov5640_wr_reg(0x5583,OV5640_EFFECTS_TBL[eft][1]);// sat U
ov5640_wr_reg(0x5584,OV5640_EFFECTS_TBL[eft][2]);// sat V
ov5640_wr_reg(0x5003,0x08);
ov5640_wr_reg(0x3212,0x13); //end group 3
ov5640_wr_reg(0x3212,0xa3); //launch group 3
}
uint8_t OV5640_Focus_Init(void)
{
uint16_t i;
uint16_t addr=0x8000;
uint8_t state=0x8F;
ov5640_wr_reg(0x3000, 0x20); //reset
for(i=0;i<sizeof(OV5640_AF_Config);i++)
{
ov5640_wr_reg(addr,OV5640_AF_Config[i]);
addr++;
}
ov5640_wr_reg(0x3022,0x00);
ov5640_wr_reg(0x3023,0x00);
ov5640_wr_reg(0x3024,0x00);
ov5640_wr_reg(0x3025,0x00);
ov5640_wr_reg(0x3026,0x00);
ov5640_wr_reg(0x3027,0x00);
ov5640_wr_reg(0x3028,0x00);
ov5640_wr_reg(0x3029,0x7f);
ov5640_wr_reg(0x3000,0x00);
i=0;
do
{
state=ov5640_rd_reg(0x3029);
hal_delay(5);
i++;
if(i>1000)return 1;
}while(state!=0x70);
return 0;
}
uint8_t OV5640_Auto_Focus(void)
{
uint8_t temp=0;
uint16_t retry=0;
ov5640_wr_reg(0x3023,0x01);
ov5640_wr_reg(0x3022,0x08);
do
{
temp=ov5640_rd_reg(0x3023);
retry++;
if(retry>1000)return 2;
hal_delay(5);
} while(temp!=0x00);
ov5640_wr_reg(0x3023,0x01);
ov5640_wr_reg(0x3022,0x04);
retry=0;
do
{
temp=ov5640_rd_reg(0x3023);
retry++;
if(retry>1000)return 2;
hal_delay(5);
}while(temp!=0x00);
return 0;
}
/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _OV5640_H
#define _OV5640_H
#include <stdint.h>
#define OV5640_ID 0X5640
#define OV5640_ADDR 0X78
#define OV5640_CHIPIDH 0X300A
#define OV5640_CHIPIDL 0X300B
#define XSIZE 320
#define YSIZE 240
#define LCD_GRAM_ADDRESS 0x60020000
#define QQVGA_160_120 0
#define QCIF_176_144 1
#define QVGA_320_240 2
#define WQVGA_400_240 3
#define CIF_352_288 4
#define jpeg_buf_size (30*1024)
uint8_t ov5640_init(void);
void ov5640_flash_lamp(uint8_t sw);
void OV5640_Brightness(uint8_t bright);
void OV5640_Exposure(uint8_t exposure);
void OV5640_Light_Mode(uint8_t mode);
void OV5640_Color_Saturation(uint8_t sat);
void OV5640_Brightness(uint8_t bright);
void OV5640_Contrast(uint8_t contrast);
void OV5640_Sharpness(uint8_t sharp);
void OV5640_Special_Effects(uint8_t eft);
uint8_t OV5640_Focus_Init(void);
uint8_t OV5640_Auto_Focus(void);
#endif
此差异已折叠。
/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License"},
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _OV5640CFG_H
#define _OV5640CFG_H
#include "drv_ov5640.h"
#if 1
const uint16_t ov5640_init_reg_tbl[][2]=
{
// 24MHz input clock, 24MHz PCLK
{0x3008, 0x42}, // software power down, bit[6]
{0x3103, 0x03}, // system clock from PLL, bit[1]
{0x3017, 0xff}, // FREX, Vsync, HREF, PCLK, D[9:6] output enable
{0x3018, 0xff}, // D[5:0], GPIO[1:0] output enable
{0x3034, 0x1a}, // MIPI 10-bit
{0x3035, 0x41},//0x41, // PLL
{0x3036, 0x90}, // PLL
{0x3037, 0x13},//0x13, // PLL root divider, bit[4], PLL pre-divider, bit[3:0]
{0x3108, 0x01}, // PCLK root divider, bit[5:4], SCLK2x root divider, bit[3:2], SCLK root divider, bit[1:0]
{0x3630, 0x36},
{0x3631, 0x0e},
{0x3632, 0xe2},
{0x3633, 0x12},
{0x3621, 0xe0},
{0x3704, 0xa0},
{0x3703, 0x5a},
{0x3715, 0x78},
{0x3717, 0x01},
{0x370b, 0x60},
{0x3705, 0x1a},
{0x3905, 0x02},
{0x3906, 0x10},
{0x3901, 0x0a},
{0x3731, 0x12},
{0x3600, 0x08}, // VCM control
{0x3601, 0x33}, // VCM control
{0x302d, 0x60}, // system control
{0x3620, 0x52},
{0x371b, 0x20},
{0x471c, 0x50},
{0x3a13, 0x43}, // pre-gain = 1.047x
{0x3a18, 0x00}, // gain ceiling
{0x3a19, 0xf8}, // gain ceiling = 15.5x
{0x3635, 0x13},
{0x3636, 0x03},
{0x3634, 0x40},
{0x3622, 0x01},
{0x3c01, 0x34}, // Band auto, bit[7]
{0x3c04, 0x28}, // threshold low sum
{0x3c05, 0x98}, // threshold high sum
{0x3c06, 0x00}, // light meter 1 threshold[15:8]
{0x3c07, 0x07}, // light meter 1 threshold[7:0]
{0x3c08, 0x00}, // light meter 2 threshold[15:8]
{0x3c09, 0x1c}, // light meter 2 threshold[7:0]
{0x3c0a, 0x9c}, // sample number[15:8]
{0x3c0b, 0x40}, // sample number[7:0]
{0x3810, 0x00}, // Timing Hoffset[11:8]
{0x3811, 0x10}, // Timing Hoffset[7:0]
{0x3812, 0x00}, // Timing Voffset[10:8]
{0x3708, 0x64},
{0x4001, 0x02}, // BLC start from line 2
{0x4005, 0x1a}, // BLC always update
{0x3000, 0x00}, // enable blocks
{0x3004, 0xff}, // enable clocks
{0x300e, 0x58}, // MIPI power down, DVP enable
{0x302e, 0x00},
{0x4300, 0x61},
{0X501F, 0x01},
{0x3820, 0x40}, // flip
{0x3821, 0x00}, // mirror
{0x3814, 0x71}, // timing X inc
{0x3815, 0x35}, // timing Y inc
{0x3800, 0x00}, // HS
{0x3801, 0x00}, // HS
{0x3802, 0x00}, // VS
{0x3803, 0x00}, // VS
{0x3804, 0x0a}, // HW (HE)
{0x3805, 0x3f}, // HW (HE)
{0x3806, 0x07}, // VH (VE)
{0x3807, 0x9f}, // VH (VE)
{0x3808, (320 >> 8)}, // DVPHO
{0x3809, (320 & 0xff)}, // DVPHO
{0x380a, (240 >> 8)}, // DVPVO
{0x380b, (240 & 0xff)}, // DVPVO
{0x380c, 0x07}, // HTS
{0x380d, 0x58}, // HTS
{0x380e, 0x01}, // VTS
{0x380f, 0xf0}, // VTS
{0x3810, 0x00}, // HTS
{0x3811, 0x08}, // HTS
{0x3812, 0x00}, // VTS
{0x3813, 0x02}, // VTS
{0x3618, 0x00},
{0x3612, 0x29},
{0x3709, 0x52},
{0x370c, 0x03},
{0x3a02, 0x02}, // 60Hz max exposure
{0x3a03, 0xe0}, // 60Hz max exposure
{0x3a14, 0x02}, // 50Hz max exposure
{0x3a15, 0xe0}, // 50Hz max exposure
{0x4004, 0x02}, // BLC line number
{0x3002, 0x1c}, // reset JFIFO, SFIFO, JPG
{0x3006, 0xc3}, // disable clock of JPEG2x, JPEG
{0x4713, 0x03}, // JPEG mode 3
{0x4407, 0x04}, // Quantization scale
{0x460b, 0x37},
{0x460c, 0x20},
{0x4837, 0x16}, // MIPI global timing
{0x3824, 0x04}, // PCLK manual divider
{0x5001, 0xA3}, // SDE on, scale on, UV average off, color matrix on, AWB on
{0x3503, 0x00}, // AEC/AGC on
{0x440e, 0x00},
{0x5000, 0xa7}, // Lenc on, raw gamma on, BPC on, WPC on, CIP on
{0x3a0f, 0x30}, // stable range in high
{0x3a10, 0x28}, // stable range in low
{0x3a1b, 0x30}, // stable range out high
{0x3a1e, 0x26}, // stable range out low
{0x3a11, 0x60}, // fast zone high
{0x3a1f, 0x14}, // fast zone low
{0x5800, 0x23},
{0x5801, 0x14},
{0x5802, 0x0f},
{0x5803, 0x0f},
{0x5804, 0x12},
{0x5805, 0x26},
{0x5806, 0x0c},
{0x5807, 0x08},
{0x5808, 0x05},
{0x5809, 0x05},
{0x580a, 0x08},
{0x580b, 0x0d},
{0x580c, 0x08},
{0x580d, 0x03},
{0x580e, 0x00},
{0x580f, 0x00},
{0x5810, 0x03},
{0x5811, 0x09},
{0x5812, 0x07},
{0x5813, 0x03},
{0x5814, 0x00},
{0x5815, 0x01},
{0x5816, 0x03},
{0x5817, 0x08},
{0x5818, 0x0d},
{0x5819, 0x08},
{0x581a, 0x05},
{0x581b, 0x06},
{0x581c, 0x08},
{0x581d, 0x0e},
{0x581e, 0x29},
{0x581f, 0x17},
{0x5820, 0x11},
{0x5821, 0x11},
{0x5822, 0x15},
{0x5823, 0x28},
{0x5824, 0x46},
{0x5825, 0x26},
{0x5826, 0x08},
{0x5827, 0x26},
{0x5828, 0x64},
{0x5829, 0x26},
{0x582a, 0x24},
{0x582b, 0x22},
{0x582c, 0x24},
{0x582d, 0x24},
{0x582e, 0x06},
{0x582f, 0x22},
{0x5830, 0x40},
{0x5831, 0x42},
{0x5832, 0x24},
{0x5833, 0x26},
{0x5834, 0x24},
{0x5835, 0x22},
{0x5836, 0x22},
{0x5837, 0x26},
{0x5838, 0x44},
{0x5839, 0x24},
{0x583a, 0x26},
{0x583b, 0x28},
{0x583c, 0x42},
{0x583d, 0xce}, // lenc BR offset
{0x5180, 0xff}, // AWB B block
{0x5181, 0xf2}, // AWB control
{0x5182, 0x00}, // [7:4] max local counter, [3:0] max fast counter
{0x5183, 0x14}, // AWB advanced
{0x5184, 0x25},
{0x5185, 0x24},
{0x5186, 0x09},
{0x5187, 0x09},
{0x5188, 0x09},
{0x5189, 0x75},
{0x518a, 0x54},
{0x518b, 0xe0},
{0x518c, 0xb2},
{0x518d, 0x42},
{0x518e, 0x3d},
{0x518f, 0x56},
{0x5190, 0x46},
{0x5191, 0xf8}, // AWB top limit
{0x5192, 0x04}, // AWB bottom limit
{0x5193, 0x70}, // red limit
{0x5194, 0xf0}, // green limit
{0x5195, 0xf0}, // blue limit
{0x5196, 0x03}, // AWB control
{0x5197, 0x01}, // local limit
{0x5198, 0x04},
{0x5199, 0x12},
{0x519a, 0x04},
{0x519b, 0x00},
{0x519c, 0x06},
{0x519d, 0x82},
{0x519e, 0x38}, // AWB control
{0x5480, 0x01}, // Gamma bias plus on, bit[0]
{0x5481, 0x08},
{0x5482, 0x14},
{0x5483, 0x28},
{0x5484, 0x51},
{0x5485, 0x65},
{0x5486, 0x71},
{0x5487, 0x7d},
{0x5488, 0x87},
{0x5489, 0x91},
{0x548a, 0x9a},
{0x548b, 0xaa},
{0x548c, 0xb8},
{0x548d, 0xcd},
{0x548e, 0xdd},
{0x548f, 0xea},
{0x5490, 0x1d},
{0x5381, 0x1e}, // CMX1 for Y
{0x5382, 0x5b}, // CMX2 for Y
{0x5383, 0x08}, // CMX3 for Y
{0x5384, 0x0a}, // CMX4 for U
{0x5385, 0x7e}, // CMX5 for U
{0x5386, 0x88}, // CMX6 for U
{0x5387, 0x7c}, // CMX7 for V
{0x5388, 0x6c}, // CMX8 for V
{0x5389, 0x10}, // CMX9 for V
{0x538a, 0x01}, // sign[9]
{0x538b, 0x98}, // sign[8:1]
{0x5580, 0x06}, // saturation on, bit[1]
{0x5583, 0x40},
{0x5584, 0x10},
{0x5589, 0x10},
{0x558a, 0x00},
{0x558b, 0xf8},
{0x501d, 0x40}, // enable manual offset of contrast
{0x5300, 0x08}, // CIP sharpen MT threshold 1
{0x5301, 0x30}, // CIP sharpen MT threshold 2
{0x5302, 0x10}, // CIP sharpen MT offset 1
{0x5303, 0x00}, // CIP sharpen MT offset 2
{0x5304, 0x08}, // CIP DNS threshold 1
{0x5305, 0x30}, // CIP DNS threshold 2
{0x5306, 0x08}, // CIP DNS offset 1
{0x5307, 0x16}, // CIP DNS offset 2
{0x5309, 0x08}, // CIP sharpen TH threshold 1
{0x530a, 0x30}, // CIP sharpen TH threshold 2
{0x530b, 0x04}, // CIP sharpen TH offset 1
{0x530c, 0x06}, // CIP sharpen TH offset 2
{0x5025, 0x00},
{0x3008, 0x02}, // wake up from standby, bit[6]
{0x4740, 0X21}, //VSYNC active HIGH
};
#else
const uint16_t ov5640_init_reg_tbl[][2]=
{
//; for the setting , 24M Mlck input and 24M Plck output
//;15fps YUV mode
{0x3103 ,0x11},
{0x3008 ,0x82},
{0x3008 ,0x42},
{0x3103 ,0x03},
{0x3017 ,0xff},
{0x3018 ,0xff},
{0x3034 ,0x1a},
{0x3035 ,0x11},
{0x3036 ,0x46},
{0x3037 ,0x13},
{0x3108 ,0x01},
{0x3630 ,0x36},
{0x3631 ,0x0e},
{0x3632 ,0xe2},
{0x3633 ,0x12},
{0x3621 ,0xe0},
{0x3704 ,0xa0},
{0x3703 ,0x5a},
{0x3715 ,0x78},
{0x3717 ,0x01},
{0x370b ,0x60},
{0x3705 ,0x1a},
{0x3905 ,0x02},
{0x3906 ,0x10},
{0x3901 ,0x0a},
{0x3731 ,0x12},
{0x3600 ,0x08},
{0x3601 ,0x33},
{0x302d ,0x60},
{0x3620 ,0x52},
{0x371b ,0x20},
{0x471c ,0x50},
{0x3a13 ,0x43},
{0x3a18 ,0x00},
{0x3a19 ,0xf8},
{0x3635 ,0x13},
{0x3636 ,0x03},
{0x3634 ,0x40},
{0x3622 ,0x01},
//Confidential For Actions Only
{0x3c01 ,0x34},
{0x3c04 ,0x28},
{0x3c05 ,0x98},
{0x3c06 ,0x00},
{0x3c07 ,0x08},
{0x3c08 ,0x00},
{0x3c09 ,0x1c},
{0x3c0a ,0x9c},
{0x3c0b ,0x40},
{0x3820 ,0x40},
{0x3821 ,0x00},
{0x3814 ,0x31},
{0x3815 ,0x31},
// {0x3800 ,0x00},
// {0x3801 ,0x00},
// {0x3802 ,0x00},
// {0x3803 ,0x04},
// {0x3804 ,0x0a},
// {0x3805 ,0x3f},
// {0x3806 ,0x07},
// {0x3807 ,0x9b},
// {0x3808 ,0x02},
// {0x3809 ,0x80},
// {0x380a ,0x01},
// {0x380b ,0xe0},
// {0x380c ,0x07},
// {0x380d ,0x68},
// {0x380e ,0x03},
// {0x380f ,0xd8},
{0x3800 ,0x0 },
{0x3801 ,0x0 },
{0x3802 ,0x0 },
{0x3803 ,0x4 },
{0x3804 ,0xa },
{0x3805 ,0x3f},
{0x3806 ,0x7 },
{0x3807 ,0x9b},
{0x3808 ,0x1 },
{0x3809 ,0x40},
{0x380a ,0x0 },
{0x380b ,0xf0},
{0x380c ,0x7 },
{0x380d ,0x68},
{0x380e ,0x3 },
{0x380f ,0xd8},
{0x3810 ,0x00},
{0x3811 ,0x10},
{0x3812 ,0x00},
{0x3813 ,0x06},
{0x3618 ,0x00},
{0x3612 ,0x29},
{0x3708 ,0x64},
{0x3709 ,0x52},
{0x370c ,0x03},
{0x3a02 ,0x03},
{0x3a03 ,0xd8},
{0x3a08 ,0x01},
{0x3a09 ,0x27},
{0x3a0a ,0x00},
{0x3a0b ,0xf6},
{0x3a0e ,0x03},
{0x3a0d ,0x04},
{0x3a14 ,0x03},
{0x3a15 ,0xd8},
//Confidential For Actions Only
{0x4001 ,0x02},
{0x4004 ,0x02},
{0x3000 ,0x00},
{0x3002 ,0x1c},
{0x3004 ,0xff},
{0x3006 ,0xc3},
{0x300e ,0x58},
{0x302e ,0x00},
// {0x4300 ,0x30},
// {0x501f ,0x00},
{0x4300 ,0x61},
{0x501f ,0x01},
{0x4713 ,0x03},
{0x4407 ,0x04},
{0x440e ,0x00},
{0x460b ,0x35},
{0x460c ,0x22},
{0x3824 ,0x02},
{0x5000 ,0xa7},
{0x5001 ,0xa3},
{0x5180 ,0xff},
{0x5181 ,0xf2},
{0x5182 ,0x00},
{0x5183 ,0x14},
{0x5184 ,0x25},
{0x5185 ,0x24},
{0x5186 ,0x09},
{0x5187 ,0x09},
{0x5188 ,0x09},
{0x5189 ,0x75},
{0x518a ,0x54},
{0x518b ,0xe0},
{0x518c ,0xb2},
{0x518d ,0x42},
{0x518e ,0x3d},
{0x518f ,0x56},
{0x5190 ,0x46},
{0x5191 ,0xf8},
{0x5192 ,0x04},
{0x5193 ,0x70},
{0x5194 ,0xf0},
{0x5195 ,0xf0},
{0x5196 ,0x03},
{0x5197 ,0x01},
{0x5198 ,0x04},
{0x5199 ,0x12},
{0x519a ,0x04},
{0x519b ,0x00},
{0x519c ,0x06},
{0x519d ,0x82},
//Confidential For Actions Only
{0x519e ,0x38},
{0x5381 ,0x1e},
{0x5382 ,0x5b},
{0x5383 ,0x08},
{0x5384 ,0x0a},
{0x5385 ,0x7e},
{0x5386 ,0x88},
{0x5387 ,0x7c},
{0x5388 ,0x6c},
{0x5389 ,0x10},
{0x538a ,0x01},
{0x538b ,0x98},
{0x5300 ,0x08},
{0x5301 ,0x30},
{0x5302 ,0x10},
{0x5303 ,0x00},
{0x5304 ,0x08},
{0x5305 ,0x30},
{0x5306 ,0x08},
{0x5307 ,0x16},
{0x5309 ,0x08},
{0x530a ,0x30},
{0x530b ,0x04},
{0x530c ,0x06},
{0x5480 ,0x01},
{0x5481 ,0x08},
{0x5482 ,0x14},
{0x5483 ,0x28},
{0x5484 ,0x51},
{0x5485 ,0x65},
{0x5486 ,0x71},
{0x5487 ,0x7d},
{0x5488 ,0x87},
{0x5489 ,0x91},
{0x548a ,0x9a},
{0x548b ,0xaa},
{0x548c ,0xb8},
{0x548d ,0xcd},
{0x548e ,0xdd},
{0x548f ,0xea},
{0x5490 ,0x1d},
{0x5580 ,0x02},
{0x5583 ,0x40},
{0x5584 ,0x10},
{0x5589 ,0x10},
{0x558a ,0x00},
{0x558b ,0xf8},
{0x5800 ,0x23},
//Confidential For Actions Only
{0x5801 ,0x14},
{0x5802 ,0x0f},
{0x5803 ,0x0f},
{0x5804 ,0x12},
{0x5805 ,0x26},
{0x5806 ,0x0c},
{0x5807 ,0x08},
{0x5808 ,0x05},
{0x5809 ,0x05},
{0x580a ,0x08},
{0x580b ,0x0d},
{0x580c ,0x08},
{0x580d ,0x03},
{0x580e ,0x00},
{0x580f ,0x00},
{0x5810 ,0x03},
{0x5811 ,0x09},
{0x5812 ,0x07},
{0x5813 ,0x03},
{0x5814 ,0x00},
{0x5815 ,0x01},
{0x5816 ,0x03},
{0x5817 ,0x08},
{0x5818 ,0x0d},
{0x5819 ,0x08},
{0x581a ,0x05},
{0x581b ,0x06},
{0x581c ,0x08},
{0x581d ,0x0e},
{0x581e ,0x29},
{0x581f ,0x17},
{0x5820 ,0x11},
{0x5821 ,0x11},
{0x5822 ,0x15},
{0x5823 ,0x28},
{0x5824 ,0x46},
{0x5825 ,0x26},
{0x5826 ,0x08},
{0x5827 ,0x26},
{0x5828 ,0x64},
{0x5829 ,0x26},
{0x582a ,0x24},
{0x582b ,0x22},
{0x582c ,0x24},
{0x582d ,0x24},
{0x582e ,0x06},
{0x582f ,0x22},
{0x5830 ,0x40},
//Confidential For Actions Only
{0x5831 ,0x42},
{0x5832 ,0x24},
{0x5833 ,0x26},
{0x5834 ,0x24},
{0x5835 ,0x22},
{0x5836 ,0x22},
{0x5837 ,0x26},
{0x5838 ,0x44},
{0x5839 ,0x24},
{0x583a ,0x26},
{0x583b ,0x28},
{0x583c ,0x42},
{0x583d ,0xce},
{0x5025 ,0x00},
{0x3a0f ,0x30},
{0x3a10 ,0x28},
{0x3a1b ,0x30},
{0x3a1e ,0x26},
{0x3a11 ,0x60},
{0x3a1f ,0x14},
{0x3008 ,0x02},
{0x3035 ,0x21},
//Band,0x50Hz
{0x3c01,0xb4},
{0x3c00,0x04},
//gain ceiling
{0x3a19,0x7c},
//OV5640 LENC setting
{0x5800 ,0x2c},
{0x5801 ,0x17},
{0x5802 ,0x11},
{0x5803 ,0x11},
{0x5804 ,0x15},
{0x5805 ,0x29},
{0x5806 ,0x08},
{0x5807 ,0x06},
{0x5808 ,0x04},
{0x5809 ,0x04},
{0x580a ,0x05},
{0x580b ,0x07},
{0x580c ,0x06},
{0x580d ,0x03},
{0x580e ,0x01},
{0x580f ,0x01},
{0x5810 ,0x03},
{0x5811 ,0x06},
//Confidential For Actions Only
{0x5812 ,0x06},
{0x5813 ,0x02},
{0x5814 ,0x01},
{0x5815 ,0x01},
{0x5816 ,0x04},
{0x5817 ,0x07},
{0x5818 ,0x06},
{0x5819 ,0x07},
{0x581a ,0x06},
{0x581b ,0x06},
{0x581c ,0x06},
{0x581d ,0x0e},
{0x581e ,0x31},
{0x581f ,0x12},
{0x5820 ,0x11},
{0x5821 ,0x11},
{0x5822 ,0x11},
{0x5823 ,0x2f},
{0x5824 ,0x12},
{0x5825 ,0x25},
{0x5826 ,0x39},
{0x5827 ,0x29},
{0x5828 ,0x27},
{0x5829 ,0x39},
{0x582a ,0x26},
{0x582b ,0x33},
{0x582c ,0x24},
{0x582d ,0x39},
{0x582e ,0x28},
{0x582f ,0x21},
{0x5830 ,0x40},
{0x5831 ,0x21},
{0x5832 ,0x17},
{0x5833 ,0x17},
{0x5834 ,0x15},
{0x5835 ,0x11},
{0x5836 ,0x24},
{0x5837 ,0x27},
{0x5838 ,0x26},
{0x5839 ,0x26},
{0x583a ,0x26},
{0x583b ,0x28},
{0x583c ,0x14},
{0x583d ,0xee},
{0x4005 ,0x1a},
//color
{0x5381,0x26},
{0x5382,0x50},
//Confidential For Actions Only
{0x5383,0x0c},
{0x5384,0x09},
{0x5385,0x74},
{0x5386,0x7d},
{0x5387,0x7e},
{0x5388,0x75},
{0x5389,0x09},
{0x538b,0x98},
{0x538a,0x01},
//UVAdjust Auto Mode
{0x5580,0x02},
{0x5588,0x01},
{0x5583,0x40},
{0x5584,0x10},
{0x5589,0x0f},
{0x558a,0x00},
{0x558b,0x3f},
//De-Noise,0xAuto
{0x5308,0x25},
{0x5304,0x08},
{0x5305,0x30},
{0x5306,0x10},
{0x5307,0x20},
//awb
{0x5180,0xff},
{0x5181,0xf2},
{0x5182,0x11},
{0x5183,0x14},
{0x5184,0x25},
{0x5185,0x24},
{0x5186,0x10},
{0x5187,0x12},
{0x5188,0x10},
{0x5189,0x80},
{0x518a,0x54},
{0x518b,0xb8},
{0x518c,0xb2},
{0x518d,0x42},
{0x518e,0x3a},
{0x518f,0x56},
{0x5190,0x46},
{0x5191,0xf0},
{0x5192,0xf},
{0x5193,0x70},
//Confidential For Actions Only
{0x5194,0xf0},
{0x5195,0xf0},
{0x5196,0x3},
{0x5197,0x1},
{0x5198,0x6},
{0x5199,0x62},
{0x519a,0x4},
{0x519b,0x0},
{0x519c,0x4},
{0x519d,0xe7},
{0x519e,0x38},
};
#endif
#endif
#include <rtthread.h>
#include <fpioa.h>
#include <drv_io_config.h>
#include <sysctl.h>
#define HS_GPIO(n) (FUNC_GPIOHS0 + n)
static struct io_config
{
int io_num;
fpioa_function_t func;
} io_config[] =
{
#ifdef BSP_USING_LCD
{BSP_LCD_CS_PIN, FUNC_SPI0_SS0}, /* LCD CS PIN */
{BSP_LCD_WR_PIN, FUNC_SPI0_SCLK}, /* LCD WR PIN */
{BSP_LCD_DC_PIN, HS_GPIO(LCD_DC_PIN)}, /* LCD DC PIN */
#endif
#ifdef BSP_USING_CAMERA
{BSP_CAMERA_SCCB_SDA_PIN, FUNC_SCCB_SDA},
{BSP_CAMERA_SCCB_SCLK_PIN, FUNC_SCCB_SCLK},
{BSP_CAMERA_CMOS_RST_PIN, FUNC_CMOS_RST},
{BSP_CAMERA_CMOS_VSYNC_PIN, FUNC_CMOS_VSYNC},
{BSP_CAMERA_CMOS_PWDN_PIN, FUNC_CMOS_PWDN},
{BSP_CAMERA_CMOS_XCLK_PIN, FUNC_CMOS_XCLK},
{BSP_CAMERA_CMOS_PCLK_PIN, FUNC_CMOS_PCLK},
#endif
#ifdef BSP_USING_SPI1
{17, FUNC_CMOS_HREF},
{24, FUNC_SPI1_SS3},
{29, FUNC_SPI1_SCLK},
{30, FUNC_SPI1_D0},
{31, FUNC_SPI1_D1},
#ifdef BSP_USING_SPI1_AS_QSPI
{32, FUNC_SPI1_D2},
{33, FUNC_SPI1_D3},
#endif
#endif
#ifdef BSP_USING_SDCARD
{32, HS_GPIO(SD_CS_PIN)},
#endif
};
int io_config_init(void)
{
int count = sizeof(io_config) / sizeof(io_config[0]);
int i;
sysctl_set_power_mode(SYSCTL_POWER_BANK0, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK1, SYSCTL_POWER_V18);
sysctl_set_power_mode(SYSCTL_POWER_BANK2, SYSCTL_POWER_V18);
for(i = 0; i < count; i++)
{
fpioa_set_function(io_config[i].io_num, io_config[i].func);
}
#if defined(BSP_USING_CAMERA) || defined(BSP_USING_LCD)
sysctl_set_spi0_dvp_data(1);
#endif
}
INIT_BOARD_EXPORT(io_config_init);
#ifndef __DRV_IO_CONFIG_H__
#define __DRV_IO_CONFIG_H__
enum HS_GPIO_CONFIG
{
#ifdef BSP_USING_LCD
LCD_DC_PIN = 0, /* LCD DC PIN */
#endif
#ifdef BSP_USING_SDCARD
SD_CS_PIN, /* SD_CS_PIN */
#endif
};
extern int io_config_init(void);
#endif
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-12 ZYH first version
*/
#include <rtthread.h>
#ifdef BSP_USING_LCD
#include <rtdevice.h>
#include "drv_lcd.h"
#include <board.h>
#include <gpiohs.h>
#include <spi.h>
#include <drv_io_config.h>
#include <rthw.h>
#define DBG_ENABLE
#define DBG_SECTION_NAME "LCD"
#define DBG_LEVEL DBG_WARNING
#define DBG_COLOR
#include <rtdbg.h>
#define NO_OPERATION 0x00
#define SOFTWARE_RESET 0x01
#define READ_ID 0x04
#define READ_STATUS 0x09
#define READ_POWER_MODE 0x0A
#define READ_MADCTL 0x0B
#define READ_PIXEL_FORMAT 0x0C
#define READ_IMAGE_FORMAT 0x0D
#define READ_SIGNAL_MODE 0x0E
#define READ_SELT_DIAG_RESULT 0x0F
#define SLEEP_ON 0x10
#define SLEEP_OFF 0x11
#define PARTIAL_DISPALY_ON 0x12
#define NORMAL_DISPALY_ON 0x13
#define INVERSION_DISPALY_OFF 0x20
#define INVERSION_DISPALY_ON 0x21
#define GAMMA_SET 0x26
#define DISPALY_OFF 0x28
#define DISPALY_ON 0x29
#define HORIZONTAL_ADDRESS_SET 0x2A
#define VERTICAL_ADDRESS_SET 0x2B
#define MEMORY_WRITE 0x2C
#define COLOR_SET 0x2D
#define MEMORY_READ 0x2E
#define PARTIAL_AREA 0x30
#define VERTICAL_SCROL_DEFINE 0x33
#define TEAR_EFFECT_LINE_OFF 0x34
#define TEAR_EFFECT_LINE_ON 0x35
#define MEMORY_ACCESS_CTL 0x36
#define VERTICAL_SCROL_S_ADD 0x37
#define IDLE_MODE_OFF 0x38
#define IDLE_MODE_ON 0x39
#define PIXEL_FORMAT_SET 0x3A
#define WRITE_MEMORY_CONTINUE 0x3C
#define READ_MEMORY_CONTINUE 0x3E
#define SET_TEAR_SCANLINE 0x44
#define GET_SCANLINE 0x45
#define WRITE_BRIGHTNESS 0x51
#define READ_BRIGHTNESS 0x52
#define WRITE_CTRL_DISPALY 0x53
#define READ_CTRL_DISPALY 0x54
#define WRITE_BRIGHTNESS_CTL 0x55
#define READ_BRIGHTNESS_CTL 0x56
#define WRITE_MIN_BRIGHTNESS 0x5E
#define READ_MIN_BRIGHTNESS 0x5F
#define READ_ID1 0xDA
#define READ_ID2 0xDB
#define READ_ID3 0xDC
#define RGB_IF_SIGNAL_CTL 0xB0
#define NORMAL_FRAME_CTL 0xB1
#define IDLE_FRAME_CTL 0xB2
#define PARTIAL_FRAME_CTL 0xB3
#define INVERSION_CTL 0xB4
#define BLANK_PORCH_CTL 0xB5
#define DISPALY_FUNCTION_CTL 0xB6
#define ENTRY_MODE_SET 0xB7
#define BACKLIGHT_CTL1 0xB8
#define BACKLIGHT_CTL2 0xB9
#define BACKLIGHT_CTL3 0xBA
#define BACKLIGHT_CTL4 0xBB
#define BACKLIGHT_CTL5 0xBC
#define BACKLIGHT_CTL7 0xBE
#define BACKLIGHT_CTL8 0xBF
#define POWER_CTL1 0xC0
#define POWER_CTL2 0xC1
#define VCOM_CTL1 0xC5
#define VCOM_CTL2 0xC7
#define NV_MEMORY_WRITE 0xD0
#define NV_MEMORY_PROTECT_KEY 0xD1
#define NV_MEMORY_STATUS_READ 0xD2
#define READ_ID4 0xD3
#define POSITIVE_GAMMA_CORRECT 0xE0
#define NEGATIVE_GAMMA_CORRECT 0xE1
#define DIGITAL_GAMMA_CTL1 0xE2
#define DIGITAL_GAMMA_CTL2 0xE3
#define INTERFACE_CTL 0xF6
typedef enum _lcd_dir
{
DIR_XY_RLUD = 0x00,
DIR_YX_RLUD = 0x20,
DIR_XY_LRUD = 0x40,
DIR_YX_LRUD = 0x60,
DIR_XY_RLDU = 0x80,
DIR_YX_RLDU = 0xA0,
DIR_XY_LRDU = 0xC0,
DIR_YX_LRDU = 0xE0,
DIR_XY_MASK = 0x20,
DIR_MASK = 0xE0,
} lcd_dir_t;
#define LCD_SPI_CHANNEL SPI_DEVICE_0
#define LCD_SPI_CHIP_SELECT SPI_CHIP_SELECT_0
typedef struct lcd_8080_device
{
struct rt_device parent;
struct rt_device_graphic_info lcd_info;
int spi_channel;
int cs;
int dc_pin;
int dma_channel;
} * lcd_8080_device_t;
static void drv_lcd_cmd(lcd_8080_device_t lcd, rt_uint8_t cmd)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_LOW);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
spi_init_non_standard(lcd->spi_channel, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, &cmd, 1, SPI_TRANS_CHAR);
}
static void drv_lcd_data_byte(lcd_8080_device_t lcd, rt_uint8_t *data_buf, rt_uint32_t length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
spi_init_non_standard(lcd->spi_channel, 8 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_CHAR);
}
static void drv_lcd_data_half_word(lcd_8080_device_t lcd, rt_uint16_t *data_buf, rt_uint32_t length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 16, 0);
spi_init_non_standard(lcd->spi_channel, 16 /*instrction length*/, 0 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_SHORT);
}
static void drv_lcd_data_word(lcd_8080_device_t lcd, rt_uint32_t *data_buf, rt_uint32_t length)
{
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0);
spi_init_non_standard(lcd->spi_channel, 0 /*instrction length*/, 32 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_send_data_normal_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, data_buf, length, SPI_TRANS_INT);
}
static void drv_lcd_hw_init(lcd_8080_device_t lcd)
{
gpiohs_set_drive_mode(lcd->dc_pin, GPIO_DM_OUTPUT);
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 8, 0);
spi_set_clk_rate(lcd->spi_channel, 25000000);
}
static void drv_lcd_set_direction(lcd_8080_device_t lcd, lcd_dir_t dir)
{
#if !BOARD_LICHEEDAN
dir |= 0x08;
#endif
if (dir & DIR_XY_MASK)
{
lcd->lcd_info.width = BSP_LCD_Y_MAX;
lcd->lcd_info.height = BSP_LCD_X_MAX;
}
else
{
lcd->lcd_info.width = BSP_LCD_X_MAX;
lcd->lcd_info.height = BSP_LCD_Y_MAX;
}
drv_lcd_cmd(lcd, MEMORY_ACCESS_CTL);
drv_lcd_data_byte(lcd, (rt_uint8_t *)&dir, 1);
}
static void drv_lcd_set_area(lcd_8080_device_t lcd, rt_uint16_t x1, rt_uint16_t y1, rt_uint16_t x2, rt_uint16_t y2)
{
rt_uint8_t data[4] = {0};
data[0] = (rt_uint8_t)(x1 >> 8);
data[1] = (rt_uint8_t)(x1);
data[2] = (rt_uint8_t)(x2 >> 8);
data[3] = (rt_uint8_t)(x2);
drv_lcd_cmd(lcd, HORIZONTAL_ADDRESS_SET);
drv_lcd_data_byte(lcd, data, 4);
data[0] = (rt_uint8_t)(y1 >> 8);
data[1] = (rt_uint8_t)(y1);
data[2] = (rt_uint8_t)(y2 >> 8);
data[3] = (rt_uint8_t)(y2);
drv_lcd_cmd(lcd, VERTICAL_ADDRESS_SET);
drv_lcd_data_byte(lcd, data, 4);
drv_lcd_cmd(lcd, MEMORY_WRITE);
}
static void drv_lcd_set_pixel(lcd_8080_device_t lcd, uint16_t x, uint16_t y, uint16_t color)
{
drv_lcd_set_area(lcd, x, y, x, y);
drv_lcd_data_half_word(lcd, &color, 1);
}
static void drv_lcd_clear(lcd_8080_device_t lcd, uint16_t color)
{
uint32_t data = ((uint32_t)color << 16) | (uint32_t)color;
drv_lcd_set_area(lcd, 0, 0, lcd->lcd_info.width - 1, lcd->lcd_info.height - 1);
gpiohs_set_pin(lcd->dc_pin, GPIO_PV_HIGH);
spi_init(lcd->spi_channel, SPI_WORK_MODE_0, SPI_FF_OCTAL, 32, 0);
spi_init_non_standard(lcd->spi_channel, 0 /*instrction length*/, 32 /*address length*/, 0 /*wait cycles*/,
SPI_AITM_AS_FRAME_FORMAT /*spi address trans mode*/);
spi_fill_data_dma(lcd->dma_channel, lcd->spi_channel, lcd->cs, (const uint32_t *)&data, lcd->lcd_info.width * lcd->lcd_info.height / 2);
}
static void rt_bitblt(rt_uint16_t * dest, int dest_segment, int dest_common, int dest_x, int dest_y, int width, int height,
rt_uint16_t *src, int src_segment, int src_common, int src_x, int src_y)
{
int sx0, sx1, sy0, sy1;
int dx0, dx1, dy0, dy1;
rt_uint16_t *buff_src;
rt_uint16_t *buff_dest;
int x, y;
if (width <= 0) {
return;
}
if (height <= 0) {
return;
}
sx0 = src_x;
sy0 = src_y;
sx1 = sx0 + width - 1;
sy1 = sy0 + height - 1;
dx0 = dest_x;
dy0 = dest_y;
dx1 = dx0 + width - 1;
dy1 = dy0 + height - 1;
if (sx0 < 0) {
dx0 -= sx0;
sx0 = 0;
}
if (sy0 < 0) {
dy0 -= sy0;
sy0 = 0;
}
if (sx1 >= src_segment) {
dx1 -= (sx1 - src_segment + 1);
sx1 = src_segment - 1;
}
if (sy1 >= src_common) {
dy1 -= (sy1 - src_common + 1);
sy1 = src_common - 1;
}
if (dx0 < 0) {
sx0 -= dx0;
dx0 = 0;
}
if (dy0 < 0) {
sy0 -= dy0;
dy0 = 0;
}
if (dx1 >= dest_segment) {
sx1 -= (dx1 - dest_segment + 1);
dx1 = dest_segment - 1;
}
if (dy1 >= dest_common) {
sy1 -= (dy1 - dest_common + 1);
dy1 = dest_common - 1;
}
if (sx1 < 0 || sx0 >= src_segment) {
return;
}
if (sy1 < 0 || sy0 >= src_common) {
return;
}
if (dx1 < 0 || dx0 >= dest_segment) {
return;
}
if (dy1 < 0 || dy0 >= dest_common) {
return;
}
if ((rt_ubase_t)dest < (rt_ubase_t)src) {
buff_src = src + (sy0 * src_segment) + sx0;
buff_dest = dest + (dy0 * dest_segment) + dx0;
for (y = sy0; y <= sy1; y++) {
src = buff_src;
dest = buff_dest;
for (x = sx0; x <= sx1; x++) {
*dest++ = *src++;
}
buff_src += src_segment;
buff_dest += dest_segment;
}
} else {
buff_src = src + (sy1 * src_segment) + sx1;
buff_dest = dest + (dy1 * dest_segment) + dx1;
for (y = sy1; y >= sy0; y--) {
src = buff_src;
dest = buff_dest;
for (x = sx1; x >= sx0; x--) {
*dest-- = *src--;
}
buff_src -= src_segment;
buff_dest -= dest_segment;
}
}
}
static void drv_lcd_rect_update(lcd_8080_device_t lcd, uint16_t x1, uint16_t y1, uint16_t width, uint16_t height)
{
static rt_uint16_t * rect_buffer = RT_NULL;
if(!rect_buffer)
{
rect_buffer = rt_malloc_align(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8), 64);
if(!rect_buffer)
{
return;
}
}
if(x1 == 0 && y1 == 0 && width == lcd->lcd_info.width && height == lcd->lcd_info.height)
{
drv_lcd_set_area(lcd, x1, y1, x1 + width - 1, y1 + height - 1);
drv_lcd_data_word(lcd, (rt_uint32_t *)lcd->lcd_info.framebuffer, width * height / (lcd->lcd_info.bits_per_pixel / 8));
}
else
{
rt_bitblt(rect_buffer, width, height, 0, 0, width, height,
(rt_uint16_t *)lcd->lcd_info.framebuffer, lcd->lcd_info.width, lcd->lcd_info.height, x1, y1);
drv_lcd_set_area(lcd, x1, y1, x1 + width - 1, y1 + height - 1);
drv_lcd_data_word(lcd, (rt_uint32_t *)rect_buffer, width * height / 2);
}
}
static rt_err_t drv_lcd_init(rt_device_t dev)
{
rt_err_t ret = RT_EOK;
lcd_8080_device_t lcd = (lcd_8080_device_t)dev;
rt_uint8_t data = 0;
if(!lcd)
{
return RT_ERROR;
}
drv_lcd_hw_init(lcd);
/* reset LCD */
drv_lcd_cmd(lcd, SOFTWARE_RESET);
rt_thread_mdelay(100);
/* Enter normal status */
drv_lcd_cmd(lcd, SLEEP_OFF);
rt_thread_mdelay(100);
/* pixel format rgb565 */
drv_lcd_cmd(lcd, PIXEL_FORMAT_SET);
data = 0x55;
drv_lcd_data_byte(lcd, &data, 1);
/* set direction */
drv_lcd_set_direction(lcd, DIR_YX_RLUD);
lcd->lcd_info.framebuffer = rt_malloc_align(lcd->lcd_info.height * lcd->lcd_info.width * (lcd->lcd_info.bits_per_pixel / 8), 64);
RT_ASSERT(lcd->lcd_info.framebuffer);
/*display on*/
drv_lcd_cmd(lcd, DISPALY_ON);
/* set to black */
drv_lcd_clear(lcd, 0x0000);
return ret;
}
static rt_err_t drv_lcd_open(rt_device_t dev, rt_uint16_t oflag)
{
/* Not need */
return RT_EOK;
}
static rt_err_t drv_lcd_close(rt_device_t dev)
{
/* Not need */
return RT_EOK;
}
static rt_size_t drv_lcd_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
/* Not need */
return 0;
}
static rt_size_t drv_lcd_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
/* Not need */
return 0;
}
static rt_err_t drv_lcd_control(rt_device_t dev, int cmd, void *args)
{
rt_err_t ret = RT_EOK;
lcd_8080_device_t lcd = (lcd_8080_device_t)dev;
rt_base_t level;
struct rt_device_rect_info* rect_info = (struct rt_device_rect_info*)args;
RT_ASSERT(dev != RT_NULL);
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
if(!rect_info)
{
LOG_E("RTGRAPHIC_CTRL_RECT_UPDATE error args");
return -RT_ERROR;
}
drv_lcd_rect_update(lcd, rect_info->x, rect_info->y, rect_info->width, rect_info->height);
break;
case RTGRAPHIC_CTRL_POWERON:
/* Todo: power on */
ret = -RT_ENOSYS;
break;
case RTGRAPHIC_CTRL_POWEROFF:
/* Todo: power off */
ret = -RT_ENOSYS;
break;
case RTGRAPHIC_CTRL_GET_INFO:
*(struct rt_device_graphic_info *)args = lcd->lcd_info;
break;
case RTGRAPHIC_CTRL_SET_MODE:
ret = -RT_ENOSYS;
break;
case RTGRAPHIC_CTRL_GET_EXT:
ret = -RT_ENOSYS;
break;
default:
LOG_E("drv_lcd_control cmd: %d", cmd);
break;
}
return ret;
}
#ifdef RT_USING_DEVICE_OPS
const static struct rt_device_ops drv_lcd_ops =
{
drv_lcd_init,
drv_lcd_open,
drv_lcd_close,
drv_lcd_read,
drv_lcd_write,
drv_lcd_control
};
#endif
int rt_hw_lcd_init(void)
{
rt_err_t ret = RT_EOK;
lcd_8080_device_t lcd_dev = (lcd_8080_device_t)rt_malloc(sizeof(struct lcd_8080_device));
if(!lcd_dev)
{
return -1;
}
lcd_dev->cs = SPI_CHIP_SELECT_0;
lcd_dev->dc_pin = LCD_DC_PIN;
lcd_dev->dma_channel = DMAC_CHANNEL0;
lcd_dev->spi_channel = SPI_DEVICE_0;
lcd_dev->lcd_info.bits_per_pixel = 16;
lcd_dev->lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
lcd_dev->parent.type = RT_Device_Class_Graphic;
lcd_dev->parent.rx_indicate = RT_NULL;
lcd_dev->parent.tx_complete = RT_NULL;
#ifdef RT_USING_DEVICE_OPS
lcd_dev->parent.ops = &drv_lcd_ops;
#else
lcd_dev->parent.init = drv_lcd_init;
lcd_dev->parent.open = drv_lcd_open;
lcd_dev->parent.close = drv_lcd_close;
lcd_dev->parent.read = drv_lcd_read;
lcd_dev->parent.write = drv_lcd_write;
lcd_dev->parent.control = drv_lcd_control;
#endif
lcd_dev->parent.user_data = RT_NULL;
ret = rt_device_register(&lcd_dev->parent, "lcd", RT_DEVICE_FLAG_RDWR);
return ret;
}
INIT_DEVICE_EXPORT(rt_hw_lcd_init);
#endif
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-03-07 ZYH first version
*/
#ifndef DRV_LCD_H__
#define DRV_LCD_H__
int rt_hw_lcd_init(void);
#endif
......@@ -62,7 +62,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uarths"
#define RT_VER_NUM 0x40000
#define RT_VER_NUM 0x40001
#define ARCH_CPU_64BIT
#define ARCH_RISCV
#define ARCH_RISCV64
......@@ -118,6 +118,7 @@
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
/* RT_USING_CAN is not set */
/* RT_USING_HWTIMER is not set */
/* RT_USING_CPUTIME is not set */
......@@ -134,6 +135,7 @@
/* RT_USING_SPI is not set */
/* RT_USING_WDT is not set */
/* RT_USING_AUDIO is not set */
/* RT_USING_SENSOR is not set */
/* Using WiFi */
......@@ -207,6 +209,7 @@
/* Wiced WiFi */
/* PKG_USING_WLAN_WICED is not set */
/* PKG_USING_RW007 is not set */
/* PKG_USING_COAP is not set */
/* PKG_USING_NOPOLL is not set */
/* PKG_USING_NETUTILS is not set */
......@@ -220,6 +223,8 @@
/* PKG_USING_ALI_IOTKIT is not set */
/* PKG_USING_AZURE is not set */
/* PKG_USING_TENCENT_IOTKIT is not set */
/* PKG_USING_NIMBLE is not set */
/* PKG_USING_OTA_DOWNLOADER is not set */
/* security packages */
......@@ -247,6 +252,7 @@
/* PKG_USING_RDB is not set */
/* PKG_USING_QRCODE is not set */
/* PKG_USING_ULOG_EASYFLASH is not set */
/* PKG_USING_ADBD is not set */
/* system packages */
......@@ -265,6 +271,16 @@
/* peripheral libraries and drivers */
/* sensors drivers */
/* PKG_USING_LSM6DSL is not set */
/* PKG_USING_LPS22HB is not set */
/* PKG_USING_HTS221 is not set */
/* PKG_USING_LSM303AGR is not set */
/* PKG_USING_BME280 is not set */
/* PKG_USING_BMA400 is not set */
/* PKG_USING_BMI160_BMX160 is not set */
/* PKG_USING_SPL0601 is not set */
/* PKG_USING_REALTEK_AMEBA is not set */
/* PKG_USING_SHT2X is not set */
/* PKG_USING_AHT10 is not set */
......@@ -275,6 +291,7 @@
/* PKG_USING_BUTTON is not set */
/* PKG_USING_MPU6XXX is not set */
/* PKG_USING_PCF8574 is not set */
/* PKG_USING_SX12XX is not set */
#define PKG_USING_KENDRYTE_SDK
#define PKG_USING_KENDRYTE_SDK_V052
/* PKG_USING_KENDRYTE_SDK_LATEST_VERSION is not set */
......@@ -300,11 +317,13 @@
/* PKG_USING_NETWORK_SAMPLES is not set */
/* PKG_USING_PERIPHERAL_SAMPLES is not set */
/* PKG_USING_HELLO is not set */
/* PKG_USING_VI is not set */
/* Privated Packages of RealThread */
/* PKG_USING_CODEC is not set */
/* PKG_USING_PLAYER is not set */
/* PKG_USING_MPLAYER is not set */
/* PKG_USING_PERSIMMON_SRC is not set */
/* PKG_USING_JS_PERSIMMON is not set */
/* PKG_USING_JERRYSCRIPT_WIN32 is not set */
......@@ -320,6 +339,34 @@
/* PKG_USING_RTINSIGHT is not set */
/* PKG_USING_SMARTCONFIG is not set */
/* PKG_USING_RTX is not set */
/* RT_USING_TESTCASE is not set */
/* PKG_USING_NGHTTP2 is not set */
/* PKG_USING_AVS is not set */
/* PKG_USING_STS is not set */
/* PKG_USING_DLMS is not set */
/* Test Packages of RealThread */
/* RT-Thread Senior Membership Packages */
/* system packages */
/* PKG_USING_FTL_SRC is not set */
/* IoT - internet of things */
/* Webnet: A web server package for rt-thread */
/* rtpkgs online packages */
/* PKG_USING_CSTRING is not set */
/* PKG_USING_ARGPARSE is not set */
/* PKG_USING_LIBBMPREAD is not set */
/* PKG_USING_LIBUTILS is not set */
/* PKG_USING_SAM is not set */
/* PKG_USING_LIBCALLBACK is not set */
/* PKG_USING_Z_EVENT is not set */
/* PKG_USING_LIBSTM32HAL is not set */
#define BOARD_K210_EVB
#define BSP_USING_UART_HS
/* BSP_USING_UART1 is not set */
......@@ -327,6 +374,20 @@
/* BSP_USING_UART3 is not set */
/* BSP_USING_I2C1 is not set */
/* BSP_USING_SPI1 is not set */
#define BSP_USING_LCD
#define BSP_LCD_CS_PIN 6
#define BSP_LCD_WR_PIN 7
#define BSP_LCD_DC_PIN 8
#define BSP_LCD_X_MAX 240
#define BSP_LCD_Y_MAX 320
#define BSP_USING_CAMERA
#define BSP_CAMERA_SCCB_SDA_PIN 9
#define BSP_CAMERA_SCCB_SCLK_PIN 10
#define BSP_CAMERA_CMOS_RST_PIN 11
#define BSP_CAMERA_CMOS_VSYNC_PIN 12
#define BSP_CAMERA_CMOS_PWDN_PIN 13
#define BSP_CAMERA_CMOS_XCLK_PIN 14
#define BSP_CAMERA_CMOS_PCLK_PIN 15
#define __STACKSIZE__ 4096
#endif
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