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2700130e
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体验新版 GitCode,发现更多精彩内容 >>
提交
2700130e
编写于
12月 05, 2019
作者:
Q
qiyongzhong0
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
add stm32l4r5-st-nucleo BSP
上级
0dc7da68
变更
38
展开全部
隐藏空白更改
内联
并排
Showing
38 changed file
with
18046 addition
and
0 deletion
+18046
-0
bsp/stm32/stm32l4r5-st-nucleo/.config
bsp/stm32/stm32l4r5-st-nucleo/.config
+422
-0
bsp/stm32/stm32l4r5-st-nucleo/.gitignore
bsp/stm32/stm32l4r5-st-nucleo/.gitignore
+42
-0
bsp/stm32/stm32l4r5-st-nucleo/Kconfig
bsp/stm32/stm32l4r5-st-nucleo/Kconfig
+21
-0
bsp/stm32/stm32l4r5-st-nucleo/README.md
bsp/stm32/stm32l4r5-st-nucleo/README.md
+116
-0
bsp/stm32/stm32l4r5-st-nucleo/SConscript
bsp/stm32/stm32l4r5-st-nucleo/SConscript
+15
-0
bsp/stm32/stm32l4r5-st-nucleo/SConstruct
bsp/stm32/stm32l4r5-st-nucleo/SConstruct
+59
-0
bsp/stm32/stm32l4r5-st-nucleo/applications/SConscript
bsp/stm32/stm32l4r5-st-nucleo/applications/SConscript
+9
-0
bsp/stm32/stm32l4r5-st-nucleo/applications/main.c
bsp/stm32/stm32l4r5-st-nucleo/applications/main.c
+39
-0
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/.mxproject
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/.mxproject
+14
-0
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Inc/main.h
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Inc/main.h
+71
-0
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h
...r5-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h
+440
-0
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_it.h
...tm32l4r5-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_it.h
+69
-0
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/STM32L4R5ZITx.ioc
...stm32l4r5-st-nucleo/board/CubeMX_Config/STM32L4R5ZITx.ioc
+164
-0
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/main.c
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/main.c
+254
-0
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c
...4r5-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c
+150
-0
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_it.c
...tm32l4r5-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_it.c
+203
-0
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/system_stm32l4xx.c
...l4r5-st-nucleo/board/CubeMX_Config/Src/system_stm32l4xx.c
+337
-0
bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig
bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig
+239
-0
bsp/stm32/stm32l4r5-st-nucleo/board/SConscript
bsp/stm32/stm32l4r5-st-nucleo/board/SConscript
+40
-0
bsp/stm32/stm32l4r5-st-nucleo/board/board.c
bsp/stm32/stm32l4r5-st-nucleo/board/board.c
+60
-0
bsp/stm32/stm32l4r5-st-nucleo/board/board.h
bsp/stm32/stm32l4r5-st-nucleo/board/board.h
+43
-0
bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.icf
bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.icf
+36
-0
bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.lds
bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.lds
+155
-0
bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.sct
bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.sct
+19
-0
bsp/stm32/stm32l4r5-st-nucleo/figures/board.jpg
bsp/stm32/stm32l4r5-st-nucleo/figures/board.jpg
+0
-0
bsp/stm32/stm32l4r5-st-nucleo/project.ewd
bsp/stm32/stm32l4r5-st-nucleo/project.ewd
+2974
-0
bsp/stm32/stm32l4r5-st-nucleo/project.ewp
bsp/stm32/stm32l4r5-st-nucleo/project.ewp
+2340
-0
bsp/stm32/stm32l4r5-st-nucleo/project.ewt
bsp/stm32/stm32l4r5-st-nucleo/project.ewt
+2629
-0
bsp/stm32/stm32l4r5-st-nucleo/project.eww
bsp/stm32/stm32l4r5-st-nucleo/project.eww
+10
-0
bsp/stm32/stm32l4r5-st-nucleo/project.uvoptx
bsp/stm32/stm32l4r5-st-nucleo/project.uvoptx
+196
-0
bsp/stm32/stm32l4r5-st-nucleo/project.uvprojx
bsp/stm32/stm32l4r5-st-nucleo/project.uvprojx
+886
-0
bsp/stm32/stm32l4r5-st-nucleo/rtconfig.h
bsp/stm32/stm32l4r5-st-nucleo/rtconfig.h
+171
-0
bsp/stm32/stm32l4r5-st-nucleo/rtconfig.py
bsp/stm32/stm32l4r5-st-nucleo/rtconfig.py
+143
-0
bsp/stm32/stm32l4r5-st-nucleo/template.ewd
bsp/stm32/stm32l4r5-st-nucleo/template.ewd
+2974
-0
bsp/stm32/stm32l4r5-st-nucleo/template.ewp
bsp/stm32/stm32l4r5-st-nucleo/template.ewp
+2106
-0
bsp/stm32/stm32l4r5-st-nucleo/template.eww
bsp/stm32/stm32l4r5-st-nucleo/template.eww
+10
-0
bsp/stm32/stm32l4r5-st-nucleo/template.uvoptx
bsp/stm32/stm32l4r5-st-nucleo/template.uvoptx
+196
-0
bsp/stm32/stm32l4r5-st-nucleo/template.uvprojx
bsp/stm32/stm32l4r5-st-nucleo/template.uvprojx
+394
-0
未找到文件。
bsp/stm32/stm32l4r5-st-nucleo/.config
0 → 100644
浏览文件 @
2700130e
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX
=
8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE
=
4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32
=
y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX
=
32
CONFIG_RT_TICK_PER_SECOND
=
1000
CONFIG_RT_USING_OVERFLOW_CHECK
=
y
CONFIG_RT_USING_HOOK
=
y
CONFIG_RT_USING_IDLE_HOOK
=
y
CONFIG_RT_IDLE_HOOK_LIST_SIZE
=
4
CONFIG_IDLE_THREAD_STACK_SIZE
=
256
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_DEBUG
=
y
CONFIG_RT_DEBUG_COLOR
=
y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE
=
y
CONFIG_RT_USING_MUTEX
=
y
CONFIG_RT_USING_EVENT
=
y
CONFIG_RT_USING_MAILBOX
=
y
CONFIG_RT_USING_MESSAGEQUEUE
=
y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
# CONFIG_RT_USING_MEMPOOL is not set
CONFIG_RT_USING_MEMHEAP
=
y
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM
=
y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP
=
y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE
=
y
CONFIG_RT_USING_DEVICE_OPS
=
y
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE
=
y
CONFIG_RT_CONSOLEBUF_SIZE
=
256
CONFIG_RT_CONSOLE_DEVICE_NAME
=
"lpuart1"
CONFIG_RT_VER_NUM
=
0
x40002
CONFIG_ARCH_ARM
=
y
CONFIG_RT_USING_CPU_FFS
=
y
CONFIG_ARCH_ARM_CORTEX_M
=
y
CONFIG_ARCH_ARM_CORTEX_M4
=
y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT
=
y
CONFIG_RT_USING_USER_MAIN
=
y
CONFIG_RT_MAIN_THREAD_STACK_SIZE
=
2048
CONFIG_RT_MAIN_THREAD_PRIORITY
=
10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH
=
y
CONFIG_FINSH_THREAD_NAME
=
"tshell"
CONFIG_FINSH_USING_HISTORY
=
y
CONFIG_FINSH_HISTORY_LINES
=
5
CONFIG_FINSH_USING_SYMTAB
=
y
CONFIG_FINSH_USING_DESCRIPTION
=
y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY
=
20
CONFIG_FINSH_THREAD_STACK_SIZE
=
4096
CONFIG_FINSH_CMD_SIZE
=
80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH
=
y
CONFIG_FINSH_USING_MSH_DEFAULT
=
y
CONFIG_FINSH_USING_MSH_ONLY
=
y
CONFIG_FINSH_ARG_MAX
=
10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC
=
y
CONFIG_RT_PIPE_BUFSZ
=
512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL
=
y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ
=
64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN
=
y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_LIBC_USING_TIME is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
CONFIG_SOC_FAMILY_STM32
=
y
CONFIG_SOC_SERIES_STM32L4
=
y
#
# Hardware Drivers Config
#
CONFIG_SOC_STM32L4R5ZI
=
y
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_STLINK_TO_USART
=
y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO
=
y
CONFIG_BSP_USING_UART
=
y
CONFIG_BSP_USING_LPUART1
=
y
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_UART5 is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_USBD is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_TIM is not set
# CONFIG_BSP_USING_PWM is not set
#
# Board extended module Drivers
#
bsp/stm32/stm32l4r5-st-nucleo/.gitignore
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2700130e
*.pyc
*.map
*.dblite
*.elf
*.bin
*.hex
*.axf
*.exe
*.pdb
*.idb
*.ilk
*.old
build
Debug
documentation/html
packages/
*~
*.o
*.obj
*.out
*.bak
*.dep
*.lib
*.i
*.d
.DS_Stor*
.config 3
.config 4
.config 5
Midea-X1
*.uimg
GPATH
GRTAGS
GTAGS
.vscode
JLinkLog.txt
JLinkSettings.ini
DebugConfig/
RTE/
settings/
*.uvguix*
cconfig.h
bsp/stm32/stm32l4r5-st-nucleo/Kconfig
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2700130e
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../libraries/Kconfig"
source "board/Kconfig"
bsp/stm32/stm32l4r5-st-nucleo/README.md
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# STM32L4R5ZI-NUCLEO 开发板bsp说明
## 简介
由 QYZ 为 STM32L4R5ZI-NUCLEO 开发板提供的 BSP (板级支持包) 说明。
主要内容如下:
-
开发板资源介绍
-
BSP 快速上手
-
进阶使用方法
通过阅读快速上手章节开发者可以快速地上手该 BSP,将 RT-Thread 运行在开发板上。在进阶使用指南章节,将会介绍更多高级功能,帮助开发者利用 RT-Thread 驱动更多板载资源。
## 开发板介绍
开发板外观如下图所示:
![
board
](
figures/board.bmp
)
该开发板常用
**板载资源**
如下:
-
MCU:STM32L4R5ZI,主频 120MHz,2048KB FLASH ,640KB RAM
-
常用外设
-
状态指示灯:3个,LD1 - 3
-
按键:2个
-
板载 ST LINK
-
常用接口:USB OTG Micro USB 接口
-
调试接口,ST-LINK Micro USB 接口
开发板更多详细信息请参考 ST 的
[
STM32L4R5ZI-NUCLEO
](
https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html
)
介绍。
## 外设支持
本 BSP 目前对外设的支持情况如下:
|
**板载外设**
|
**支持情况**
|
**备注**
|
| :----------------- | :----------: | :-----------------------------------------|
| 板载 ST-LINK 转串口 | 支持 | PG7 PG8 LPUART1 |
| SRAM | 支持 | |
|
**片上外设**
|
**支持情况**
|
**备注**
|
| GPIO | 支持 | |
| UART | 支持 | USART3 |
## 使用说明
使用说明分为如下两个章节:
-
快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明,遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上,看到实验效果 。
-
进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置,可以开启更多板载资源,实现更多高级功能。
### 快速上手
本 BSP 为开发者提供 MDK5 和 IAR 工程,并且支持 GCC 开发环境。下面以 MDK5 开发环境为例,介绍如何将系统运行起来。
#### 硬件连接
使用数据线连接开发板到 PC,打开电源开关。
#### 编译下载
双击 project.eww 文件,打开 IAR 工程,编译并下载程序到开发板。
> 工程默认配置使用 板载STLINK 仿真器下载程序,在通过 STLINK 连接开发板的基础上,点击下载按钮即可下载程序到开发板
#### 运行结果
下载程序成功之后,系统会自动运行,观察开发板上 LED 的运行效果, LED 会周期性闪烁。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口(115200-8-1-N),复位设备后,可以看到 RT-Thread 的输出信息:
```
bash
\
| /
- RT - Thread Operating System
/ |
\
4.0.1 build Apr 4 2019
2006 - 2019 Copyright by rt-thread team
msh
>
```
### 进阶使用
此 BSP 默认只开启了 GPIO 和 LPUART1的功能,如果需使用 USB、Flash 等更多高级功能,需要利用 ENV 工具对BSP 进行配置,步骤如下:
1.
在 bsp 下打开 env 工具。
2.
输入
`menuconfig`
命令配置工程,配置好之后保存退出。
3.
输入
`pkgs --update`
命令更新软件包。
4.
输入
`scons --target=mdk5/iar`
命令重新生成工程。
本章节更多详细的介绍请参考
[
STM32 系列 BSP 外设驱动使用教程
](
../docs/STM32系列BSP外设驱动使用教程.md
)
。
## 注意事项
-
调试串口为LPUART1 映射到PG7 PG8
-
stm32L4R5ZI 共有三块内部RAM区域 具体使用情况入如下
```
RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192K sram 用于程序定义全局变量 静态变量存放*/
RAM2 (rw) : ORIGIN = 0x10000000, LENGTH = 64k /* 64K sram 暂未使用 */
RAM3 (rw) : ORIGIN = 0x20040000, LENGTH = 384k /* 384K sram 用于heap空间*/
```
## 联系人信息
维护人:
bsp/stm32/stm32l4r5-st-nucleo/SConscript
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# for module compiling
import
os
Import
(
'RTT_ROOT'
)
from
building
import
*
cwd
=
GetCurrentDir
()
objs
=
[]
list
=
os
.
listdir
(
cwd
)
for
d
in
list
:
path
=
os
.
path
.
join
(
cwd
,
d
)
if
os
.
path
.
isfile
(
os
.
path
.
join
(
path
,
'SConscript'
)):
objs
=
objs
+
SConscript
(
os
.
path
.
join
(
d
,
'SConscript'
))
Return
(
'objs'
)
bsp/stm32/stm32l4r5-st-nucleo/SConstruct
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2700130e
import
os
import
sys
import
rtconfig
if
os
.
getenv
(
'RTT_ROOT'
):
RTT_ROOT
=
os
.
getenv
(
'RTT_ROOT'
)
else
:
RTT_ROOT
=
os
.
path
.
normpath
(
os
.
getcwd
()
+
'/../../..'
)
sys
.
path
=
sys
.
path
+
[
os
.
path
.
join
(
RTT_ROOT
,
'tools'
)]
try
:
from
building
import
*
except
:
print
(
'Cannot found RT-Thread root directory, please check RTT_ROOT'
)
print
(
RTT_ROOT
)
exit
(
-
1
)
TARGET
=
'rt-thread.'
+
rtconfig
.
TARGET_EXT
env
=
Environment
(
tools
=
[
'mingw'
],
AS
=
rtconfig
.
AS
,
ASFLAGS
=
rtconfig
.
AFLAGS
,
CC
=
rtconfig
.
CC
,
CCFLAGS
=
rtconfig
.
CFLAGS
,
AR
=
rtconfig
.
AR
,
ARFLAGS
=
'-rc'
,
CXX
=
rtconfig
.
CXX
,
CXXFLAGS
=
rtconfig
.
CXXFLAGS
,
LINK
=
rtconfig
.
LINK
,
LINKFLAGS
=
rtconfig
.
LFLAGS
)
env
.
PrependENVPath
(
'PATH'
,
rtconfig
.
EXEC_PATH
)
if
rtconfig
.
PLATFORM
==
'iar'
:
env
.
Replace
(
CCCOM
=
[
'$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'
])
env
.
Replace
(
ARFLAGS
=
[
''
])
env
.
Replace
(
LINKCOM
=
env
[
"LINKCOM"
]
+
' --map rt-thread.map'
)
Export
(
'RTT_ROOT'
)
Export
(
'rtconfig'
)
SDK_ROOT
=
os
.
path
.
abspath
(
'./'
)
if
os
.
path
.
exists
(
SDK_ROOT
+
'/libraries'
):
libraries_path_prefix
=
SDK_ROOT
+
'/libraries'
else
:
libraries_path_prefix
=
os
.
path
.
dirname
(
SDK_ROOT
)
+
'/libraries'
SDK_LIB
=
libraries_path_prefix
Export
(
'SDK_LIB'
)
# prepare building environment
objs
=
PrepareBuilding
(
env
,
RTT_ROOT
,
has_libcpu
=
False
)
stm32_library
=
'STM32L4xx_HAL'
rtconfig
.
BSP_LIBRARY_TYPE
=
stm32_library
# include libraries
objs
.
extend
(
SConscript
(
os
.
path
.
join
(
libraries_path_prefix
,
stm32_library
,
'SConscript'
)))
# include drivers
objs
.
extend
(
SConscript
(
os
.
path
.
join
(
libraries_path_prefix
,
'HAL_Drivers'
,
'SConscript'
)))
# make a building
DoBuilding
(
TARGET
,
objs
)
bsp/stm32/stm32l4r5-st-nucleo/applications/SConscript
0 → 100644
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2700130e
from
building
import
*
cwd
=
GetCurrentDir
()
src
=
Glob
(
'*.c'
)
CPPPATH
=
[
str
(
Dir
(
'#'
)),
cwd
]
group
=
DefineGroup
(
'Applications'
,
src
,
depend
=
[
''
],
CPPPATH
=
CPPPATH
)
Return
(
'group'
)
bsp/stm32/stm32l4r5-st-nucleo/applications/main.c
0 → 100644
浏览文件 @
2700130e
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-06 SummerGift first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
/* defined the LED1 pin: PC7 */
#define LED1_PIN GET_PIN(C, 7)
/* defined the LED2 pin: PB7 */
#define LED2_PIN GET_PIN(B, 7)
/* defined the LED3 pin: PB14 */
#define LED3_PIN GET_PIN(B, 14)
#define LED_RUN_PIN LED3_PIN
int
main
(
void
)
{
int
count
=
1
;
rt_pin_mode
(
LED_RUN_PIN
,
PIN_MODE_OUTPUT
);
while
(
count
++
)
{
rt_pin_write
(
LED_RUN_PIN
,
PIN_HIGH
);
rt_thread_mdelay
(
500
);
rt_pin_write
(
LED_RUN_PIN
,
PIN_LOW
);
rt_thread_mdelay
(
500
);
}
return
RT_EOK
;
}
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/.mxproject
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2700130e
[PreviousGenFiles]
HeaderPath=E:/Work/GitLib/rt-thread/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Inc
HeaderFiles=stm32l4xx_it.h;stm32l4xx_hal_conf.h;main.h;gpio.h;adc.h;iwdg.h;lptim.h;usart.h;rtc.h;spi.h;tim.h;usb_otg.h;
SourcePath=E:/Work/GitLib/rt-thread/bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src
SourceFiles=stm32l4xx_it.c;stm32l4xx_hal_msp.c;main.c;gpio.c;adc.c;iwdg.c;lptim.c;usart.c;rtc.c;spi.c;tim.c;usb_otg.c;
[PreviousLibFiles]
LibFiles=Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h;Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rcc_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h;Drivers/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_exti.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r5xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h;Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h;
[PreviousUsedIarFiles]
SourceFiles=..\Src\main.c;..\Src\stm32l4xx_it.c;..\Src\stm32l4xx_hal_msp.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;../\Src/system_stm32l4xx.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c;../Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c;../\Src/system_stm32l4xx.c;../Drivers/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c;null;
HeaderPath=..\Drivers\STM32L4xx_HAL_Driver\Inc;..\Drivers\STM32L4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32L4xx\Include;..\Drivers\CMSIS\Include;..\Inc;
CDefines=USE_HAL_DRIVER;STM32L4R5xx;USE_HAL_DRIVER;STM32L4R5xx;
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Inc/main.h
0 → 100644
浏览文件 @
2700130e
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.h
* @brief : Header for main.c file.
* This file contains the common defines of the application.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __MAIN_H
#define __MAIN_H
#ifdef __cplusplus
extern
"C"
{
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32l4xx_hal.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void
Error_Handler
(
void
);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
}
#endif
#endif
/* __MAIN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h
0 → 100644
浏览文件 @
2700130e
/**
******************************************************************************
* @file stm32l4xx_hal_conf.h
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_HAL_CONF_H
#define __STM32L4xx_HAL_CONF_H
#ifdef __cplusplus
extern
"C"
{
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_CAN_MODULE_ENABLED */
/*#define HAL_COMP_MODULE_ENABLED */
/*#define HAL_CRC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_DAC_MODULE_ENABLED */
/*#define HAL_DCMI_MODULE_ENABLED */
/*#define HAL_DMA2D_MODULE_ENABLED */
/*#define HAL_DFSDM_MODULE_ENABLED */
/*#define HAL_DSI_MODULE_ENABLED */
/*#define HAL_FIREWALL_MODULE_ENABLED */
/*#define HAL_GFXMMU_MODULE_ENABLED */
/*#define HAL_HCD_MODULE_ENABLED */
/*#define HAL_HASH_MODULE_ENABLED */
/*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_IRDA_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */
/*#define HAL_LTDC_MODULE_ENABLED */
/*#define HAL_LCD_MODULE_ENABLED */
/*#define HAL_LPTIM_MODULE_ENABLED */
/*#define HAL_MMC_MODULE_ENABLED */
/*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_NOR_MODULE_ENABLED */
/*#define HAL_OPAMP_MODULE_ENABLED */
/*#define HAL_OSPI_MODULE_ENABLED */
/*#define HAL_OSPI_MODULE_ENABLED */
/*#define HAL_PCD_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SAI_MODULE_ENABLED */
/*#define HAL_SD_MODULE_ENABLED */
/*#define HAL_SMBUS_MODULE_ENABLED */
/*#define HAL_SMARTCARD_MODULE_ENABLED */
/*#define HAL_SPI_MODULE_ENABLED */
/*#define HAL_SRAM_MODULE_ENABLED */
/*#define HAL_SWPMI_MODULE_ENABLED */
/*#define HAL_TIM_MODULE_ENABLED */
/*#define HAL_TSC_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED
/*#define HAL_USART_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */
/*#define HAL_EXTI_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000U)
/*!< Value of the External oscillator in Hz */
#endif
/* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U)
/*!< Time out for HSE start up, in ms */
#endif
/* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal Multiple Speed oscillator (MSI) default value.
* This value is the default MSI range value after Reset.
*/
#if !defined (MSI_VALUE)
#define MSI_VALUE ((uint32_t)4000000U)
/*!< Value of the Internal oscillator in Hz*/
#endif
/* MSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000U)
/*!< Value of the Internal oscillator in Hz*/
#endif
/* HSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
* This internal oscillator is mainly dedicated to provide a high precision clock to
* the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
* When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
* which is subject to manufacturing process variations.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000U)
/*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
The real value my vary depending on manufacturing process variations.*/
#endif
/* HSI48_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000U)
/*!< LSI Typical Value in Hz*/
#endif
/* LSI_VALUE */
/*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768U)
/*!< Value of the External oscillator in Hz*/
#endif
/* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U)
/*!< Time out for LSE start up, in ms */
#endif
/* HSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for SAI1 peripheral
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
* frequency.
*/
#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
#define EXTERNAL_SAI1_CLOCK_VALUE ((uint32_t)2097000U)
/*!< Value of the SAI1 External clock source in Hz*/
#endif
/* EXTERNAL_SAI1_CLOCK_VALUE */
/**
* @brief External clock source for SAI2 peripheral
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
* frequency.
*/
#if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
#define EXTERNAL_SAI2_CLOCK_VALUE ((uint32_t)2097000U)
/*!< Value of the SAI2 External clock source in Hz*/
#endif
/* EXTERNAL_SAI2_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300U)
/*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0U)
/*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 0U
#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 0U
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32l4xx_hal_rcc.h"
#include "stm32l4xx_hal_rcc_ex.h"
#endif
/* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32l4xx_hal_exti.h"
#endif
/* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32l4xx_hal_gpio.h"
#endif
/* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32l4xx_hal_dma.h"
#include "stm32l4xx_hal_dma_ex.h"
#endif
/* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32l4xx_hal_dfsdm.h"
#endif
/* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32l4xx_hal_cortex.h"
#endif
/* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32l4xx_hal_adc.h"
#endif
/* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32l4xx_hal_can.h"
#endif
/* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32l4xx_hal_comp.h"
#endif
/* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32l4xx_hal_crc.h"
#endif
/* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32l4xx_hal_cryp.h"
#endif
/* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32l4xx_hal_dac.h"
#endif
/* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32l4xx_hal_dcmi.h"
#endif
/* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32l4xx_hal_dma2d.h"
#endif
/* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DSI_MODULE_ENABLED
#include "stm32l4xx_hal_dsi.h"
#endif
/* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_FIREWALL_MODULE_ENABLED
#include "stm32l4xx_hal_firewall.h"
#endif
/* HAL_FIREWALL_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32l4xx_hal_flash.h"
#endif
/* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32l4xx_hal_hash.h"
#endif
/* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32l4xx_hal_sram.h"
#endif
/* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32l4xx_hal_mmc.h"
#endif
/* HAL_MMC_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32l4xx_hal_nor.h"
#endif
/* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32l4xx_hal_nand.h"
#endif
/* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32l4xx_hal_i2c.h"
#endif
/* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32l4xx_hal_iwdg.h"
#endif
/* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LCD_MODULE_ENABLED
#include "stm32l4xx_hal_lcd.h"
#endif
/* HAL_LCD_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32l4xx_hal_lptim.h"
#endif
/* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32l4xx_hal_ltdc.h"
#endif
/* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_OPAMP_MODULE_ENABLED
#include "stm32l4xx_hal_opamp.h"
#endif
/* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_OSPI_MODULE_ENABLED
#include "stm32l4xx_hal_ospi.h"
#endif
/* HAL_OSPI_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32l4xx_hal_pwr.h"
#endif
/* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32l4xx_hal_qspi.h"
#endif
/* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32l4xx_hal_rng.h"
#endif
/* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32l4xx_hal_rtc.h"
#endif
/* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32l4xx_hal_sai.h"
#endif
/* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32l4xx_hal_sd.h"
#endif
/* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32l4xx_hal_smbus.h"
#endif
/* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32l4xx_hal_spi.h"
#endif
/* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_SWPMI_MODULE_ENABLED
#include "stm32l4xx_hal_swpmi.h"
#endif
/* HAL_SWPMI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32l4xx_hal_tim.h"
#endif
/* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED
#include "stm32l4xx_hal_tsc.h"
#endif
/* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32l4xx_hal_uart.h"
#endif
/* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32l4xx_hal_usart.h"
#endif
/* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32l4xx_hal_irda.h"
#endif
/* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32l4xx_hal_smartcard.h"
#endif
/* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32l4xx_hal_wwdg.h"
#endif
/* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32l4xx_hal_pcd.h"
#endif
/* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32l4xx_hal_hcd.h"
#endif
/* HAL_HCD_MODULE_ENABLED */
#ifdef HAL_GFXMMU_MODULE_ENABLED
#include "stm32l4xx_hal_gfxmmu.h"
#endif
/* HAL_GFXMMU_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void
assert_failed
(
char
*
file
,
uint32_t
line
);
#else
#define assert_param(expr) ((void)0U)
#endif
/* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif
/* __STM32L4xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Inc/stm32l4xx_it.h
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32l4xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L4xx_IT_H
#define __STM32L4xx_IT_H
#ifdef __cplusplus
extern
"C"
{
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void
NMI_Handler
(
void
);
void
HardFault_Handler
(
void
);
void
MemManage_Handler
(
void
);
void
BusFault_Handler
(
void
);
void
UsageFault_Handler
(
void
);
void
SVC_Handler
(
void
);
void
DebugMon_Handler
(
void
);
void
PendSV_Handler
(
void
);
void
SysTick_Handler
(
void
);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif
/* __STM32L4xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/STM32L4R5ZITx.ioc
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#MicroXplorer Configuration settings - do not modify
File.Version=6
KeepUserPlacement=false
Mcu.Family=STM32L4
Mcu.IP0=LPUART1
Mcu.IP1=NVIC
Mcu.IP2=RCC
Mcu.IP3=SYS
Mcu.IPNb=4
Mcu.Name=STM32L4R5Z(G-I)Tx
Mcu.Package=LQFP144
Mcu.Pin0=PC14-OSC32_IN (PC14)
Mcu.Pin1=PC15-OSC32_OUT (PC15)
Mcu.Pin2=PG7
Mcu.Pin3=PG8
Mcu.Pin4=VP_SYS_VS_Systick
Mcu.PinsNb=5
Mcu.ThirdPartyNb=0
Mcu.UserConstants=
Mcu.UserName=STM32L4R5ZITx
MxCube.Version=5.3.0
MxDb.Version=DB.5.0.30
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator
PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN
PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator
PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT
PCC.Checker=true
PCC.Line=STM32L4R5/S5
PCC.MCU=STM32L4R5Z(G-I)Tx
PCC.PartNumber=STM32L4R5ZITx
PCC.Seq0=0
PCC.Series=STM32L4
PCC.Temperature=25
PCC.Vdd=3.0
PG7.GPIOParameters=GPIO_Speed,GPIO_PuPd
PG7.GPIO_PuPd=GPIO_PULLUP
PG7.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PG7.Locked=true
PG7.Mode=Asynchronous
PG7.Signal=LPUART1_TX
PG8.GPIOParameters=GPIO_Speed,GPIO_PuPd
PG8.GPIO_PuPd=GPIO_PULLUP
PG8.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
PG8.Locked=true
PG8.Mode=Asynchronous
PG8.Signal=LPUART1_RX
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32L4R5ZITx
ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.14.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x000
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=0
ProjectManager.MainLocation=Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=STM32L4R5ZITx.ioc
ProjectManager.ProjectName=STM32L4R5ZITx
ProjectManager.StackSize=0x800
ProjectManager.TargetToolchain=EWARM V8
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=false
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_LPUART1_UART_Init-LPUART1-false-HAL-true
RCC.ADCFreq_Value=48000000
RCC.AHBFreq_Value=100000000
RCC.APB1CLKDivider=RCC_HCLK_DIV2
RCC.APB1Freq_Value=50000000
RCC.APB1TimFreq_Value=100000000
RCC.APB2CLKDivider=RCC_HCLK_DIV2
RCC.APB2Freq_Value=50000000
RCC.APB2TimFreq_Value=100000000
RCC.CK48CLockSelection=RCC_USBCLKSOURCE_HSI48
RCC.CRSFreq_Value=48000000
RCC.CortexFreq_Value=100000000
RCC.DFSDMAudioFreq_Value=4000000
RCC.DFSDMFreq_Value=50000000
RCC.FCLKCortexFreq_Value=100000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=100000000
RCC.HSE_VALUE=8000000
RCC.HSI48_VALUE=48000000
RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=50000000
RCC.I2C2Freq_Value=50000000
RCC.I2C3Freq_Value=50000000
RCC.I2C4Freq_Value=50000000
RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CK48CLockSelection,CRSFreq_Value,CortexFreq_Value,DFSDMAudioFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,LCDTFTFreq_Value,LPTIM1CLockSelection,LPTIM1Freq_Value,LPTIM2CLockSelection,LPTIM2Freq_Value,LPUART1CLockSelection,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,OCTOSPIMFreq_Value,PLLM1,PLLM2,PLLM3,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2QoutputFreq_Value,PLLSAI2RoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4CLockSelection,UART4Freq_Value,UART5CLockSelection,UART5Freq_Value,USART1CLockSelection,USART1Freq_Value,USART2CLockSelection,USART2Freq_Value,USART3CLockSelection,USART3Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value
RCC.LCDTFTFreq_Value=16000000
RCC.LPTIM1CLockSelection=RCC_LPTIM1CLKSOURCE_LSE
RCC.LPTIM1Freq_Value=32768
RCC.LPTIM2CLockSelection=RCC_LPTIM2CLKSOURCE_LSE
RCC.LPTIM2Freq_Value=32768
RCC.LPUART1CLockSelection=RCC_LPUART1CLKSOURCE_HSI
RCC.LPUART1Freq_Value=16000000
RCC.LSCOPinFreq_Value=32000
RCC.LSI_VALUE=32000
RCC.MCO1PinFreq_Value=100000000
RCC.MSI_VALUE=4000000
RCC.OCTOSPIMFreq_Value=100000000
RCC.PLLM1=2
RCC.PLLM2=2
RCC.PLLM3=2
RCC.PLLN=25
RCC.PLLPoutputFreq_Value=100000000
RCC.PLLQoutputFreq_Value=100000000
RCC.PLLRCLKFreq_Value=100000000
RCC.PLLSAI1N=12
RCC.PLLSAI1PoutputFreq_Value=48000000
RCC.PLLSAI1QoutputFreq_Value=48000000
RCC.PLLSAI1RoutputFreq_Value=48000000
RCC.PLLSAI2PoutputFreq_Value=32000000
RCC.PLLSAI2QoutputFreq_Value=32000000
RCC.PLLSAI2RoutputFreq_Value=32000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSI
RCC.PWRFreq_Value=100000000
RCC.RNGFreq_Value=48000000
RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE
RCC.RTCFreq_Value=32768
RCC.SAI1Freq_Value=48000000
RCC.SAI2Freq_Value=48000000
RCC.SDMMCFreq_Value=100000000
RCC.SYSCLKFreq_VALUE=100000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.UART4CLockSelection=RCC_UART4CLKSOURCE_HSI
RCC.UART4Freq_Value=16000000
RCC.UART5CLockSelection=RCC_UART5CLKSOURCE_HSI
RCC.UART5Freq_Value=16000000
RCC.USART1CLockSelection=RCC_USART1CLKSOURCE_HSI
RCC.USART1Freq_Value=16000000
RCC.USART2CLockSelection=RCC_USART2CLKSOURCE_HSI
RCC.USART2Freq_Value=16000000
RCC.USART3CLockSelection=RCC_USART3CLKSOURCE_HSI
RCC.USART3Freq_Value=16000000
RCC.USBFreq_Value=48000000
RCC.VCOInput2Freq_Value=8000000
RCC.VCOInput3Freq_Value=8000000
RCC.VCOInputFreq_Value=8000000
RCC.VCOOutputFreq_Value=200000000
RCC.VCOSAI1OutputFreq_Value=96000000
RCC.VCOSAI2OutputFreq_Value=64000000
VP_SYS_VS_Systick.Mode=SysTick
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
board=custom
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/main.c
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
UART_HandleTypeDef
hlpuart1
;
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void
SystemClock_Config
(
void
);
static
void
MX_GPIO_Init
(
void
);
static
void
MX_LPUART1_UART_Init
(
void
);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int
main
(
void
)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init
();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config
();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init
();
MX_LPUART1_UART_Init
();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while
(
1
)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void
SystemClock_Config
(
void
)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
RCC_PeriphCLKInitTypeDef
PeriphClkInit
=
{
0
};
/** Configure the main internal regulator output voltage
*/
if
(
HAL_PWREx_ControlVoltageScaling
(
PWR_REGULATOR_VOLTAGE_SCALE1_BOOST
)
!=
HAL_OK
)
{
Error_Handler
();
}
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_HSI
;
RCC_OscInitStruct
.
HSIState
=
RCC_HSI_ON
;
RCC_OscInitStruct
.
HSICalibrationValue
=
RCC_HSICALIBRATION_DEFAULT
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSI
;
RCC_OscInitStruct
.
PLL
.
PLLM
=
2
;
RCC_OscInitStruct
.
PLL
.
PLLN
=
25
;
RCC_OscInitStruct
.
PLL
.
PLLP
=
RCC_PLLP_DIV2
;
RCC_OscInitStruct
.
PLL
.
PLLQ
=
RCC_PLLQ_DIV2
;
RCC_OscInitStruct
.
PLL
.
PLLR
=
RCC_PLLR_DIV2
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_HCLK
|
RCC_CLOCKTYPE_SYSCLK
|
RCC_CLOCKTYPE_PCLK1
|
RCC_CLOCKTYPE_PCLK2
;
RCC_ClkInitStruct
.
SYSCLKSource
=
RCC_SYSCLKSOURCE_PLLCLK
;
RCC_ClkInitStruct
.
AHBCLKDivider
=
RCC_SYSCLK_DIV1
;
RCC_ClkInitStruct
.
APB1CLKDivider
=
RCC_HCLK_DIV2
;
RCC_ClkInitStruct
.
APB2CLKDivider
=
RCC_HCLK_DIV2
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_4
)
!=
HAL_OK
)
{
Error_Handler
();
}
PeriphClkInit
.
PeriphClockSelection
=
RCC_PERIPHCLK_LPUART1
;
PeriphClkInit
.
Lpuart1ClockSelection
=
RCC_LPUART1CLKSOURCE_HSI
;
if
(
HAL_RCCEx_PeriphCLKConfig
(
&
PeriphClkInit
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
/**
* @brief LPUART1 Initialization Function
* @param None
* @retval None
*/
static
void
MX_LPUART1_UART_Init
(
void
)
{
/* USER CODE BEGIN LPUART1_Init 0 */
/* USER CODE END LPUART1_Init 0 */
/* USER CODE BEGIN LPUART1_Init 1 */
/* USER CODE END LPUART1_Init 1 */
hlpuart1
.
Instance
=
LPUART1
;
hlpuart1
.
Init
.
BaudRate
=
209700
;
hlpuart1
.
Init
.
WordLength
=
UART_WORDLENGTH_7B
;
hlpuart1
.
Init
.
StopBits
=
UART_STOPBITS_1
;
hlpuart1
.
Init
.
Parity
=
UART_PARITY_NONE
;
hlpuart1
.
Init
.
Mode
=
UART_MODE_TX_RX
;
hlpuart1
.
Init
.
HwFlowCtl
=
UART_HWCONTROL_NONE
;
hlpuart1
.
Init
.
OneBitSampling
=
UART_ONE_BIT_SAMPLE_DISABLE
;
hlpuart1
.
Init
.
ClockPrescaler
=
UART_PRESCALER_DIV1
;
hlpuart1
.
AdvancedInit
.
AdvFeatureInit
=
UART_ADVFEATURE_NO_INIT
;
hlpuart1
.
FifoMode
=
UART_FIFOMODE_DISABLE
;
if
(
HAL_UART_Init
(
&
hlpuart1
)
!=
HAL_OK
)
{
Error_Handler
();
}
if
(
HAL_UARTEx_SetTxFifoThreshold
(
&
hlpuart1
,
UART_TXFIFO_THRESHOLD_1_8
)
!=
HAL_OK
)
{
Error_Handler
();
}
if
(
HAL_UARTEx_SetRxFifoThreshold
(
&
hlpuart1
,
UART_RXFIFO_THRESHOLD_1_8
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN LPUART1_Init 2 */
/* USER CODE END LPUART1_Init 2 */
}
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static
void
MX_GPIO_Init
(
void
)
{
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE
();
__HAL_RCC_GPIOG_CLK_ENABLE
();
HAL_PWREx_EnableVddIO2
();
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void
Error_Handler
(
void
)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void
assert_failed
(
char
*
file
,
uint32_t
line
)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif
/* USE_FULL_ASSERT */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_hal_msp.c
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* File Name : stm32l4xx_hal_msp.c
* Description : This file provides code for the MSP Initialization
* and de-Initialization codes.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN Define */
/* USER CODE END Define */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN Macro */
/* USER CODE END Macro */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* External functions --------------------------------------------------------*/
/* USER CODE BEGIN ExternalFunctions */
/* USER CODE END ExternalFunctions */
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void
HAL_MspInit
(
void
)
{
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE
();
__HAL_RCC_PWR_CLK_ENABLE
();
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
/**
* @brief UART MSP Initialization
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void
HAL_UART_MspInit
(
UART_HandleTypeDef
*
huart
)
{
GPIO_InitTypeDef
GPIO_InitStruct
=
{
0
};
if
(
huart
->
Instance
==
LPUART1
)
{
/* USER CODE BEGIN LPUART1_MspInit 0 */
/* USER CODE END LPUART1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_LPUART1_CLK_ENABLE
();
__HAL_RCC_GPIOG_CLK_ENABLE
();
HAL_PWREx_EnableVddIO2
();
/**LPUART1 GPIO Configuration
PG7 ------> LPUART1_TX
PG8 ------> LPUART1_RX
*/
GPIO_InitStruct
.
Pin
=
GPIO_PIN_7
|
GPIO_PIN_8
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_PULLUP
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF8_LPUART1
;
HAL_GPIO_Init
(
GPIOG
,
&
GPIO_InitStruct
);
/* USER CODE BEGIN LPUART1_MspInit 1 */
/* USER CODE END LPUART1_MspInit 1 */
}
}
/**
* @brief UART MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void
HAL_UART_MspDeInit
(
UART_HandleTypeDef
*
huart
)
{
if
(
huart
->
Instance
==
LPUART1
)
{
/* USER CODE BEGIN LPUART1_MspDeInit 0 */
/* USER CODE END LPUART1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_LPUART1_CLK_DISABLE
();
/**LPUART1 GPIO Configuration
PG7 ------> LPUART1_TX
PG8 ------> LPUART1_RX
*/
HAL_GPIO_DeInit
(
GPIOG
,
GPIO_PIN_7
|
GPIO_PIN_8
);
/* USER CODE BEGIN LPUART1_MspDeInit 1 */
/* USER CODE END LPUART1_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/stm32l4xx_it.c
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/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32l4xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32l4xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex-M4 Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void
NMI_Handler
(
void
)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void
HardFault_Handler
(
void
)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while
(
1
)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void
MemManage_Handler
(
void
)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while
(
1
)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void
BusFault_Handler
(
void
)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while
(
1
)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void
UsageFault_Handler
(
void
)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while
(
1
)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles System service call via SWI instruction.
*/
void
SVC_Handler
(
void
)
{
/* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
/**
* @brief This function handles Debug monitor.
*/
void
DebugMon_Handler
(
void
)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/**
* @brief This function handles Pendable request for system service.
*/
void
PendSV_Handler
(
void
)
{
/* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
/**
* @brief This function handles System tick timer.
*/
void
SysTick_Handler
(
void
)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick
();
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
/******************************************************************************/
/* STM32L4xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32l4xx.s). */
/******************************************************************************/
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32l4r5-st-nucleo/board/CubeMX_Config/Src/system_stm32l4xx.c
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/**
******************************************************************************
* @file system_stm32l4xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32l4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* After each device reset the MSI (4 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
* configure the system clock before to branch to main program.
*
* This file configures the system clock as follows:
*=============================================================================
*-----------------------------------------------------------------------------
* System Clock source | MSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 4000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 4000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* PLL_M | 1
*-----------------------------------------------------------------------------
* PLL_N | 8
*-----------------------------------------------------------------------------
* PLL_P | 7
*-----------------------------------------------------------------------------
* PLL_Q | 2
*-----------------------------------------------------------------------------
* PLL_R | 2
*-----------------------------------------------------------------------------
* PLLSAI1_P | NA
*-----------------------------------------------------------------------------
* PLLSAI1_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI1_R | NA
*-----------------------------------------------------------------------------
* PLLSAI2_P | NA
*-----------------------------------------------------------------------------
* PLLSAI2_Q | NA
*-----------------------------------------------------------------------------
* PLLSAI2_R | NA
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Disabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32l4xx_system
* @{
*/
/** @addtogroup STM32L4xx_System_Private_Includes
* @{
*/
#include "stm32l4xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U
/*!< Value of the External oscillator in Hz */
#endif
/* HSE_VALUE */
#if !defined (MSI_VALUE)
#define MSI_VALUE 4000000U
/*!< Value of the Internal oscillator in Hz*/
#endif
/* MSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE 16000000U
/*!< Value of the Internal oscillator in Hz*/
#endif
/* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00
/*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t
SystemCoreClock
=
4000000U
;
const
uint8_t
AHBPrescTable
[
16
]
=
{
0U
,
0U
,
0U
,
0U
,
0U
,
0U
,
0U
,
0U
,
1U
,
2U
,
3U
,
4U
,
6U
,
7U
,
8U
,
9U
};
const
uint8_t
APBPrescTable
[
8
]
=
{
0U
,
0U
,
0U
,
0U
,
1U
,
2U
,
3U
,
4U
};
const
uint32_t
MSIRangeTable
[
12
]
=
{
100000U
,
200000U
,
400000U
,
800000U
,
1000000U
,
2000000U
,
\
4000000U
,
8000000U
,
16000000U
,
24000000U
,
32000000U
,
48000000U
};
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32L4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void
SystemInit
(
void
)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB
->
CPACR
|=
((
3UL
<<
10
*
2
)
|
(
3UL
<<
11
*
2
));
/* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set MSION bit */
RCC
->
CR
|=
RCC_CR_MSION
;
/* Reset CFGR register */
RCC
->
CFGR
=
0x00000000U
;
/* Reset HSEON, CSSON , HSION, and PLLON bits */
RCC
->
CR
&=
0xEAF6FFFFU
;
/* Reset PLLCFGR register */
RCC
->
PLLCFGR
=
0x00001000U
;
/* Reset HSEBYP bit */
RCC
->
CR
&=
0xFFFBFFFFU
;
/* Disable all interrupts */
RCC
->
CIER
=
0x00000000U
;
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB
->
VTOR
=
SRAM_BASE
|
VECT_TAB_OFFSET
;
/* Vector Table Relocation in Internal SRAM */
#else
SCB
->
VTOR
=
FLASH_BASE
|
VECT_TAB_OFFSET
;
/* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void
SystemCoreClockUpdate
(
void
)
{
uint32_t
tmp
=
0U
,
msirange
=
0U
,
pllvco
=
0U
,
pllr
=
2U
,
pllsource
=
0U
,
pllm
=
2U
;
/* Get MSI Range frequency--------------------------------------------------*/
if
((
RCC
->
CR
&
RCC_CR_MSIRGSEL
)
==
RESET
)
{
/* MSISRANGE from RCC_CSR applies */
msirange
=
(
RCC
->
CSR
&
RCC_CSR_MSISRANGE
)
>>
8U
;
}
else
{
/* MSIRANGE from RCC_CR applies */
msirange
=
(
RCC
->
CR
&
RCC_CR_MSIRANGE
)
>>
4U
;
}
/*MSI frequency range in HZ*/
msirange
=
MSIRangeTable
[
msirange
];
/* Get SYSCLK source -------------------------------------------------------*/
switch
(
RCC
->
CFGR
&
RCC_CFGR_SWS
)
{
case
0x00
:
/* MSI used as system clock source */
SystemCoreClock
=
msirange
;
break
;
case
0x04
:
/* HSI used as system clock source */
SystemCoreClock
=
HSI_VALUE
;
break
;
case
0x08
:
/* HSE used as system clock source */
SystemCoreClock
=
HSE_VALUE
;
break
;
case
0x0C
:
/* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource
=
(
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLSRC
);
pllm
=
((
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLM
)
>>
4U
)
+
1U
;
switch
(
pllsource
)
{
case
0x02
:
/* HSI used as PLL clock source */
pllvco
=
(
HSI_VALUE
/
pllm
);
break
;
case
0x03
:
/* HSE used as PLL clock source */
pllvco
=
(
HSE_VALUE
/
pllm
);
break
;
default:
/* MSI used as PLL clock source */
pllvco
=
(
msirange
/
pllm
);
break
;
}
pllvco
=
pllvco
*
((
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLN
)
>>
8U
);
pllr
=
(((
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLLR
)
>>
25U
)
+
1U
)
*
2U
;
SystemCoreClock
=
pllvco
/
pllr
;
break
;
default:
SystemCoreClock
=
msirange
;
break
;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp
=
AHBPrescTable
[((
RCC
->
CFGR
&
RCC_CFGR_HPRE
)
>>
4U
)];
/* HCLK clock frequency */
SystemCoreClock
>>=
tmp
;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32l4r5-st-nucleo/board/Kconfig
0 → 100644
浏览文件 @
2700130e
menu "Hardware Drivers Config"
config SOC_STM32L4R5ZI
bool
select SOC_SERIES_STM32L4
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_STLINK_TO_USART
bool "Enable STLINK TO USART (lpuart1)"
select BSP_USING_UART
select BSP_USING_LPUART1
default y
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config RT_SERIAL_USING_DMA
bool "Enable uart using DMA"
default n
config BSP_USING_LPUART1
bool "Enable LPUART1"
default y
config BSP_LPUART1_RX_USING_DMA
bool "Enable LPUART1 RX DMA"
depends on BSP_USING_LPUART1 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART1
bool "Enable UART1"
default n
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_UART2_RX_USING_DMA
bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART3
bool "Enable UART3"
default n
config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART4
bool "Enable UART4"
default n
config BSP_UART4_RX_USING_DMA
bool "Enable UART4 RX DMA"
depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART5
bool "Enable UART5"
default n
config BSP_UART5_RX_USING_DMA
bool "Enable UART5 RX DMA"
depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
default n
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
config BSP_USING_USBD
bool "Enable OTGFS as USB device"
select RT_USING_USB_DEVICE
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC1
bool "Enable ADC1"
default n
endif
menuconfig BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
select RT_USING_LIBC
default n
if BSP_USING_ONCHIP_RTC
choice
prompt "Select clock source"
default BSP_RTC_USING_LSE
config BSP_RTC_USING_LSE
bool "RTC USING LSE"
config BSP_RTC_USING_LSI
bool "RTC USING LSI"
endchoice
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_SPI1_TX_USING_DMA
bool "Enable SPI1 TX DMA"
depends on BSP_USING_SPI1
default n
config BSP_SPI1_RX_USING_DMA
bool "Enable SPI1 RX DMA"
depends on BSP_USING_SPI1
select BSP_SPI1_TX_USING_DMA
default n
config BSP_USING_SPI2
bool "Enable SPI2 BUS"
default n
config BSP_SPI2_TX_USING_DMA
bool "Enable SPI2 TX DMA"
depends on BSP_USING_SPI2
default n
config BSP_SPI2_RX_USING_DMA
bool "Enable SPI2 RX DMA"
depends on BSP_USING_SPI2
select BSP_SPI2_TX_USING_DMA
default n
config BSP_USING_SPI3
bool "Enable SPI3 BUS"
default n
config BSP_SPI3_TX_USING_DMA
bool "Enable SPI3 TX DMA"
depends on BSP_USING_SPI3
default n
config BSP_SPI3_RX_USING_DMA
bool "Enable SPI3 RX DMA"
depends on BSP_USING_SPI3
select BSP_SPI3_TX_USING_DMA
default n
endif
menuconfig BSP_USING_I2C
bool "Enable using I2C BUS (software simulation)"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default n
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
int "i2c1 scl pin number"
range 1 144
default 100
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 1 144
default 101
endif
menuconfig BSP_USING_I2C2
bool "Enable I2C2 BUS (software simulation)"
default n
if BSP_USING_I2C2
config BSP_I2C2_SCL_PIN
int "i2c2 scl pin number"
range 1 144
default 10
config BSP_I2C2_SDA_PIN
int "I2C2 sda pin number"
range 1 144
default 11
endif
endif
menuconfig BSP_USING_TIM
bool "Enable timer"
default n
select RT_USING_HWTIMER
if BSP_USING_TIM
config BSP_USING_TIM1
bool "Enable TIM1"
default n
config BSP_USING_TIM2
bool "Enable TIM2"
default n
config BSP_USING_TIM3
bool "Enable TIM3"
default n
endif
menuconfig BSP_USING_PWM
bool "Using PWM"
default n
select RT_USING_PWM
if BSP_USING_PWM
config BSP_USING_PWM1
bool "Using PWM1
default n
if BSP_USING_PWM1
config BSP_USING_PWM1_CH1
bool "Enable Channel 1 (PA8)"
default n
config BSP_USING_PWM1_CH2
bool "Enable Channel 2 (PA9)"
default n
config BSP_USING_PWM1_CH3
bool "Enable Channel 3 (PA10)"
default n
config BSP_USING_PWM1_CH4
bool "Enable Channel 4 (PA11)"
default n
endif
endif
endmenu
menu "Board extended module Drivers"
endmenu
endmenu
bsp/stm32/stm32l4r5-st-nucleo/board/SConscript
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import
os
import
rtconfig
from
building
import
*
Import
(
'SDK_LIB'
)
cwd
=
GetCurrentDir
()
# add general drivers
src
=
Split
(
'''
board.c
CubeMX_Config/Src/stm32l4xx_hal_msp.c
'''
)
path
=
[
cwd
]
path
+=
[
cwd
+
'/CubeMX_Config/Inc'
]
startup_path_prefix
=
SDK_LIB
if
rtconfig
.
CROSS_TOOL
==
'gcc'
:
src
+=
[
startup_path_prefix
+
'/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/gcc/startup_stm32l4r5xx.s'
]
elif
rtconfig
.
CROSS_TOOL
==
'keil'
:
src
+=
[
startup_path_prefix
+
'/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/arm/startup_stm32l4r5xx.s'
]
elif
rtconfig
.
CROSS_TOOL
==
'iar'
:
src
+=
[
startup_path_prefix
+
'/STM32L4xx_HAL/CMSIS/Device/ST/STM32L4xx/Source/Templates/iar/startup_stm32l4r5xx.s'
]
# STM32L412xx || STM32L422xx || STM32L431xx
# STM32L432xx || STM32L433xx || STM32L442xx
# STM32L443xx || STM32L451xx || STM32L452xx
# STM32L462xx || STM32L471xx || STM32L475xx
# STM32L476xx || STM32L485xx || STM32L486xx
# STM32L496xx || STM32L4A6xx || STM32L4R5xx
# STM32L4R7xx || STM32L4R9xx || STM32L4S5xx
# STM32L4S7xx || STM32L4S9xx
# You can select chips from the list above
CPPDEFINES
=
[
'STM32L4R5xx'
]
group
=
DefineGroup
(
'Drivers'
,
src
,
depend
=
[
''
],
CPPPATH
=
path
,
CPPDEFINES
=
CPPDEFINES
)
Return
(
'group'
)
bsp/stm32/stm32l4r5-st-nucleo/board/board.c
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-06 SummerGift first version
*/
#include "board.h"
void
SystemClock_Config
(
void
)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
RCC_PeriphCLKInitTypeDef
PeriphClkInit
=
{
0
};
/** Configure the main internal regulator output voltage
*/
if
(
HAL_PWREx_ControlVoltageScaling
(
PWR_REGULATOR_VOLTAGE_SCALE1_BOOST
)
!=
HAL_OK
)
{
Error_Handler
();
}
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_HSI
;
RCC_OscInitStruct
.
HSIState
=
RCC_HSI_ON
;
RCC_OscInitStruct
.
HSICalibrationValue
=
RCC_HSICALIBRATION_DEFAULT
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSI
;
RCC_OscInitStruct
.
PLL
.
PLLM
=
2
;
RCC_OscInitStruct
.
PLL
.
PLLN
=
25
;
RCC_OscInitStruct
.
PLL
.
PLLP
=
RCC_PLLP_DIV2
;
RCC_OscInitStruct
.
PLL
.
PLLQ
=
RCC_PLLQ_DIV2
;
RCC_OscInitStruct
.
PLL
.
PLLR
=
RCC_PLLR_DIV2
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_HCLK
|
RCC_CLOCKTYPE_SYSCLK
|
RCC_CLOCKTYPE_PCLK1
|
RCC_CLOCKTYPE_PCLK2
;
RCC_ClkInitStruct
.
SYSCLKSource
=
RCC_SYSCLKSOURCE_PLLCLK
;
RCC_ClkInitStruct
.
AHBCLKDivider
=
RCC_SYSCLK_DIV1
;
RCC_ClkInitStruct
.
APB1CLKDivider
=
RCC_HCLK_DIV2
;
RCC_ClkInitStruct
.
APB2CLKDivider
=
RCC_HCLK_DIV2
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_4
)
!=
HAL_OK
)
{
Error_Handler
();
}
PeriphClkInit
.
PeriphClockSelection
=
RCC_PERIPHCLK_LPUART1
;
PeriphClkInit
.
Lpuart1ClockSelection
=
RCC_LPUART1CLKSOURCE_HSI
;
if
(
HAL_RCCEx_PeriphCLKConfig
(
&
PeriphClkInit
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
bsp/stm32/stm32l4r5-st-nucleo/board/board.h
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/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-5 SummerGift first version
* 2019-04-09 jhb
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <rtthread.h>
#include <stm32l4xx.h>
#include "drv_common.h"
#include "drv_gpio.h"
#ifdef __cplusplus
extern
"C"
{
#endif
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
#define STM32_FLASH_SIZE (2048 * 1024)
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
#define STM32_SRAM3_SIZE (384)
#define STM32_SRAM3_START (0x20040000)
#define STM32_SRAM3_END (STM32_SRAM3_START + STM32_SRAM3_SIZE * 1024)
#define HEAP_BEGIN STM32_SRAM3_START
#define HEAP_END STM32_SRAM3_END
void
SystemClock_Config
(
void
);
void
SystemClock_ReConfig
(
int
run_mode
);
#ifdef __cplusplus
}
#endif
#endif
bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.icf
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x08200000;
define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM1_end__ = 0x20030000;
define symbol __ICFEDIT_region_RAM2_start__ = 0x20040000;
define symbol __ICFEDIT_region_RAM2_end__ = 0x200A0000;
define symbol __ICFEDIT_region_RAM3_start__ = 0x10000000;
define symbol __ICFEDIT_region_RAM3_end__ = 0x10010000;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x0800;
define symbol __ICFEDIT_size_heap__ = 0x0000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
define region RAM3_region = mem:[from __ICFEDIT_region_RAM3_start__ to __ICFEDIT_region_RAM3_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM1_region { readwrite, last block CSTACK };
place in RAM2_region { section .sram };
bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.lds
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浏览文件 @
2700130e
/*
* linker script for STM32L4XX with GNU ld
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 2048k /* 2048KB flash */
RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192K sram */
RAM2 (rw) : ORIGIN = 0x20040000, LENGTH = 384k /* 384K sram */
RAM3 (rw) : ORIGIN = 0x10000000, LENGTH = 64k /* 64K sram */
}
ENTRY(Reset_Handler)
_system_stack_size = 0x800;
SECTIONS
{
.text :
{
. = ALIGN(4);
_stext = .;
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
. = ALIGN(4);
_etext = .;
} > ROM = 0
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > ROM
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM1
.stack :
{
. = ALIGN(4);
_sstack = .;
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
} >RAM1
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
*(.bss.init)
} > RAM1
__bss_end = .;
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.sct
0 → 100644
浏览文件 @
2700130e
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00200000 { ; load region size_region
ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00030000 { ; RW data
.ANY (+RW +ZI)
}
}
bsp/stm32/stm32l4r5-st-nucleo/figures/board.jpg
0 → 100644
浏览文件 @
2700130e
318.6 KB
bsp/stm32/stm32l4r5-st-nucleo/project.ewd
0 → 100644
浏览文件 @
2700130e
此差异已折叠。
点击以展开。
bsp/stm32/stm32l4r5-st-nucleo/project.ewp
0 → 100644
浏览文件 @
2700130e
此差异已折叠。
点击以展开。
bsp/stm32/stm32l4r5-st-nucleo/project.ewt
0 → 100644
浏览文件 @
2700130e
此差异已折叠。
点击以展开。
bsp/stm32/stm32l4r5-st-nucleo/project.eww
0 → 100644
浏览文件 @
2700130e
<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>
$WS_DIR$\project.ewp
</path>
</project>
<batchBuild/>
</workspace>
bsp/stm32/stm32l4r5-st-nucleo/project.uvoptx
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2700130e
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt
xmlns:xsi=
"http://www.w3.org/2001/XMLSchema-instance"
xsi:noNamespaceSchemaLocation=
"project_optx.xsd"
>
<SchemaVersion>
1.0
</SchemaVersion>
<Header>
### uVision Project, (C) Keil Software
</Header>
<Extensions>
<cExt>
*.c
</cExt>
<aExt>
*.s*; *.src; *.a*
</aExt>
<oExt>
*.obj; *.o
</oExt>
<lExt>
*.lib
</lExt>
<tExt>
*.txt; *.h; *.inc
</tExt>
<pExt>
*.plm
</pExt>
<CppX>
*.cpp
</CppX>
<nMigrate>
0
</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>
0
</dwLowDateTime>
<dwHighDateTime>
0
</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>
rt-thread
</TargetName>
<ToolsetNumber>
0x4
</ToolsetNumber>
<ToolsetName>
ARM-ADS
</ToolsetName>
<TargetOption>
<CLKADS>
12000000
</CLKADS>
<OPTTT>
<gFlags>
1
</gFlags>
<BeepAtEnd>
1
</BeepAtEnd>
<RunSim>
0
</RunSim>
<RunTarget>
1
</RunTarget>
<RunAbUc>
0
</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>
1
</HexSelection>
<FlashByte>
65535
</FlashByte>
<HexRangeLowAddress>
0
</HexRangeLowAddress>
<HexRangeHighAddress>
0
</HexRangeHighAddress>
<HexOffset>
0
</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>
79
</PageWidth>
<PageLength>
66
</PageLength>
<TabStop>
8
</TabStop>
<ListingPath>
.\build\keil\List\
</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>
1
</CreateCListing>
<CreateAListing>
1
</CreateAListing>
<CreateLListing>
1
</CreateLListing>
<CreateIListing>
0
</CreateIListing>
<AsmCond>
1
</AsmCond>
<AsmSymb>
1
</AsmSymb>
<AsmXref>
0
</AsmXref>
<CCond>
1
</CCond>
<CCode>
0
</CCode>
<CListInc>
0
</CListInc>
<CSymb>
0
</CSymb>
<LinkerCodeListing>
0
</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>
1
</LMap>
<LComments>
1
</LComments>
<LGenerateSymbols>
1
</LGenerateSymbols>
<LLibSym>
1
</LLibSym>
<LLines>
1
</LLines>
<LLocSym>
1
</LLocSym>
<LPubSym>
1
</LPubSym>
<LXref>
0
</LXref>
<LExpSel>
0
</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>
0
</tvExp>
<tvExpOptDlg>
0
</tvExpOptDlg>
<IsCurrentTarget>
1
</IsCurrentTarget>
</OPTFL>
<CpuCode>
18
</CpuCode>
<DebugOpt>
<uSim>
0
</uSim>
<uTrg>
1
</uTrg>
<sLdApp>
1
</sLdApp>
<sGomain>
1
</sGomain>
<sRbreak>
1
</sRbreak>
<sRwatch>
1
</sRwatch>
<sRmem>
1
</sRmem>
<sRfunc>
1
</sRfunc>
<sRbox>
1
</sRbox>
<tLdApp>
1
</tLdApp>
<tGomain>
1
</tGomain>
<tRbreak>
1
</tRbreak>
<tRwatch>
1
</tRwatch>
<tRmem>
1
</tRmem>
<tRfunc>
0
</tRfunc>
<tRbox>
1
</tRbox>
<tRtrace>
1
</tRtrace>
<sRSysVw>
1
</sRSysVw>
<tRSysVw>
1
</tRSysVw>
<sRunDeb>
0
</sRunDeb>
<sLrtime>
0
</sLrtime>
<bEvRecOn>
1
</bEvRecOn>
<bSchkAxf>
0
</bSchkAxf>
<bTchkAxf>
0
</bTchkAxf>
<nTsel>
6
</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>
STLink\ST-LINKIII-KEIL_SWO.dll
</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>
0
</Number>
<Key>
ST-LINKIII-KEIL_SWO
</Key>
<Name>
-U066EFF495056867767053013 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM)
</Name>
</SetRegEntry>
<SetRegEntry>
<Number>
0
</Number>
<Key>
UL2CM3
</Key>
<Name>
UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32L4xx_512 -FL080000 -FS08000000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM)
</Name>
</SetRegEntry>
<SetRegEntry>
<Number>
0
</Number>
<Key>
JL2CM3
</Key>
<Name>
-U -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM)
</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>
0
</THDelay>
</Tracepoint>
<DebugFlag>
<trace>
0
</trace>
<periodic>
0
</periodic>
<aLwin>
0
</aLwin>
<aCover>
0
</aCover>
<aSer1>
0
</aSer1>
<aSer2>
0
</aSer2>
<aPa>
0
</aPa>
<viewmode>
0
</viewmode>
<vrSel>
0
</vrSel>
<aSym>
0
</aSym>
<aTbox>
0
</aTbox>
<AscS1>
0
</AscS1>
<AscS2>
0
</AscS2>
<AscS3>
0
</AscS3>
<aSer3>
0
</aSer3>
<eProf>
0
</eProf>
<aLa>
0
</aLa>
<aPa1>
0
</aPa1>
<AscS4>
0
</AscS4>
<aSer4>
0
</aSer4>
<StkLoc>
0
</StkLoc>
<TrcWin>
0
</TrcWin>
<newCpu>
0
</newCpu>
<uProt>
0
</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>
0
</bLintAuto>
<bAutoGenD>
0
</bAutoGenD>
<LntExFlags>
0
</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>
1
</Enable>
<EnableLog>
0
</EnableLog>
<Protocol>
2
</Protocol>
<DbgClock>
10000000
</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
<Group>
<GroupName>
Source Group 1
</GroupName>
<tvExp>
0
</tvExp>
<tvExpOptDlg>
0
</tvExpOptDlg>
<cbSel>
0
</cbSel>
<RteFlg>
0
</RteFlg>
</Group>
</ProjectOpt>
bsp/stm32/stm32l4r5-st-nucleo/project.uvprojx
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此差异已折叠。
点击以展开。
bsp/stm32/stm32l4r5-st-nucleo/rtconfig.h
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define RT_DEBUG
#define RT_DEBUG_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* Memory Management */
#define RT_USING_MEMHEAP
#define RT_USING_SMALL_MEM
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_DEVICE_OPS
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "lpuart1"
#define RT_VER_NUM 0x40002
#define ARCH_ARM
#define RT_USING_CPU_FFS
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M4
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* Command shell */
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_USING_MSH_ONLY
#define FINSH_ARG_MAX 10
/* Device virtual file system */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
/* Using USB */
/* POSIX layer and C standard library */
/* Network */
/* Socket abstraction layer */
/* Network interface device */
/* light weight TCP/IP stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
/* peripheral libraries and drivers */
/* miscellaneous packages */
/* samples: kernel and components samples */
#define SOC_FAMILY_STM32
#define SOC_SERIES_STM32L4
/* Hardware Drivers Config */
#define SOC_STM32L4R5ZI
/* Onboard Peripheral Drivers */
#define BSP_USING_STLINK_TO_USART
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_LPUART1
/* Board extended module Drivers */
#endif
bsp/stm32/stm32l4r5-st-nucleo/rtconfig.py
0 → 100644
浏览文件 @
2700130e
import
os
# toolchains options
ARCH
=
'arm'
CPU
=
'cortex-m4'
CROSS_TOOL
=
'gcc'
# bsp lib config
BSP_LIBRARY_TYPE
=
None
if
os
.
getenv
(
'RTT_CC'
):
CROSS_TOOL
=
os
.
getenv
(
'RTT_CC'
)
if
os
.
getenv
(
'RTT_ROOT'
):
RTT_ROOT
=
os
.
getenv
(
'RTT_ROOT'
)
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if
CROSS_TOOL
==
'gcc'
:
PLATFORM
=
'gcc'
EXEC_PATH
=
r
'C:\Users\XXYYZZ'
elif
CROSS_TOOL
==
'keil'
:
PLATFORM
=
'armcc'
EXEC_PATH
=
r
'C:/Keil_v5'
elif
CROSS_TOOL
==
'iar'
:
PLATFORM
=
'iar'
EXEC_PATH
=
r
'C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4'
if
os
.
getenv
(
'RTT_EXEC_PATH'
):
EXEC_PATH
=
os
.
getenv
(
'RTT_EXEC_PATH'
)
BUILD
=
'debug'
if
PLATFORM
==
'gcc'
:
# toolchains
PREFIX
=
'arm-none-eabi-'
CC
=
PREFIX
+
'gcc'
AS
=
PREFIX
+
'gcc'
AR
=
PREFIX
+
'ar'
CXX
=
PREFIX
+
'g++'
LINK
=
PREFIX
+
'gcc'
TARGET_EXT
=
'elf'
SIZE
=
PREFIX
+
'size'
OBJDUMP
=
PREFIX
+
'objdump'
OBJCPY
=
PREFIX
+
'objcopy'
DEVICE
=
' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
CFLAGS
=
DEVICE
+
' -Dgcc'
AFLAGS
=
' -c'
+
DEVICE
+
' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS
=
DEVICE
+
' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
CPATH
=
''
LPATH
=
''
if
BUILD
==
'debug'
:
CFLAGS
+=
' -O0 -gdwarf-2 -g'
AFLAGS
+=
' -gdwarf-2'
else
:
CFLAGS
+=
' -O2'
CXXFLAGS
=
CFLAGS
POST_ACTION
=
OBJCPY
+
' -O binary $TARGET rtthread.bin
\n
'
+
SIZE
+
' $TARGET
\n
'
elif
PLATFORM
==
'armcc'
:
# toolchains
CC
=
'armcc'
CXX
=
'armcc'
AS
=
'armasm'
AR
=
'armar'
LINK
=
'armlink'
TARGET_EXT
=
'axf'
DEVICE
=
' --cpu Cortex-M4.fp '
CFLAGS
=
'-c '
+
DEVICE
+
' --apcs=interwork --c99'
AFLAGS
=
DEVICE
+
' --apcs=interwork '
LFLAGS
=
DEVICE
+
' --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict --scatter "board\linker_scripts\link.sct"'
CFLAGS
+=
' -I'
+
EXEC_PATH
+
'/ARM/ARMCC/include'
LFLAGS
+=
' --libpath='
+
EXEC_PATH
+
'/ARM/ARMCC/lib'
CFLAGS
+=
' -D__MICROLIB '
AFLAGS
+=
' --pd "__MICROLIB SETA 1" '
LFLAGS
+=
' --library_type=microlib '
EXEC_PATH
+=
'/ARM/ARMCC/bin/'
if
BUILD
==
'debug'
:
CFLAGS
+=
' -g -O0'
AFLAGS
+=
' -g'
else
:
CFLAGS
+=
' -O2'
CXXFLAGS
=
CFLAGS
CFLAGS
+=
' -std=c99'
POST_ACTION
=
'fromelf --bin $TARGET --output rtthread.bin
\n
fromelf -z $TARGET'
elif
PLATFORM
==
'iar'
:
# toolchains
CC
=
'iccarm'
CXX
=
'iccarm'
AS
=
'iasmarm'
AR
=
'iarchive'
LINK
=
'ilinkarm'
TARGET_EXT
=
'out'
DEVICE
=
'-Dewarm'
CFLAGS
=
DEVICE
CFLAGS
+=
' --diag_suppress Pa050'
CFLAGS
+=
' --no_cse'
CFLAGS
+=
' --no_unroll'
CFLAGS
+=
' --no_inline'
CFLAGS
+=
' --no_code_motion'
CFLAGS
+=
' --no_tbaa'
CFLAGS
+=
' --no_clustering'
CFLAGS
+=
' --no_scheduling'
CFLAGS
+=
' --endian=little'
CFLAGS
+=
' --cpu=Cortex-M4'
CFLAGS
+=
' -e'
CFLAGS
+=
' --fpu=VFPv4_sp'
CFLAGS
+=
' --dlib_config "'
+
EXEC_PATH
+
'/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS
+=
' --silent'
AFLAGS
=
DEVICE
AFLAGS
+=
' -s+'
AFLAGS
+=
' -w+'
AFLAGS
+=
' -r'
AFLAGS
+=
' --cpu Cortex-M4'
AFLAGS
+=
' --fpu VFPv4_sp'
AFLAGS
+=
' -S'
if
BUILD
==
'debug'
:
CFLAGS
+=
' --debug'
CFLAGS
+=
' -On'
else
:
CFLAGS
+=
' -Oh'
LFLAGS
=
' --config "board/linker_scripts/link.icf"'
LFLAGS
+=
' --entry __iar_program_start'
CXXFLAGS
=
CFLAGS
EXEC_PATH
=
EXEC_PATH
+
'/arm/bin/'
POST_ACTION
=
'ielftool --bin $TARGET rtthread.bin'
bsp/stm32/stm32l4r5-st-nucleo/template.ewd
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bsp/stm32/stm32l4r5-st-nucleo/template.ewp
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bsp/stm32/stm32l4r5-st-nucleo/template.eww
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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>
$WS_DIR$\template.ewp
</path>
</project>
<batchBuild/>
</workspace>
bsp/stm32/stm32l4r5-st-nucleo/template.uvoptx
0 → 100644
浏览文件 @
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt
xmlns:xsi=
"http://www.w3.org/2001/XMLSchema-instance"
xsi:noNamespaceSchemaLocation=
"project_optx.xsd"
>
<SchemaVersion>
1.0
</SchemaVersion>
<Header>
### uVision Project, (C) Keil Software
</Header>
<Extensions>
<cExt>
*.c
</cExt>
<aExt>
*.s*; *.src; *.a*
</aExt>
<oExt>
*.obj; *.o
</oExt>
<lExt>
*.lib
</lExt>
<tExt>
*.txt; *.h; *.inc
</tExt>
<pExt>
*.plm
</pExt>
<CppX>
*.cpp
</CppX>
<nMigrate>
0
</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>
0
</dwLowDateTime>
<dwHighDateTime>
0
</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>
rt-thread
</TargetName>
<ToolsetNumber>
0x4
</ToolsetNumber>
<ToolsetName>
ARM-ADS
</ToolsetName>
<TargetOption>
<CLKADS>
12000000
</CLKADS>
<OPTTT>
<gFlags>
1
</gFlags>
<BeepAtEnd>
1
</BeepAtEnd>
<RunSim>
0
</RunSim>
<RunTarget>
1
</RunTarget>
<RunAbUc>
0
</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>
1
</HexSelection>
<FlashByte>
65535
</FlashByte>
<HexRangeLowAddress>
0
</HexRangeLowAddress>
<HexRangeHighAddress>
0
</HexRangeHighAddress>
<HexOffset>
0
</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>
79
</PageWidth>
<PageLength>
66
</PageLength>
<TabStop>
8
</TabStop>
<ListingPath>
.\build\keil\List\
</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>
1
</CreateCListing>
<CreateAListing>
1
</CreateAListing>
<CreateLListing>
1
</CreateLListing>
<CreateIListing>
0
</CreateIListing>
<AsmCond>
1
</AsmCond>
<AsmSymb>
1
</AsmSymb>
<AsmXref>
0
</AsmXref>
<CCond>
1
</CCond>
<CCode>
0
</CCode>
<CListInc>
0
</CListInc>
<CSymb>
0
</CSymb>
<LinkerCodeListing>
0
</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>
1
</LMap>
<LComments>
1
</LComments>
<LGenerateSymbols>
1
</LGenerateSymbols>
<LLibSym>
1
</LLibSym>
<LLines>
1
</LLines>
<LLocSym>
1
</LLocSym>
<LPubSym>
1
</LPubSym>
<LXref>
0
</LXref>
<LExpSel>
0
</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>
0
</tvExp>
<tvExpOptDlg>
0
</tvExpOptDlg>
<IsCurrentTarget>
1
</IsCurrentTarget>
</OPTFL>
<CpuCode>
18
</CpuCode>
<DebugOpt>
<uSim>
0
</uSim>
<uTrg>
1
</uTrg>
<sLdApp>
1
</sLdApp>
<sGomain>
1
</sGomain>
<sRbreak>
1
</sRbreak>
<sRwatch>
1
</sRwatch>
<sRmem>
1
</sRmem>
<sRfunc>
1
</sRfunc>
<sRbox>
1
</sRbox>
<tLdApp>
1
</tLdApp>
<tGomain>
1
</tGomain>
<tRbreak>
1
</tRbreak>
<tRwatch>
1
</tRwatch>
<tRmem>
1
</tRmem>
<tRfunc>
0
</tRfunc>
<tRbox>
1
</tRbox>
<tRtrace>
1
</tRtrace>
<sRSysVw>
1
</sRSysVw>
<tRSysVw>
1
</tRSysVw>
<sRunDeb>
0
</sRunDeb>
<sLrtime>
0
</sLrtime>
<bEvRecOn>
1
</bEvRecOn>
<bSchkAxf>
0
</bSchkAxf>
<bTchkAxf>
0
</bTchkAxf>
<nTsel>
6
</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>
STLink\ST-LINKIII-KEIL_SWO.dll
</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>
0
</Number>
<Key>
ST-LINKIII-KEIL_SWO
</Key>
<Name>
-U066EFF495056867767053013 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM)
</Name>
</SetRegEntry>
<SetRegEntry>
<Number>
0
</Number>
<Key>
UL2CM3
</Key>
<Name>
UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32L4xx_512 -FL080000 -FS08000000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM)
</Name>
</SetRegEntry>
<SetRegEntry>
<Number>
0
</Number>
<Key>
JL2CM3
</Key>
<Name>
-U -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32L4xx_512.FLM -FS08000000 -FL080000 -FP0($$Device:STM32L475VETx$CMSIS\Flash\STM32L4xx_512.FLM)
</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>
0
</THDelay>
</Tracepoint>
<DebugFlag>
<trace>
0
</trace>
<periodic>
0
</periodic>
<aLwin>
0
</aLwin>
<aCover>
0
</aCover>
<aSer1>
0
</aSer1>
<aSer2>
0
</aSer2>
<aPa>
0
</aPa>
<viewmode>
0
</viewmode>
<vrSel>
0
</vrSel>
<aSym>
0
</aSym>
<aTbox>
0
</aTbox>
<AscS1>
0
</AscS1>
<AscS2>
0
</AscS2>
<AscS3>
0
</AscS3>
<aSer3>
0
</aSer3>
<eProf>
0
</eProf>
<aLa>
0
</aLa>
<aPa1>
0
</aPa1>
<AscS4>
0
</AscS4>
<aSer4>
0
</aSer4>
<StkLoc>
0
</StkLoc>
<TrcWin>
0
</TrcWin>
<newCpu>
0
</newCpu>
<uProt>
0
</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>
0
</bLintAuto>
<bAutoGenD>
0
</bAutoGenD>
<LntExFlags>
0
</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
<DebugDescription>
<Enable>
1
</Enable>
<EnableLog>
0
</EnableLog>
<Protocol>
2
</Protocol>
<DbgClock>
10000000
</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
<Group>
<GroupName>
Source Group 1
</GroupName>
<tvExp>
0
</tvExp>
<tvExpOptDlg>
0
</tvExpOptDlg>
<cbSel>
0
</cbSel>
<RteFlg>
0
</RteFlg>
</Group>
</ProjectOpt>
bsp/stm32/stm32l4r5-st-nucleo/template.uvprojx
0 → 100644
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