Merge pull request #1865 from nongxiaoming/master

 [bsp][stm32] Fix compile failure when using ARM Compiler V6.

bsp/stm32f0x/applications/startup.c

@@ -26,7 +26,7 @@
 
 extern int  rt_application_init(void);
 
-#ifdef __CC_ARM
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
 #define STM32_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
 #elif __ICCARM__

bsp/stm32f107/applications/startup.c

@@ -25,7 +25,7 @@
 
 extern int  rt_application_init(void);
 
-#ifdef __CC_ARM
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
 #define STM32_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
 #elif __ICCARM__

bsp/stm32f10x/applications/startup.c

@@ -25,7 +25,7 @@
 
 extern int  rt_application_init(void);
 
-#ifdef __CC_ARM
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
 #elif __ICCARM__
 #pragma section="HEAP"
@@ -66,7 +66,7 @@ void rtthread_startup(void)
 #if STM32_EXT_SRAM
     rt_system_heap_init((void*)STM32_EXT_SRAM_BEGIN, (void*)STM32_EXT_SRAM_END);
 #else
-#ifdef __CC_ARM
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
     rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)STM32_SRAM_END);
 #elif __ICCARM__
     rt_system_heap_init(__segment_end("HEAP"), (void*)STM32_SRAM_END);

bsp/stm32f20x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F2xx/system_stm32f2xx.c

@@ -385,7 +385,7 @@ static void SetSysClock(void)
     RCC->CFGR |= RCC_CFGR_SW_PLL;
 
     /* Wait till the main PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL)
     {
     }
   }

bsp/stm32f20x/applications/startup.c

@@ -26,7 +26,7 @@
 
 extern int  rt_application_init(void);
 
-#ifdef __CC_ARM
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
 #elif __ICCARM__
 #pragma section="HEAP"
@@ -78,7 +78,7 @@ void rtthread_startup(void)
 #if STM32_EXT_SRAM
 	rt_system_heap_init((void*)STM32_EXT_SRAM_BEGIN, (void*)STM32_EXT_SRAM_END);
 #else
-	#ifdef __CC_ARM
+	#if defined(__CC_ARM) || defined(__CLANG_ARM)
 		rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)STM32_SRAM_END);
 	#elif __ICCARM__
 	    rt_system_heap_init(__segment_end("HEAP"), (void*)STM32_SRAM_END);

bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c

@@ -400,7 +400,7 @@ static void SetSysClock(void)
     RCC->CFGR |= RCC_CFGR_SW_PLL;
 
     /* Wait till the main PLL is used as system clock source */
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL)
     {
     }
   }

bsp/stm32f40x/drivers/board.h

@@ -46,7 +46,7 @@ extern char __ICFEDIT_region_RAM_end__;
 #define STM32_SRAM_END          (0x20000000 + STM32_SRAM_SIZE * 1024)
 #endif
 
-#ifdef __CC_ARM
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
 #define STM32_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
 #elif __ICCARM__

bsp/stm32f411-nucleo/drivers/board.h

@@ -23,7 +23,7 @@
 #define STM32_SRAM_SIZE         128
 #define STM32_SRAM_END          (0x20000000 + STM32_SRAM_SIZE * 1024)
 
-#ifdef __CC_ARM
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
 #define HEAP_BEGIN  ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
 #elif __ICCARM__

bsp/stm32f429-apollo/drivers/board.h

@@ -46,7 +46,7 @@ extern char __ICFEDIT_region_RAM_end__;
 #define STM32_SRAM_END          (0x20000000 + STM32_SRAM_SIZE * 1024)
 #endif
 
-#ifdef __CC_ARM
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
 #define HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
 #elif __ICCARM__

bsp/stm32f429-armfly/drivers/board.h

@@ -33,7 +33,7 @@ extern char __ICFEDIT_region_RAM_end__;
 #define STM32_SRAM_END          (0x20000000 + STM32_SRAM_SIZE * 1024)
 #endif
 
-#ifdef __CC_ARM
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RTT_HEAP$$ZI$$Base;
 extern int Image$$RTT_HEAP$$ZI$$Limit;
 #define HEAP_BEGIN      (&Image$$RTT_HEAP$$ZI$$Base)

bsp/stm32f429-disco/drivers/board.h

@@ -44,7 +44,7 @@ extern char __ICFEDIT_region_RAM_end__;
 #define STM32_SRAM_END          (0x20000000 + STM32_SRAM_SIZE * 1024)
 #endif
 
-#ifdef __CC_ARM
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
 #define HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
 #elif __ICCARM__

bsp/stm32f7-disco/drivers/board.h

@@ -21,7 +21,7 @@
 #define EXT_SDRAM_SIZE     (0x800000)
 #define EXT_SDRAM_END      (EXT_SDRAM_BEGIN + EXT_SDRAM_SIZE)
 
-#ifdef __CC_ARM
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
 #define HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
 #elif __ICCARM__

bsp/stm32l072/app/startup.c

@@ -26,7 +26,7 @@
 
 extern int  rt_application_init(void);
 
-#ifdef __CC_ARM
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
 #define STM32_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
 #elif __ICCARM__

bsp/stm32l475-iot-disco/drivers/board.h

@@ -29,7 +29,7 @@ extern char __ICFEDIT_region_RAM_end__;
 #define STM32_SRAM_END          (0x20000000 + STM32_SRAM_SIZE * 1024)
 #endif
 
-#ifdef __CC_ARM
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
 #define HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
 #elif __ICCARM__

bsp/stm32l476-nucleo/drivers/board.h

@@ -36,7 +36,7 @@ extern char __ICFEDIT_region_RAM_end__;
 #define STM32_SRAM_END          (0x20000000 + STM32_SRAM_SIZE * 1024)
 #endif
 
-#ifdef __CC_ARM
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
 extern int Image$$RW_IRAM1$$ZI$$Limit;
 #define HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
 #elif __ICCARM__