modified start_gcc.s, and added lowlevel_init.S to initialize sdram.

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@493 bbd45198-f89e-11dd-88c7-29a3b14d5316

libcpu/arm/s3c24x0/lowlevel_init.S

+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-03-16     Gary Lee     the first version
+ */
+
+#define BWSCON	        0x48000000
+
+/* BWSCON */
+#define DW8				(0x0)
+#define DW16			(0x1)
+#define DW32			(0x2)
+#define WAIT			(0x1<<2)
+#define UBLB			(0x1<<3)
+
+#define B1_BWSCON		(DW16)
+#define B2_BWSCON		(DW16)
+#define B3_BWSCON		(DW16 + WAIT + UBLB)
+#define B4_BWSCON		(DW16)
+#define B5_BWSCON		(DW16)
+#define B6_BWSCON		(DW32)
+#define B7_BWSCON		(DW32)
+
+#define B0_Tacs			0x0
+#define B0_Tcos			0x0
+#define B0_Tacc			0x7
+#define B0_Tcoh			0x0
+#define B0_Tah			0x0
+#define B0_Tacp			0x0
+#define B0_PMC			0x0
+
+#define B1_Tacs			0x0
+#define B1_Tcos			0x0
+#define B1_Tacc			0x7
+#define B1_Tcoh			0x0
+#define B1_Tah			0x0
+#define B1_Tacp			0x0
+#define B1_PMC			0x0
+
+#define B2_Tacs			0x0
+#define B2_Tcos			0x0
+#define B2_Tacc			0x7
+#define B2_Tcoh			0x0
+#define B2_Tah			0x0
+#define B2_Tacp			0x0
+#define B2_PMC			0x0
+
+#define B3_Tacs			0xc
+#define B3_Tcos			0x7
+#define B3_Tacc			0xf
+#define B3_Tcoh			0x1
+#define B3_Tah			0x0
+#define B3_Tacp			0x0
+#define B3_PMC			0x0
+
+#define B4_Tacs			0x0
+#define B4_Tcos			0x0
+#define B4_Tacc			0x7
+#define B4_Tcoh			0x0
+#define B4_Tah			0x0
+#define B4_Tacp			0x0
+#define B4_PMC			0x0
+
+#define B5_Tacs			0xc
+#define B5_Tcos			0x7
+#define B5_Tacc			0xf
+#define B5_Tcoh			0x1
+#define B5_Tah			0x0
+#define B5_Tacp			0x0
+#define B5_PMC			0x0
+
+#define B6_MT			0x3				/* SDRAM 											*/
+#define B6_Trcd			0x1
+#define B6_SCAN			0x1				/* 9bit 											*/
+
+#define B7_MT			0x3				/* SDRAM 											*/
+#define B7_Trcd			0x1				/* 3clk 											*/
+#define B7_SCAN			0x1				/* 9bit 											*/
+
+/* REFRESH parameter 					*/
+#define REFEN			0x1				/* Refresh enable 									*/
+#define TREFMD			0x0				/* CBR(CAS before RAS)/Auto refresh 				*/
+#define Trc				0x3				/* 7clk 											*/
+#define Tchr			0x2				/* 3clk 											*/
+
+#define Trp				0x2				/* 4clk 											*/
+#define REFCNT			1012
+
+/**************************************/
+
+.globl lowlevel_init
+lowlevel_init:
+	/* memory control configuration 	*/
+	/* make r0 relative the current location so that it 									*/
+	/* reads SMRDATA out of FLASH rather than memory ! 										*/
+	ldr     r0, =SMRDATA
+	ldr	    r1, =lowlevel_init
+	sub	    r0, r0, r1
+	adr	    r3, lowlevel_init			/* r3 <- current position of code   				*/
+	add     r0, r0, r3
+	ldr	    r1, =BWSCON					/* Bus Width Status Controller 						*/
+	add     r2, r0, #13*4
+0:
+	ldr     r3, [r0], #4
+	str     r3, [r1], #4
+	cmp     r2, r0
+	bne     0b
+
+	/* everything is fine now 			*/
+	mov	    pc, lr
+
+	.ltorg
+/* the literal pools origin 			*/
+
+SMRDATA:
+    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
+    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
+    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
+    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
+    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
+    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
+    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
+    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
+    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
+    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
+    .word 0xb2
+    .word 0x30
+    .word 0x30
+    

libcpu/arm/s3c24x0/start_gcc.s

@@ -12,6 +12,7 @@
  * 2006-03-13     Bernard      first version
  * 2006-10-05     Alsor.Z      for s3c2440 initialize
  * 2008-01-29     Yi.Qiu       for QEMU emulator
+ * 2010-03-15	  Gary Lee	   Modified the structure of startcode
  */
 
 #define CONFIG_STACKSIZE 	512
@@ -37,6 +38,10 @@
 #define S_R1  				4
 #define S_R0 				0
 
+#define CLK_CTL_BASE	    0x4C000000	/* Gary Lee 				*/
+#define MDIV_405		    0x7f << 12	/* Gary Lee 				*/
+#define PSDIV_405		    0x21		/* Gary Lee 				*/
+
 .equ 	USERMODE, 			0x10
 .equ 	FIQMODE,			0x11
 .equ 	IRQMODE,			0x12
@@ -88,14 +93,14 @@
 
 .globl _start
 _start:
-	b		reset
-	ldr		pc, _vector_undef
-	ldr		pc, _vector_swi
-	ldr		pc, _vector_pabt
-	ldr		pc, _vector_dabt
-	ldr		pc, _vector_resv
-	ldr		pc, _vector_irq
-	ldr		pc, _vector_fiq
+	b		    reset
+	ldr		    pc, _vector_undef
+	ldr		    pc, _vector_swi
+	ldr		    pc, _vector_pabt
+	ldr		    pc, _vector_dabt
+	ldr		    pc, _vector_resv
+	ldr		    pc, _vector_irq
+	ldr		    pc, _vector_fiq
 
 _vector_undef:	.word vector_undef
 _vector_swi:	.word vector_swi
@@ -105,7 +110,7 @@ _vector_resv:	.word vector_resv
 _vector_irq:	.word vector_irq
 _vector_fiq:	.word vector_fiq
 
-.balignl 	16,0xdeadbeef
+.balignl 	    16, 0xdeadbeef
 
 /*
  *************************************************************************
@@ -116,26 +121,21 @@ _vector_fiq:	.word vector_fiq
  * jump to second stage
  *
  *************************************************************************
- */
-
-_TEXT_BASE:
+ */       
+_TEXT_BASE:                  /* TEXT_BASE was defined in rtconfig.py */
 	.word	TEXT_BASE
 
-/*
- * rtthread kernel start and end
- * which are defined in linker script
- */
+/* rtthread kernel start and end which are defined in linker script */
 .globl _rtthread_start
 _rtthread_start:
 	.word _start
-	
+
+/* _end	was defined in link script                                  */
 .globl _rtthread_end
 _rtthread_end:
 	.word  _end
 
-/*
- * rtthread bss start and end which are defined in linker script
- */
+/* rtthread bss start and end which are defined in linker script    */
 .globl _bss_start
 _bss_start:	
 	.word __bss_start
@@ -165,21 +165,73 @@ ABORT_STACK_START:
 _STACK_START:
 	.word _svc_stack_start + 4096
 
-/* ----------------------------------entry------------------------------*/
+.globl _load_address
+#if defined (__FLASH_BUILD__)
+_load_address: 
+	.word ROM_BASE + _TEXT_BASE
+#else
+_load_address: 
+	.word RAM_BASE + _TEXT_BASE
+#endif	
+
+/*
+ *************************************************************************
+ * Actual start (entry point)
+ *************************************************************************
+ */
 reset:
+    bl      mode_svn32
+    bl      watchdog_disable
+    bl      interrupt_disable
+    bl     sys_clock_setup
+    bl		cpu_crit_init
+    bl		interrupt_vector_setup
+	bl		stack_setup
+    bl      bss_clear
+	/* call C++ constructors of global objects 							*/
+	ldr 	r0, =__ctors_start__
+	ldr 	r1, =__ctors_end__
 	
-	/* set the cpu to SVC32 mode 	*/
-	mrs		r0,cpsr
-	bic		r0,r0,#MODEMASK
-	orr		r0,r0,#SVCMODE
-	msr		cpsr,r0
-	
-	/* watch dog disable 			*/
-	ldr 	r0,=WTCON
-	ldr 	r1,=0x0
-	str 	r1,[r0]
+ctor_loop:
+    cmp     r0, r1
+	beq 	kernel_start
+	ldr 	r2, [r0], #4
+	stmfd 	sp!, {r0-r1}
+	mov 	lr, pc
+	bx 		r2
+	ldmfd 	sp!, {r0-r1}
+	b		ctor_loop
+
+kernel_start:
+	/* start RT-Thread Kernel 		                                    */
+	ldr		pc, _rtthread_startup
+
+_rtthread_startup: 
+	.word rtthread_startup	
+/*
+ *************************************************************************
+ * Subroutines
+ *************************************************************************
+ */
+	/* set the cpu to SVC32 mode 	                                    */
+mode_svn32:
+	mrs		r0, cpsr
+	bic		r0, r0,#MODEMASK
+	orr		r0, r0,#SVCMODE
+	msr		cpsr, r0
+
+	mov     pc, lr
+
+    /* watch dog disable 			                                    */
+watchdog_disable:    
+	ldr 	r0, =WTCON
+	ldr 	r1, =0x0
+	str 	r1, [r0]
+
+	mov     pc, lr
 
 	/* mask all IRQs by clearing all bits in the INTMRs 				*/
+interrupt_disable:	
 	ldr		r1, =INTMSK
 	ldr		r0, =0xffffffff
 	str		r0, [r1]
@@ -187,8 +239,50 @@ reset:
 	ldr		r0, =0x7fff				/*all sub interrupt disable			*/
 	str		r0, [r1]
 
+	mov     pc, lr
+
+sys_clock_setup:	/* FCLK:HCLK:PCLK = 1:4:8           */	
+    ldr		r0, =CLKDIVN	
+    mov		r1, #5	
+    str		r1, [r0]
+    
+    mrc		p15, 0, r1, c1, c0, 0		/* switch to asynchronous mode			*/	
+    orr		r1, r1, #0xc0000000			
+    mcr		p15, 0, r1, c1, c0, 0
+    
+    mov		r1, #CLK_CTL_BASE		
+    mov		r2, #MDIV_405		
+    add		r2, r2, #PSDIV_405		
+    str		r2, [r1, #0x04]				/* MPLLCON Gary Lee 					*/ 
+
+    mov     pc, lr
+
+/*==============================================================================*/
+cpu_crit_init:
+	/* flush v4 I/D caches              */
+
+	mov		r0, #0
+	mcr		p15, 0, r0, c7, c7, 0		/* flush v3/v4 cache 					*/
+	mcr		p15, 0, r0, c8, c7, 0		/* flush v4 TLB 						*/
+
+	/* disable MMU stuff and caches     */
+	mrc		p15, 0, r0, c1, c0, 0
+	bic		r0, r0, #0x00002300	        /* clear bits 13, 9:8 (--V- --RS)       */
+	bic		r0, r0, #0x00000087	        /* clear bits 7,  2:0 (B--- -CAM)        */
+	orr		r0, r0, #0x00000002	        /* set bit 2  (A) Align                  */
+	orr		r0, r0, #0x00001000	        /* set bit 12 (I) I-Cache               */
+	mcr		p15, 0, r0, c1, c0, 0
+
+	mov	    ip, lr
+
+	bl		lowlevel_init
+
+	mov		lr, ip
+	mov		pc, lr
+
 	/* set interrupt vector 		*/
-	ldr 	r0, _load_address
+interrupt_vector_setup:
+	ldr 	r0, _load_address       /* _load_address = 0x30000000       */
 	mov		r1, #0x0				/* target address    				*/
 	add		r2, r0, #0x20			/* size, 32bytes         			*/
 
@@ -198,10 +292,39 @@ copy_loop:
 	cmp		r0, r2					/* until source end addreee [r2]    */
 	ble		copy_loop
 
-	/* setup stack */
-	bl		stack_setup
+	mov		pc, lr	
+	
+stack_setup:
+	mrs		r0, cpsr
+	bic		r0, r0, #MODEMASK
+	orr		r1, r0, #UNDEFMODE|NOINT
+	msr		cpsr_cxsf, r1			/* undef mode						*/
+	ldr		sp, UNDEFINED_STACK_START
+
+	orr		r1,r0,#ABORTMODE|NOINT
+	msr		cpsr_cxsf,r1			/* abort mode						*/
+	ldr		sp, ABORT_STACK_START
 
-	/* clear .bss */
+	orr		r1,r0,#IRQMODE|NOINT
+	msr		cpsr_cxsf,r1			/* IRQ mode							*/
+	ldr		sp, IRQ_STACK_START
+
+	orr		r1,r0,#FIQMODE|NOINT
+	msr		cpsr_cxsf,r1			/* FIQ mode							*/
+	ldr		sp, FIQ_STACK_START
+
+	bic		r0,r0,#MODEMASK
+	orr		r1,r0,#SVCMODE|NOINT
+	msr		cpsr_cxsf,r1			/* SVC mode							*/
+
+	ldr		sp, _STACK_START
+
+	/* USER mode is not initialized. */
+
+	mov		pc,lr					/* The LR register may be not valid for the mode changes.*/
+
+    /* clear .bss */
+bss_clear:    
 	mov   	r0,#0                   /* get a zero 						*/
 	ldr   	r1,=__bss_start         /* bss start 						*/
 	ldr   	r2,=__bss_end           /* bss end 							*/
@@ -209,37 +332,10 @@ copy_loop:
 bss_loop:
 	cmp   	r1,r2                   /* check if data to clear 			*/
 	strlo 	r0,[r1],#4              /* clear 4 bytes 					*/
-	blo   	bss_loop                /* loop until done 					*/
+	blo   	bss_loop                /* loop until done 					*/	
 
-	/* call C++ constructors of global objects 							*/
-	ldr 	r0, =__ctors_start__
-	ldr 	r1, =__ctors_end__
+	mov     pc, lr
 	
-ctor_loop:
-	cmp 	r0, r1
-	beq 	ctor_end
-	ldr 	r2, [r0], #4
-	stmfd 	sp!, {r0-r1}
-	mov 	lr, pc
-	bx 		r2
-	ldmfd 	sp!, {r0-r1}
-	b		ctor_loop
-	
-ctor_end:
-
-	/* start RT-Thread Kernel 		*/
-	ldr		pc, _rtthread_startup
-
-_rtthread_startup: 
-	.word rtthread_startup
-#if defined (__FLASH_BUILD__)
-_load_address: 
-	.word ROM_BASE + _TEXT_BASE
-#else
-_load_address: 
-	.word RAM_BASE + _TEXT_BASE
-#endif
-
 /*
  *************************************************************************
  *
@@ -358,33 +454,4 @@ _interrupt_thread_switch:
 
 	ldmfd	sp!, {r0-r12,lr,pc}		/* pop new task's r0-r12,lr & pc	*/
 
-stack_setup:
-	mrs		r0, cpsr
-	bic		r0, r0, #MODEMASK
-	orr		r1, r0, #UNDEFMODE|NOINT
-	msr		cpsr_cxsf, r1			/* undef mode						*/
-	ldr		sp, UNDEFINED_STACK_START
-
-	orr		r1,r0,#ABORTMODE|NOINT
-	msr		cpsr_cxsf,r1			/* abort mode						*/
-	ldr		sp, ABORT_STACK_START
-
-	orr		r1,r0,#IRQMODE|NOINT
-	msr		cpsr_cxsf,r1			/* IRQ mode							*/
-	ldr		sp, IRQ_STACK_START
-
-	orr		r1,r0,#FIQMODE|NOINT
-	msr		cpsr_cxsf,r1			/* FIQ mode							*/
-	ldr		sp, FIQ_STACK_START
-
-	bic		r0,r0,#MODEMASK
-	orr		r1,r0,#SVCMODE|NOINT
-	msr		cpsr_cxsf,r1			/* SVC mode							*/
-
-	ldr		sp, _STACK_START
-
-	/* USER mode is not initialized. */
-
-	mov		pc,lr					/* The LR register may be not valid for the mode changes.*/
-
 /*/*}*/