add more options.

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@108 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/stm3210/board.c

@@ -53,15 +53,15 @@ void NVIC_Configuration(void)
  *******************************************************************************/
 void  SysTick_Configuration(void)
 {
-    RCC_ClocksTypeDef  rcc_clocks;
-    rt_uint32_t         cnts;
+	RCC_ClocksTypeDef  rcc_clocks;
+	rt_uint32_t         cnts;
 
-    RCC_GetClocksFreq(&rcc_clocks);
+	RCC_GetClocksFreq(&rcc_clocks);
 
-    cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
+	cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
 
-    SysTick_Config(cnts);
-    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
+	SysTick_Config(cnts);
+	SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
 }
 
 /**
@@ -70,7 +70,13 @@ void  SysTick_Configuration(void)
  */
 void rt_hw_timer_handler(void)
 {
+	/* enter interrupt */
+	rt_interrupt_enter();
+
 	rt_tick_increase();
+
+	/* leave interrupt */
+	rt_interrupt_leave();
 }
 
 /**
@@ -87,33 +93,83 @@ void rt_hw_board_init()
 	rt_hw_console_init();
 }
 
+#if STM32_CONSOLE_USART == 1
+#define CONSOLE_RX_PIN	    GPIO_Pin_9
+#define CONSOLE_TX_PIN	    GPIO_Pin_10
+#define CONSOLE_GPIO	    GPIOA
+#define CONSOLE_USART	    USART1
+#define CONSOLE_RCC         RCC_APB2Periph_USART1
+#define CONSOLE_RCC_GPIO    RCC_APB2Periph_GPIOA
+#elif STM32_CONSOLE_USART == 2
+
+#if defined(STM32F10X_LD) || defined(STM32F10X_MD) || defined(STM32F10X_CL)
+#define CONSOLE_RX_PIN	    GPIO_Pin_6
+#define CONSOLE_TX_PIN	    GPIO_Pin_5
+#define CONSOLE_GPIO	    GPIOD
+#define CONSOLE_RCC         RCC_APB1Periph_USART2
+#define CONSOLE_RCC_GPIO    RCC_APB2Periph_GPIOD
+#elif defined(STM32F10X_HD)
+#define CONSOLE_RX_PIN	    GPIO_Pin_3
+#define CONSOLE_TX_PIN	    GPIO_Pin_2
+#define CONSOLE_GPIO	    GPIOA
+#define CONSOLE_RCC         RCC_APB1Periph_USART2
+#define CONSOLE_RCC_GPIO    RCC_APB2Periph_GPIOA
+#endif
+
+#define CONSOLE_USART	USART2
+#elif STM32_CONSOLE_USART == 2
+#define CONSOLE_RX_PIN	    GPIO_Pin_11
+#define CONSOLE_TX_PIN	    GPIO_Pin_10
+#define CONSOLE_GPIO	    GPIOB
+#define CONSOLE_USART	    USART3
+#define CONSOLE_RCC         RCC_APB1Periph_USART3
+#define CONSOLE_RCC_GPIO    RCC_APB2Periph_GPIOB
+#endif
+
 /* init console to support rt_kprintf */
 static void rt_hw_console_init()
 {
+#if STM32_CONSOLE_USART == 0
+#else
+    /* Enable GPIOx clock */
+    RCC_APB2PeriphClockCmd(CONSOLE_RCC_GPIO, ENABLE);
+
+#if STM32_CONSOLE_USART == 1
 	/* Enable USART1 and GPIOA clocks */
-	RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
+	RCC_APB2PeriphClockCmd(CONSOLE_RCC, ENABLE);
+#else
+    RCC_APB1PeriphClockCmd(CONSOLE_RCC, ENABLE);
+#endif
+
+#if (STM32_CONSOLE_USART == 2)  && (defined(STM32F10X_LD) || defined(STM32F10X_MD) || defined(STM32F10X_CL))
+    /* Enable AFIO clock */
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
+
+    /* Enable the USART2 Pins Software Remapping */
+    GPIO_PinRemapConfig(GPIO_Remap_USART2, ENABLE);
+#endif
 
 	/* GPIO configuration */
 	{
-	GPIO_InitTypeDef GPIO_InitStructure;
-
-	/* Configure USART1 Tx (PA.09) as alternate function push-pull */
-	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
-	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-	GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-	/* Configure USART1 Rx (PA.10) as input floating */
-	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
-	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-	GPIO_Init(GPIOA, &GPIO_InitStructure);
+		GPIO_InitTypeDef GPIO_InitStructure;
+
+		/* Configure USART1 Tx (PA.09) as alternate function push-pull */
+		GPIO_InitStructure.GPIO_Pin = CONSOLE_RX_PIN;
+		GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+		GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+		GPIO_Init(CONSOLE_GPIO, &GPIO_InitStructure);
+
+		/* Configure USART1 Rx (PA.10) as input floating */
+		GPIO_InitStructure.GPIO_Pin = CONSOLE_TX_PIN;
+		GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+		GPIO_Init(CONSOLE_GPIO, &GPIO_InitStructure);
 	}
 
 	/* USART configuration */
 	{
-	USART_InitTypeDef USART_InitStructure;
+		USART_InitTypeDef USART_InitStructure;
 
-	/* USART1 configured as follow:
+		/* USART configured as follow:
 		- BaudRate = 115200 baud
 		- Word Length = 8 Bits
 		- One Stop Bit
@@ -124,18 +180,19 @@ static void rt_hw_console_init()
 		- USART CPOL: Clock is active low
 		- USART CPHA: Data is captured on the middle
 		- USART LastBit: The clock pulse of the last data bit is not output to
-		  the SCLK pin
-	*/
-	USART_InitStructure.USART_BaudRate = 115200;
-	USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-	USART_InitStructure.USART_StopBits = USART_StopBits_1;
-	USART_InitStructure.USART_Parity = USART_Parity_No;
-	USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-	USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-	USART_Init(USART1, &USART_InitStructure);
-	/* Enable USART1 */
-	USART_Cmd(USART1, ENABLE);
+		the SCLK pin
+		*/
+		USART_InitStructure.USART_BaudRate = 115200;
+		USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+		USART_InitStructure.USART_StopBits = USART_StopBits_1;
+		USART_InitStructure.USART_Parity = USART_Parity_No;
+		USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+		USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+		USART_Init(CONSOLE_USART, &USART_InitStructure);
+		/* Enable USART1 */
+		USART_Cmd(CONSOLE_USART, ENABLE);
 	}
+#endif
 }
 
 /* write one character to serial, must not trigger interrupt */
@@ -147,8 +204,8 @@ static void rt_hw_console_putc(const char c)
 	*/
 	if (c=='\n')rt_hw_console_putc('\r');
 
-	while (!(USART1->SR & USART_FLAG_TXE));
-	USART1->DR = (c & 0x1FF);
+	while (!(CONSOLE_USART->SR & USART_FLAG_TXE));
+	CONSOLE_USART->DR = (c & 0x1FF);
 }
 
 /**
@@ -158,10 +215,14 @@ static void rt_hw_console_putc(const char c)
  */
 void rt_hw_console_output(const char* str)
 {
+#if STM32_CONSOLE_USART == 0
+	/* no console */
+#else
 	while (*str)
 	{
 		rt_hw_console_putc (*str++);
 	}
+#endif
 }
 
 /*@}*/

bsp/stm3210/stm32_eth.c

@@ -3059,11 +3059,13 @@ uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab)
 #include <netif/ethernetif.h>
 #include "lwipopts.h"
 
-#define DP83848_PHY        /* Ethernet pins mapped on STM3210C-EVAL Board */
-#define PHY_ADDRESS       0x01 /* Relative to STM3210C-EVAL Board */
+#define STM32_ETH_DEBUG		1
 
-#define ETH_RXBUFNB        8
-#define ETH_TXBUFNB        2
+#define DP83848_PHY        	/* Ethernet pins mapped on STM3210C-EVAL Board */
+#define PHY_ADDRESS       	0x01 /* Relative to STM3210C-EVAL Board */
+
+#define ETH_RXBUFNB        	8
+#define ETH_TXBUFNB        	2
 ETH_InitTypeDef ETH_InitStructure;
 ETH_DMADESCTypeDef  DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB];
 rt_uint8_t Rx_Buff[ETH_RXBUFNB][ETH_MAX_PACKET_SIZE], Tx_Buff[ETH_TXBUFNB][ETH_MAX_PACKET_SIZE];
@@ -3080,21 +3082,38 @@ struct rt_stm32_eth
 static struct rt_stm32_eth stm32_eth_device;
 
 /* interrupt service routine */
-void rt_stm32_eth_isr(int irqno)
+void rt_hw_stm32_eth_isr(int irqno)
 {
 	rt_uint32_t status;
 
-	if (status) /* packet receiption */
+	status = ETH->DMASR;
+	
+	rt_kprintf("eth dma status: 0x%08x\n", ETH->DMASR);
+
+	//Clear received IT
+	if ((status & ETH_DMA_IT_NIS) != (u32)RESET)
+		ETH->DMASR = (u32)ETH_DMA_IT_NIS;
+	if ((status & ETH_DMA_IT_AIS) != (u32)RESET)
+		ETH->DMASR = (u32)ETH_DMA_IT_AIS;
+	if ((status & ETH_DMA_IT_RO) != (u32)RESET)
+		ETH->DMASR = (u32)ETH_DMA_IT_RO;
+	if ((status & ETH_DMA_IT_RBU) != (u32)RESET)
+		ETH->DMASR = (u32)ETH_DMA_IT_RBU;
+
+	if (ETH_GetDMAITStatus(ETH_DMA_IT_R) == SET) /* packet receiption */
 	{
 		rt_err_t result;
 
 		/* a frame has been received */
 		result = eth_device_ready(&(stm32_eth_device.parent));
 		RT_ASSERT(result == RT_EOK);
+
+		ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
 	}
 
-	if (status) /* packet transmission */
+	if (ETH_GetDMAITStatus(ETH_DMA_IT_T) == SET) /* packet transmission */
 	{
+		ETH_DMAClearITPendingBit(ETH_DMA_IT_T);
 	}
 }
 
@@ -3134,13 +3153,17 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
 	/* Configure ETHERNET */
 	Value = ETH_Init(&ETH_InitStructure, PHY_ADDRESS);
 
-	ETH_MACITConfig(ETH_MAC_IT_PMT, ENABLE);
+	/* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */
+	ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R, ENABLE);
 	
 	/* Initialize Tx Descriptors list: Chain Mode */
 	ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
 	/* Initialize Rx Descriptors list: Chain Mode  */
 	ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
 
+	/* MAC address configuration */
+	ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]);
+
 	/* Enable MAC and DMA transmission and reception */
 	ETH_Start();
 
@@ -3190,27 +3213,52 @@ static rt_err_t rt_stm32_eth_control(rt_device_t dev, rt_uint8_t cmd, void *args
 /* transmit packet. */
 rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
 {
+#if STM32_ETH_DEBUG	
+	int cnt = 0;
+#endif
 	struct pbuf* q;
+	rt_uint32_t offset;
 
 	/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
 	if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)
 	{
+#if STM32_ETH_DEBUG	
+		rt_kprintf("error: own bit set\n");
+#endif
+
 		/* Return ERROR: OWN bit set */
 		return -RT_ERROR;
 	}
 
+#if STM32_ETH_DEBUG
+	rt_kprintf("tx dump:\n");
+#endif
+	offset = 0;
 	for (q = p; q != NULL; q = q->next)
 	{
-		rt_uint32_t offset;
 		rt_uint8_t* ptr;
+		rt_uint32_t len;
+
+		len = q->len;
+		ptr = q->payload;
 
 		/* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
-		for(offset = 0, ptr = q->payload; offset < q->len; offset++)
+		while (len)
 		{
-			(*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ptr + offset));
+			(*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = *ptr;
+
+#if STM32_ETH_DEBUG
+			rt_kprintf("%02x ", *ptr);
+			if (++cnt % 16 == 0) rt_kprintf("\n");
+#endif
+			offset ++; ptr ++; len --;
 		}
 	}
 
+#if STM32_ETH_DEBUG
+	rt_kprintf("\n");
+#endif
+
 	/* Setting the Frame Length: bits[12:0] */
 	DMATxDescToSet->ControlBufferSize = (p->tot_len & ETH_DMATxDesc_TBS1);
 	/* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
@@ -3222,7 +3270,7 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
 	{
 		/* Clear TBUS ETHERNET DMA flag */
 		ETH->DMASR = ETH_DMASR_TBUS;
-		/* Resume DMA transmission*/
+		/* Transmit Poll Demand to resume DMA transmission*/
 		ETH->DMATPDR = 0;
 	}
 
@@ -3261,11 +3309,19 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
 	p = RT_NULL;
 
 	/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
-	if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) &&
-			((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
-			((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
-			((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
+	if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET))
+		return p;
+
+	if (((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&
+		((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&
+		((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))
 	{
+#if STM32_ETH_DEBUG
+		int cnt = 0;
+		
+		rt_kprintf("rx dump:\n");
+#endif
+		
 		/* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
 		framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;
 
@@ -3286,11 +3342,18 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
 				while (len)
 				{
 					*ptr = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset));
-					ptr ++;
-					len --;
-					offset ++;
+#if STM32_ETH_DEBUG
+					rt_kprintf("%02x ", *ptr);
+					if (++cnt % 16 == 0) rt_kprintf("\n");
+#endif
+
+					offset ++; ptr ++; len --;
 				}
 			}
+			
+#if STM32_ETH_DEBUG
+			rt_kprintf("\n");
+#endif
 		}
 	}
 
@@ -3330,10 +3393,32 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
 	return p;
 }
 
+static void RCC_Configuration(void)
+{
+	/* Enable ETHERNET clock  */
+	RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC | RCC_AHBPeriph_ETH_MAC_Tx |
+						  RCC_AHBPeriph_ETH_MAC_Rx, ENABLE);
+}
+
+static void NVIC_Configuration(void)
+{
+    NVIC_InitTypeDef NVIC_InitStructure;
+
+    /* Configure one bit for preemption priority */
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
+
+    /* Enable the EXTI0 Interrupt */
+    NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+}
+
 /*
  * GPIO Configuration for ETH
  */
-void GPIO_Configuration(void)
+static void GPIO_Configuration(void)
 {
 	GPIO_InitTypeDef GPIO_InitStructure;
 
@@ -3442,6 +3527,17 @@ void GPIO_Configuration(void)
 
 void rt_hw_stm32_eth_init()
 {
+	GPIO_Configuration();
+	RCC_Configuration();
+	NVIC_Configuration();
+
+    stm32_eth_device.dev_addr[0] = 0x01;
+    stm32_eth_device.dev_addr[1] = 0x60;
+    stm32_eth_device.dev_addr[2] = 0x6E;
+    stm32_eth_device.dev_addr[3] = 0x11;
+    stm32_eth_device.dev_addr[4] = 0x02;
+    stm32_eth_device.dev_addr[5] = 0x0F;
+
 	stm32_eth_device.parent.parent.init       = rt_stm32_eth_init;
 	stm32_eth_device.parent.parent.open       = rt_stm32_eth_open;
 	stm32_eth_device.parent.parent.close      = rt_stm32_eth_close;
@@ -3455,3 +3551,4 @@ void rt_hw_stm32_eth_init()
 
 	eth_device_init(&(stm32_eth_device.parent), "e0");
 }
+

bsp/stm3210/stm32f10x_it.c

 /**
   ******************************************************************************
-  * @file    Project/Template/stm32f10x_it.c 
+  * @file    Project/Template/stm32f10x_it.c
   * @author  MCD Application Team
   * @version V3.1.0
   * @date    06/19/2009
   * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
+  *          This file provides template for all exceptions handler and
   *          peripherals interrupt service routine.
   ******************************************************************************
   * @copy
@@ -18,7 +18,7 @@
   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
   *
   * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f10x_it.h"
@@ -192,7 +192,7 @@ void USART1_IRQHandler(void)
 #ifdef RT_USING_UART1
     extern struct rt_device uart1_device;
 	extern void rt_hw_serial_isr(struct rt_device *device);
-	
+
     /* enter interrupt */
     rt_interrupt_enter();
 
@@ -299,7 +299,7 @@ void EXTI0_IRQHandler(void)
 
 /**
   * @}
-  */ 
+  */
 
 
 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/

bsp/stm3210/stm32f10x_it.h

 /**
   ******************************************************************************
-  * @file    Project/Template/stm32f10x_it.h 
+  * @file    Project/Template/stm32f10x_it.h
   * @author  MCD Application Team
   * @version V3.1.0
   * @date    06/19/2009
@@ -16,7 +16,7 @@
   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
   *
   * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32F10x_IT_H
@@ -24,7 +24,7 @@
 
 #ifdef __cplusplus
  extern "C" {
-#endif 
+#endif
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f10x.h"