Merge pull request #2058 from greedyhao/master

[WIP][🏅BSP][stm32] 添加野火stm32f767开发板bsp

bsp/stm32/README.md

@@ -9,6 +9,7 @@ STM32 系列 BSP 目前支持情况如下表所示：
 | [stm32f407-atk-explorer](stm32f407-atk-explorer/)    | 正点原子 F407 探索者开发板 |
 | [stm32f429-atk-apollo](stm32f429-atk-apollo/)      | 正点原子 F429 阿波罗开发板 |
 | [stm32f429-fire-challenger](stm32f429-fire-challenger/) | 野火 F429 挑战者开发板     |
+| [stm32f767-fire-challenger](stm32f767-fire-challenger/) | 野火 F767 挑战者开发板     |
 
 了解每个 BSP 的详细情况可以阅读该 BSP 下的 readme 文件，如需使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档：
 

bsp/stm32/docs/STM32系列BSP添加教程.md

@@ -59,6 +59,7 @@ STM32 BSP 由三部分组成，分别是 (1) 通用库、(2) BSP 模板和 (3)
 | ------- | ---- |
 | libraries/templates/stm32f10x | F1系列芯片模板 |
 | libraries/templates/stm32f4xx | F4系列芯片模板 |
+| libraries/templates/stm32f7xx | F7系列芯片模板 |
 | libraries/templates/stm32l4xx | L4系列芯片模板 |
 
 拷贝 `stm32/libraries/templates/stm32f10x` 文件夹并改名为 `stm32/stm32f103-atk-nano` 。如下图所示：

bsp/stm32/libraries/HAL_Drivers/SConscript

@@ -47,6 +47,9 @@ if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F1']):
 if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F4']):
     src += ['drv_flash/drv_flash_f4.c']
     
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F7']):
+    src += ['drv_flash/drv_flash_f7.c']
+
 if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']):
     src += ['drv_flash/drv_flash_l4.c']
 

bsp/stm32/libraries/HAL_Drivers/config/f7/adc_config.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#endif /* __ADC_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   change to new framework
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_SPI1
+#define SPI1_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SPI1,                                \
+        .bus_name = "spi1",                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream2,                 \
+        .dma_rx.channel = DMA_CHANNEL_3,                 \
+        .dma_rx.dma_irq = DMA2_Stream2_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream3,                 \
+        .dma_tx.channel = DMA_CHANNEL_3,                 \
+        .dma_tx.dma_irq = DMA2_Stream3_IRQn,             \
+    }
+
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler    
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#endif
+
+#ifdef BSP_USING_SPI2
+#define SPI2_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SPI2,                                \
+        .bus_name = "spi2",                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN,            \
+        .dma_rx.Instance = DMA1_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_0,                 \
+        .dma_rx.dma_irq = DMA1_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA1_Stream4,                 \
+        .dma_tx.channel = DMA_CHANNEL_0,                 \
+        .dma_tx.dma_irq = DMA1_Stream4_IRQn,             \
+    }
+
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler    
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#endif
+
+#ifdef BSP_USING_SPI3
+#define SPI3_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SPI3,                                \
+        .bus_name = "spi3",                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN,            \
+        .dma_rx.Instance = DMA1_Stream0,                 \
+        .dma_rx.channel = DMA_CHANNEL_0,                 \
+        .dma_rx.dma_irq = DMA1_Stream0_IRQn,             \
+        .dma_tx.Instance = DMA1_Stream7,                 \
+        .dma_tx.channel = DMA_CHANNEL_0,                 \
+        .dma_tx.dma_irq = DMA1_Stream7_IRQn,             \
+    }
+
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler    
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#endif
+
+#ifdef BSP_USING_SPI4
+#define SPI4_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SPI4,                                \
+        .bus_name = "spi4",                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream0,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream0_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream1,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream1_IRQn,             \
+    }
+
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler    
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#endif
+
+#ifdef BSP_USING_SPI5
+#define SPI5_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SPI5,                                \
+        .bus_name = "spi5",                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_2,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream4,                 \
+        .dma_tx.channel = DMA_CHANNEL_2,                 \
+        .dma_tx.dma_irq = DMA2_Stream4_IRQn,             \
+    }
+
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler    
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#endif
+
+#ifdef BSP_USING_SPI6
+#define SPI5_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SPI6,                                \
+        .bus_name = "spi6",                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream6,                 \
+        .dma_rx.channel = DMA_CHANNEL_1,                 \
+        .dma_rx.dma_irq = DMA2_Stream6_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream5,                 \
+        .dma_tx.channel = DMA_CHANNEL_1,                 \
+        .dma_tx.dma_irq = DMA2_Stream5_IRQn,             \
+    }
+
+#define SPI6_DMA_RX_IRQHandler           DMA2_Stream6_IRQHandler    
+#define SPI6_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   change to new framework
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#if defined(BSP_USING_UART1)
+#define UART1_CONFIG                                       \
+    {                                                      \
+        .name = "uart1",                                   \
+        .Instance = USART1,                                \
+        .irq_type = USART1_IRQn,                           \
+        .dma.stream_channel.Instance = DMA2_Stream5,       \
+        .dma.stream_channel.channel = DMA_CHANNEL_4,       \
+        .dma_rcc = RCC_AHB1ENR_DMA2EN,                     \
+        .dma_irq = DMA2_Stream5_IRQn,                      \
+    }
+
+#define USART1_RX_DMA_ISR                        DMA2_Stream5_IRQHandler
+#endif
+
+#if defined(BSP_USING_UART2)
+#define UART2_CONFIG                                       \
+    {                                                      \
+        .name = "uart2",                                   \
+        .Instance = USART2,                                \
+        .irq_type = USART2_IRQn,                           \
+        .dma.stream_channel.Instance = DMA1_Stream5,       \
+        .dma.stream_channel.channel = DMA_CHANNEL_4,       \
+        .dma_rcc = RCC_AHB1ENR_DMA1EN,                     \
+        .dma_irq = DMA1_Stream5_IRQn,                      \
+    }
+
+#define USART2_RX_DMA_ISR                        DMA1_Stream5_IRQHandler
+#endif
+
+#if defined(BSP_USING_UART3)
+#define UART3_CONFIG                                       \
+    {                                                      \
+        .name = "uart3",                                   \
+        .Instance = USART3,                                \
+        .irq_type = USART3_IRQn,                           \
+        .dma.stream_channel.Instance = DMA1_Stream1,       \
+        .dma.stream_channel.channel = DMA_CHANNEL_4,       \
+        .dma_rcc = RCC_AHB1ENR_DMA1EN,                     \
+        .dma_irq = DMA1_Stream1_IRQn,                      \
+    }
+
+#define USART3_RX_DMA_ISR                        DMA1_Stream1_IRQHandler
+#endif
+
+#if defined(BSP_USING_UART4)
+#define UART4_CONFIG                                       \
+    {                                                      \
+        .name = "uart4",                                   \
+        .Instance = UART4,                                 \
+        .irq_type = UART4_IRQn,                            \
+        .dma.stream_channel.Instance = DMA1_Stream2,       \
+        .dma.stream_channel.channel = DMA_CHANNEL_4,       \
+        .dma_rcc = RCC_AHB1ENR_DMA1EN,                     \
+        .dma_irq = DMA1_Stream2_IRQn,                      \
+    }
+
+#define USART4_RX_DMA_ISR                        DMA1_Stream2_IRQHandler
+#endif
+
+#if defined(BSP_USING_UART5)
+#define UART5_CONFIG                                       \
+    {                                                      \
+        .name = "uart5",                                   \
+        .Instance = UART5,                                 \
+        .irq_type = UART5_IRQn,                            \
+        .dma.stream_channel.Instance = DMA1_Stream0,       \
+        .dma.stream_channel.channel = DMA_CHANNEL_4,       \
+        .dma_rcc = RCC_AHB1ENR_DMA1EN,                     \
+        .dma_irq = DMA1_Stream0_IRQn,                      \
+    }
+
+#define USART5_RX_DMA_ISR                        DMA1_Stream0_IRQHandler
+#endif
+
+#endif

bsp/stm32/libraries/HAL_Drivers/drv_adc.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2018-12-05     zylx         first version
+ * 2018-12-12     greedyhao    Porting for stm32f7xx
  */
 
 #include <board.h>
@@ -126,7 +127,7 @@ static rt_uint32_t stm32_adc_get_channel(rt_uint32_t channel)
     case 17:
         stm32_channel = ADC_CHANNEL_17;
         break;
-#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
+#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
     case 18:
         stm32_channel = ADC_CHANNEL_18;
         break;
@@ -148,7 +149,7 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
 
 #if defined(SOC_SERIES_STM32F1)
     if (channel <= 17)
-#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
+#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
     if (channel <= 18)
 #endif
     {
@@ -159,7 +160,7 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
     {
 #if defined(SOC_SERIES_STM32F1)
         LOG_E("ADC channel must be between 0 and 17.");
-#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
+#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
         LOG_E("ADC channel must be between 0 and 18.");
 #endif
         return -RT_ERROR;
@@ -167,12 +168,12 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
     ADC_ChanConf.Rank = 1;
 #if defined(SOC_SERIES_STM32F1)
     ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_55CYCLES_5;
-#elif defined(SOC_SERIES_STM32F4)
+#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
     ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES;
 #elif defined(SOC_SERIES_STM32L4)
     ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
 #endif
-#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
+#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
     ADC_ChanConf.Offset = 0;
 #endif
 #ifdef SOC_SERIES_STM32L4

bsp/stm32/libraries/HAL_Drivers/drv_config.h

@@ -22,6 +22,10 @@
 #include "f4/uart_config.h"
 #include "f4/spi_config.h"
 #include "f4/adc_config.h"
+#elif  defined(SOC_SERIES_STM32F7)
+#include "f7/uart_config.h"
+#include "f7/spi_config.h"
+#include "f7/adc_config.h"
 #elif  defined(SOC_SERIES_STM32L4)
 #include "l4/uart_config.h"
 #include "l4/spi_config.h"

bsp/stm32/libraries/HAL_Drivers/drv_dma.h

@@ -18,7 +18,7 @@
 
 #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
 #define DMA_INSTANCE_TYPE              DMA_Channel_TypeDef
-#elif defined(SOC_SERIES_STM32F4)
+#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
 #define DMA_INSTANCE_TYPE              DMA_Stream_TypeDef
 #endif /*  defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) */
 
@@ -27,7 +27,7 @@ struct dma_config {
     rt_uint32_t dma_rcc;
     IRQn_Type dma_irq;
 
-#if defined(SOC_SERIES_STM32F4)
+#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
     rt_uint32_t channel;
 #endif
 

bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f7.c

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-5      SummerGift   first version
+ */
+
+#include "board.h"
+
+#ifdef BSP_USING_ON_CHIP_FLASH
+#include "drv_config.h"
+#include "drv_flash.h"
+
+#if defined(PKG_USING_FAL)
+#include "fal.h"
+#endif
+
+//#define DRV_DEBUG
+#define LOG_TAG                "drv.flash"
+#include <drv_log.h>
+
+/* Base address of the Flash sectors Bank 1 */
+#define ADDR_FLASH_SECTOR_0     ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_1     ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_2     ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_3     ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_4     ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */
+#define ADDR_FLASH_SECTOR_5     ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_6     ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_7     ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_8     ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_9     ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_10    ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_11    ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */
+
+/* Base address of the Flash sectors Bank 2 */
+#define ADDR_FLASH_SECTOR_12     ((uint32_t)0x08100000) /* Base @ of Sector 0, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_13     ((uint32_t)0x08104000) /* Base @ of Sector 1, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_14     ((uint32_t)0x08108000) /* Base @ of Sector 2, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_15     ((uint32_t)0x0810C000) /* Base @ of Sector 3, 16 Kbytes */
+#define ADDR_FLASH_SECTOR_16     ((uint32_t)0x08110000) /* Base @ of Sector 4, 64 Kbytes */
+#define ADDR_FLASH_SECTOR_17     ((uint32_t)0x08120000) /* Base @ of Sector 5, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_18     ((uint32_t)0x08140000) /* Base @ of Sector 6, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_19     ((uint32_t)0x08160000) /* Base @ of Sector 7, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_20     ((uint32_t)0x08180000) /* Base @ of Sector 8, 128 Kbytes  */
+#define ADDR_FLASH_SECTOR_21     ((uint32_t)0x081A0000) /* Base @ of Sector 9, 128 Kbytes  */
+#define ADDR_FLASH_SECTOR_22     ((uint32_t)0x081C0000) /* Base @ of Sector 10, 128 Kbytes */
+#define ADDR_FLASH_SECTOR_23     ((uint32_t)0x081E0000) /* Base @ of Sector 11, 128 Kbytes */
+
+/**
+  * @brief  Gets the sector of a given address
+  * @param  None
+  * @retval The sector of a given address
+  */
+static rt_uint32_t GetSector(rt_uint32_t Address)
+{
+    rt_uint32_t sector = 0;
+
+    if((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
+    {
+        sector = FLASH_SECTOR_0;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1))
+    {
+        sector = FLASH_SECTOR_1;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2))
+    {
+        sector = FLASH_SECTOR_2;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3))
+    {
+        sector = FLASH_SECTOR_3;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4))
+    {
+        sector = FLASH_SECTOR_4;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5))
+    {
+        sector = FLASH_SECTOR_5;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6))
+    {
+        sector = FLASH_SECTOR_6;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7))
+    {
+        sector = FLASH_SECTOR_7;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
+    {
+        sector = FLASH_SECTOR_8;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9))
+    {
+        sector = FLASH_SECTOR_9;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10))
+    {
+        sector = FLASH_SECTOR_10;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_12) && (Address >= ADDR_FLASH_SECTOR_11))
+    {
+        sector = FLASH_SECTOR_11;
+    }
+#if defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx)|| defined(STM32F777xx) || defined(STM32F779xx)
+    else if((Address < ADDR_FLASH_SECTOR_13) && (Address >= ADDR_FLASH_SECTOR_12))
+    {
+        sector = FLASH_SECTOR_12;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_14) && (Address >= ADDR_FLASH_SECTOR_13))
+    {
+        sector = FLASH_SECTOR_13;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_15) && (Address >= ADDR_FLASH_SECTOR_14))
+    {
+        sector = FLASH_SECTOR_14;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_16) && (Address >= ADDR_FLASH_SECTOR_15))
+    {
+        sector = FLASH_SECTOR_15;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_17) && (Address >= ADDR_FLASH_SECTOR_16))
+    {
+        sector = FLASH_SECTOR_16;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_18) && (Address >= ADDR_FLASH_SECTOR_17))
+    {
+        sector = FLASH_SECTOR_17;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_19) && (Address >= ADDR_FLASH_SECTOR_18))
+    {
+        sector = FLASH_SECTOR_18;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_20) && (Address >= ADDR_FLASH_SECTOR_19))
+    {
+        sector = FLASH_SECTOR_19;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_21) && (Address >= ADDR_FLASH_SECTOR_20))
+    {
+        sector = FLASH_SECTOR_20;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_22) && (Address >= ADDR_FLASH_SECTOR_21))
+    {
+        sector = FLASH_SECTOR_21;
+    }
+    else if((Address < ADDR_FLASH_SECTOR_23) && (Address >= ADDR_FLASH_SECTOR_22))
+    {
+        sector = FLASH_SECTOR_22;
+    }
+    else /* (Address < FLASH_END_ADDR) && (Address >= ADDR_FLASH_SECTOR_23) */
+    {
+        sector = FLASH_SECTOR_23;
+    }
+#endif
+    return sector;
+}
+
+/**
+ * Read data from flash.
+ * @note This operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+int stm32_flash_read(long offset, rt_uint8_t *buf, size_t size)
+{
+    size_t i;
+    rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("read outrange flash size! addr is (0x%p)", (void*)(addr + size));
+        return -1;
+    }
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * Write data to flash.
+ * @note This operation's units is word.
+ * @note This operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+int stm32_flash_write(long offset, const rt_uint8_t *buf, size_t size)
+{
+    rt_err_t result      = RT_EOK;
+    rt_uint32_t addr     = STM32_FLASH_START_ADRESS + offset;
+    rt_uint32_t end_addr = addr + size;
+
+    if ((end_addr) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("write outrange flash size! addr is (0x%p)", (void*)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    if (size < 1)
+    {
+        return -RT_EINVAL;
+    }
+
+    HAL_FLASH_Unlock();
+
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR);
+
+    for (size_t i = 0; i < size; i++, addr++, buf++)
+    {
+        /* write data to flash */
+        if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_BYTE, addr, (rt_uint64_t)(*buf)) == HAL_OK)
+        {
+            if (*(rt_uint8_t *)addr != *buf)
+            {
+                result = -RT_ERROR;
+                break;
+            }
+        }
+        else
+        {
+            result = -RT_ERROR;
+            break;
+        }
+    }
+
+    HAL_FLASH_Lock();
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+/**
+ * Erase data on flash.
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+int stm32_flash_erase(long offset, size_t size)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint32_t addr = STM32_FLASH_START_ADRESS + offset;
+    rt_uint32_t FirstSector = 0, NbOfSectors = 0;
+    rt_uint32_t SECTORError = 0;
+
+    if ((addr + size) > STM32_FLASH_END_ADDRESS)
+    {
+        LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void*)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    /*Variable used for Erase procedure*/
+    FLASH_EraseInitTypeDef EraseInitStruct;
+
+    /* Unlock the Flash to enable the flash control register access */
+    HAL_FLASH_Unlock();
+
+    /* Get the 1st sector to erase */
+    FirstSector = GetSector(addr);
+    /* Get the number of sector to erase from 1st sector*/
+    NbOfSectors = GetSector(addr + size) - FirstSector + 1;
+    /* Fill EraseInit structure*/
+    EraseInitStruct.TypeErase     = FLASH_TYPEERASE_SECTORS;
+    EraseInitStruct.VoltageRange  = FLASH_VOLTAGE_RANGE_3;
+    EraseInitStruct.Sector        = FirstSector;
+    EraseInitStruct.NbSectors     = NbOfSectors;
+
+    if (HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError) != HAL_OK)
+    {
+        result = -RT_ERROR;
+        goto __exit;
+    }
+
+__exit:
+    HAL_FLASH_Lock();
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    LOG_D("erase done: addr (0x%p), size %d", (void*)addr, size);
+    return result;
+}
+
+#if defined(PKG_USING_FAL)
+const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, (128 * 1024), {NULL, stm32_flash_read, stm32_flash_write, stm32_flash_erase} };
+#endif
+#endif /* BSP_USING_ON_CHIP_FLASH */

bsp/stm32/libraries/HAL_Drivers/drv_qspi.c

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2018-11-27     zylx         change to new framework
+ * 2018-12-12     greedyhao    Porting for stm32f7xx
  */
 
 #include "board.h"
@@ -20,6 +21,14 @@
 
 #if defined(BSP_USING_QSPI)
 
+#if defined (SOC_SERIES_STM32L4)
+#define QUADSPI_DMA_IRQ                DMA1_Channel5_IRQn
+#define QUADSPI_DMA_IRQHandler         DMA1_Channel5_IRQHandler
+#elif defined (SOC_SERIES_STM32F7)
+#define QUADSPI_DMA_IRQ                DMA2_Stream2_IRQn
+#define QUADSPI_DMA_IRQHandler         DMA2_Stream2_IRQHandler
+#endif /*   SOC_SERIES_STM32L4  */
+
 struct stm32_hw_spi_cs
 {
     uint16_t Pin;
@@ -97,14 +106,19 @@ static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configu
     /* QSPI interrupts must be enabled when using the HAL_QSPI_Receive_DMA */
     HAL_NVIC_SetPriority(QUADSPI_IRQn, 0, 0);
     HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
-    HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 0, 0);
-    HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);
+    HAL_NVIC_SetPriority(QUADSPI_DMA_IRQ, 0, 0);
+    HAL_NVIC_EnableIRQ(QUADSPI_DMA_IRQ);
 
-    /* init QSPI DMA */
-     __HAL_RCC_DMA1_CLK_ENABLE();
+    /* init QSPI DMA */ 
+    __HAL_RCC_DMA1_CLK_ENABLE();
     HAL_DMA_DeInit(qspi_bus->QSPI_Handler.hdma);
+#if defined(SOC_SERIES_STM32F4)
     qspi_bus->hdma_quadspi.Instance = DMA1_Channel5;
     qspi_bus->hdma_quadspi.Init.Request = DMA_REQUEST_5;
+#elif defined(SOC_SERIES_STM32F7)
+    qspi_bus->hdma_quadspi.Instance = DMA2_Stream2;
+    qspi_bus->hdma_quadspi.Init.channel = DMA_CHANNEL_11;
+#endif
     qspi_bus->hdma_quadspi.Init.Direction = DMA_PERIPH_TO_MEMORY;
     qspi_bus->hdma_quadspi.Init.PeriphInc = DMA_PINC_DISABLE;
     qspi_bus->hdma_quadspi.Init.MemInc = DMA_MINC_ENABLE;
@@ -377,7 +391,7 @@ void QUADSPI_IRQHandler(void)
     rt_interrupt_leave();
 }
 
-void DMA1_Channel5_IRQHandler(void)
+void QUADSPI_DMA_IRQHandler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();

bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.c

@@ -18,7 +18,7 @@
 #define LOG_TAG              "drv.i2c"
 #include <drv_log.h>
 
-#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3)
+#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4) 
 #error "Please define at least one BSP_USING_I2Cx"
 /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
 #endif
@@ -34,6 +34,9 @@ static const struct stm32_soft_i2c_config soft_i2c_config[] =
 #ifdef BSP_USING_I2C3
     I2C3_BUS_CONFIG,
 #endif
+#ifdef BSP_USING_I2C4
+    I2C4_BUS_CONFIG,
+#endif
 };
 
 static struct stm32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];

bsp/stm32/libraries/HAL_Drivers/drv_soft_i2c.h

@@ -56,6 +56,15 @@ struct stm32_i2c
     }
 #endif
 
+#ifdef BSP_USING_I2C4
+#define I2C4_BUS_CONFIG                                  \
+    {                                                    \
+        .scl = BSP_I2C4_SCL_PIN,                         \
+        .sda = BSP_I2C4_SDA_PIN,                         \
+        .bus_name = "i2c4",                              \
+    }
+#endif
+
 int rt_hw_i2c_init(void);
 
 #endif

bsp/stm32/libraries/HAL_Drivers/drv_spi.c

@@ -6,13 +6,14 @@
  * Change Logs:
  * Date           Author       Notes
  * 2018-11-5      SummerGift   change to new framework
+ * 2018-12-11     greedyhao    Porting for stm32f7xx
  */
 
 #include "board.h"
 
 #ifdef RT_USING_SPI
 
-#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) 
+#if defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) || defined(BSP_USING_SPI4) || defined(BSP_USING_SPI5) || defined(BSP_USING_SPI6) 
 /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
 
 #include "drv_spi.h"
@@ -39,6 +40,9 @@ enum
 #ifdef BSP_USING_SPI5
     SPI5_INDEX,
 #endif
+#ifdef BSP_USING_SPI6
+    SPI6_INDEX,
+#endif
 };
 
 static struct stm32_spi_config spi_config[] =
@@ -62,6 +66,10 @@ static struct stm32_spi_config spi_config[] =
 #ifdef BSP_USING_SPI5
     SPI5_BUS_CONFIG,
 #endif
+
+#ifdef BSP_USING_SPI6
+    SPI6_BUS_CONFIG,
+#endif
 };
 
 static struct stm32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])];
@@ -194,7 +202,7 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
         return RT_EIO;
     }
 
-#if defined(SOC_SERIES_STM32L4)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7)
     SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
 #endif
 
@@ -220,7 +228,7 @@ static void spi_dma_transfer_prepare(struct rt_spi_bus * spi_bus, struct rt_spi_
      * Check if the DMA Stream is disabled before enabling it.
      * Note that this step is useful when the same Stream is used multiple times.
      */
-#if defined(SOC_SERIES_STM32F4)
+#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
     while (hdma_tx->Instance->CR & DMA_SxCR_EN);
     while (hdma_rx->Instance->CR & DMA_SxCR_EN);
 #endif
@@ -348,7 +356,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
                 *(volatile rt_uint8_t *)(&spi_handle->Instance->DR) = data;
 
                 /* receive data once */
-#if defined(SOC_SERIES_STM32L4)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7)
                 SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
 #endif
                 while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_RXNE) == RESET);
@@ -379,7 +387,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
                 *(volatile rt_uint16_t *)(&spi_handle->Instance->DR) = data;
 
                 /* receive data once */
-#if defined(SOC_SERIES_STM32L4)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7)
                 SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
 #endif
                 while (__HAL_SPI_GET_FLAG(spi_handle, SPI_FLAG_RXNE) == RESET);
@@ -434,7 +442,7 @@ static int rt_hw_spi_bus_init(void)
 #ifdef BSP_SPI_USING_DMA
         /* Configure the DMA handler for Transmission process */
         spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx.Instance;
-#if defined(SOC_SERIES_STM32F4)
+#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
         spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx.channel;
 #elif defined(SOC_SERIES_STM32L4)
         spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx.request;
@@ -445,7 +453,7 @@ static int rt_hw_spi_bus_init(void)
         spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
         spi_bus_obj[i].dma.handle_tx.Init.Mode                = DMA_NORMAL;
         spi_bus_obj[i].dma.handle_tx.Init.Priority            = DMA_PRIORITY_LOW;
-#if defined(SOC_SERIES_STM32F4)
+#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
         spi_bus_obj[i].dma.handle_tx.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
         spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
         spi_bus_obj[i].dma.handle_tx.Init.MemBurst            = DMA_MBURST_INC4;
@@ -453,7 +461,7 @@ static int rt_hw_spi_bus_init(void)
 #endif
 
         spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx.Instance;
-#if defined(SOC_SERIES_STM32F4)
+#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
         spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx.channel;
 #elif defined(SOC_SERIES_STM32L4)
         spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx.request;
@@ -464,7 +472,7 @@ static int rt_hw_spi_bus_init(void)
         spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
         spi_bus_obj[i].dma.handle_rx.Init.Mode                = DMA_NORMAL;
         spi_bus_obj[i].dma.handle_rx.Init.Priority            = DMA_PRIORITY_HIGH;
-#if defined(SOC_SERIES_STM32F4)
+#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
         spi_bus_obj[i].dma.handle_rx.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
         spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
         spi_bus_obj[i].dma.handle_rx.Init.MemBurst            = DMA_MBURST_INC4;
@@ -476,7 +484,7 @@ static int rt_hw_spi_bus_init(void)
             /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
             SET_BIT(RCC->AHBENR, spi_config[i].dma_rx.dma_rcc);
             tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx.dma_rcc);
-#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
+#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4) 
             SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx.dma_rcc);
             /* Delay after an RCC peripheral clock enabling */
             tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx.dma_rcc);
@@ -709,6 +717,40 @@ void SPI5_DMA_TX_IRQHandler(void)
 }
 #endif /* defined(BSP_USING_SPI5) && defined(BSP_SPI_USING_DMA) */
 
+#if defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA)
+/**
+  * @brief  This function handles DMA Rx interrupt request.
+  * @param  None
+  * @retval None
+  */
+void SPI6_DMA_RX_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    HAL_DMA_IRQHandler(&spi_bus_obj[SPI6_INDEX].dma.handle_rx);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+  * @brief  This function handles DMA Tx interrupt request.
+  * @param  None
+  * @retval None
+  */
+void SPI6_DMA_TX_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    HAL_DMA_IRQHandler(&spi_bus_obj[SPI6_INDEX].dma.handle_tx);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* defined(BSP_USING_SPI6) && defined(BSP_SPI_USING_DMA) */
+
 int rt_hw_spi_init(void)
 {
     return rt_hw_spi_bus_init();

bsp/stm32/libraries/HAL_Drivers/drv_usart.c

@@ -23,6 +23,12 @@
 /* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
 #endif
 
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4)
+#define UART_INSTANCE_CLEAR_FUNCTION    __HAL_UART_CLEAR_FLAG
+#elif defined(SOC_SERIES_STM32F7)
+#define UART_INSTANCE_CLEAR_FUNCTION    __HAL_UART_CLEAR_IT
+#endif
+
 #ifdef BSP_UART_USING_DMA_RX
 static void stm32_dma_config(struct rt_serial_device *serial);
 #endif
@@ -174,8 +180,8 @@ static int stm32_putc(struct rt_serial_device *serial, char c)
     RT_ASSERT(serial != RT_NULL);
 
     uart = (struct stm32_uart *)serial->parent.user_data;
-    __HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_TC);
-#if defined(SOC_SERIES_STM32L4)
+    UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7)
     uart->handle.Instance->TDR = c;
 #else
     uart->handle.Instance->DR = c;
@@ -195,7 +201,7 @@ static int stm32_getc(struct rt_serial_device *serial)
     ch = -1;
     if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
     {
-#if defined(SOC_SERIES_STM32L4)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7)
         ch = uart->handle.Instance->RDR & 0xff;
 #else
         ch = uart->handle.Instance->DR & 0xff;
@@ -236,7 +242,7 @@ static void uart_isr(struct rt_serial_device *serial)
     {
         rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
         /* Clear RXNE interrupt flag */
-        __HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_RXNE);
+        UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
     }
 #ifdef BSP_UART_USING_DMA_RX
     else if ((__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET) &&
@@ -253,9 +259,9 @@ static void uart_isr(struct rt_serial_device *serial)
             rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
         }
 
-        __HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_IDLE);
+        UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_IDLE);
         rt_uint32_t ch;
-#if defined(SOC_SERIES_STM32L4)
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7)
         ch = uart->handle.Instance->RDR;
 #else
         ch = uart->handle.Instance->DR;
@@ -267,46 +273,81 @@ static void uart_isr(struct rt_serial_device *serial)
     {
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ORE) != RESET)
         {
-            __HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_ORE);
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_ORE);
         }
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_NE) != RESET)
         {
-            __HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_NE);
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_NE);
         }
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_FE) != RESET)
         {
-            __HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_FE);
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_FE);
         }
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_PE) != RESET)
         {
-            __HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_PE);
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_PE);
         }
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTS) != RESET)
         {
-            __HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_CTS);
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTS);
         }
-#if !defined(SOC_SERIES_STM32L4)
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4)
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
         {
-            __HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_LBD);
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
+        }
+#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
+        if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBDF) != RESET)
+        {
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBDF);
         }
 #endif
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TXE) != RESET)
         {
-            __HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_TXE);
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TXE);
         }
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TC) != RESET)
         {
-            __HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_TC);
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
         }
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
         {
-            __HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_RXNE);
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_RXNE);
         }
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_IDLE) != RESET)
         {
-            __HAL_UART_CLEAR_FLAG(&(uart->handle), UART_FLAG_IDLE);
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_IDLE);
+        }
+#if defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
+        if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_TEACK) != RESET)
+        {
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TEACK);
+        }
+        if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_SBKF) != RESET)
+        {
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_SBKF);
+        }
+        if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CMF) != RESET)
+        {
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CMF);
+        }
+        if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_BUSY) != RESET)
+        {
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_BUSY);
+        }
+        if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ABRF) != RESET)
+        {
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_ABRF);
+        }
+        if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_ABRE) != RESET)
+        {
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_ABRE);
+        }
+        if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_CTSIF) != RESET)
+        {
+            UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_CTSIF);
         }
+#endif         
     }
 }
 
@@ -451,7 +492,7 @@ static void stm32_dma_config(struct rt_serial_device *serial)
         /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
         SET_BIT(RCC->AHBENR, uart->config->dma_rcc);
         tmpreg = READ_BIT(RCC->AHBENR, uart->config->dma_rcc);
-#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
+#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
         /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
         SET_BIT(RCC->AHB1ENR, uart->config->dma_rcc);
         tmpreg = READ_BIT(RCC->AHB1ENR, uart->config->dma_rcc);
@@ -463,7 +504,7 @@ static void stm32_dma_config(struct rt_serial_device *serial)
 
 #if defined(SOC_SERIES_STM32F1) 
     uart->dma.handle.Instance                 = uart->config->dma.Instance;
-#elif defined(SOC_SERIES_STM32F4)
+#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
     uart->dma.handle.Instance                 = uart->config->dma.Instance;
     uart->dma.handle.Init.Channel             = uart->config->dma.stream_channel.channel;
 #elif defined(SOC_SERIES_STM32L4) 
@@ -477,7 +518,7 @@ static void stm32_dma_config(struct rt_serial_device *serial)
     uart->dma.handle.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
     uart->dma.handle.Init.Mode                = DMA_CIRCULAR;
     uart->dma.handle.Init.Priority            = DMA_PRIORITY_MEDIUM;
-#if defined(SOC_SERIES_STM32F4)  
+#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
     uart->dma.handle.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
 #endif
     if (HAL_DMA_DeInit(&(uart->dma.handle)) != HAL_OK)

bsp/stm32/libraries/HAL_Drivers/drv_usart.h

@@ -20,7 +20,7 @@ int rt_hw_usart_init(void);
 
 #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
 #define DMA_INSTANCE_TYPE              DMA_Channel_TypeDef
-#elif defined(SOC_SERIES_STM32F4)
+#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
 #define DMA_INSTANCE_TYPE              DMA_Stream_TypeDef
 #endif /*  defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) */
 
@@ -41,7 +41,7 @@ struct stm32_uart_config
         } channel;
 #endif
 
-#if defined(SOC_SERIES_STM32F4)
+#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
         /* the DMA config has stream and channel, such as on STM32F4xx */
         struct {
             DMA_INSTANCE_TYPE *Instance;

bsp/stm32/libraries/Kconfig

@@ -11,6 +11,11 @@ config SOC_SERIES_STM32F4
     select ARCH_ARM_CORTEX_M4
     select SOC_FAMILY_STM32
 
+config SOC_SERIES_STM32F7
+    bool
+    select ARCH_ARM_CORTEX_M7
+    select SOC_FAMILY_STM32
+
 config SOC_SERIES_STM32L4
     bool
     select ARCH_ARM_CORTEX_M4

bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h

+/**
+  ******************************************************************************
+  * @file    stm32f7xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32F7xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32F7xx device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e.
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f7xx
+  * @{
+  */
+
+#ifndef __STM32F7xx_H
+#define __STM32F7xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined  (STM32F7)
+#define STM32F7
+#endif /* STM32F7 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+   application
+  */
+#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
+    !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
+	!defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx)
+  /* #define STM32F756xx */   /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
+                                   STM32F756NG Devices */
+  /* #define STM32F746xx */   /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
+                                   STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */
+  /* #define STM32F745xx */   /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */
+  /* #define STM32F765xx */   /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,
+                                   STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */
+  /* #define STM32F767xx */   /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
+                                   STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */
+  /* #define STM32F769xx */   /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
+                                   STM32F769NG, STM32F769NI, STM32F768AI Devices */
+  /* #define STM32F777xx */   /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */
+  /* #define STM32F779xx */   /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */
+  /* #define STM32F722xx */   /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,
+                                   STM32F722VC, STM32F722RC Devices */
+  /* #define STM32F723xx */   /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */
+  /* #define STM32F732xx */   /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */
+  /* #define STM32F733xx */   /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.2.2
+  */
+#define __STM32F7_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32F7_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
+#define __STM32F7_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
+#define __STM32F7_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32F7_CMSIS_VERSION        ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32F7_CMSIS_VERSION))
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+#if defined(STM32F722xx)
+  #include "stm32f722xx.h"
+#elif defined(STM32F723xx)
+  #include "stm32f723xx.h"
+#elif defined(STM32F732xx)
+  #include "stm32f732xx.h"
+#elif defined(STM32F733xx)
+  #include "stm32f733xx.h"
+#elif defined(STM32F756xx)
+  #include "stm32f756xx.h"
+#elif defined(STM32F746xx)
+  #include "stm32f746xx.h"
+#elif defined(STM32F745xx)
+  #include "stm32f745xx.h"
+#elif defined(STM32F765xx)
+  #include "stm32f765xx.h"
+#elif defined(STM32F767xx)
+  #include "stm32f767xx.h"
+#elif defined(STM32F769xx)
+  #include "stm32f769xx.h"
+#elif defined(STM32F777xx)
+  #include "stm32f777xx.h"
+#elif defined(STM32F779xx)
+  #include "stm32f779xx.h"
+#else
+ #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0U,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0U,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0U,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+/**
+  * @}
+  */
+
+#ifdef USE_HAL_DRIVER
+ #include "stm32f7xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F7xx_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h

+/**
+  ******************************************************************************
+  * @file    system_stm32f7xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.       
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f7xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F7XX_H
+#define __SYSTEM_STM32F7XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F7xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F7xx_System_Exported_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+    */
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F7XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/linker/stm32f722xx_ITCM_flash.icf

+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00200000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__     = 0x00200000;
+define symbol __ICFEDIT_region_ROM_end__       = 0x0027FFFF;
+define symbol __ICFEDIT_region_RAM_start__     = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__       = 0x2003FFFF;
+define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ITCMRAM_end__   = 0x00003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region ITCMRAM_region  = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+place in ITCMRAM_region { };						
\ No newline at end of file