[bsp] Add MB9BF618 porting.

bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S

+;/************************************************************************/
+;/*               (C) Fujitsu Semiconductor Europe GmbH                  */
+;/*                                                                      */
+;/* The following software deliverable is intended for and must only be  */
+;/* used for reference and in an evaluation laboratory environment.      */
+;/* It is provided on an as-is basis without charge and is subject to    */
+;/* alterations.                                                         */
+;/* It is the user’s obligation to fully test the software in its        */
+;/* environment and to ensure proper functionality, qualification and    */
+;/* compliance with component specifications.                            */
+;/*                                                                      */
+;/* In the event the software deliverable includes the use of open       */
+;/* source components, the provisions of the governing open source       */
+;/* license agreement shall apply with respect to such software          */
+;/* deliverable.                                                         */
+;/* FSEU does not warrant that the deliverables do not infringe any      */
+;/* third party intellectual property right (IPR). In the event that     */
+;/* the deliverables infringe a third party IPR it is the sole           */
+;/* responsibility of the customer to obtain necessary licenses to       */
+;/* continue the usage of the deliverable.                               */
+;/*                                                                      */
+;/* To the maximum extent permitted by applicable law FSEU disclaims all */
+;/* warranties, whether express or implied, in particular, but not       */
+;/* limited to, warranties of merchantability and fitness for a          */
+;/* particular purpose for which the deliverable is not designated.      */
+;/*                                                                      */
+;/* To the maximum extent permitted by applicable law, FSEU's liability  */
+;/* is restricted to intention and gross negligence.                     */
+;/* FSEU is not liable for consequential damages.                        */
+;/*                                                                      */
+;/* (V1.4)                                                               */
+;/************************************************************************/
+;/*  Startup for ARM                                                     */
+;/*  Version     V1.02                                                   */
+;/*  Date        2011-07-25                                              */
+;/*  Target-mcu  MB9B61x                                                 */
+;/************************************************************************/
+
+; Stack Configuration
+;  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+;  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                DCD     CSV_Handler               ; 0: Clock Super Visor
+                DCD     SWDT_Handler              ; 1: Software Watchdog Timer
+                DCD     LVD_Handler               ; 2: Low Voltage Detector
+                DCD     MFT_WG_IRQHandler         ; 3: Wave Form Generator / DTIF
+                DCD     INT0_7_Handler            ; 4: External Interrupt Request ch.0 to ch.7
+                DCD     INT8_31_Handler           ; 5: External Interrupt Request ch.8 to ch.31
+                DCD     DT_Handler                ; 6: Dual Timer / Quad Decoder
+                DCD     MFS0RX_IRQHandler         ; 7: MultiFunction Serial ch.0
+                DCD     MFS0TX_IRQHandler         ; 8: MultiFunction Serial ch.0
+                DCD     MFS1RX_IRQHandler         ; 9: MultiFunction Serial ch.1
+                DCD     MFS1TX_IRQHandler         ; 10: MultiFunction Serial ch.1
+                DCD     MFS2RX_IRQHandler         ; 11: MultiFunction Serial ch.2
+                DCD     MFS2TX_IRQHandler         ; 12: MultiFunction Serial ch.2
+                DCD     MFS3RX_IRQHandler         ; 13: MultiFunction Serial ch.3
+                DCD     MFS3TX_IRQHandler         ; 14: MultiFunction Serial ch.3
+                DCD     MFS4RX_IRQHandler         ; 15: MultiFunction Serial ch.4
+                DCD     MFS4TX_IRQHandler         ; 16: MultiFunction Serial ch.4
+                DCD     MFS5RX_IRQHandler         ; 17: MultiFunction Serial ch.5
+                DCD     MFS5TX_IRQHandler         ; 18: MultiFunction Serial ch.5
+                DCD     MFS6RX_IRQHandler         ; 19: MultiFunction Serial ch.6
+                DCD     MFS6TX_IRQHandler         ; 20: MultiFunction Serial ch.6
+                DCD     MFS7RX_IRQHandler         ; 21: MultiFunction Serial ch.7
+                DCD     MFS7TX_IRQHandler         ; 22: MultiFunction Serial ch.7
+                DCD     PPG_Handler               ; 23: PPG
+                DCD     TIM_IRQHandler            ; 24: OSC / PLL / Watch Counter
+                DCD     ADC0_IRQHandler           ; 25: ADC0
+                DCD     ADC1_IRQHandler           ; 26: ADC1
+                DCD     ADC2_IRQHandler           ; 27: ADC2
+                DCD     MFT_FRT_IRQHandler        ; 28: Free-run Timer
+                DCD     MFT_IPC_IRQHandler        ; 29: Input Capture
+                DCD     MFT_OPC_IRQHandler        ; 30: Output Compare
+                DCD     BT0_7_IRQHandler          ; 31: Base Timer ch.0 to ch.7
+                DCD     ETHER_MAC0_IRQHandler     ; 32: Ethernet MAC ch.0
+                DCD     ETHER_MAC1_IRQHandler     ; 33: Ethernet MAC ch.1
+                DCD     USB0F_Handler             ; 34: USB0 Function
+                DCD     USB0_Handler              ; 35: USB0 Function / USB0 HOST
+                DCD     USB1F_Handler             ; 36: USB1 Function
+                DCD     USB1_Handler              ; 37: USB1 Function / USB1 HOST
+                DCD     DMAC0_Handler             ; 38: DMAC ch.0
+                DCD     DMAC1_Handler             ; 39: DMAC ch.1
+                DCD     DMAC2_Handler             ; 40: DMAC ch.2
+                DCD     DMAC3_Handler             ; 41: DMAC ch.3
+                DCD     DMAC4_Handler             ; 42: DMAC ch.4
+                DCD     DMAC5_Handler             ; 43: DMAC ch.5
+                DCD     DMAC6_Handler             ; 44: DMAC ch.6
+                DCD     DMAC7_Handler             ; 45: DMAC ch.7
+                DCD     BT8_15_IRQHandler         ; 46: Base Timer ch.8 to ch.15
+                DCD     DummyHandler              ; 47: Reserved
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  CSV_Handler	          [WEAK]
+                EXPORT  SWDT_Handler              [WEAK]
+                EXPORT  LVD_Handler               [WEAK]
+                EXPORT  MFT_WG_IRQHandler         [WEAK]
+                EXPORT  INT0_7_Handler            [WEAK]
+                EXPORT  INT8_31_Handler           [WEAK]
+                EXPORT  DT_Handler                [WEAK]
+                EXPORT  MFS0RX_IRQHandler         [WEAK]
+                EXPORT  MFS0TX_IRQHandler         [WEAK]
+                EXPORT  MFS1RX_IRQHandler         [WEAK]
+                EXPORT  MFS1TX_IRQHandler         [WEAK]
+                EXPORT  MFS2RX_IRQHandler         [WEAK]
+                EXPORT  MFS2TX_IRQHandler         [WEAK]
+                EXPORT  MFS3RX_IRQHandler         [WEAK]
+                EXPORT  MFS3TX_IRQHandler         [WEAK]
+                EXPORT  MFS4RX_IRQHandler         [WEAK]
+                EXPORT  MFS4TX_IRQHandler         [WEAK]
+                EXPORT  MFS5RX_IRQHandler         [WEAK]
+                EXPORT  MFS5TX_IRQHandler         [WEAK]
+                EXPORT  MFS6RX_IRQHandler         [WEAK]
+                EXPORT  MFS6TX_IRQHandler         [WEAK]
+                EXPORT  MFS7RX_IRQHandler         [WEAK]
+                EXPORT  MFS7TX_IRQHandler         [WEAK]
+                EXPORT  PPG_Handler               [WEAK]
+                EXPORT  TIM_IRQHandler            [WEAK]
+                EXPORT  ADC0_IRQHandler           [WEAK]
+                EXPORT  ADC1_IRQHandler           [WEAK]
+                EXPORT  ADC2_IRQHandler           [WEAK]
+                EXPORT  MFT_FRT_IRQHandler        [WEAK]
+                EXPORT  MFT_IPC_IRQHandler        [WEAK]
+                EXPORT  MFT_OPC_IRQHandler        [WEAK]
+                EXPORT  BT0_7_IRQHandler          [WEAK]
+                EXPORT  ETHER_MAC0_IRQHandler     [WEAK]
+                EXPORT  ETHER_MAC1_IRQHandler     [WEAK]
+                EXPORT  USB0F_Handler             [WEAK]
+                EXPORT  USB0_Handler              [WEAK]
+                EXPORT  USB1F_Handler             [WEAK]
+                EXPORT  USB1_Handler              [WEAK]
+                EXPORT  DMAC0_Handler             [WEAK]
+                EXPORT  DMAC1_Handler             [WEAK]
+                EXPORT  DMAC2_Handler             [WEAK]
+                EXPORT  DMAC3_Handler             [WEAK]
+                EXPORT  DMAC4_Handler             [WEAK]
+                EXPORT  DMAC5_Handler             [WEAK]
+                EXPORT  DMAC6_Handler             [WEAK]
+                EXPORT  DMAC7_Handler             [WEAK]
+                EXPORT  BT8_15_IRQHandler         [WEAK]
+                EXPORT  DummyHandler              [WEAK]
+
+CSV_Handler
+SWDT_Handler
+LVD_Handler
+MFT_WG_IRQHandler
+INT0_7_Handler
+INT8_31_Handler
+DT_Handler
+MFS0RX_IRQHandler
+MFS0TX_IRQHandler
+MFS1RX_IRQHandler
+MFS1TX_IRQHandler
+MFS2RX_IRQHandler
+MFS2TX_IRQHandler
+MFS3RX_IRQHandler
+MFS3TX_IRQHandler
+MFS4RX_IRQHandler
+MFS4TX_IRQHandler
+MFS5RX_IRQHandler
+MFS5TX_IRQHandler
+MFS6RX_IRQHandler
+MFS6TX_IRQHandler
+MFS7RX_IRQHandler
+MFS7TX_IRQHandler
+PPG_Handler
+TIM_IRQHandler
+ADC0_IRQHandler
+ADC1_IRQHandler
+ADC2_IRQHandler
+MFT_FRT_IRQHandler
+MFT_IPC_IRQHandler
+MFT_OPC_IRQHandler
+BT0_7_IRQHandler
+DMAC0_Handler
+DMAC1_Handler
+DMAC2_Handler
+DMAC3_Handler
+DMAC4_Handler
+DMAC5_Handler
+DMAC6_Handler
+DMAC7_Handler
+ETHER_MAC0_IRQHandler
+ETHER_MAC1_IRQHandler
+USB0F_Handler
+USB0_Handler
+USB1F_Handler
+USB1_Handler
+BT8_15_IRQHandler
+DummyHandler
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END

bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c

+/*
+ ****************************************************************************
+**
+**  File        : startup_mb9bf61x.c
+**
+**  Abstract    : This file contains interrupt vector and startup code.
+**
+**  Functions   : Reset_Handler
+**
+**  Target      : Fujitsu FM3 microcontrollers
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed as is, without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+ ****************************************************************************
+*/
+
+/**
+**===========================================================================
+**  Revisions
+**===========================================================================
+**       Date        Modification
+**       2011-08-18  First issue.
+**===========================================================================
+*/
+
+/**
+**===========================================================================
+**  External declarations
+**===========================================================================
+*/
+extern unsigned long _sdata, _edata, _sidata, _sbss, _ebss, _isr_vector;
+extern unsigned long _estack;
+extern void __libc_init_array();
+extern void SystemInit();
+extern void main();
+
+/**
+**===========================================================================
+**  Default interrupt handler
+**===========================================================================
+*/
+void Default_Handler()
+{
+	/* Hang here */
+	while(1)
+	{
+	}
+}
+
+/**
+**===========================================================================
+**  Reset handler
+**===========================================================================
+*/
+__attribute__((naked)) void Reset_Handler()
+{
+	/* Data and BSS variables */
+	unsigned long *srcdata, *dstdata, *sbss;
+
+	/* Set up the stack pointer */
+	asm("ldr sp,=_estack\n\t");
+
+    /* Set up vector table offset register */
+	dstdata = (unsigned long *)0xe000ed08;
+	*dstdata = (unsigned long)&_isr_vector;
+
+	srcdata = &_sidata;
+	dstdata = &_sdata;
+	sbss = &_sbss;
+
+	/* Copy data */
+	while(dstdata != &_edata)
+	{
+		*(dstdata++) = *(srcdata++);
+	}
+
+	/* Clear BSS */
+	while(sbss != &_ebss)
+	{
+		*(sbss++) = '\0';
+	}
+
+	/* Run static constructors */
+	//__libc_init_array();
+
+	/* Call the clock system initialization function.*/
+	SystemInit();
+
+	/* Jump to main */
+	main();
+
+	/* In case main returns, use default handler */
+	Default_Handler();
+}
+
+/**
+**===========================================================================
+**  Weak definitions of handlers point to Default_Handler if not implemented
+**===========================================================================
+*/
+void NMI_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DebugMonitor_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler() __attribute__ ((weak, alias("Default_Handler")));
+
+void CSV_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void SWDT_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void LVD_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void MFT_WG_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void INT0_7_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void INT8_31_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DT_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS0RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS0TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS1RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS1TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS2RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS2TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS3RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS3TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS4RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS4TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS5RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS5TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS6RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS6TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS7RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS7TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void PPG_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void TIM_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ADC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ADC1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ADC2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFT_FRT_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFT_IPC_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFT_OPC_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void BT0_7_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ETHER_MAC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ETHER_MAC1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void USB0F_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void USB0_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void USB1F_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void USB1_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC0_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC1_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC2_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC3_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC4_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC5_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC6_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC7_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void BT8_15_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+
+
+/**
+**===========================================================================
+**  Interrupt Vector Table
+**===========================================================================
+*/
+void (* const InterruptVector[])() __attribute__ ((section(".isr_vector"))) = {
+		/* Processor exceptions */
+		(void (*)(void))&_estack, /* 0 - Stack pointer */
+		Reset_Handler,            /* 1 - Reset */
+		NMI_Handler,              /* 2 - NMI  */
+		HardFault_Handler,        /* 3 - Hard fault */
+		MemManage_Handler,        /* 4 - Memory management fault */
+		BusFault_Handler,         /* 5 - Bus fault */
+		UsageFault_Handler,       /* 6 - Usage fault */
+		0,                        /* 7 - Reserved */
+		0,                        /* 8 - Reserved */
+		0,                        /* 9 - Reserved */
+		0,                        /* 10 - Reserved */
+		SVC_Handler,              /* 11 - SVCall */
+		DebugMonitor_Handler,     /* 12 - Reserved for Debug */
+		0,                        /* 13 - Reserved */
+		PendSV_Handler,           /* 14 - PendSV */
+		SysTick_Handler,          /* 15 - Systick */
+
+		/* External Interrupts */
+		CSV_Handler,              /* 0: Clock Super Visor */
+		SWDT_Handler,             /* 1: Software Watchdog Timer */
+		LVD_Handler,              /* 2: Low Voltage Detector */
+		MFT_WG_IRQHandler,        /* 3: Wave Form Generator / DTIF */
+		INT0_7_Handler,           /* 4: External Interrupt Request ch.0 to ch.7 */
+		INT8_31_Handler,          /* 5: External Interrupt Request ch.8 to ch.31 */
+		DT_Handler,               /* 6: Dual Timer / Quad Decoder */
+		MFS0RX_IRQHandler,        /* 7: MultiFunction Serial ch.0 */
+		MFS0TX_IRQHandler,        /* 8: MultiFunction Serial ch.0 */
+		MFS1RX_IRQHandler,        /* 9: MultiFunction Serial ch.1 */
+		MFS1TX_IRQHandler,        /* 10: MultiFunction Serial ch.1 */
+		MFS2RX_IRQHandler,        /* 11: MultiFunction Serial ch.2 */
+		MFS2TX_IRQHandler,        /* 12: MultiFunction Serial ch.2 */
+		MFS3RX_IRQHandler,        /* 13: MultiFunction Serial ch.3 */
+		MFS3TX_IRQHandler,        /* 14: MultiFunction Serial ch.3 */
+		MFS4RX_IRQHandler,        /* 15: MultiFunction Serial ch.4 */
+		MFS4TX_IRQHandler,        /* 16: MultiFunction Serial ch.4 */
+		MFS5RX_IRQHandler,        /* 17: MultiFunction Serial ch.5 */
+		MFS5TX_IRQHandler,        /* 18: MultiFunction Serial ch.5 */
+		MFS6RX_IRQHandler,        /* 19: MultiFunction Serial ch.6 */
+		MFS6TX_IRQHandler,        /* 20: MultiFunction Serial ch.6 */
+		MFS7RX_IRQHandler,        /* 21: MultiFunction Serial ch.7 */
+		MFS7TX_IRQHandler,        /* 22: MultiFunction Serial ch.7 */
+		PPG_Handler,              /* 23: PPG */
+		TIM_IRQHandler,           /* 24: OSC / PLL / Watch Counter */
+		ADC0_IRQHandler,          /* 25: ADC0 */
+		ADC1_IRQHandler,          /* 26: ADC1 */
+		ADC2_IRQHandler,          /* 27: ADC2 */
+		MFT_FRT_IRQHandler,       /* 28: Free-run Timer */
+		MFT_IPC_IRQHandler,       /* 29: Input Capture */
+		MFT_OPC_IRQHandler,       /* 30: Output Compare */
+		BT0_7_IRQHandler,         /* 31: Base Timer ch.0 to ch.7 */
+		ETHER_MAC0_IRQHandler,    /* 32: Ethernet MAC ch.0 */
+		ETHER_MAC1_IRQHandler,    /* 33: Ethernet MAC ch.1 */
+		USB0F_Handler,            /* 34: USB0 Function */
+		USB0_Handler,             /* 35: USB0 Function / USB0 HOST */
+		USB1F_Handler,            /* 36: USB1 Function */
+		USB1_Handler,             /* 37: USB1 Function / USB1 HOST */
+		DMAC0_Handler,            /* 38: DMAC ch.0 */
+		DMAC1_Handler,            /* 39: DMAC ch.1 */
+		DMAC2_Handler,            /* 40: DMAC ch.2 */
+		DMAC3_Handler,            /* 41: DMAC ch.3 */
+		DMAC4_Handler,            /* 42: DMAC ch.4 */
+		DMAC5_Handler,            /* 43: DMAC ch.5 */
+		DMAC6_Handler,            /* 44: DMAC ch.6 */
+		DMAC7_Handler,            /* 45: DMAC ch.7 */
+		BT8_15_IRQHandler,        /* 46: Base Timer ch.8 to ch.15 */
+		Default_Handler           /* 47: Reserved */
+};

bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S

+;/************************************************************************/
+;/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */
+;/*                                                                      */
+;/* The following software deliverable is intended for and must only be  */
+;/* used for reference and in an evaluation laboratory environment.      */
+;/* It is provided on an as-is basis without charge and is subject to    */
+;/* alterations.                                                         */
+;/* It is the user's obligation to fully test the software in its        */
+;/* environment and to ensure proper functionality, qualification and    */
+;/* compliance with component specifications.                            */
+;/*                                                                      */
+;/* In the event the software deliverable includes the use of open       */
+;/* source components, the provisions of the governing open source       */
+;/* license agreement shall apply with respect to such software          */
+;/* deliverable.                                                         */
+;/* FSEU does not warrant that the deliverables do not infringe any      */
+;/* third party intellectual property right (IPR). In the event that     */
+;/* the deliverables infringe a third party IPR it is the sole           */
+;/* responsibility of the customer to obtain necessary licenses to       */
+;/* continue the usage of the deliverable.                               */
+;/*                                                                      */
+;/* To the maximum extent permitted by applicable law FSEU disclaims all */
+;/* warranties, whether express or implied, in particular, but not       */
+;/* limited to, warranties of merchantability and fitness for a          */
+;/* particular purpose for which the deliverable is not designated.      */
+;/*                                                                      */
+;/* To the maximum extent permitted by applicable law, FSEU's liability  */
+;/* is restricted to intentional misconduct and gross negligence.        */
+;/* FSEU is not liable for consequential damages.                        */
+;/*                                                                      */
+;/* (V1.5)                                                               */
+;/************************************************************************/
+;/*  Startup for IAR                                                     */
+;/*  Version     V1.00                                                   */
+;/*  Date        2011-07-25                                              */
+;/*  Target-mcu  MB9B610                                                 */
+;/************************************************************************/
+
+
+                MODULE  ?cstartup
+
+                ;; Forward declaration of sections.
+                SECTION CSTACK:DATA:NOROOT(3)
+
+                SECTION .intvec:CODE:NOROOT(2)
+
+                EXTERN  __iar_program_start
+                EXTERN  SystemInit
+                PUBLIC  __vector_table
+
+                DATA
+__vector_table  DCD     sfe(CSTACK)               ; Top of Stack
+		        DCD     Reset_Handler             ; Reset
+                DCD     NMI_Handler               ; NMI
+                DCD     HardFault_Handler         ; Hard Fault
+                DCD     MemManage_Handler         ; MPU Fault
+                DCD     BusFault_Handler          ; Bus Fault
+                DCD     UsageFault_Handler        ; Usage Fault
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall
+                DCD     DebugMon_Handler          ; Debug Monitor
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV
+                DCD     SysTick_Handler           ; SysTick
+
+                DCD     CSV_Handler               ; 0: Clock Super Visor
+                DCD     SWDT_Handler              ; 1: Software Watchdog Timer
+                DCD     LVD_Handler               ; 2: Low Voltage Detector
+                DCD     MFT_WG_IRQHandler         ; 3: Wave Form Generator / DTIF
+                DCD     INT0_7_Handler            ; 4: External Interrupt Request ch.0 to ch.7
+                DCD     INT8_31_Handler           ; 5: External Interrupt Request ch.8 to ch.31
+                DCD     DT_Handler                ; 6: Dual Timer / Quad Decoder
+                DCD     MFS0RX_IRQHandler         ; 7: MultiFunction Serial ch.0
+                DCD     MFS0TX_IRQHandler         ; 8: MultiFunction Serial ch.0
+                DCD     MFS1RX_IRQHandler         ; 9: MultiFunction Serial ch.1
+                DCD     MFS1TX_IRQHandler         ; 10: MultiFunction Serial ch.1
+                DCD     MFS2RX_IRQHandler         ; 11: MultiFunction Serial ch.2
+                DCD     MFS2TX_IRQHandler         ; 12: MultiFunction Serial ch.2
+                DCD     MFS3RX_IRQHandler         ; 13: MultiFunction Serial ch.3
+                DCD     MFS3TX_IRQHandler         ; 14: MultiFunction Serial ch.3
+                DCD     MFS4RX_IRQHandler         ; 15: MultiFunction Serial ch.4
+                DCD     MFS4TX_IRQHandler         ; 16: MultiFunction Serial ch.4
+                DCD     MFS5RX_IRQHandler         ; 17: MultiFunction Serial ch.5
+                DCD     MFS5TX_IRQHandler         ; 18: MultiFunction Serial ch.5
+                DCD     MFS6RX_IRQHandler         ; 19: MultiFunction Serial ch.6
+                DCD     MFS6TX_IRQHandler         ; 20: MultiFunction Serial ch.6
+                DCD     MFS7RX_IRQHandler         ; 21: MultiFunction Serial ch.7
+                DCD     MFS7TX_IRQHandler         ; 22: MultiFunction Serial ch.7
+                DCD     PPG_Handler               ; 23: PPG
+                DCD     TIM_IRQHandler            ; 24: OSC / PLL / Watch Counter
+                DCD     ADC0_IRQHandler           ; 25: ADC0
+                DCD     ADC1_IRQHandler           ; 26: ADC1
+                DCD     ADC2_IRQHandler           ; 27: ADC2
+                DCD     MFT_FRT_IRQHandler        ; 28: Free-run Timer
+                DCD     MFT_IPC_IRQHandler        ; 29: Input Capture
+                DCD     MFT_OPC_IRQHandler        ; 30: Output Compare
+                DCD     BT0_7_IRQHandler          ; 31: Base Timer ch.0 to ch.7
+                DCD     ETHER_MAC0_IRQHandler     ; 32: Ethernet MAC ch.0
+                DCD     ETHER_MAC1_IRQHandler     ; 33: Ethernet MAC ch.1
+                DCD     USB0F_Handler             ; 34: USB0 Function
+                DCD     USB0_Handler              ; 35: USB0 Function / USB0 HOST
+                DCD     USB1F_Handler             ; 36: USB1 Function
+                DCD     USB1_Handler              ; 37: USB1 Function / USB1 HOST
+                DCD     DMAC0_Handler             ; 38: DMAC ch.0
+                DCD     DMAC1_Handler             ; 39: DMAC ch.1
+                DCD     DMAC2_Handler             ; 40: DMAC ch.2
+                DCD     DMAC3_Handler             ; 41: DMAC ch.3
+                DCD     DMAC4_Handler             ; 42: DMAC ch.4
+                DCD     DMAC5_Handler             ; 43: DMAC ch.5
+                DCD     DMAC6_Handler             ; 44: DMAC ch.6
+                DCD     DMAC7_Handler             ; 45: DMAC ch.7
+                DCD     BT8_15_IRQHandler         ; 46: Base Timer ch.8 to ch.15
+                DCD     DummyHandler              ; 47: Reserved
+
+                THUMB
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+                PUBWEAK Reset_Handler
+                SECTION .text:CODE:REORDER(2)
+Reset_Handler
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__iar_program_start
+                BX      R0
+
+                PUBWEAK NMI_Handler
+                SECTION .text:CODE:REORDER(1)
+NMI_Handler
+                B       NMI_Handler
+
+                PUBWEAK HardFault_Handler
+                SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+                B       HardFault_Handler
+
+                PUBWEAK MemManage_Handler
+                SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+                B       MemManage_Handler
+
+                PUBWEAK BusFault_Handler
+                SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+                B       BusFault_Handler
+
+                PUBWEAK UsageFault_Handler
+                SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+                B       UsageFault_Handler
+
+                PUBWEAK SVC_Handler
+                SECTION .text:CODE:REORDER(1)
+SVC_Handler
+                B       SVC_Handler
+
+                PUBWEAK DebugMon_Handler
+                SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+                B       DebugMon_Handler
+
+                PUBWEAK PendSV_Handler
+                SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+                B       PendSV_Handler
+
+                PUBWEAK SysTick_Handler
+                SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+                B       SysTick_Handler
+
+
+
+                PUBWEAK CSV_Handler
+                SECTION .text:CODE:REORDER(1)
+CSV_Handler
+                B       CSV_Handler
+
+                PUBWEAK SWDT_Handler
+                SECTION .text:CODE:REORDER(1)
+SWDT_Handler
+                B       SWDT_Handler
+
+                PUBWEAK LVD_Handler
+                SECTION .text:CODE:REORDER(1)
+LVD_Handler
+                B       LVD_Handler
+
+                PUBWEAK MFT_WG_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFT_WG_IRQHandler
+                B       MFT_WG_IRQHandler
+                
+                PUBWEAK INT0_7_Handler
+                SECTION .text:CODE:REORDER(1)
+INT0_7_Handler
+                B       INT0_7_Handler
+
+                PUBWEAK INT8_31_Handler
+                SECTION .text:CODE:REORDER(1)
+INT8_31_Handler
+                B       INT8_31_Handler
+                
+                PUBWEAK DT_Handler
+                SECTION .text:CODE:REORDER(1)
+DT_Handler
+                B       DT_Handler
+
+                PUBWEAK MFS0RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS0RX_IRQHandler
+                B       MFS0RX_IRQHandler
+
+                PUBWEAK MFS0TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS0TX_IRQHandler
+                B       MFS0TX_IRQHandler
+
+                PUBWEAK MFS1RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS1RX_IRQHandler
+                B       MFS1RX_IRQHandler
+
+                PUBWEAK MFS1TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS1TX_IRQHandler
+                B       MFS1TX_IRQHandler
+
+                PUBWEAK MFS2RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS2RX_IRQHandler
+                B       MFS2RX_IRQHandler
+
+                PUBWEAK MFS2TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS2TX_IRQHandler
+                B       MFS2TX_IRQHandler
+
+                PUBWEAK MFS3RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS3RX_IRQHandler
+                B       MFS3RX_IRQHandler
+
+                PUBWEAK MFS3TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS3TX_IRQHandler
+                B       MFS3TX_IRQHandler
+
+                PUBWEAK MFS4RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS4RX_IRQHandler
+                B       MFS4RX_IRQHandler
+
+                PUBWEAK MFS4TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS4TX_IRQHandler
+                B       MFS4TX_IRQHandler
+
+                PUBWEAK MFS5RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS5RX_IRQHandler
+                B       MFS5RX_IRQHandler
+
+                PUBWEAK MFS5TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS5TX_IRQHandler
+                B       MFS5TX_IRQHandler
+
+                PUBWEAK MFS6RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS6RX_IRQHandler
+                B       MFS6RX_IRQHandler
+
+                PUBWEAK MFS6TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS6TX_IRQHandler
+                B       MFS6TX_IRQHandler
+
+                PUBWEAK MFS7RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS7RX_IRQHandler
+                B       MFS7RX_IRQHandler
+
+                PUBWEAK MFS7TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS7TX_IRQHandler
+                B       MFS7TX_IRQHandler
+
+                PUBWEAK PPG_Handler
+                SECTION .text:CODE:REORDER(1)
+PPG_Handler
+                B       PPG_Handler
+
+                PUBWEAK TIM_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+TIM_IRQHandler
+                B       TIM_IRQHandler
+
+                PUBWEAK ADC0_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+ADC0_IRQHandler
+                B       ADC0_IRQHandler
+
+                PUBWEAK ADC1_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+                B       ADC1_IRQHandler
+
+                PUBWEAK ADC2_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+ADC2_IRQHandler
+                B       ADC2_IRQHandler
+
+                PUBWEAK MFT_FRT_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFT_FRT_IRQHandler
+                B       MFT_FRT_IRQHandler
+
+                PUBWEAK MFT_IPC_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFT_IPC_IRQHandler
+                B       MFT_IPC_IRQHandler
+
+                PUBWEAK MFT_OPC_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFT_OPC_IRQHandler
+                B       MFT_OPC_IRQHandler
+
+                PUBWEAK BT0_7_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+BT0_7_IRQHandler
+                B       BT0_7_IRQHandler
+
+                PUBWEAK ETHER_MAC0_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+ETHER_MAC0_IRQHandler
+                B       ETHER_MAC0_IRQHandler
+
+                PUBWEAK ETHER_MAC1_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+ETHER_MAC1_IRQHandler
+                B       ETHER_MAC1_IRQHandler
+
+                PUBWEAK USB0F_Handler
+                SECTION .text:CODE:REORDER(1)
+USB0F_Handler
+                B       USB0F_Handler
+
+                PUBWEAK USB0_Handler
+                SECTION .text:CODE:REORDER(1)
+USB0_Handler
+                B       USB0_Handler
+
+                PUBWEAK USB1F_Handler
+                SECTION .text:CODE:REORDER(1)
+USB1F_Handler
+                B       USB1F_Handler
+
+                PUBWEAK USB1_Handler
+                SECTION .text:CODE:REORDER(1)
+USB1_Handler
+                B       USB1_Handler
+
+                PUBWEAK DMAC0_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC0_Handler
+                B       DMAC0_Handler
+
+
+                PUBWEAK DMAC1_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC1_Handler
+                B       DMAC1_Handler
+
+                PUBWEAK DMAC2_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC2_Handler
+                B       DMAC2_Handler
+
+                PUBWEAK DMAC3_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC3_Handler
+                B       DMAC3_Handler
+
+                PUBWEAK DMAC4_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC4_Handler
+                B       DMAC4_Handler
+
+                PUBWEAK DMAC5_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC5_Handler
+                B       DMAC5_Handler
+
+                PUBWEAK DMAC6_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC6_Handler
+                B       DMAC6_Handler
+
+                PUBWEAK DMAC7_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC7_Handler
+                B       DMAC7_Handler
+
+                PUBWEAK BT8_15_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+BT8_15_IRQHandler
+                B       BT8_15_IRQHandler
+
+                PUBWEAK DummyHandler
+                SECTION .text:CODE:REORDER(1)
+DummyHandler
+                B       DummyHandler
+
+                END

bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.c

+/************************************************************************/
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */
+/*                                                                      */
+/* The following software deliverable is intended for and must only be  */
+/* used for reference and in an evaluation laboratory environment.      */
+/* It is provided on an as-is basis without charge and is subject to    */
+/* alterations.                                                         */
+/* It is the user's obligation to fully test the software in its        */
+/* environment and to ensure proper functionality, qualification and    */
+/* compliance with component specifications.                            */
+/*                                                                      */
+/* In the event the software deliverable includes the use of open       */
+/* source components, the provisions of the governing open source       */
+/* license agreement shall apply with respect to such software          */
+/* deliverable.                                                         */
+/* FSEU does not warrant that the deliverables do not infringe any      */
+/* third party intellectual property right (IPR). In the event that     */
+/* the deliverables infringe a third party IPR it is the sole           */
+/* responsibility of the customer to obtain necessary licenses to       */
+/* continue the usage of the deliverable.                               */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law FSEU disclaims all */
+/* warranties, whether express or implied, in particular, but not       */
+/* limited to, warranties of merchantability and fitness for a          */
+/* particular purpose for which the deliverable is not designated.      */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law, FSEU's liability  */
+/* is restricted to intentional misconduct and gross negligence.        */
+/* FSEU is not liable for consequential damages.                        */
+/*                                                                      */
+/* (V1.5)                                                               */
+/************************************************************************/
+
+#include "board.h"
+
+/** \file system_mb9bf61x.c
+ **
+ ** FM3 system initialization functions
+ ** All adjustments can be done in belonging header file.
+ **
+ ** History:
+ ** 2011-07-07 V1.0 MWi original version
+ ******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** System Clock Frequency (Core Clock) Variable according CMSIS
+ ******************************************************************************/
+uint32_t SystemCoreClock = __HCLK;
+
+/**
+ ******************************************************************************
+ ** \brief  Update the System Core Clock with current core Clock retrieved from
+ ** cpu registers.
+ ** \param  none
+ ** \return none
+ ******************************************************************************/
+void SystemCoreClockUpdate (void) {
+  uint32_t masterClk;
+  uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance
+
+  switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) {
+    case 0:                                 /* internal High-speed Cr osc.    */
+      masterClk = __CLKHC;
+      break;
+
+    case 1:                                 /* external main osc.             */
+      masterClk = __CLKMO;
+      break;
+
+    case 2:                                 /* PLL clock                      */
+  // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
+  // violation:
+  //   "Unordered accesses to a volatile location"
+      u32RegisterRead = (__CLKMO  * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1));
+      masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1));
+      break;
+
+    case 4:                                 /* internal Low-speed CR osc.     */
+      masterClk = __CLKLC;
+      break;
+
+    case 5:                                 /* external Sub osc.              */
+      masterClk = __CLKSO;
+      break;
+
+    default:
+      masterClk = 0Ul;
+      break;
+  }
+
+  switch (FM3_CRG->BSC_PSR & 0x07) {
+    case 0:
+      SystemCoreClock = masterClk;
+      break;
+
+    case 1:
+      SystemCoreClock = masterClk / 2;
+      break;
+
+    case 2:
+      SystemCoreClock = masterClk / 3;
+      break;
+
+    case 3:
+      SystemCoreClock = masterClk / 4;
+      break;
+
+    case 4:
+      SystemCoreClock = masterClk / 6;
+      break;
+
+    case 5:
+      SystemCoreClock = masterClk /8;
+      break;
+
+    case 6:
+      SystemCoreClock = masterClk /16;
+      break;
+
+    default:
+      SystemCoreClock = 0Ul;
+      break;
+  }
+
+}
+
+/**
+ ******************************************************************************
+ ** \brief  Setup the microcontroller system. Initialize the System and update
+ ** the SystemCoreClock variable.
+ **
+ ** \param  none
+ ** \return none
+ ******************************************************************************/
+void SystemInit (void) {
+
+  static uint32_t u32IoRegisterRead;  // Workaround variable for MISRA C rule conformance
+
+#if (HWWD_DISABLE)                                 /* HW Watchdog Disable */
+  FM3_HWWDT->WDG_LCK = 0x1ACCE551;                 /* HW Watchdog Unlock */
+  FM3_HWWDT->WDG_LCK = 0xE5331AAE;
+  FM3_HWWDT->WDG_CTL = 0;                          /* HW Watchdog stop */
+#endif
+
+#if (CLOCK_SETUP)                                   /* Clock Setup */
+  FM3_CRG->BSC_PSR   = BSC_PSR_Val;                /* set System Clock presacaler */
+  FM3_CRG->APBC0_PSR = APBC0_PSR_Val;              /* set APB0 presacaler */
+  FM3_CRG->APBC1_PSR = APBC1_PSR_Val;              /* set APB1 presacaler */
+  FM3_CRG->APBC2_PSR = APBC2_PSR_Val;              /* set APB2 presacaler */
+  FM3_CRG->SWC_PSR   = SWC_PSR_Val | (1UL << 7);   /* set SW Watchdog presacaler */
+  FM3_CRG->TTC_PSR   = TTC_PSR_Val;                /* set Trace Clock presacaler */
+
+  FM3_CRG->CSW_TMR   = CSW_TMR_Val;                /* set oscillation stabilization wait time */
+
+  if (SCM_CTL_Val & (1UL << 1)) {                    /* Main clock oscillator enabled ? */
+    FM3_CRG->SCM_CTL |= (1UL << 1);                /* enable main oscillator */
+    while (!(FM3_CRG->SCM_STR & (1UL << 1)));      /* wait for Main clock oscillation stable */
+  }
+
+  if (SCM_CTL_Val & (1UL << 3)) {                    /* Sub clock oscillator enabled ? */
+    FM3_CRG->SCM_CTL |= (1UL << 3);                /* enable sub oscillator */
+    while (!(FM3_CRG->SCM_STR & (1UL << 3)));      /* wait for Sub clock oscillation stable */
+  }
+
+  FM3_CRG->PSW_TMR   = PSW_TMR_Val;                /* set PLL stabilization wait time */
+  FM3_CRG->PLL_CTL1  = PLL_CTL1_Val;               /* set PLLM and PLLK */
+  FM3_CRG->PLL_CTL2  = PLL_CTL2_Val;               /* set PLLN          */
+
+  if (SCM_CTL_Val & (1UL << 4)) {                    /* PLL enabled ? */
+    FM3_CRG->SCM_CTL  |= (1UL << 4);               /* enable PLL */
+    while (!(FM3_CRG->SCM_STR & (1UL << 4)));      /* wait for PLL stable */
+  }
+
+  FM3_CRG->SCM_CTL  |= (SCM_CTL_Val & 0xE0);       /* Set Master Clock switch */
+
+  {
+      volatile unsigned int i;
+      for(i=0;i<200000;i++);
+  }
+  // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
+  // violations:
+  //   "Unordered reads and writes to or from same location" and
+  //   "Unordered accesses to a volatile location"
+  do
+  {
+    u32IoRegisterRead = (FM3_CRG->SCM_CTL & 0xE0);
+  }while ((FM3_CRG->SCM_STR & 0xE0) != u32IoRegisterRead);
+#endif // (CLOCK_SETUP)
+
+#if (CR_TRIM_SETUP)
+  /* CR Trimming Data  */
+  if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) )
+  {
+    /* UnLock (MCR_FTRM) */
+    FM3_CRTRIM->MCR_RLR = 0x1ACCE554;
+    /* Set MCR_FTRM */
+    FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM;
+    /* Lock (MCR_FTRM) */
+    FM3_CRTRIM->MCR_RLR = 0x00000000;
+  }
+#endif // (CR_TRIM_SETUP)
+}
+
+
+

bsp/mb9bf618s/CMSIS/Include/arm_common_tables.h

+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_common_tables.h
+*
+* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+#endif /*  ARM_COMMON_TABLES_H */

bsp/mb9bf618s/CMSIS/Include/arm_const_structs.h

+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_const_structs.h
+*
+* Description:  This file has constant structs that are initialized for
+*               user convenience.  For example, some can be given as
+*               arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
+      16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
+      32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
+      64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
+      128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
+      256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
+      512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
+      1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
+      2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
+      4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
+   };
+
+#endif

bsp/mb9bf618s/CMSIS/Include/core_cmFunc.h

+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */

bsp/mb9bf618s/CMSIS/README.txt

+* -------------------------------------------------------------------
+* Copyright (C) 2011-2013 ARM Limited. All rights reserved.  
+* 
+* Date:        18 March 2013  
+* Revision:    V3.20 
+*  
+* Project:     Cortex Microcontroller Software Interface Standard (CMSIS)
+* Title:       Release Note for CMSIS
+*
+* -------------------------------------------------------------------
+
+
+NOTE - Open the index.html file to access CMSIS documentation
+
+
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all 
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects 
+and reduces time-to-market for new embedded applications.
+
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
+Any user of the software package is bound to the terms and conditions of the end user license agreement.
+
+
+You will find the following sub-directories:
+
+Documentation           - Contains CMSIS documentation.
+ 
+DSP_Lib                 - MDK project files, Examples and source files etc.. to build the 
+                          CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
+
+Include                 - CMSIS Core Support and CMSIS DSP Include Files.
+
+Lib                     - CMSIS DSP Libraries.
+
+RTOS                    - CMSIS RTOS API template header file.
+
+SVD                     - CMSIS SVD Schema files and Conversion Utility.

bsp/mb9bf618s/CMSIS/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('DeviceSupport/fujitsu/mb9bf61x/*.c')
+
+CPPPATH = [cwd + '/Include', cwd + '/DeviceSupport/fujitsu/mb9bf61x/']
+
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+	src += ['DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c']
+elif rtconfig.CROSS_TOOL == 'keil':
+	src += ['DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S']
+elif rtconfig.CROSS_TOOL == 'iar':
+	src += ['DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S']
+
+CPPDEFINES = [rtconfig.FM3_TYPE]
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/mb9bf618s/SConscript

+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/mb9bf618s/SConstruct

+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+	env.Replace(ARFLAGS = '')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/mb9bf618s/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/mb9bf618s/drivers/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'drivers')
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/mb9bf618s/rtthread-fm3.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00100000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x1FFF0000 0x00020000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+