[BSP] Add imx6sx

bsp/imx6sx/README.md

+# i.MX6 SoloX
+
+Freescale's Smart Application Blueprint for Rapid Engineering (SABRE) board for smart devices
+
+Rev.B
+
+CPU: MCIMX6X4EVM10AB
+
+* ARM Cortex-A9 @ 1GHz
+* ARM Cortex-M4 @ 200MHz
+
+* Freescale PF0200 PMIC
+* 1GB DDR3
+* 32 MB x2 QuadSPI Flash
+
+* Freescale MMA8451 3-Axis Accelerometer
+* Freescale MAG3110 3D Magnetometer

bsp/imx6sx/cortex-a9/SConscript

+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/imx6sx/cortex-a9/SConstruct

+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.join(os.getcwd(), '..', '..', '..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-imx6.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+        CXX= rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT,has_libcpu=True)
+
+objs += SConscript('../iMX6_Platform_SDK/SConscript', variant_dir='build/iMX6_Platform_SDK/SConscript', duplicate=0)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/imx6sx/cortex-a9/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/imx6sx/cortex-a9/applications/application.c

+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2012, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-11-20     Bernard    the first version
+ */
+
+#include <rtthread.h>
+#include <components.h>
+
+#include <sdk.h>
+#include <core/ccm_pll.h>
+
+void show_freq(void)
+{
+    rt_kprintf("CPU: %d MHz\n", get_main_clock(CPU_CLK)/1000000);
+    rt_kprintf("DDR: %d MHz\n", get_main_clock(MMDC_CH0_AXI_CLK)/1000000);
+    rt_kprintf("IPG: %d MHz\n", get_main_clock(IPG_CLK)/1000000);
+}
+
+void init_thread(void* parameter)
+{
+    rt_kprintf("Freescale i.MX6 Platform SDK %s\n", SDK_VERSION_STRING);
+    show_freq();
+
+    rt_components_init();
+}
+
+int rt_application_init()
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init", init_thread, RT_NULL,
+        1024, RT_THREAD_PRIORITY_MAX/3, 10);
+    if (tid != RT_NULL) rt_thread_startup(tid);
+
+    return 0;
+}

bsp/imx6sx/cortex-a9/applications/startup.c

+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2012-12-05     Bernard      the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include <board.h>
+
+extern int  rt_application_init(void);
+extern void rt_hw_board_init(void);
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    // platform_init();
+    // print_version();
+
+    /* initialzie hardware interrupt */
+    rt_hw_interrupt_init();
+
+    /* initialize board */
+    rt_hw_board_init();
+
+    /* show RT-Thread version */
+    rt_show_version();
+
+    /* initialize memory system */
+#ifdef RT_USING_HEAP
+    rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+#endif
+
+    /* initialize scheduler system */
+    rt_system_scheduler_init();
+
+    /* initialize timer and soft timer thread */
+    rt_system_timer_init();
+    rt_system_timer_thread_init();
+
+    /* initialize application */
+    rt_application_init();
+
+    /* initialize idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* invoke rtthread_startup */
+    rtthread_startup();
+
+    return 0;
+}

bsp/imx6sx/cortex-a9/board/SConscript

+import copy
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/imx6sx/cortex-a9/board/ccm_iomux_config.c

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: ccm_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for ccm module.
+void ccm_iomux_config(void)
+{
+    // Config ccm.CCM_CLKO1 to pad GPIO00(T5)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_GPIO00(0x020E020C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ccm signal: CCM_CLKO1
+    //     ALT2 (2) - Select instance: kpp signal: KEY_COL5
+    //     ALT3 (3) - Select instance: asrc signal: ASRC_EXT_CLK
+    //     ALT4 (4) - Select instance: epit1 signal: EPIT1_OUT
+    //     ALT5 (5) - Select instance: gpio1 signal: GPIO1_IO00
+    //     ALT6 (6) - Select instance: usb signal: USB_H1_PWR
+    //     ALT7 (7) - Select instance: snvs signal: SNVS_VIO_5
+    HW_IOMUXC_SW_MUX_CTL_PAD_GPIO00_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_GPIO00_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_GPIO00(0x020E05DC)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //                 NOTE: Read Only Field
+    //                 The value of this field is fixed and cannot be changed.
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_GPIO00_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_GPIO00_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/dcic_iomux_config.c

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: dcic_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regsdcic.h"
+#include "io.h"
+#include <assert.h>
+
+void dcic_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_DCIC1:
+            return dcic1_iomux_config();
+
+        case HW_DCIC2:
+            return dcic2_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/board/ecspi_iomux_config.c

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: ecspi_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regsecspi.h"
+#include "io.h"
+#include <assert.h>
+
+void ecspi_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_ECSPI1:
+            return ecspi1_iomux_config();
+
+        case HW_ECSPI2:
+            return ecspi2_iomux_config();
+
+        case HW_ECSPI3:
+            return ecspi3_iomux_config();
+
+        case HW_ECSPI4:
+            return ecspi4_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/board/epit_iomux_config.c

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: epit_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regsepit.h"
+#include "io.h"
+#include <assert.h>
+
+void epit_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_EPIT1:
+            return epit1_iomux_config();
+
+        case HW_EPIT2:
+            return epit2_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/board/flexcan1_iomux_config.c

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: flexcan1_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for flexcan1 module.
+void flexcan1_iomux_config(void)
+{
+    // Config flexcan1.FLEXCAN1_RX to pad KEY_ROW2(W4)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR(0x0001B0B0);
+    // HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_WR(0x00000001);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2(0x020E0260)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SS2
+    //     ALT1 (1) - Select instance: enet signal: ENET_TX_DATA2
+    //     ALT2 (2) - Select instance: flexcan1 signal: FLEXCAN1_RX
+    //     ALT3 (3) - Select instance: kpp signal: KEY_ROW2
+    //     ALT4 (4) - Select instance: usdhc2 signal: SD2_VSELECT
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO11
+    //     ALT6 (6) - Select instance: hdmi signal: HDMI_TX_CEC_LINE
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2(0x020E0648)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_SRE_V(SLOW));
+    // Pad KEY_ROW2 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_FLEXCAN1_RX_SELECT_INPUT(0x020E07C8)
+    //   DAISY [1:0] - MUX Mode Select Field Reset: GPIO08_ALT3
+    //                 Selecting Pads Involved in Daisy Chain.
+    //     GPIO08_ALT3 (0) - Select signal flexcan1 FLEXCAN1_RX as input from pad GPIO08(ALT3).
+    //     KEY_ROW2_ALT2 (1) - Select signal flexcan1 FLEXCAN1_RX as input from pad KEY_ROW2(ALT2).
+    //     SD3_CLK_ALT2 (2) - Select signal flexcan1 FLEXCAN1_RX as input from pad SD3_CLK(ALT2).
+    HW_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_WR(
+            BF_IOMUXC_FLEXCAN1_RX_SELECT_INPUT_DAISY_V(KEY_ROW2_ALT2));
+
+    // Config flexcan1.FLEXCAN1_TX to pad KEY_COL2(W6)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_WR(0x00000002);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_KEY_COL2(0x020E024C)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: ecspi1 signal: ECSPI1_SS1
+    //     ALT1 (1) - Select instance: enet signal: ENET_RX_DATA2
+    //     ALT2 (2) - Select instance: flexcan1 signal: FLEXCAN1_TX
+    //     ALT3 (3) - Select instance: kpp signal: KEY_COL2
+    //     ALT4 (4) - Select instance: enet signal: ENET_MDC
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO10
+    //     ALT6 (6) - Select instance: usb signal: USB_H1_PWR_CTL_WAKE
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_MUX_MODE_V(ALT2));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_KEY_COL2(0x020E0634)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/flexcan2_iomux_config.c

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: flexcan2_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+
+// Function to configure IOMUXC for flexcan2 module.
+void flexcan2_iomux_config(void)
+{
+    // Config flexcan2.FLEXCAN2_RX to pad KEY_ROW4(V5)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR(0x0001B0B0);
+    // HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_WR(0x00000000);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4(0x020E0268)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: flexcan2 signal: FLEXCAN2_RX
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_SISG5
+    //     ALT2 (2) - Select instance: usb signal: USB_OTG_PWR
+    //     ALT3 (3) - Select instance: kpp signal: KEY_ROW4
+    //     ALT4 (4) - Select instance: uart5 signal: UART5_CTS_B
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO15
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4(0x020E0650)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PD
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE_V(SLOW));
+    // Pad KEY_ROW4 is involved in Daisy Chain.
+    // Input Select Register:
+    // IOMUXC_FLEXCAN2_RX_SELECT_INPUT(0x020E07CC)
+    //   DAISY [0] - MUX Mode Select Field Reset: KEY_ROW4_ALT0
+    //               Selecting Pads Involved in Daisy Chain.
+    //     KEY_ROW4_ALT0 (0) - Select signal flexcan2 FLEXCAN2_RX as input from pad KEY_ROW4(ALT0).
+    //     SD3_DATA1_ALT2 (1) - Select signal flexcan2 FLEXCAN2_RX as input from pad SD3_DATA1(ALT2).
+    HW_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_WR(
+            BF_IOMUXC_FLEXCAN2_RX_SELECT_INPUT_DAISY_V(KEY_ROW4_ALT0));
+
+    // Config flexcan2.FLEXCAN2_TX to pad KEY_COL4(T6)
+    // HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR(0x00000000);
+    // HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR(0x0001B0B0);
+    // Mux Register:
+    // IOMUXC_SW_MUX_CTL_PAD_KEY_COL4(0x020E0254)
+    //   SION [4] - Software Input On Field Reset: DISABLED
+    //              Force the selected mux mode Input path no matter of MUX_MODE functionality.
+    //     DISABLED (0) - Input Path is determined by functionality of the selected mux mode (regular).
+    //     ENABLED (1) - Force input path of pad.
+    //   MUX_MODE [2:0] - MUX Mode Select Field Reset: ALT5
+    //                    Select iomux modes to be used for pad.
+    //     ALT0 (0) - Select instance: flexcan2 signal: FLEXCAN2_TX
+    //     ALT1 (1) - Select instance: ipu1 signal: IPU1_SISG4
+    //     ALT2 (2) - Select instance: usb signal: USB_OTG_OC
+    //     ALT3 (3) - Select instance: kpp signal: KEY_COL4
+    //     ALT4 (4) - Select instance: uart5 signal: UART5_RTS_B
+    //     ALT5 (5) - Select instance: gpio4 signal: GPIO4_IO14
+    HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR(
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION_V(DISABLED) | 
+            BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE_V(ALT0));
+    // Pad Control Register:
+    // IOMUXC_SW_PAD_CTL_PAD_KEY_COL4(0x020E063C)
+    //   HYS [16] - Hysteresis Enable Field Reset: ENABLED
+    //     DISABLED (0) - CMOS input
+    //     ENABLED (1) - Schmitt trigger input
+    //   PUS [15:14] - Pull Up / Down Config. Field Reset: 100K_OHM_PU
+    //     100K_OHM_PD (0) - 100K Ohm Pull Down
+    //     47K_OHM_PU (1) - 47K Ohm Pull Up
+    //     100K_OHM_PU (2) - 100K Ohm Pull Up
+    //     22K_OHM_PU (3) - 22K Ohm Pull Up
+    //   PUE [13] - Pull / Keep Select Field Reset: PULL
+    //     KEEP (0) - Keeper Enabled
+    //     PULL (1) - Pull Enabled
+    //   PKE [12] - Pull / Keep Enable Field Reset: ENABLED
+    //     DISABLED (0) - Pull/Keeper Disabled
+    //     ENABLED (1) - Pull/Keeper Enabled
+    //   ODE [11] - Open Drain Enable Field Reset: DISABLED
+    //              Enables open drain of the pin.
+    //     DISABLED (0) - Output is CMOS.
+    //     ENABLED (1) - Output is Open Drain.
+    //   SPEED [7:6] - Speed Field Reset: 100MHZ
+    //     RESERVED0 (0) - Reserved
+    //     50MHZ (1) - Low (50 MHz)
+    //     100MHZ (2) - Medium (100 MHz)
+    //     200MHZ (3) - Maximum (200 MHz)
+    //   DSE [5:3] - Drive Strength Field Reset: 40_OHM
+    //     HIZ (0) - HI-Z
+    //     240_OHM (1) - 240 Ohm
+    //     120_OHM (2) - 120 Ohm
+    //     80_OHM (3) - 80 Ohm
+    //     60_OHM (4) - 60 Ohm
+    //     48_OHM (5) - 48 Ohm
+    //     40_OHM (6) - 40 Ohm
+    //     34_OHM (7) - 34 Ohm
+    //   SRE [0] - Slew Rate Field Reset: SLOW
+    //             Slew rate control.
+    //     SLOW (0) - Slow Slew Rate
+    //     FAST (1) - Fast Slew Rate
+    HW_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_WR(
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS_V(100K_OHM_PU) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE_V(PULL) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE_V(ENABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE_V(DISABLED) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED_V(100MHZ) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE_V(40_OHM) | 
+            BF_IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE_V(SLOW));
+}

bsp/imx6sx/cortex-a9/board/flexcan_iomux_config.c

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: flexcan_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regsflexcan.h"
+#include "io.h"
+#include <assert.h>
+
+void flexcan_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_FLEXCAN1:
+            return flexcan1_iomux_config();
+
+        case HW_FLEXCAN2:
+            return flexcan2_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/board/gpio_iomux_config.c

+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+// File: gpio_iomux_config.c
+
+/* ------------------------------------------------------------------------------
+ * <auto-generated>
+ *     This code was generated by a tool.
+ *     Runtime Version:3.4.0.0
+ *
+ *     Changes to this file may cause incorrect behavior and will be lost if
+ *     the code is regenerated.
+ * </auto-generated>
+ * ------------------------------------------------------------------------------
+*/
+
+#include "iomux_config.h"
+#include "registers/regsiomuxc.h"
+#include "registers/regsgpio.h"
+#include "io.h"
+#include <assert.h>
+
+void gpio_iomux_config(int instance)
+{
+    switch (instance)
+    {
+        case HW_GPIO1:
+            return gpio1_iomux_config();
+
+        case HW_GPIO2:
+            return gpio2_iomux_config();
+
+        case HW_GPIO3:
+            return gpio3_iomux_config();
+
+        case HW_GPIO4:
+            return gpio4_iomux_config();
+
+        case HW_GPIO5:
+            return gpio5_iomux_config();
+
+        case HW_GPIO6:
+            return gpio6_iomux_config();
+
+        case HW_GPIO7:
+            return gpio7_iomux_config();
+
+        default:
+            assert(false);
+    }
+}
+

bsp/imx6sx/cortex-a9/cpu/SConscript

+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'iar':
+        src += Glob('*_iar.S')
+elif rtconfig.PLATFORM == 'gcc':
+        src += Glob('*_gcc.S')
+elif rtconfig.PLATFORM == 'armcc':
+        src += Glob('*_rvds.S')
+
+group = DefineGroup('AM335x', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')