[libcpu] Sync to latest version.

libcpu/Kconfig

@@ -86,6 +86,14 @@ config ARCH_RISCV
 config ARCH_IA32
     bool
 
+config ARCH_TIDSP
+    bool
+
+config ARCH_TIDSP_C28X
+    bool
+    select ARCH_TIDSP
+    select ARCH_CPU_STACK_GROWS_UPWARD
+
 config ARCH_HOST_SIMULATOR
     bool
 

libcpu/SConscript

@@ -2,30 +2,37 @@ Import('RTT_ROOT')
 Import('rtconfig')
 from building import *
 
+arch = rtconfig.ARCH
 comm = rtconfig.ARCH + '/common'
 path = rtconfig.ARCH + '/' + rtconfig.CPU
+src  = []
 ASFLAGS = ''
 
 # The set of source files associated with this SConscript file.
 if rtconfig.PLATFORM == 'armcc':
-	src = Glob(path + '/*.c') + Glob(path + '/*_rvds.S') + Glob(comm + '/*.c')
+    src += Glob(path + '/*.c') + Glob(path + '/*_rvds.S') 
+    src += Glob(comm + '/*.c') + Glob(comm + '/*_rvds.S')
 
 if rtconfig.PLATFORM == 'gcc':
-	src = Glob(path + '/*.c') + Glob(path + '/*_gcc.S') + Glob(comm + '/*.c') + Glob(path + '/*_init.S')
+    src += Glob(path + '/*_init.S')
+    src += Glob(path + '/*.c') + Glob(path + '/*_gcc.S') 
+    src += Glob(comm + '/*.c') + Glob(comm + '/*_gcc.S')
 
 if rtconfig.PLATFORM == 'iar':
-	src = Glob(path + '/*.c') + Glob(path + '/*_iar.S') + Glob(comm + '/*.c')
+    src += Glob(path + '/*.c') + Glob(path + '/*_iar.S')
+    src += Glob(comm + '/*.c') + Glob(comm + '/*_iar.S')
 
 if rtconfig.PLATFORM == 'cl':
-	src = Glob(path + '/*.c')
+    src = Glob(path + '/*.c')
 
 if rtconfig.PLATFORM == 'mingw':
-	src = Glob(path + '/*.c')
+    src = Glob(path + '/*.c')
 
 if rtconfig.PLATFORM == 'armcc' and rtconfig.ARCH == 'arm' and rtconfig.CPU == 'arm926':
     ASFLAGS = ' --cpreproc'
-    
-CPPPATH = [RTT_ROOT + '/libcpu/' + rtconfig.ARCH + '/' + rtconfig.CPU, RTT_ROOT + '/libcpu/' + rtconfig.ARCH + '/common']
+
+CPPPATH = [RTT_ROOT + '/libcpu/' + arch + '/' + rtconfig.CPU, RTT_ROOT + '/libcpu/' + arch + '/common']
+
 group = DefineGroup(rtconfig.CPU.upper(), src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
 
 Return('group')

libcpu/arm/AT91SAM7X/interrupt.c

@@ -91,7 +91,7 @@ void rt_hw_interrupt_umask(int vector)
  * @return the old handler
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, 
-									void *param, char *name)
+									void *param, const char *name)
 {
 	rt_isr_handler_t old_handler = RT_NULL;
 	if(vector >= 0 && vector < MAX_HANDLERS)

libcpu/arm/am335x/interrupt.c

@@ -158,7 +158,7 @@ void rt_hw_interrupt_ack(int fiq_irq)
  * @param old_handler the old interrupt service routine
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, char *name)
+        void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
 

libcpu/arm/arm926/start_rvds.S

@@ -25,7 +25,14 @@
 ; * 2015-06-04     aozima     Align stack address to 8 byte.
 ; */
 
-#include "rt_low_level_init.h"
+;#include "rt_low_level_init.h"
+UND_STK_SIZE EQU 512
+SVC_STK_SIZE EQU 4096
+ABT_STK_SIZE EQU 512
+IRQ_STK_SIZE EQU 1024
+FIQ_STK_SIZE EQU 1024
+SYS_STK_SIZE EQU 512
+Heap_Size    EQU 512
 
 S_FRAME_SIZE    EQU     (18*4)   ;72
 ;S_SPSR          EQU     (17*4)   ;SPSR

libcpu/arm/cortex-a/interrupt.c

@@ -110,7 +110,7 @@ void rt_hw_interrupt_umask(int vector)
  * @param old_handler the old interrupt service routine
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, char *name)
+        void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
 

libcpu/arm/cortex-m0/cpuport.c

@@ -114,3 +114,22 @@ void rt_hw_hard_fault_exception(struct exception_stack_frame *contex)
 
     while (1);
 }
+
+#define SCB_CFSR        (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */
+#define SCB_HFSR        (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
+#define SCB_MMAR        (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
+#define SCB_BFAR        (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
+#define SCB_AIRCR       (*(volatile unsigned long *)0xE000ED00)  /* Reset control Address Register */
+#define SCB_RESET_VALUE 0x05FA0004                               /* Reset value, write to SCB_AIRCR can reset cpu */
+
+#define SCB_CFSR_MFSR   (*(volatile const unsigned char*)0xE000ED28)  /* Memory-management Fault Status Register */
+#define SCB_CFSR_BFSR   (*(volatile const unsigned char*)0xE000ED29)  /* Bus Fault Status Register */
+#define SCB_CFSR_UFSR   (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */
+
+/**
+ * reset CPU
+ */
+RT_WEAK void rt_hw_cpu_reset(void)
+{
+    SCB_AIRCR  = SCB_RESET_VALUE;//((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |SCB_AIRCR_SYSRESETREQ_Msk);
+}

libcpu/arm/cortex-r4/interrupt.c

@@ -86,7 +86,7 @@ void rt_hw_interrupt_umask(int vector)
  * @return the old handler
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-									void *param, char *name)
+									void *param, const char *name)
 {
 	rt_isr_handler_t old_handler = RT_NULL;
 

libcpu/arm/lpc214x/cpuport.c

@@ -137,7 +137,7 @@ void rt_hw_interrupt_umask(int vector)
  * @return old handler
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-                                         void *param, char *name)
+                                         void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
 

libcpu/arm/lpc24xx/interrupt.c

@@ -83,7 +83,7 @@ void rt_hw_interrupt_umask(int vector)
  * @return the old handler
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, 
-									void *param, char *name)
+									void *param, const char *name)
 {
 	rt_isr_handler_t old_handler = RT_NULL;
 

libcpu/arm/realview-a8-vmm/interrupt.c

@@ -103,7 +103,7 @@ void rt_hw_interrupt_umask(int vector)
  * @param old_handler the old interrupt service routine
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, char *name)
+        void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
 

libcpu/arm/s3c24x0/interrupt.c

@@ -104,7 +104,7 @@ void rt_hw_interrupt_umask(int vector)
  * @param old_handler the old interrupt service routine
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-                                        void *param, char *name)
+                                        void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
 

libcpu/arm/sep4020/interrupt.c

@@ -107,7 +107,7 @@ void rt_hw_interrupt_umask(int vector)
  * @param old_handler the old interrupt service routine
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-                                        void *param, char *name)
+                                        void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
 

libcpu/arm/zynq7000/interrupt.c

@@ -112,7 +112,7 @@ void rt_hw_interrupt_umask(int vector)
  * @param old_handler the old interrupt service routine
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, char *name)
+        void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
 

libcpu/ia32/interrupt.c

@@ -131,7 +131,7 @@ void rt_hw_interrupt_mask(int vector)
 rt_isr_handler_t rt_hw_interrupt_install(int              vector,
                                          rt_isr_handler_t handler,
                                          void            *param,
-                                         char            *name)
+                                         const char      *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
 

libcpu/mips/loongson_1b/interrupt.c

@@ -96,7 +96,7 @@ void rt_hw_interrupt_umask(int vector)
  * @param old_handler the old interrupt service routine
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-                                         void *param, char *name)
+                                         void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
 

libcpu/mips/loongson_1c/interrupt.c

@@ -112,7 +112,7 @@ void rt_hw_interrupt_umask(int vector)
  * @param old_handler the old interrupt service routine
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-                                         void *param, char *name)
+                                         void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
 

libcpu/mips/x1000/interrupt.c

@@ -80,7 +80,7 @@ void rt_hw_interrupt_umask(int vector)
 }
 
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, char *name)
+        void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
 

libcpu/mips/xburst/interrupt.c

@@ -95,7 +95,7 @@ void rt_hw_interrupt_umask(int vector)
  * @return old handler
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, char *name)
+        void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
 

libcpu/ppc/ppc405/interrupt.c

@@ -79,7 +79,7 @@ void uic_interrupt(rt_uint32_t uic_base, int vec_base)
 }
 
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, 
-    void* param, char* name)
+    void* param, const char* name)
 {
     int	intVal;
     rt_isr_handler_t old_handler;

libcpu/ti-dsp/c28x/context.s

+;
+; Copyright (c) 2006-2018, RT-Thread Development Team
+;
+; SPDX-License-Identifier: Apache-2.0
+;
+; Change Logs:
+; Date           Author       Notes
+; 2018-09-01     xuzhuoyi     the first version.
+;
+
+    .ref   _rt_interrupt_to_thread
+    .ref   _rt_interrupt_from_thread
+    .ref   _rt_thread_switch_interrupt_flag
+
+    .def   _RTOSINT_Handler
+    .def   _rt_hw_get_st0
+    .def   _rt_hw_get_st1
+    .def   _rt_hw_context_switch_interrupt
+    .def   _rt_hw_context_switch
+    .def   _rt_hw_context_switch_to
+    .def   _rt_hw_interrupt_thread_switch
+    .def   _rt_hw_interrupt_disable
+    .def   _rt_hw_interrupt_enable
+
+
+RT_CTX_SAVE  .macro      
+
+
+    PUSH    AR1H:AR0H
+    PUSH    XAR2
+    PUSH    XAR3
+    PUSH    XAR4
+    PUSH    XAR5
+    PUSH    XAR6
+    PUSH    XAR7
+    PUSH    XT
+    PUSH    RPC
+
+ 
+    .endm
+
+
+RT_CTX_RESTORE  .macro
+                                  
+    POP     RPC
+    POP     XT
+    POP     XAR7
+    POP     XAR6
+    POP     XAR5
+    POP     XAR4
+    POP     XAR3
+    POP     XAR2
+
+
+    MOVZ    AR0 , @SP                                           
+    SUBB    XAR0, #6
+    MOVL    ACC , *XAR0
+    AND     ACC, #0xFFFF << 16
+    MOV     AL, IER
+    MOVL   *XAR0, ACC
+
+
+    POP     AR1H:AR0H
+
+    .endm
+
+
+.text
+    .newblock
+
+;
+; rt_base_t rt_hw_interrupt_disable();
+;
+    .asmfunc
+_rt_hw_interrupt_disable:
+    DINT
+    LRETR
+    .endasmfunc
+
+;
+; void rt_hw_interrupt_enable(rt_base_t level);
+;
+    .asmfunc
+_rt_hw_interrupt_enable:
+    EINT
+    LRETR
+    .endasmfunc
+    
+;
+; void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; r0 --> from
+; r4 --> to
+
+ 
+    .asmfunc
+_rt_hw_context_switch_interrupt:
+_rt_hw_context_switch:
+    MOVL    XAR0, #0
+    MOV     AR0, AL
+    MOVL    XAR4, *-SP[4]
+    ; set rt_thread_switch_interrupt_flag to 1 
+    MOVL    XAR5, #_rt_thread_switch_interrupt_flag
+    MOVL    XAR6, *XAR5
+    MOVL    ACC, XAR6
+    CMPB    AL, #1
+    B       _reswitch, EQ
+    MOVL     XAR6, #1
+    MOVL    *XAR5, XAR6
+
+    MOVL    XAR5, #_rt_interrupt_from_thread   ; set rt_interrupt_from_thread
+    MOVL    *XAR5, XAR0
+
+_reswitch:
+    MOVL    XAR5, #_rt_interrupt_to_thread     ; set rt_interrupt_to_thread
+    MOVL    *XAR5, XAR4
+
+    TRAP    #16
+    LRETR
+    .endasmfunc
+     
+     .asmfunc
+_RTOSINT_Handler:
+; disable interrupt to protect context switch 
+    DINT
+
+    ; get rt_thread_switch_interrupt_flag 
+    MOV     AR0, #_rt_thread_switch_interrupt_flag
+    MOV     AL, *AR0
+    MOV     AR1, AL
+    CMP     AR1, #0
+    B       rtosint_exit, EQ         ; pendsv already handled 
+
+    ; clear rt_thread_switch_interrupt_flag to 0 
+    MOV     AR1, #0x00
+    MOV     *AR0, AR1
+
+    MOV     AR0, #_rt_interrupt_from_thread
+    MOV     AL, *AR0
+    MOV     AR1, AL
+    CMP     AR1, #0
+    B       switch_to_thread, EQ    ; skip register save at the first time 
+
+    ;MOVZ    AR1, @SP                 ; get from thread stack pointer 
+    
+;#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+;    TST     lr, #0x10           ; if(!EXC_RETURN[4]) 
+;    VSTMDBEQ r1!, {d8 - d15}    ; push FPU register s16~s31 
+;#endif
+    
+    RT_CTX_SAVE     ; push r4 - r11 register 
+
+;#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+;    MOV     r4, #0x00           ; flag = 0 
+
+;    TST     lr, #0x10           ; if(!EXC_RETURN[4]) 
+;    MOVEQ   r4, #0x01           ; flag = 1 
+
+;    STMFD   r1!, {r4}           ; push flag 
+;#endif
+
+    MOV     AL, *AR0
+    MOV     AR1, AL
+    MOVZ    AR1, @SP                 ; get from thread stack pointer
+    MOV     *AR0, AR1                ; update from thread stack pointer 
+
+switch_to_thread:
+    MOV     AR1, #_rt_interrupt_to_thread
+    MOV     AL, *AR1
+    MOV     AR1, AL
+    MOV     AL, *AR1
+    MOV     AR1, AL                ; load thread stack pointer 
+
+;#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+;    LDMFD   r1!, {r3}           ; pop flag 
+;#endif
+
+    MOV     @SP, AR1
+    INC     SP
+    RT_CTX_RESTORE     ; pop r4 - r11 register
+
+rtosint_exit:
+    ; restore interrupt 
+    EINT
+
+    IRET
+    .endasmfunc
+
+    .asmfunc
+_rt_hw_get_st0:
+    PUSH    ST0
+    POP     AL
+    LRETR
+    .endasmfunc
+
+    .asmfunc
+_rt_hw_get_st1:
+    PUSH    ST1
+    POP     AL
+    LRETR
+    .endasmfunc
+
+;
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+ 
+    .asmfunc
+_rt_hw_context_switch_to:
+    MOV     AR1, #_rt_interrupt_to_thread
+    MOV     *AR1, AL
+
+;#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    ; CLEAR CONTROL.FPCA 
+;    MRS     r2, CONTROL         ; read 
+;    BIC     r2, #0x04           ; modify 
+;    MSR     CONTROL, r2         ; write-back 
+;#endif
+
+    ; set from thread to 0 
+    MOV     AR1, #_rt_interrupt_from_thread
+    MOV     AR0, #0x0
+    MOV     *AR1, AR0
+
+    ; set interrupt flag to 1 
+    MOV     AR1, #_rt_thread_switch_interrupt_flag
+    MOV     AR0, #1
+    MOV     *AR1, AR0
+
+    TRAP    #16
+
+
+    ; never reach here! 
+    .endasmfunc
+    
+; compatible with old version 
+    .asmfunc
+_rt_hw_interrupt_thread_switch:
+    LRETR
+    NOP
+    .endasmfunc
+    
+.end

libcpu/ti-dsp/c28x/cpuport.c

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-09-01     xuzhuoyi     the first version.
+ */
+
+#include <rtthread.h>
+
+/* exception and interrupt handler table */
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+/* exception hook */
+static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
+
+struct exception_stack_frame
+{
+    rt_uint32_t t_st0;
+    rt_uint32_t acc;
+    rt_uint32_t p;
+    rt_uint32_t ar1_ar0;
+    rt_uint32_t dp_st1;
+    rt_uint32_t dbgstat_ier;
+    rt_uint32_t return_address;
+};
+
+struct stack_frame
+{
+    struct exception_stack_frame exception_stack_frame;
+
+    /* r4 ~ r11 register */
+    rt_uint16_t ar0h;
+    rt_uint16_t ar1h;
+    rt_uint32_t xar2;
+    rt_uint32_t xar3;
+    rt_uint32_t xar4;
+    rt_uint32_t xar5;
+    rt_uint32_t xar6;
+    rt_uint32_t xar7;
+    rt_uint32_t xt;
+    rt_uint32_t rpc;
+
+
+};
+
+rt_uint8_t *rt_hw_stack_init(void       *tentry,
+                             void       *parameter,
+                             rt_uint8_t *stack_addr,
+                             void       *texit)
+{
+    struct stack_frame *stack_frame;
+    rt_uint8_t         *stk;
+    unsigned long       i;
+
+    stk  = stack_addr;
+    stk  = (rt_uint8_t *)RT_ALIGN((rt_uint32_t)stk, 8);
+    //stk -= sizeof(struct stack_frame);
+
+    stack_frame = (struct stack_frame *)stk;
+
+    /* init all register */
+    for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++)
+    {
+        ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef;
+    }
+
+    stack_frame->exception_stack_frame.t_st0   = 0x11110000 | rt_hw_get_st0();
+    stack_frame->exception_stack_frame.acc     = 0x33332222;
+    stack_frame->exception_stack_frame.ar1_ar0 = 0x00001111 & (unsigned long)parameter; /* ar0 : argument */
+    stack_frame->exception_stack_frame.p       = 0x55554444;                            /* p */
+    stack_frame->exception_stack_frame.dp_st1  = (0x00000000) | rt_hw_get_st1();        /* dp_st1 */
+    stack_frame->exception_stack_frame.dbgstat_ier    = 0;                              /* dbgstat_ier */
+    stack_frame->exception_stack_frame.return_address = (unsigned long)tentry;          /* return_address */
+    stack_frame->rpc = (unsigned long)texit;
+
+    /* return task's current stack address */
+    return stk + sizeof(struct stack_frame);
+}
+
+/**
+ * This function set the hook, which is invoked on fault exception handling.
+ *
+ * @param exception_handle the exception handling hook function.
+ */
+void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
+{
+    rt_exception_hook = exception_handle;
+}
+
+
+struct exception_info
+{
+    rt_uint32_t exc_return;
+    struct stack_frame stack_frame;
+};
+
+
+/**
+ * shutdown CPU
+ */
+void rt_hw_cpu_shutdown(void)
+{
+    rt_kprintf("shutdown...\n");
+
+    RT_ASSERT(0);
+}

libcpu/unicore32/sep6200/interrupt.c

@@ -199,7 +199,7 @@ void rt_hw_interrupt_umask(int irq)
  * @param old_handler the old interrupt service routine
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-                                        void *param, char *name)
+                                        void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;