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提交 017e673c 编写于 作者: wuyangyong's avatar wuyangyong
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update STM32F4xx_StdPeriph_Driver to V1.1.0. 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1959 bbd45198-f89e-11dd-88c7-29a3b14d5316
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bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Include/system_stm32f4xx.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention
......
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Release_Notes.html
浏览文件 @ 017e673c
......@@ -5,7 +5,7 @@
<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">
<link rel="File-List" href="Library_files/filelist.xml">
<link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM32F40x CMSIS</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
<link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM32F4xx CMSIS</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
......@@ -72,7 +72,7 @@ div.Section1
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
<tbody>
<tr>
<td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../Release_Notes.html">Back to Release page</a></span></td>
<td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../../Release_Notes.html">Back to Release page</a></span></td>
</tr>
<tr style="">
<td style="padding: 1.5pt;">
......@@ -97,7 +97,11 @@ update History</a><o:p></o:p></span></li>
</ol>
<span style="font-family: &quot;Times New Roman&quot;;"></span>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F4xx CMSIS
update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 176px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC1 / 25-August-2011<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 30-September-2011<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release for&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32F40x/41x</span> devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add startup file for <span style="font-style: italic;">TASKING</span> toolchain</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">system_stm32f4xx.c: driver's&nbsp;comments update</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC2 / 26-September-2011<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Official version (V1.0.0) Release Candidate2&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">for <span style="font-weight: bold; font-style: italic;">STM32F40x/41x</span> devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add define for Cortex-M4 revision&nbsp;<span style="font-style: italic;">__CM4_REV</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Correct <span style="font-style: italic;">RCC_CFGR_PPRE2_DIV16</span> bit&nbsp;(in&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">RCC_CFGR</span><span style="font-size: 10pt; font-family: Verdana;"> register) value to&nbsp;0x0000E000</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Correct some&nbsp;bits definition to be in line with naming used in the Reference Manual </span><span style="font-size: 10pt; font-family: Verdana;"> (RM0090)</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_<span style="font-weight: bold;">OTYPER</span>_IDR_x</span> changed to <span style="font-style: italic;">GPIO_<span style="font-weight: bold;">IDR</span>_IDR_x</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_<span style="font-weight: bold;">OTYPER</span>_ODR_x</span> changed to <span style="font-style: italic;">GPIO_<span style="font-weight: bold;">ODR</span>_ODR_x</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SYSCFG_PMC_MII_RMII</span> changed to&nbsp;</span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">SYSCFG_PMC_MII_RMII<span style="font-weight: bold;">_SEL</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">RCC_APB2RSTR_SPI1</span> changed to&nbsp;<span style="font-style: italic;">RCC_APB2RSTR_SPI1<span style="font-weight: bold;">RST</span></span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">DBGMCU_APB1_FZ_DBG_IWD<span style="font-weight: bold;">E</span>G_STOP</span> changed to&nbsp;<span style="font-style: italic;">DBGMCU_APB1_FZ_DBG_IWDG_STOP</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">PWR_CR_PMODE</span> changed to&nbsp;<span style="font-style: italic;">PWR_CR_VOS</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">PWR_CSR_REGRDY</span> changed to&nbsp;<span style="font-style: italic;">PWR_CSR_VOSRDY</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new define <span style="font-style: italic;">RCC_AHB1ENR_CCMDATARAMEN</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new defines&nbsp;<span style="font-style: italic;">SRAM2_BASE, CCMDATARAM_BASE </span>and<span style="font-style: italic;"> BKPSRAM_BASE</span></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">GPIO_TypeDef structure: in the comment change AFR[2] address mapping&nbsp;to <span style="font-style: italic;">0x20-0x24</span> instead of <span style="font-style: italic;">0x24-0x28</span></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">system_stm32f4xx.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span>: add code to enable the FPU</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SetSysClock()</span>: change <span style="font-style: italic;">PWR_CR_PMODE</span> by&nbsp;<span style="font-style: italic;">PWR_CR_VOS</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit_ExtMemCtl()</span>: remove commented values</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">startup (for all compilers)</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Delete code used to enable the FPU (moved to system_stm32f4xx.c file)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">File&#8217;s header updated</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 176px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC1 / 25-August-2011<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Official version (V1.0.0) Release Candidate1 for <span style="font-weight: bold; font-style: italic;">STM32F4xx devices</span></span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span><span style="font-weight: bold; font-style: italic;"></span></span>
......
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/TASKING/cstart_thumb2.asm
浏览文件 @ 017e673c
......@@ -14,7 +14,9 @@
.weak __get_argcv
.extern __argcvbuf
.weak __argcvbuf
.extern SystemInit
;;.extern __init_hardware
.extern SystemInit
.if @defined('__PROF_ENABLE__')
.extern __prof_init
......@@ -38,12 +40,6 @@ _Next:
;; initialize the stack pointer
ldr r1,=_lc_ub_stack ; TODO: make this part of the vector table
mov sp,r1
;FPU settings
ldr r0, =0xE000ED88 ; Enable CP10,CP11
ldr r1,[r0]
orr r1,r1,#(0xF << 20)
str r1,[r0]
; Call the clock system intitialization function.
bl SystemInit
......@@ -84,6 +80,7 @@ clear:
done:
.if @defined('__POSIX__')
;; posix stack buffer for system upbringing
......
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/TrueSTUDIO/startup_stm32f4xx.s
浏览文件 @ 017e673c
......@@ -2,15 +2,15 @@
******************************************************************************
* @file startup_stm32f4xx.s
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief STM32F4xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system and the external SRAM mounted on
* STM3220F-EVAL board to be used as data memory (optional,
* STM324xG-EVAL board to be used as data memory (optional,
* to be enabled by user)
* - Branches to main in the C library (which eventually
* calls main()).
......@@ -92,14 +92,7 @@ LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/*FPU settings*/
ldr r0, =0xE000ED88 // Enable CP10,CP11
ldr r1,[r0]
orr r1,r1,#(0xF << 20)
str r1,[r0]
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
......
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/arm/startup_stm32f4xx.s
浏览文件 @ 017e673c
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f4xx.s
;* Author : MCD Application Team
;* Version : V1.0.0RC1
;* Date : 25-August-2011
;* Version : V1.0.0
;* Date : 30-September-2011
;* Description : STM32F4xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
......@@ -169,12 +172,6 @@ Reset_Handler PROC
IMPORT SystemInit
IMPORT __main
;FPU settings
LDR R0, =0xE000ED88 ; Enable CP10,CP11
LDR R1,[R0]
ORR R1,R1,#(0xF << 20)
STR R1,[R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
......
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f4xx.s
浏览文件 @ 017e673c
......@@ -2,15 +2,15 @@
******************************************************************************
* @file startup_stm32f4xx.s
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief STM32F4xx Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system and the external SRAM mounted on
* STM3220F-EVAL board to be used as data memory (optional,
* STM324xG-EVAL board to be used as data memory (optional,
* to be enabled by user)
* - Branches to main in the C library (which eventually
* calls main()).
......@@ -93,12 +93,6 @@ LoopFillZerobss:
cmp r2, r3
bcc FillZerobss
/* FPU settings */
ldr r0, =0xE000ED88 /* Enable CP10,CP11 */
ldr r1,[r0]
orr r1,r1,#(0xF << 20)
str r1,[r0]
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/
......
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/iar/startup_stm32f4xx.s
浏览文件 @ 017e673c
;/******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f4xx.s
;* Author : MCD Application Team
;* Version : V1.0.0RC1
;* Date : 25-August-2011
;* Description : STM32F40x devices vector table for EWARM toolchain.
;* Version : V1.0.0
;* Date : 30-September-2011
;* Description : STM32F4xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
......@@ -160,12 +165,6 @@ __vector_table
SECTION .text:CODE:REORDER(2)
Reset_Handler
;FPU settings
LDR R0, =0xE000ED88 ; Enable CP10,CP11
LDR R1,[R0]
ORR R1,R1,#(0xF << 20)
STR R1,[R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
......
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F4xx devices,
* and is generated by the clock configuration tool
......@@ -74,7 +74,7 @@
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* High Performance mode | Enabled
* Main regulator output voltage | Scale1 mode
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 5
*-----------------------------------------------------------------------------
......@@ -132,6 +132,7 @@
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM324xG_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
......@@ -141,8 +142,9 @@
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/************************* PLL Parameters *************************************/
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M 25
#define PLL_N 336
......@@ -153,6 +155,8 @@
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 7
/******************************************************************************/
/**
* @}
*/
......@@ -203,6 +207,11 @@ static void SetSysClock(void);
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
......@@ -358,9 +367,9 @@ static void SetSysClock(void)
if (HSEStatus == (uint32_t)0x01)
{
/* Enable high performance mode, System frequency up to 168 MHz */
/* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_PMODE;
PWR->CR |= PWR_CR_VOS;
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
......@@ -496,14 +505,14 @@ void SystemInit_ExtMemCtl(void)
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001015;
FSMC_Bank1->BTCR[3] = 0x00010603;//0x00010400;
FSMC_Bank1->BTCR[3] = 0x00010603;
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
/*
Bank1_SRAM2 is configured as follow:
p.FSMC_AddressSetupTime = 3;//0;
p.FSMC_AddressSetupTime = 3;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 6;//4;
p.FSMC_DataSetupTime = 6;
p.FSMC_BusTurnAroundDuration = 1;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/Release_Notes.html
浏览文件 @ 017e673c
......@@ -916,7 +916,11 @@ ul
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"><a href="#License">License</a><o:p></o:p></span></li>
</ol>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F4xx
Standard Peripherals Library Drivers&nbsp; update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 176px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC1 / 25-August-2011<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Standard Peripherals Library Drivers&nbsp; update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 198px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 30-September-2011</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release for&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32F40x/41x</span> devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx_rtc.c: remove useless code from <span style="font-style: italic;">RTC_GetDate()</span> function<br></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx_rcc.c, stm32f4xx_spi.c, stm32f4xx_wwdg.c and stm32f4xx_syscfg.c: </span><span style="font-size: 10pt; font-family: Verdana;">driver's comments update</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 198px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC2 / 26-September-2011</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Official version (V1.0.0) Release Candidate1<span style="font-weight: bold; font-style: italic;"> </span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"> </span><span style="font-style: italic;">for</span><span style="font-weight: bold; font-style: italic;"> STM32F40x/</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32F41x</span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;"> devices</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx_usart.h/.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update procedure to check on&nbsp;overrun error interrupt pending bit, defines for the following flag are added:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">USART_IT_ORE_RX:</span> this flag is set if&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">overrun error interrupt</span><span style="font-size: 10pt; font-family: Verdana;"> occurs and&nbsp;RXNEIE bit is set</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">USART_IT_ORE_ER:</span> </span><span style="font-size: 10pt; font-family: Verdana;">this flag is&nbsp;set if&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">overrun error interrupt</span><span style="font-size: 10pt; font-family: Verdana;"> occurs and EIE bit is set</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx_tim.c</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">TIM_UpdateRequestConfig():&nbsp;</span>correct function header's comment&nbsp;</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">TIM_ICInit(): </span>add&nbsp;assert macros to test&nbsp;if the passed TIM parameter has channel 2, 3 or 4</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx_pwr.h/.c</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename&nbsp;<span style="font-style: italic;">PWR_FLAG_REGRDY</span> constant to <span style="font-style: italic;">PWR_CSR_REGRDY</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename&nbsp;<span style="font-style: italic;">PWR_FLAG_VOSRDY </span></span><span style="font-size: 10pt; font-family: Verdana;">constant </span><span style="font-size: 10pt; font-family: Verdana;">to <span style="font-style: italic;">PWR_CSR_VOSRDY</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename<span style="font-style: italic;"> PWR_HighPerformanceModeCmd(FunctionalState NewState) </span>function to<span style="font-style: italic;"> PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)<br></span></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx_rcc.h/.c</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">RCC_AHB1PeriphClockCmd(): add new constant <span style="font-style: italic;">RCC_AHB1Periph_CCMDATARAMEN </span>as value for<span style="font-style: italic;"> RCC_AHB1Periph </span>parameter</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f4xx_spi.h</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">IS_I2S_EXT_PERIPH(): add check on&nbsp;<span style="font-style: italic;">I2S3ext</span> peripheral</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC1 / 25-August-2011<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Official version (V1.0.0) Release Candidate1<span style="font-weight: bold; font-style: italic;"> for STM32F4xx devices</span></span></li></ul>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file misc.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the miscellaneous
* firmware library functions (add-on to CMSIS functions).
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_adc.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_can.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the CAN firmware
* library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_crc.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the CRC firmware
* library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_cryp.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the Cryptographic
* processor(CRYP) firmware library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dac.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dbgmcu.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the DBGMCU firmware library.
******************************************************************************
* @attention
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dcmi.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the DCMI firmware library.
******************************************************************************
* @attention
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dma.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the DMA firmware
* library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_exti.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the EXTI firmware
* library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_flash.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_fsmc.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the FSMC firmware
* library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_gpio.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the GPIO firmware
* library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hash.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the HASH
* firmware library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_i2c.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_iwdg.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the IWDG
* firmware library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_pwr.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the PWR firmware
* library.
******************************************************************************
......@@ -87,6 +87,14 @@
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
/** @defgroup PWR_Regulator_Voltage_Scale
* @{
*/
#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x00004000)
#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00000000)
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || ((VOLTAGE) == PWR_Regulator_Voltage_Scale2))
/**
* @}
......@@ -100,11 +108,19 @@
#define PWR_FLAG_SB PWR_CSR_SBF
#define PWR_FLAG_PVDO PWR_CSR_PVDO
#define PWR_FLAG_BRR PWR_CSR_BRR
#define PWR_FLAG_REGRDY PWR_CSR_REGRDY
#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
/** @defgroup PWR_Flag_Legacy
* @{
*/
#define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY
/**
* @}
*/
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
((FLAG) == PWR_FLAG_REGRDY))
((FLAG) == PWR_FLAG_VOSRDY))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
/**
......@@ -131,11 +147,11 @@ void PWR_PVDCmd(FunctionalState NewState);
/* WakeUp pins configuration functions ****************************************/
void PWR_WakeUpPinCmd(FunctionalState NewState);
/* Backup Regulator configuration functions ***********************************/
/* Main and Backup Regulators configuration functions *************************/
void PWR_BackupRegulatorCmd(FunctionalState NewState);
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
/* Performance Mode and FLASH Power Down configuration functions **************/
void PWR_HighPerformanceModeCmd(FunctionalState NewState);
/* FLASH Power Down configuration functions ***********************************/
void PWR_FlashPowerDownCmd(FunctionalState NewState);
/* Low Power modes configuration functions ************************************/
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rcc.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the RCC firmware library.
******************************************************************************
* @attention
......@@ -263,6 +263,7 @@ typedef struct
#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
......@@ -271,7 +272,7 @@ typedef struct
#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x819BEE00) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00))
/**
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rng.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the Random
* Number Generator(RNG) firmware library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rtc.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the RTC firmware
* library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_sdio.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the SDIO firmware
* library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_spi.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the SPI
* firmware library.
******************************************************************************
......@@ -129,7 +129,7 @@ typedef struct
((PERIPH) == I2S3ext))
#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \
((PERIPH) == I2S2ext))
((PERIPH) == I2S3ext))
/** @defgroup SPI_data_direction
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_syscfg.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the SYSCFG firmware
* library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_tim.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the TIM firmware
* library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_usart.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the USART
* firmware library.
******************************************************************************
......@@ -238,13 +238,23 @@ typedef struct
#define USART_IT_TXE ((uint16_t)0x0727)
#define USART_IT_TC ((uint16_t)0x0626)
#define USART_IT_RXNE ((uint16_t)0x0525)
#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
#define USART_IT_IDLE ((uint16_t)0x0424)
#define USART_IT_LBD ((uint16_t)0x0846)
#define USART_IT_CTS ((uint16_t)0x096A)
#define USART_IT_ERR ((uint16_t)0x0060)
#define USART_IT_ORE ((uint16_t)0x0360)
#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
#define USART_IT_NE ((uint16_t)0x0260)
#define USART_IT_FE ((uint16_t)0x0160)
/** @defgroup USART_Legacy
* @{
*/
#define USART_IT_ORE USART_IT_ORE_ER
/**
* @}
*/
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
......@@ -253,6 +263,7 @@ typedef struct
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_wwdg.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the WWDG firmware
* library.
******************************************************************************
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file misc.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides all the miscellaneous firmware functions (add-on
* to CMSIS functions).
*
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_adc.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* - Initialization and Configuration (in addition to ADC multi mode
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_can.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Controller area network (CAN) peripheral:
* - Initialization and Configuration
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_crc.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides all the CRC firmware functions.
******************************************************************************
* @attention
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_cryp.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Cryptographic processor (CRYP) peripheral:
* - Initialization and Configuration functions
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_cryp_aes.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides high level functions to encrypt and decrypt an
* input message using AES in ECB/CBC/CTR modes.
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_cryp_des.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides high level functions to encrypt and decrypt an
* input message using DES in ECB/CBC modes.
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_tdes.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_cryp_tdes.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides high level functions to encrypt and decrypt an
* input message using TDES in ECB/CBC modes .
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dac.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dac.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
* - DAC channels configuration: trigger, output buffer, data format
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dbgmcu.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides all the DBGMCU firmware functions.
******************************************************************************
* @attention
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dcmi.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the DCMI peripheral:
* - Initialization and Configuration
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dma.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access controller (DMA):
* - Initialization and Configuration
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_exti.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the EXTI peripheral:
* - Initialization and Configuration
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_flash.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the FLASH peripheral:
* - FLASH Interface configuration
......@@ -119,13 +119,13 @@
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 |
|5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 |
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 |
|6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 |
|---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120|
|7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120|
|***************|****************|****************|*****************|*****************|*****************************+
| | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V |
......@@ -134,7 +134,9 @@
|---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
|PSIZE[1:0] | 10 | 01 | 00 | 11 |
+-------------------------------------------------------------------------------------------------------------------+
@note When VOS bit (in PWR_CR register) is reset to '0’, the maximum value of HCLK is 144 MHz.
You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
- void FLASH_PrefetchBufferCmd(FunctionalState NewState)
- void FLASH_InstructionCacheCmd(FunctionalState NewState)
- void FLASH_DataCacheCmd(FunctionalState NewState)
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_fsmc.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the FSMC peripheral:
* - Interface with SRAM, PSRAM, NOR and OneNAND memories
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_gpio.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the GPIO peripheral:
* - Initialization and Configuration
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hash.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the HASH / HMAC Processor (HASH) peripheral:
* - Initialization and Configuration functions
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hash_md5.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides high level functions to compute the HASH MD5 and
* HMAC MD5 Digest of an input message.
* It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_sha1.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hash_sha1.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides high level functions to compute the HASH SHA1 and
* HMAC SHA1 Digest of an input message.
* It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_i2c.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_i2c.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Inter-integrated circuit (I2C)
* - Initialization and Configuration
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_iwdg.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Independent watchdog (IWDG) peripheral:
* - Prescaler and Counter configuration
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c
浏览文件 @ 017e673c
......@@ -2,15 +2,15 @@
******************************************************************************
* @file stm32f4xx_pwr.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* - Backup Domain Access
* - PVD configuration
* - WakeUp pin configuration
* - Backup Regulator configuration
* - Performance Mode and FLASH Power Down configuration functions
* - Main and Backup Regulators configuration
* - FLASH Power Down configuration
* - Low Power modes configuration
* - Flags management
*
......@@ -249,12 +249,12 @@ void PWR_WakeUpPinCmd(FunctionalState NewState)
* @}
*/
/** @defgroup PWR_Group4 Backup Regulator configuration functions
* @brief Backup Regulator configuration functions
/** @defgroup PWR_Group4 Main and Backup Regulators configuration functions
* @brief Main and Backup Regulators configuration functions
*
@verbatim
===============================================================================
Backup Regulator configuration functions
Main and Backup Regulators configuration functions
===============================================================================
- The backup domain includes 4 Kbytes of backup SRAM accessible only from the
......@@ -275,6 +275,16 @@ void PWR_WakeUpPinCmd(FunctionalState NewState)
a protection level change from level 1 to level 0 is requested.
Refer to the description of Read protection (RDP) in the Flash programming manual.
- The main internal regulator can be configured to have a tradeoff between performance
and power consumption when the device does not operate at the maximum frequency.
This is done through PWR_MainRegulatorModeConfig() function which configure VOS bit
in PWR_CR register:
- When this bit is set (Regulator voltage output Scale 1 mode selected) the System
frequency can go up to 168 MHz.
- When this bit is reset (Regulator voltage output Scale 2 mode selected) the System
frequency can go up to 144 MHz.
Refer to the datasheets for more details.
@endverbatim
* @{
*/
......@@ -293,24 +303,45 @@ void PWR_BackupRegulatorCmd(FunctionalState NewState)
*(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
}
/**
* @brief Configures the main internal regulator output voltage.
* @param PWR_Regulator_Voltage: specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption when the device does
* not operate at the maximum frequency (refer to the datasheets for more details).
* This parameter can be one of the following values:
* @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode,
* System frequency up to 168 MHz.
* @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode,
* System frequency up to 144 MHz.
* @retval None
*/
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
{
/* Check the parameters */
assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
if (PWR_Regulator_Voltage == PWR_Regulator_Voltage_Scale2)
{
PWR->CR &= ~PWR_Regulator_Voltage_Scale1;
}
else
{
PWR->CR |= PWR_Regulator_Voltage_Scale1;
}
}
/**
* @}
*/
/** @defgroup PWR_Group5 Performance Mode and FLASH Power Down configuration functions
* @brief Performance Mode and FLASH Power Down configuration functions
/** @defgroup PWR_Group5 FLASH Power Down configuration functions
* @brief FLASH Power Down configuration functions
*
@verbatim
===============================================================================
Performance Mode and FLASH Power Down configuration functions
FLASH Power Down configuration functions
===============================================================================
- By setting the PMODE bit in the PWR_CR register by using the PWR_HighPerformanceModeCmd()
function, the high performance mode is selected and the high voltage regulator
minimum value should be around 1.2V.
When reset, the low performance mode is selected and the low voltage regulator
minimum value should be around 1.08V.
- By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd()
function, the Flash memory also enters power down mode when the device enters
Stop mode. When the Flash memory is in power down mode, an additional startup
......@@ -320,20 +351,6 @@ void PWR_BackupRegulatorCmd(FunctionalState NewState)
* @{
*/
/**
* @brief Enables or disables the high performance mode.
* @param NewState: new state of the performance mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_HighPerformanceModeCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CR_PMODE_BB = (uint32_t)NewState;
}
/**
* @brief Enables or disables the Flash Power Down in STOP mode.
* @param NewState: new state of the Flash power mode.
......@@ -581,7 +598,8 @@ void PWR_EnterSTANDBYMode(void)
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
* when the device wakes up from Standby mode or by a system reset
* or power reset.
* @arg PWR_FLAG_REGRDY: Main regulator ready flag.
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
* scaling output selection is ready.
* @retval The new state of PWR_FLAG (SET or RESET).
*/
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
浏览文件 @ 017e673c
......@@ -2,10 +2,10 @@
******************************************************************************
* @file stm32f4xx_rcc.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Reset and clock control (RCC) peripheral:
* functionalities of the Reset and clock control (RCC) peripheral:
* - Internal/external clocks, PLL, CSS and MCO configuration
* - System, AHB and APB busses clocks configuration
* - Peripheral clocks configuration
......@@ -156,7 +156,7 @@ static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6
4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
5. PLL (clocked by HSI or HSE), featuring two different output clocks:
- The first output is used to generate the high speed system clock (up to 120 MHz)
- The first output is used to generate the high speed system clock (up to 168 MHz)
- The second output is used to generate the clock for the USB OTG FS (48 MHz),
the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
......@@ -421,7 +421,7 @@ void RCC_LSICmd(FunctionalState NewState)
*
* @param PLLP: specifies the division factor for main system clock (SYSCLK)
* This parameter must be a number in the range {2, 4, 6, or 8}.
* @note You have to set the PLLP parameter correctly to not exceed 120 MHz on
* @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
* the System clock frequency.
*
* @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
......@@ -465,8 +465,7 @@ void RCC_PLLCmd(FunctionalState NewState)
/**
* @brief Configures the PLLI2S clock multiplication and division factors.
*
* @note PLLI2S is available only in Silicon RevisionB and RevisionY.
*
* @note This function must be used only when the PLLI2S is disabled.
* @note PLLI2S clock source is common with the main PLL (configured in
* RCC_PLLConfig function )
......@@ -493,8 +492,7 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
}
/**
* @brief Enables or disables the PLLI2S.
* @note PLLI2S is available only in RevisionB and RevisionY
* @brief Enables or disables the PLLI2S.
* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
* @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
* @retval None
......@@ -635,7 +633,7 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
to 48. This clock is derived of the main PLL through PLLQ divider.
- IWDG clock which is always the LSI clock.
2. The maximum frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz.
2. The maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 82 MHz and PCLK1 42 MHz.
Depending on the device voltage range, the maximum frequency should be
adapted accordingly:
+-------------------------------------------------------------------------------------+
......@@ -652,15 +650,16 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 |
|5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 |
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 |
|6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 |
|---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120|
|7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120|
+-------------------------------------------------------------------------------------+
@note When VOS bit (in PWR_CR register) is reset to '0’, the maximum value of HCLK is 144 MHz.
You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
@endverbatim
* @{
......@@ -1036,10 +1035,7 @@ void RCC_BackupResetCmd(FunctionalState NewState)
/**
* @brief Configures the I2S clock source (I2SCLK).
*
* @note This function must be called before enabling the I2S APB clock.
* @note This function applies only to Silicon RevisionB and RevisionY.
*
* @param RCC_I2SCLKSource: specifies the I2S clock source.
* This parameter can be one of the following values:
* @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
......@@ -1073,6 +1069,7 @@ void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
* @arg RCC_AHB1Periph_GPIOI: GPIOI clock
* @arg RCC_AHB1Periph_CRC: CRC clock
* @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
* @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
* @arg RCC_AHB1Periph_DMA1: DMA1 clock
* @arg RCC_AHB1Periph_DMA2: DMA2 clock
* @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rng.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
* - Initialization and Configuration
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rtc.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Real-Time Clock (RTC) peripheral:
* - Initialization
......@@ -1039,7 +1039,7 @@ void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);
RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);
/* Check the input parameters format */
if (RTC_Format == RTC_Format_BIN)
......@@ -1048,7 +1048,6 @@ void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay);
}
}
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_sdio.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Secure digital input/output interface (SDIO)
* peripheral:
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c
浏览文件 @ 017e673c
......@@ -2,10 +2,10 @@
******************************************************************************
* @file stm32f4xx_spi.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Serial peripheral interface (SPI):
* functionalities of the Serial peripheral interface (SPI):
* - Initialization and Configuration
* - Data transfers functions
* - Hardware CRC Calculation
......@@ -17,7 +17,7 @@
*
* ===================================================================
* How to use this driver
* ===================================================================
* ===================================================================
*
* 1. Enable peripheral clock using the following functions
* RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1
......@@ -124,10 +124,6 @@
* rxdata[i] = SPI_I2S_ReceiveData(I2S3ext);
* ...
*
*
*
* @note This driver supports only the I2S clock scheme available in Silicon
* RevisionB and RevisionY.
*
* @note In I2S mode: if an external clock is used as source clock for the I2S,
* then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should
......@@ -368,7 +364,7 @@ void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
packetlength = 2;
}
/* Get I2S source Clock frequency (only in Silicon RevisionB and RevisionY) */
/* Get I2S source Clock frequency ****************************************/
/* If an external I2S clock has to be used, this define should be set
in the project configuration or in the stm32f4xx_conf.h file */
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_syscfg.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the SYSCFG peripheral.
*
* @verbatim
......@@ -97,13 +97,6 @@ void SYSCFG_DeInit(void)
* @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
*
* @note In remap mode, the FSMC addressing is fixed to the remap address area only
* (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) and FSMC control registers are not
* accessible. The FSMC remap function must be disabled to allows addressing
* other memory devices through the FSMC and/or to access FSMC control
* registers.
*
* @retval None
*/
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_tim.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the TIM peripheral:
* - TimeBase management
......@@ -482,10 +482,10 @@ void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
* @param TIM_UpdateSource: specifies the Update source.
* This parameter can be one of the following values:
* @arg TIM_UpdateSource_Regular: Source of update is the counter
* @arg TIM_UpdateSource_Global: Source of update is the counter
* overflow/underflow or the setting of UG bit, or an update
* generation through the slave mode controller.
* @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
* @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow.
* @retval None
*/
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
......@@ -1908,6 +1908,7 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
{
/* TI2 Configuration */
assert_param(IS_TIM_LIST2_PERIPH(TIMx));
TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
TIM_ICInitStruct->TIM_ICSelection,
TIM_ICInitStruct->TIM_ICFilter);
......@@ -1917,6 +1918,7 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
{
/* TI3 Configuration */
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
TIM_ICInitStruct->TIM_ICSelection,
TIM_ICInitStruct->TIM_ICFilter);
......@@ -1926,6 +1928,7 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
else
{
/* TI4 Configuration */
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
TIM_ICInitStruct->TIM_ICSelection,
TIM_ICInitStruct->TIM_ICFilter);
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_usart.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Universal synchronous asynchronous receiver
* transmitter (USART):
......@@ -1345,7 +1345,8 @@ void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
* @arg USART_IT_TC: Transmission complete interrupt
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
* @arg USART_IT_IDLE: Idle line detection interrupt
* @arg USART_IT_ORE: OverRun Error interrupt
* @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set
* @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set
* @arg USART_IT_NE: Noise Error interrupt
* @arg USART_IT_FE: Framing Error interrupt
* @arg USART_IT_PE: Parity Error interrupt
......
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c
浏览文件 @ 017e673c
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_wwdg.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Window watchdog (WWDG) peripheral:
* - Prescaler, Refresh window and Counter configuration
......@@ -35,7 +35,7 @@
* WWDG counter clock = PCLK1 / Prescaler
* WWDG timeout = (WWDG counter clock) * (counter value)
*
* Min-max timeout value @30 MHz(PCLK1): ~136.5 us / ~69.9 ms
* Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
*
* ===================================================================
* How to use this driver
......
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