Update IDF to 1e0710f

tools/sdk/include/config/sdkconfig.h

@@ -9,7 +9,6 @@
 #define CONFIG_PHY_ENABLED 1
 #define CONFIG_TRACEMEM_RESERVE_DRAM 0x0
 #define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16
-#define CONFIG_FOUR_MAC_ADDRESS_FROM_EFUSE 1
 #define CONFIG_SW_COEXIST_ENABLE 1
 #define CONFIG_ESPTOOLPY_FLASHSIZE_4MB 1
 #define CONFIG_ESPTOOLPY_FLASHFREQ "80m"
@@ -24,7 +23,6 @@
 #define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1
 #define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 10
 #define CONFIG_BT_RESERVE_DRAM 0x10000
-#define CONFIG_LOG_BOOTLOADER_LEVEL_ERROR 1
 #define CONFIG_CONSOLE_UART_BAUDRATE 115200
 #define CONFIG_LWIP_MAX_SOCKETS 10
 #define CONFIG_EMAC_TASK_PRIORITY 20
@@ -40,8 +38,10 @@
 #define CONFIG_CONSOLE_UART_NUM 0
 #define CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC 1
 #define CONFIG_LWIP_THREAD_LOCAL_STORAGE_INDEX 0
+#define CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS 1
 #define CONFIG_CONSOLE_UART_DEFAULT 1
 #define CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN 16384
+#define CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS 4
 #define CONFIG_ESPTOOLPY_FLASHSIZE_DETECT 1
 #define CONFIG_AUTOSTART_ARDUINO 1
 #define CONFIG_LOG_DEFAULT_LEVEL_ERROR 1
@@ -73,10 +73,8 @@
 #define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv"
 #define CONFIG_LWIP_DHCP_MAX_NTP_SERVERS 1
 #define CONFIG_PARTITION_TABLE_SINGLE_APP 1
-#define CONFIG_NUMBER_OF_MAC_ADDRESS_GENERATED_FROM_EFUSE 4
 #define CONFIG_WIFI_ENABLED 1
 #define CONFIG_FLASHMODE_QIO 1
-#define CONFIG_BASE_MAC_STORED_DEFAULT_EFUSE 1
 #define CONFIG_ESPTOOLPY_FLASHFREQ_80M 1
 #define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE 2048
 #define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000
@@ -90,11 +88,12 @@
 #define CONFIG_FREERTOS_ASSERT_FAIL_ABORT 1
 #define CONFIG_ESP32_XTAL_FREQ 0
 #define CONFIG_MONITOR_BAUD_115200B 1
-#define CONFIG_LOG_BOOTLOADER_LEVEL 1
+#define CONFIG_LOG_BOOTLOADER_LEVEL 0
 #define CONFIG_SMP_ENABLE 1
 #define CONFIG_ESPTOOLPY_BEFORE_RESET 1
 #define CONFIG_ESPTOOLPY_BAUD_OTHER_VAL 115200
 #define CONFIG_ENABLE_ARDUINO_DEPENDS 1
+#define CONFIG_LOG_BOOTLOADER_LEVEL_NONE 1
 #define CONFIG_ESP32_DEFAULT_CPU_FREQ_240 1
 #define CONFIG_ESP32_XTAL_FREQ_AUTO 1
 #define CONFIG_TCP_MAXRTX 12

tools/sdk/include/driver/driver/dac.h

@@ -28,13 +28,31 @@ typedef enum {
     DAC_CHANNEL_MAX,
 } dac_channel_t;
 
+
+/**
+  * @brief  Set DAC output voltage.
+  *
+  * @note Function has been deprecated, please use dac_output_voltage instead.
+  *       This name will be removed in a future release.
+  *       The difference is that before calling dac_output_voltage, we need to initialize the dac pad by dac_output_enable
+  *
+  *
+  * @param channel DAC channel
+  * @param dac_value DAC output value
+  *
+  * @return
+  *     - ESP_OK success
+  *     - ESP_ERR_INVALID_ARG Parameter error
+  */
+esp_err_t dac_out_voltage(dac_channel_t channel, uint8_t dac_value) __attribute__ ((deprecated));
+
 /**
  * @brief Set DAC output voltage.
  *
  * DAC output is 8-bit. Maximum (255) corresponds to VDD.
  *
- * @note When this function is called, function for the DAC
- * channel's GPIO pin is reconfigured for RTC DAC function.
+ * @note Need to configure DAC pad before calling this function.
+ *       DAC channel 1 is attached to GPIO25, DAC channel 2 is attached to GPIO26
  *
  * @param channel DAC channel
  * @param dac_value DAC output value
@@ -43,8 +61,35 @@ typedef enum {
  *     - ESP_OK success
  *     - ESP_ERR_INVALID_ARG Parameter error
  */
-esp_err_t dac_out_voltage(dac_channel_t channel, uint8_t dac_value);
+esp_err_t dac_output_voltage(dac_channel_t channel, uint8_t dac_value);
+
+/**
+ * @brief DAC pad output enable
+ *
+ * @param channel DAC channel
+ * @note DAC channel 1 is attached to GPIO25, DAC channel 2 is attached to GPIO26
+ *       I2S left channel will be mapped to DAC channel 2
+ *       I2S right channel will be mapped to DAC channel 1
+ */
+esp_err_t dac_output_enable(dac_channel_t channel);
+
+/**
+ * @brief DAC pad output disable
+ *
+ * @param channel DAC channel
+ * @note DAC channel 1 is attached to GPIO25, DAC channel 2 is attached to GPIO26
+ */
+esp_err_t dac_output_disable(dac_channel_t channel);
 
+/**
+ * @brief Enable DAC output data from I2S
+ */
+esp_err_t dac_i2s_enable();
+
+/**
+ * @brief Disable DAC output data from I2S
+ */
+esp_err_t dac_i2s_disable();
 #ifdef __cplusplus
 }
 #endif

tools/sdk/include/driver/driver/i2s.h

@@ -109,13 +109,17 @@ typedef enum {
 /**
  * @brief I2S Mode, defaut is I2S_MODE_MASTER | I2S_MODE_TX
  *
+ * @note PDM and built-in DAC functions are only supported on I2S0 for current ESP32 chip.
+ *
  */
 typedef enum {
     I2S_MODE_MASTER = 1,
     I2S_MODE_SLAVE = 2,
     I2S_MODE_TX = 4,
     I2S_MODE_RX = 8,
-    I2S_MODE_DAC_BUILT_IN = 16
+    I2S_MODE_DAC_BUILT_IN = 16,       /*!< Output I2S data to built-in DAC, no matter the data format is 16bit or 32 bit, the DAC module will only take the 8bits from MSB*/
+    //I2S_MODE_ADC_BUILT_IN = 32,     /*!< Currently not supported yet, will be added for the next version*/
+    I2S_MODE_PDM = 64,
 } i2s_mode_t;
 
 /**
@@ -144,6 +148,19 @@ typedef enum {
     I2S_EVENT_MAX,         /*!< I2S event max index*/
 } i2s_event_type_t;
 
+/**
+ * @brief I2S DAC mode for i2s_set_dac_mode.
+ *
+ * @note PDM and built-in DAC functions are only supported on I2S0 for current ESP32 chip.
+ */
+typedef enum {
+    I2S_DAC_CHANNEL_DISABLE  = 0,    /*!< Disable I2S built-in DAC signals*/
+    I2S_DAC_CHANNEL_RIGHT_EN = 1,    /*!< Enable I2S built-in DAC right channel, maps to DAC channel 1 on GPIO25*/
+    I2S_DAC_CHANNEL_LEFT_EN  = 2,    /*!< Enable I2S built-in DAC left  channel, maps to DAC channel 2 on GPIO26*/
+    I2S_DAC_CHANNEL_BOTH_EN  = 0x3,  /*!< Enable both of the I2S built-in DAC channels.*/
+    I2S_DAC_CHANNEL_MAX      = 0x4,  /*!< I2S built-in DAC mode max index*/
+} i2s_dac_mode_t;
+
 /**
  * @brief Event structure used in I2S event queue
  *
@@ -166,6 +183,7 @@ typedef struct {
     int data_in_num;    /*!< DATA in pin*/
 } i2s_pin_config_t;
 
+
 typedef intr_handle_t i2s_isr_handle_t;
 /**
  * @brief Set I2S pin number
@@ -181,12 +199,30 @@ typedef intr_handle_t i2s_isr_handle_t;
  * Inside the pin configuration structure, set I2S_PIN_NO_CHANGE for any pin where
  * the current configuration should not be changed.
  *
+ * @note if *pin is set as NULL, this function will initialize both of the built-in DAC channels by default.
+ *       if you don't want this to happen and you want to initialize only one of the DAC channels, you can call i2s_set_dac_mode instead.
+ *
  * @return
  *     - ESP_OK   Success
  *     - ESP_FAIL Parameter error
  */
 esp_err_t i2s_set_pin(i2s_port_t i2s_num, const i2s_pin_config_t *pin);
 
+/**
+ * @brief Set I2S dac mode, I2S built-in DAC is disabled by default
+ *
+ * @param dac_mode DAC mode configurations - see i2s_dac_mode_t
+ *
+ * @note Built-in DAC functions are only supported on I2S0 for current ESP32 chip.
+ *       If either of the built-in DAC channel are enabled, the other one can not
+ *       be used as RTC DAC function at the same time.
+ *
+ * @return
+ *     - ESP_OK  Success
+ *     - ESP_ERR_INVALID_ARG  Parameter error
+ */
+esp_err_t i2s_set_dac_mode(i2s_dac_mode_t dac_mode);
+
 /**
  * @brief Install and start I2S driver.
  *

tools/sdk/include/driver/driver/spi_master.h

@@ -100,6 +100,10 @@ typedef struct spi_device_t* spi_device_handle_t;  ///< Handle for a device on a
  *                 for a SPI bus allows transfers on the bus to have sizes only limited by the amount of 
  *                 internal memory. Selecting no DMA channel (by passing the value 0) limits the amount of
  *                 bytes transfered to a maximum of 32.
+ *
+ * @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in 
+ *          DMA-capable memory.
+ *
  * @return 
  *         - ESP_ERR_INVALID_ARG   if configuration is invalid
  *         - ESP_ERR_INVALID_STATE if host already is in use

tools/sdk/include/driver/driver/spi_slave.h

@@ -69,6 +69,10 @@ struct spi_slave_transaction_t {
  * @param dma_chan Either 1 or 2. A SPI bus used by this driver must have a DMA channel associated with
  *                 it. The SPI hardware has two DMA channels to share. This parameter indicates which
  *                 one to use.
+ *
+ * @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in 
+ *          DMA-capable memory.
+ *
  * @return 
  *         - ESP_ERR_INVALID_ARG   if configuration is invalid
  *         - ESP_ERR_INVALID_STATE if host already is in use

tools/sdk/include/esp32/esp_assert.h

+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __ESP_ASSERT_H__
+#define __ESP_ASSERT_H__
+
+#include "assert.h"
+
+/* Assert at compile time if possible, runtime otherwise */
+#ifndef __cplusplus
+/* __builtin_choose_expr() is only in C, makes this a lot cleaner */
+#define TRY_STATIC_ASSERT(CONDITION, MSG) do {                                                              \
+            _Static_assert(__builtin_choose_expr(__builtin_constant_p(CONDITION), (CONDITION), 1), #MSG);   \
+            assert(#MSG && (CONDITION));                                                                    \
+        } while(0)
+#else
+/* for C++, use __attribute__((error)) - works almost as well as _Static_assert */
+#define TRY_STATIC_ASSERT(CONDITION, MSG) do {                                                              \
+            if (__builtin_constant_p(CONDITION) && !(CONDITION)) {          \
+                extern __attribute__((error(#MSG))) void failed_compile_time_assert(void);      \
+                failed_compile_time_assert();                                                   \
+            }                                                                                   \
+            assert(#MSG && (CONDITION));                                                                    \
+        } while(0)
+#endif /* __cplusplus */
+
+#endif /* __ESP_ASSERT_H__ */

tools/sdk/include/esp32/esp_dport_access.h

+// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESP_DPORT_ACCESS_H_
+#define _ESP_DPORT_ACCESS_H_
+
+void esp_dport_access_stall_other_cpu_start(void);
+void esp_dport_access_stall_other_cpu_end(void);
+void esp_dport_access_int_init(void);
+
+#endif /* _ESP_DPORT_ACCESS_H_ */

tools/sdk/include/esp32/esp_err.h

@@ -37,6 +37,8 @@ typedef int32_t esp_err_t;
 #define ESP_ERR_TIMEOUT         0x107
 #define ESP_ERR_INVALID_RESPONSE    0x108
 #define ESP_ERR_INVALID_CRC     0x109
+#define ESP_ERR_INVALID_VERSION     0x10A
+#define ESP_ERR_INVALID_MAC     0x10B
 
 #define ESP_ERR_WIFI_BASE       0x3000 /*!< Starting number of WiFi error codes */
 

tools/sdk/include/esp32/esp_heap_alloc_caps.h

@@ -87,4 +87,17 @@ size_t xPortGetMinimumEverFreeHeapSizeCaps( uint32_t caps );
 
 
 
+/**
+ * @brief Convenience function to check if a pointer is DMA-capable.
+ *
+ * @param ptr         Pointer to check
+ *
+ * @return True if DMA-capable, false if not.
+ */
+static inline bool  esp_ptr_dma_capable( const void *ptr ) 
+{
+    return ( (int)ptr >= 0x3FFAE000 && (int)ptr < 0x40000000 );
+}
+
+
 #endif
\ No newline at end of file

tools/sdk/include/esp32/esp_system.h

@@ -31,9 +31,9 @@ typedef enum {
     ESP_MAC_ETH,
 } esp_mac_type_t;
 
-#define TWO_MAC_ADDRESS_FROM_EFUSE 2
-#define FOUR_MAC_ADDRESS_FROM_EFUSE 4
-#define NUM_MAC_ADDRESS_FROM_EFUSE CONFIG_NUMBER_OF_MAC_ADDRESS_GENERATED_FROM_EFUSE
+#define TWO_UNIVERSAL_MAC_ADDR 2
+#define FOUR_UNIVERSAL_MAC_ADDR 4
+#define UNIVERSAL_MAC_ADDR_NUM CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS
 
 /**
   * @attention  application don't need to call this function anymore. It do nothing and will
@@ -103,60 +103,84 @@ uint32_t system_get_free_heap_size(void)  __attribute__ ((deprecated));
 uint32_t esp_random(void);
 
 /**
-  * @brief  Set base MAC address from external storage e.g. flash and EEPROM.
+  * @brief  Set base MAC address with the MAC address which is stored in BLK3 of EFUSE or
+  *         external storage e.g. flash and EEPROM.
   *
   * Base MAC address is used to generate the MAC addresses used by the networking interfaces.
-  * If using base MAC address stored in external storage, call this API to set base MAC
-  * address from external storage before initializing WiFi/BT/Ethernet.
+  * If using base MAC address stored in BLK3 of EFUSE or external storage, call this API to set base MAC
+  * address with the MAC address which is stored in BLK3 of EFUSE or external storage before initializing
+  * WiFi/BT/Ethernet.
   *
   * @param  mac  base MAC address, length: 6 bytes.
   *
   * @return ESP_OK on success
   */
-esp_err_t esp_base_mac_addr_set_external(uint8_t *mac);
+esp_err_t esp_base_mac_addr_set(uint8_t *mac);
 
 /**
-  * @brief  Return base MAC address set using esp_mac_addr_set_external.
+  * @brief  Return base MAC address which is set using esp_base_mac_addr_set.
   *
   * @param  mac  base MAC address, length: 6 bytes.
   *
+  * @return ESP_OK on success
+  *         ESP_ERR_INVALID_MAC base MAC address has not been set
+  */
+esp_err_t esp_base_mac_addr_get(uint8_t *mac);
+
+/**
+  * @brief  Return base MAC address which was previously written to BLK3 of EFUSE.
+  *
   * Base MAC address is used to generate the MAC addresses used by the networking interfaces.
-  * If using base MAC address stored in external storage, call this API to set base MAC
-  * address from external storage before initializing WiFi/BT/Ethernet.
+  * This API returns the custom base MAC address which was previously written to BLK3 of EFUSE.
+  * Writing this EFUSE allows setting of a different (non-Espressif) base MAC address. It is also
+  * possible to store a custom base MAC address elsewhere, see esp_base_mac_addr_set() for details.
+  *
+  * @param  mac  base MAC address, length: 6 bytes.
   *
   * @return ESP_OK on success
+  *         ESP_ERR_INVALID_VERSION An invalid MAC version field was read from BLK3 of EFUSE
+  *         ESP_ERR_INVALID_CRC An invalid MAC CRC was read from BLK3 of EFUSE
   */
-esp_err_t esp_base_mac_addr_get_external(uint8_t *mac);
+esp_err_t esp_efuse_mac_get_custom(uint8_t *mac);
+
+/**
+  * @brief  Return base MAC address which is factory-programmed by Espressif in BLK0 of EFUSE.
+  *
+  * @param  mac  base MAC address, length: 6 bytes.
+  *
+  * @return ESP_OK on success
+  */
+esp_err_t esp_efuse_mac_get_default(uint8_t *mac);
 
 /**
   * @brief  Read hardware MAC address from efuse.
   *
-  * In WiFi MAC, only ESP32 station MAC is the hardware MAC, ESP32 softAP MAC is a software MAC 
-  * calculated from ESP32 station MAC. 
-  * So users need to call esp_wifi_get_macaddr to query the ESP32 softAP MAC if ESP32 station MAC changed.
+  * Function has been renamed to esp_efuse_mac_get_default.
+  * This name will be removed in a future release.
   *
   * @param  mac  hardware MAC address, length: 6 bytes.
   *
   * @return ESP_OK on success
   */
-esp_err_t esp_efuse_read_mac(uint8_t* mac);
+esp_err_t esp_efuse_read_mac(uint8_t *mac) __attribute__ ((deprecated));
 
 /**
   * @brief  Read hardware MAC address.
   *
-  * Function has been renamed to esp_efuse_read_mac.
+  * Function has been renamed to esp_efuse_mac_get_default.
   * This name will be removed in a future release.
   *
   * @param  mac  hardware MAC address, length: 6 bytes.
   * @return ESP_OK on success
   */
-esp_err_t system_efuse_read_mac(uint8_t mac[6]) __attribute__ ((deprecated));
+esp_err_t system_efuse_read_mac(uint8_t *mac) __attribute__ ((deprecated));
 
 /**
-  * @brief  Read hardware MAC address and set MAC address of the interface.
+  * @brief  Read base MAC address and set MAC address of the interface.
   *
-  * This function first reads hardware MAC address from efuse. Then set the MAC address of the interface
-  * including wifi station, wifi softap, bluetooth and ethernet.
+  * This function first get base MAC address using esp_base_mac_addr_get or reads base MAC address
+  * from BLK0 of EFUSE. Then set the MAC address of the interface including wifi station, wifi softap,
+  * bluetooth and ethernet.
   *
   * @param  mac  MAC address of the interface, length: 6 bytes.
   * @param  type  type of MAC address, 0:wifi station, 1:wifi softap, 2:bluetooth, 3:ethernet.
@@ -166,32 +190,20 @@ esp_err_t system_efuse_read_mac(uint8_t mac[6]) __attribute__ ((deprecated));
 esp_err_t esp_read_mac(uint8_t* mac, esp_mac_type_t type);
 
 /**
-  * @brief  Derive MAC address.
+  * @brief  Derive local MAC address from universal MAC address.
   *
   * This function derives a local MAC address from an universal MAC address.
-  * Addresses can either be universally administered addresses or locally administered addresses.
-  * A universally administered address is uniquely assigned to a device by its manufacturer.
-  * The first three octets (in transmission order) identify the organization that issued the identifier
-  * and are known as the Organizationally Unique Identifier (OUI).[4] The remainder of the address
-  * (three octets for MAC-48 and EUI-48 or five for EUI-64) are assigned by that organization in nearly
-  * any manner they please, subject to the constraint of uniqueness. A locally administered address is
-  * assigned to a device by a network administrator, overriding the burned-in address.
-  * Universally administered and locally administered addresses are distinguished by setting
-  * the second-least-significant bit of the first octet of the address. This bit is also referred to
-  * as the U/L bit, short for Universal/Local, which identifies how the address is administered.
-  * If the bit is 0, the address is universally administered. If it is 1, the address is locally administered.
-  * In the example address 06-00-00-00-00-00 the first octet is 06 (hex), the binary form of which is 00000110,
-  * where the second-least-significant bit is 1. Therefore, it is a locally administered address.[7] Consequently,
-  * this bit is 0 in all OUIs.
-  * In ESP32, universal MAC address is generated from the hardware MAC address in efuse.
+  * A `definition of local vs universal MAC address can be found on Wikipedia
+  * <https://en.wikipedia.org/wiki/MAC_address#Universal_vs._local>`.
+  * In ESP32, universal MAC address is generated from base MAC address in EFUSE or other external storage.
   * Local MAC address is derived from the universal MAC address.
   *
-  * @param  dst_mac  Derived local MAC address, length: 6 bytes.
-  * @param  src_mac  Source universal MAC address, length: 6 bytes.
+  * @param  local_mac  Derived local MAC address, length: 6 bytes.
+  * @param  universal_mac  Source universal MAC address, length: 6 bytes.
   *
   * @return ESP_OK on success
   */
-esp_err_t esp_derive_mac(uint8_t* dst_mac, const uint8_t* src_mac);
+esp_err_t esp_derive_local_mac(uint8_t* local_mac, const uint8_t* universal_mac);
 
 /**
  * Get SDK version
@@ -209,6 +221,38 @@ const char* system_get_sdk_version(void)  __attribute__ ((deprecated));
  */
 const char* esp_get_idf_version(void);
 
+
+/**
+ * @brief Chip models
+ */
+typedef enum {
+    CHIP_ESP32 = 1, //!< ESP32
+} esp_chip_model_t;
+
+/**
+ * Chip feature flags, used in esp_chip_info_t
+ */
+#define CHIP_FEATURE_EMB_FLASH      BIT(0)
+#define CHIP_FEATURE_WIFI_BGN       BIT(1)
+#define CHIP_FEATURE_BLE            BIT(4)
+#define CHIP_FEATURE_BT             BIT(5)
+
+/**
+ * @brief The structure represents information about the chip
+ */
+typedef struct {
+    esp_chip_model_t model;  //!< chip model, one of esp_chip_model_t
+    uint32_t features;       //!< bit mask of CHIP_FEATURE_x feature flags
+    uint8_t cores;           //!< number of CPU cores
+    uint8_t revision;        //!< chip revision number
+} esp_chip_info_t;
+
+/**
+ * @brief Fill an esp_chip_info_t structure with information about the chip
+ * @param[out] out_info structure to be filled
+ */
+void esp_chip_info(esp_chip_info_t* out_info);
+
 #ifdef __cplusplus
 }
 #endif

tools/sdk/include/esp32/rom/cache.h

@@ -15,6 +15,8 @@
 #ifndef _ROM_CACHE_H_
 #define _ROM_CACHE_H_
 
+#include "soc/dport_access.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -64,7 +66,18 @@ void mmu_init(int cpu_no);
   *                   4 : mmu table to be written is out of range
   *                   5 : vaddr is out of range
   */
-unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr,  int psize, int num);
+static inline unsigned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr,  int psize, int num)
+{
+    extern unsigned int cache_flash_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr,  int psize, int num);
+
+    unsigned int ret;
+
+    DPORT_STALL_OTHER_CPU_START();
+    ret = cache_flash_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
+    DPORT_STALL_OTHER_CPU_END();
+
+    return ret;
+}
 
 /**
   * @brief Set Ext-SRAM-Cache mmu mapping.
@@ -93,7 +106,18 @@ unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsign
   *                   4 : mmu table to be written is out of range
   *                   5 : vaddr is out of range
   */
-unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
+static inline unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num)
+{
+    extern unsigned int cache_sram_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
+
+    unsigned int ret;
+
+    DPORT_STALL_OTHER_CPU_START();
+    ret = cache_sram_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
+    DPORT_STALL_OTHER_CPU_END();
+
+    return ret;
+}
 
 /**
   * @brief Initialise cache access for the cpu.
@@ -103,7 +127,13 @@ unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigne
   *
   * @return None
   */
-void Cache_Read_Init(int cpu_no);
+static inline void IRAM_ATTR Cache_Read_Init(int cpu_no)
+{
+    extern void Cache_Read_Init_rom(int cpu_no);
+    DPORT_STALL_OTHER_CPU_START();
+    Cache_Read_Init_rom(cpu_no);
+    DPORT_STALL_OTHER_CPU_END();
+}
 
 /**
   * @brief Flush the cache value for the cpu.
@@ -113,7 +143,13 @@ void Cache_Read_Init(int cpu_no);
   *
   * @return None
   */
-void Cache_Flush(int cpu_no);
+static inline void IRAM_ATTR Cache_Flush(int cpu_no)
+{
+    extern void Cache_Flush_rom(int cpu_no);
+    DPORT_STALL_OTHER_CPU_START();
+    Cache_Flush_rom(cpu_no);
+    DPORT_STALL_OTHER_CPU_END();
+}
 
 /**
   * @brief Disable Cache access for the cpu.
@@ -123,7 +159,13 @@ void Cache_Flush(int cpu_no);
   *
   * @return None
   */
-void Cache_Read_Disable(int cpu_no);
+static inline void IRAM_ATTR Cache_Read_Disable(int cpu_no)
+{
+    extern void Cache_Read_Disable_rom(int cpu_no);
+    DPORT_STALL_OTHER_CPU_START();
+    Cache_Read_Disable_rom(cpu_no);
+    DPORT_STALL_OTHER_CPU_END();
+}
 
 /**
   * @brief Enable Cache access for the cpu.
@@ -133,7 +175,13 @@ void Cache_Read_Disable(int cpu_no);
   *
   * @return None
   */
-void Cache_Read_Enable(int cpu_no);
+static inline void IRAM_ATTR Cache_Read_Enable(int cpu_no)
+{
+    extern void Cache_Read_Enable_rom(int cpu_no);
+    DPORT_STALL_OTHER_CPU_START();
+    Cache_Read_Enable_rom(cpu_no);
+    DPORT_STALL_OTHER_CPU_END();
+}
 
 /**
   * @}

tools/sdk/include/soc/soc/dport_access.h

+// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DPORT_ACCESS_H_
+#define _DPORT_ACCESS_H_
+
+#include <stdint.h>
+#include "esp_attr.h"
+
+void esp_dport_access_stall_other_cpu_start(void);
+void esp_dport_access_stall_other_cpu_end(void);
+
+#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
+#define DPORT_STALL_OTHER_CPU_START()
+#define DPORT_STALL_OTHER_CPU_END()
+#else
+#define DPORT_STALL_OTHER_CPU_START()   esp_dport_access_stall_other_cpu_start()
+#define DPORT_STALL_OTHER_CPU_END()     esp_dport_access_stall_other_cpu_end()
+#endif
+
+//Registers Operation {{
+//Origin access operation for the base and some special scene
+#define _DPORT_REG_READ(_r)        (*(volatile uint32_t *)(_r))
+#define _DPORT_REG_WRITE(_r, _v)   (*(volatile uint32_t *)(_r)) = (_v)
+
+//write value to register
+#define DPORT_REG_WRITE(_r, _v)   _DPORT_REG_WRITE(_r, _v)
+
+//read value from register
+static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg)
+{
+    uint32_t val;
+
+    DPORT_STALL_OTHER_CPU_START();
+    val = _DPORT_REG_READ(reg);
+    DPORT_STALL_OTHER_CPU_END();
+    
+    return val;
+}
+
+//get bit or get bits from register
+#define DPORT_REG_GET_BIT(_r, _b)  (DPORT_REG_READ(_r) & (_b))
+
+//set bit or set bits to register
+#define DPORT_REG_SET_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
+
+//clear bit or clear bits of register
+#define DPORT_REG_CLR_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
+
+//set bits of register controlled by mask
+#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
+
+//get field from register, uses field _S & _V to determine mask
+#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
+
+//set field to register, used when _f is not left shifted by _f##_S
+#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f) << (_f##_S))))|(((_v) & (_f))<<(_f##_S))))
+
+//get field value from a variable, used when _f is not left shifted by _f##_S
+#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
+
+//get field value from a variable, used when _f is left shifted by _f##_S
+#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
+
+//set field value to a variable, used when _f is not left shifted by _f##_S
+#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
+
+//set field value to a variable, used when _f is left shifted by _f##_S
+#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
+
+//generate a value from a field value, used when _f is not left shifted by _f##_S
+#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
+
+//generate a value from a field value, used when _f is left shifted by _f##_S
+#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
+
+#define _READ_PERI_REG(addr) (*((volatile uint32_t *)(addr))) 
+#define _WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val) 
+
+//read value from register
+static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t addr) 
+{
+    uint32_t val;
+
+    DPORT_STALL_OTHER_CPU_START();
+    val = _READ_PERI_REG(addr);
+    DPORT_STALL_OTHER_CPU_END();
+    
+    return val;
+}
+
+//write value to register
+#define DPORT_WRITE_PERI_REG(addr, val) _WRITE_PERI_REG(addr, val)  
+
+//clear bits of register controlled by mask
+#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
+
+//set bits of register controlled by mask
+#define DPORT_SET_PERI_REG_MASK(reg, mask)   DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
+
+//get bits of register controlled by mask
+#define DPORT_GET_PERI_REG_MASK(reg, mask)   (DPORT_READ_PERI_REG(reg) & (mask))
+
+//get bits of register controlled by highest bit and lowest bit
+#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos)     ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
+
+//set bits of register controlled by mask and shift
+#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg),(DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))
+
+//get field of register
+#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift)      ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
+//}}
+
+
+#endif /* _DPORT_ACCESS_H_ */

tools/sdk/include/soc/soc/dport_reg.h

@@ -16,6 +16,14 @@
 
 #include "soc.h"
 
+#ifndef __ASSEMBLER__
+#include "dport_access.h"
+#endif
+   
+/* Registers defined in this header file must be accessed using special macros,
+ * prefixed with DPORT_. See soc/dport_access.h file for details.
+ */
+
 #define DPORT_PRO_BOOT_REMAP_CTRL_REG          (DR_REG_DPORT_BASE + 0x000)
 /* DPORT_PRO_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */
 /*description: */

tools/sdk/include/soc/soc/efuse_reg.h

@@ -79,12 +79,27 @@
 #define EFUSE_RD_WIFI_MAC_CRC_HIGH_S  0
 
 #define EFUSE_BLK0_RDATA3_REG          (DR_REG_EFUSE_BASE + 0x00c)
-/* EFUSE_RD_CHIP_VER_RESERVE : RO ;bitpos:[16:9] ;default: 8'b0 ; */
+/* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: bit is set to 1 for rev1 silicon*/
+#define EFUSE_RD_CHIP_VER_REV1  (BIT(15))
+#define EFUSE_RD_CHIP_VER_REV1_M  ((EFUSE_RD_CHIP_VER_REV1_V)<<(EFUSE_RD_CHIP_VER_REV1_S))
+#define EFUSE_RD_CHIP_VER_REV1_V  0x1
+#define EFUSE_RD_CHIP_VER_REV1_S  15
+/* EFUSE_RD_CHIP_VER_RESERVE : R/W ;bitpos:[15:12] ;default: 3'b0 ; */
 /*description: */
-#define EFUSE_RD_CHIP_VER_RESERVE  0x000000FF
+#define EFUSE_RD_CHIP_VER_RESERVE  0x00000007
 #define EFUSE_RD_CHIP_VER_RESERVE_M  ((EFUSE_RD_CHIP_VER_RESERVE_V)<<(EFUSE_RD_CHIP_VER_RESERVE_S))
-#define EFUSE_RD_CHIP_VER_RESERVE_V  0xFF
-#define EFUSE_RD_CHIP_VER_RESERVE_S  9
+#define EFUSE_RD_CHIP_VER_RESERVE_V  0x7
+#define EFUSE_RD_CHIP_VER_RESERVE_S  12
+/* EFUSE_RD_CHIP_VER : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
+/*description: chip package */
+#define EFUSE_RD_CHIP_VER  0x00000007
+#define EFUSE_RD_CHIP_VER_PKG_M  ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S))
+#define EFUSE_RD_CHIP_VER_PKG_V  0x7
+#define EFUSE_RD_CHIP_VER_PKG_S  9
+#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6  0
+#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5  1
+#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5  2
 /* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */
 /*description: read for SPI_pad_config_hd*/
 #define EFUSE_RD_SPI_PAD_CONFIG_HD  0x0000001F
@@ -297,12 +312,24 @@
 #define EFUSE_WIFI_MAC_CRC_HIGH_S  0
 
 #define EFUSE_BLK0_WDATA3_REG          (DR_REG_EFUSE_BASE + 0x028)
-/* EFUSE_CHIP_VER_RESERVE : R/W ;bitpos:[16:9] ;default: 8'b0 ; */
+/* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
 /*description: */
-#define EFUSE_CHIP_VER_RESERVE  0x000000FF
+#define EFUSE_CHIP_VER_REV1  (BIT(15))
+#define EFUSE_CHIP_VER_REV1_M  ((EFUSE_CHIP_VER_REV1_V)<<(EFUSE_CHIP_VER_REV1_S))
+#define EFUSE_CHIP_VER_REV1_V  0x1
+#define EFUSE_CHIP_VER_REV1_S  15
+/* EFUSE_CHIP_VER_RESERVE : R/W ;bitpos:[15:12] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_CHIP_VER_RESERVE  0x00000007
 #define EFUSE_CHIP_VER_RESERVE_M  ((EFUSE_CHIP_VER_RESERVE_V)<<(EFUSE_CHIP_VER_RESERVE_S))
-#define EFUSE_CHIP_VER_RESERVE_V  0xFF
-#define EFUSE_CHIP_VER_RESERVE_S  9
+#define EFUSE_CHIP_VER_RESERVE_V  0x7
+#define EFUSE_CHIP_VER_RESERVE_S  12
+/* EFUSE_CHIP_VER : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_CHIP_VER_PKG  0x00000007
+#define EFUSE_CHIP_VER_PKG_M  ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S))
+#define EFUSE_CHIP_VER_PKG_V  0x7
+#define EFUSE_CHIP_VER_PKG_S  9
 /* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */
 /*description: program for SPI_pad_config_hd*/
 #define EFUSE_SPI_PAD_CONFIG_HD  0x0000001F

tools/sdk/ld/esp32.peripherals.ld

@@ -12,11 +12,13 @@ PROVIDE ( RMT = 0x3ff56000 );
 PROVIDE ( RMTMEM = 0x3ff56800 );
 PROVIDE ( PCNT = 0x3ff57000 );
 PROVIDE ( LEDC = 0x3ff59000 );
+PROVIDE ( MCPWM0 = 0x3ff5E000 );
 PROVIDE ( TIMERG0 = 0x3ff5F000 );
 PROVIDE ( TIMERG1 = 0x3ff60000 );
 PROVIDE ( SPI2 = 0x3ff64000 );
 PROVIDE ( SPI3 = 0x3ff65000 );
 PROVIDE ( I2C1 = 0x3ff67000 );
+PROVIDE ( MCPWM1 = 0x3ff6C000 );
 PROVIDE ( I2S1 = 0x3ff6D000 );
 PROVIDE ( UART2 = 0x3ff6E000 );
 PROVIDE ( SDMMC = 0x3ff68000 );