- 18 5月, 2020 1 次提交
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由 Sunwancn 提交于
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- 22 3月, 2020 7 次提交
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由 Bernard Xiong 提交于
[bsp/stm32] add support for NUCLEO-F410RB board;
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由 Bernard Xiong 提交于
[bsp/stm32] add the bsp of stm32l496zg-nucleo board
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由 Bernard Xiong 提交于
[drv_adc.c]Fixed ADC channel configuration bug for SMT32F0/L0/H7
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由 Bernard Xiong 提交于
drv_flash_f1.c support stm32f103vg
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由 Bernard Xiong 提交于
add STM32L1 HAL DRIVER
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由 Bernard Xiong 提交于
修复 scons --target=eclipse 时,部分带值宏出错的问题
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由 guozhanxin 提交于
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- 21 3月, 2020 2 次提交
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由 Bernard Xiong 提交于
Fixed typos in Kconfig
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由 tanglj86 提交于
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- 20 3月, 2020 1 次提交
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由 Sunwancn 提交于
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- 19 3月, 2020 1 次提交
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由 Bernard Xiong 提交于
Aarch64 cache api
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- 18 3月, 2020 13 次提交
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由 supperthomas 提交于
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由 supperthomas 提交于
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由 gyd0317 提交于
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由 Bernard Xiong 提交于
fixed a typo
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由 tanglj86 提交于
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由 redoc 提交于
1、【修改】返回值。
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由 redoc 提交于
调整stm32_flash_erase的返回值
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由 redoc 提交于
1、【修改】运算方式,更加简洁易懂; 2、【修正】代码格式 tab、 LOG_D; 3、【增加】返回值; 4、【去除】bank1_flag和bank2_flag,改用bank_size判定。
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由 bigmagic 提交于
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由 bigmagic 提交于
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由 bigmagic 提交于
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由 bigmagic 提交于
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由 luhuadong 提交于
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- 17 3月, 2020 5 次提交
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由 Bernard Xiong 提交于
1. modify at32_msp default configuration 2. add hwtimer driver and fi…
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由 Bernard Xiong 提交于
[readme/update] readme architecture figures
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由 gyd0317 提交于
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由 SummerGift 提交于
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由 sheltonyu 提交于
1. modify at32_msp default configuration 2. add hwtimer driver and fix up some driver errors 3. update related files
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- 16 3月, 2020 10 次提交
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由 supperthomas 提交于
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由 Bernard Xiong 提交于
update readme :Fixed spelling mistakes
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由 Bernard Xiong 提交于
[Sensor] Support custom commands for rt_sensor_control
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由 Bernard Xiong 提交于
[skip ci] Update README.md
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由 Bernard Xiong 提交于
component: sdio: fix potential ricky clock setting
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由 andychen329 提交于
MM32L073PF -> MM32L373PF
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由 Bernard Xiong 提交于
spi: support slave mode and master mode runtime config
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由 Bernard Xiong 提交于
Support msc mode automatic switching
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由 Shawn Lin 提交于
Currently RTT mmc stack only support Highspeed mode or blow, which means the max speed should be 52MHz according to JEDEC spec. Two problems show here: (1) max_data_rate = (unsigned int)-1. The value of unsigned int depends on compilers/arch. Moreover, it makes no sense to assume cpu addressing width with IP clock rate limit. (1)hs_max_data_rate was set to 200MHz. So what should BSP drivers do if 52MHz < max_data_rate < 200MHz? Either it blindly sets a spec-violated clock rate to drive a Highspeed card, or just adjust the clock rate internally. Both cases are really bad for practice. If the card claims to support Highspeed, we set the clock to not to exceed 52MHz. Otherwise it should be set according to card->max_data_rate parsed by ext_csd. This patch fixes it as-is, and also simplify the code a lot. Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
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由 luhuadong 提交于
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