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体验新版 GitCode,发现更多精彩内容 >>
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8430b832
编写于
6月 14, 2018
作者:
X
xieyangrun
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'master' of
https://github.com/RT-Thread/rt-thread
into fixSrcRemove
上级
86ae6146
54674308
变更
8
展开全部
隐藏空白更改
内联
并排
Showing
8 changed file
with
585 addition
and
1348 deletion
+585
-1348
bsp/stm32f40x/drivers/stm32f4_rtc.c
bsp/stm32f40x/drivers/stm32f4_rtc.c
+1
-1
bsp/stm32f429-armfly/.config
bsp/stm32f429-armfly/.config
+52
-21
bsp/stm32f429-armfly/drivers/drv_eth.c
bsp/stm32f429-armfly/drivers/drv_eth.c
+112
-305
bsp/stm32f429-armfly/project.uvprojx
bsp/stm32f429-armfly/project.uvprojx
+381
-897
bsp/stm32f429-armfly/rtconfig.h
bsp/stm32f429-armfly/rtconfig.h
+12
-108
bsp/stm32f429-armfly/template.uvprojx
bsp/stm32f429-armfly/template.uvprojx
+17
-14
libcpu/arm/cortex-m3/context_gcc.S
libcpu/arm/cortex-m3/context_gcc.S
+1
-1
tools/vsc.py
tools/vsc.py
+9
-1
未找到文件。
bsp/stm32f40x/drivers/stm32f4_rtc.c
浏览文件 @
8430b832
...
...
@@ -23,7 +23,7 @@ static int get_week(int year, int month, int day)
year
-=
1
;
month
+=
12
;
}
return
(
day
+
1
+
2
*
month
+
3
*
(
month
+
1
)
/
5
+
year
+
(
year
/
4
)
-
year
/
100
+
year
/
400
)
%
7
;
return
(
day
+
1
+
2
*
month
+
3
*
(
month
+
1
)
/
5
+
year
+
(
year
/
4
)
-
year
/
100
+
year
/
400
)
%
7
+
1
;
}
static
struct
rt_device
rtc
;
...
...
bsp/stm32f429-armfly/.config
浏览文件 @
8430b832
...
...
@@ -47,6 +47,7 @@ CONFIG_RT_USING_HEAP=y
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE
=
y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE
=
y
CONFIG_RT_CONSOLEBUF_SIZE
=
128
...
...
@@ -76,6 +77,7 @@ CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES
=
5
CONFIG_FINSH_USING_SYMTAB
=
y
CONFIG_FINSH_USING_DESCRIPTION
=
y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY
=
20
CONFIG_FINSH_THREAD_STACK_SIZE
=
4096
CONFIG_FINSH_CMD_SIZE
=
80
...
...
@@ -83,6 +85,7 @@ CONFIG_FINSH_CMD_SIZE=80
CONFIG_FINSH_USING_MSH
=
y
CONFIG_FINSH_USING_MSH_DEFAULT
=
y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX
=
10
#
# Device virtual file system
...
...
@@ -111,8 +114,6 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
CONFIG_RT_DFS_ELM_REENTRANT
=
y
CONFIG_RT_USING_DFS_DEVFS
=
y
CONFIG_RT_USING_DFS_NET
=
y
CONFIG_HAVE_SYS_SELECT_H
=
y
# CONFIG_HAVE_SYS_SOCKET_H is not set
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
...
...
@@ -130,6 +131,7 @@ CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_I2C
=
y
CONFIG_RT_USING_I2C_BITOPS
=
y
CONFIG_RT_USING_PIN
=
y
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
CONFIG_RT_USING_RTC
=
y
...
...
@@ -145,6 +147,7 @@ CONFIG_RT_USING_W25QXX=y
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_AUDIO is not set
#
# Using USB
...
...
@@ -161,7 +164,7 @@ CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_AIO is not set
# CONFIG_
HAVE_SYS_SIGNALS
is not set
# CONFIG_
RT_USING_LWP
is not set
#
# Network stack
...
...
@@ -190,7 +193,7 @@ CONFIG_RT_LWIP_GWADDR="192.168.1.1"
CONFIG_RT_LWIP_MSKADDR
=
"255.255.255.0"
CONFIG_RT_LWIP_UDP
=
y
CONFIG_RT_LWIP_TCP
=
y
# CONFIG_RT_LWIP_RAW is not set
CONFIG_RT_LWIP_RAW
=
y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN
=
8
CONFIG_RT_LWIP_PBUF_NUM
=
16
...
...
@@ -203,8 +206,10 @@ CONFIG_RT_LWIP_TCP_WND=8192
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY
=
12
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE
=
4
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE
=
1024
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY
=
15
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE
=
512
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE
=
1024
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE
=
4
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK
=
1
...
...
@@ -242,28 +247,19 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
# RT-Thread online packages
#
#
# system packages
#
#
# RT-Thread GUI Engine
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PAHOMQTT_PIPE_MODE is not set
# CONFIG_PAHOMQTT_UDP_MODE is not set
# CONFIG_PKG_USING_PAHOMQTT_LATEST is not set
# CONFIG_PKG_USING_PAHOMQTT_V100 is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
...
...
@@ -285,6 +281,9 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_NETUTILS_LATEST_VERSION is not set
# CONFIG_PKG_USING_NETUTILS_V100 is not set
# CONFIG_PKG_USING_ONENET is not set
#
# security packages
...
...
@@ -292,6 +291,9 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TINYCRYPT_V110 is not set
# CONFIG_PKG_USING_TINYCRYPT_V100 is not set
# CONFIG_PKG_USING_TINYCRYPT_LATEST_VERSION is not set
#
# language packages
...
...
@@ -303,14 +305,35 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_IPERF is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_STM32F4_HAL is not set
# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
#
# miscellaneous packages
...
...
@@ -318,12 +341,20 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
#
# sample package
#
# CONFIG_PKG_USING_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
CONFIG_RT_USING_EXT_SDRAM
=
y
CONFIG_RT_USING_UART1
=
y
# CONFIG_RT_USING_UART2 is not set
...
...
bsp/stm32f429-armfly/drivers/drv_eth.c
浏览文件 @
8430b832
...
...
@@ -12,17 +12,11 @@
* 2017-06-08 tanek first implementation
*/
#include <rtthread.h>
#include <netif/ethernetif.h>
#include "lwipopts.h"
#include "board.h"
#include <rtdevice.h>
#ifdef RT_USING_FINSH
#include <finsh.h>
#endif
#ifdef RT_USING_LWIP
#include <netif/ethernetif.h>
#include "lwipopts.h"
/* debug option */
//#define DEBUG
...
...
@@ -35,68 +29,39 @@
#define STM32_ETH_PRINTF(...)
#endif
#define MAX_ADDR_LEN 6
#define DM9161_PHY_ADDRESS 0x01U
/* DP83848C and DM9161 PHY Registers is the same */
#define PHY_REG_BMCR 0x00
/* Basic Mode Control Register */
#define PHY_REG_BMSR 0x01
/* Basic Mode Status Register */
#define PHY_REG_IDR1 0x02
/* PHY Identifier 1 */
#define PHY_REG_IDR2 0x03
/* PHY Identifier 2 */
#define PHY_REG_ANAR 0x04
/* Auto-Negotiation Advertisement */
#define PHY_REG_ANLPAR 0x05
/* Auto-Neg. Link Partner Abitily */
#define PHY_REG_ANER 0x06
/* Auto-Neg. Expansion Register */
#define PHY_REG_ANNPTR 0x07
/* Auto-Neg. Next Page TX .DM9161 NO */
/* PHY Extended Registers only for DP83848C */
#define PHY_REG_STS 0x10
/* Status Register */
#define PHY_REG_MICR 0x11
/* MII Interrupt Control Register */
#define PHY_REG_MISR 0x12
/* MII Interrupt Status Register */
#define PHY_REG_FCSCR 0x14
/* False Carrier Sense Counter */
#define PHY_REG_RECR 0x15
/* Receive Error Counter */
#define PHY_REG_PCSR 0x16
/* PCS Sublayer Config. and Status */
#define PHY_REG_RBR 0x17
/* RMII and Bypass Register */
#define PHY_REG_LEDCR 0x18
/* LED Direct Control Register */
#define PHY_REG_PHYCR 0x19
/* PHY Control Register */
#define PHY_REG_10BTSCR 0x1A
/* 10Base-T Status/Control Register */
#define PHY_REG_CDCTRL1 0x1B
/* CD Test Control and BIST Extens. */
#define PHY_REG_EDCR 0x1D
/* Energy Detect Control Register */
/* PHY Extended Registers only for DM9161 */
#define PHY_REG_DSCR 0x10
/* Specified Congfiguration Register */
#define PHY_REG_DSCSR 0x11
/* Specified Congfiguration and Status Register */
#define PHY_REG_10BTCSR 0x12
/* 10Base-T Status/Control Register */
#define PHY_REG_PWDOR 0x13
/* Power Down Control Register */
#define PHY_REG_CONGFIG 0x14
/* Specified Congfig Register */
#define PHY_REG_INTERRUPT 0x15
/* Specified interrupt Register */
#define PHY_REG_SRECR 0x16
/* Specified Receive Error Counter */
#define PHY_REG_DISCR 0x17
/* Specified Disconnect Counter Register */
#define PHY_REG_RLSR 0x18
/* Hardware reset latch state Register */
#define PHY_REG_PSCR 0x1D
/* Power Saving control register */
/* Register BMCR bit defination */
#define PHY_BMCR_FULLD_100M 0x2100
/* Full Duplex 100Mbit */
#define PHY_BMCR_HALFD_100M 0x2000
/* Half Duplex 100Mbit */
#define PHY_BMCR_FULLD_10M 0x0100
/* Full Duplex 10Mbit */
#define PHY_BMCR_HALFD_10M 0x0000
/* Half Duplex 10MBit */
#define PHY_BMCR_AUTO_NEG 0x1000
/* Select Auto Negotiation */
#define PHY_BMCR_RESET ((uint16_t)0x8000U)
/*!< PHY Reset */
#define PHY_BMCR_POWERDOWN ((uint16_t)0x0800U)
/*!< Select the power down mode */
#define PHY_BMSR_AUTONEGO_COMPLETE ((uint16_t)0x0020U)
/*!< Auto-Negotiation process completed */
#define PHY_BMSR_LINKED_STATUS ((uint16_t)0x0004U)
/*!< Valid link established */
#define PHY_DSCSR_100FDX ((uint16_t)0x8000U)
#define PHY_DSCSR_100HDX ((uint16_t)0x4000U)
#define PHY_DSCSR_10FDX ((uint16_t)0x2000U)
#define PHY_DSCSR_10HDX ((uint16_t)0x1000U)
#define PHY_INT_LINK_MASK ((uint16_t)0x0C00U)
#define PHY_INT_LINK_CHANGE ((uint16_t)0x0004U)
/* RMII GPIO
ETH_MDIO -------------------------> PA2
ETH_MDC --------------------------> PC1
ETH_RMII_REF_CLK------------------> PA1
ETH_RMII_CRS_DV ------------------> PA7
ETH_RMII_RXD0 --------------------> PC4
ETH_RMII_RXD1 --------------------> PC5
ETH_RMII_TX_EN -------------------> PB11
ETH_RMII_TXD0 --------------------> PG13
ETH_RMII_TXD1 --------------------> PG14
*/
#define ETH_MDIO_PORN GPIOA
#define ETH_MDIO_PIN GPIO_PIN_2
#define ETH_MDC_PORN GPIOC
#define ETH_MDC_PIN GPIO_PIN_1
#define ETH_RMII_REF_CLK_PORN GPIOA
#define ETH_RMII_REF_CLK_PIN GPIO_PIN_1
#define ETH_RMII_CRS_DV_PORN GPIOA
#define ETH_RMII_CRS_DV_PIN GPIO_PIN_7
#define ETH_RMII_RXD0_PORN GPIOC
#define ETH_RMII_RXD0_PIN GPIO_PIN_4
#define ETH_RMII_RXD1_PORN GPIOC
#define ETH_RMII_RXD1_PIN GPIO_PIN_5
#define ETH_RMII_TX_EN_PORN GPIOG
#define ETH_RMII_TX_EN_PIN GPIO_PIN_11
#define ETH_RMII_TXD0_PORN GPIOG
#define ETH_RMII_TXD0_PIN GPIO_PIN_13
#define ETH_RMII_TXD1_PORN GPIOB
#define ETH_RMII_TXD1_PIN GPIO_PIN_13
#define PHY_ADDRESS 0x01
#define MAX_ADDR_LEN 6
struct
rt_stm32_eth
{
/* inherit from ethernet device */
...
...
@@ -110,75 +75,13 @@ struct rt_stm32_eth
};
ALIGN
(
4
)
ETH_DMADescTypeDef
DMARxDscrTab
[
ETH_RXBUFNB
];
ALIGN
(
4
)
ETH_DMADescTypeDef
DMATxDscrTab
[
ETH_TXBUFNB
];
ALIGN
(
4
)
rt_uint8_t
Rx_Buff
[
ETH_RXBUFNB
][
ETH_MAX_PACKET_SIZE
];
ALIGN
(
4
)
rt_uint8_t
Tx_Buff
[
ETH_TXBUFNB
][
ETH_MAX_PACKET_SIZE
];
static
ETH_DMADescTypeDef
DMARxDscrTab
[
ETH_RXBUFNB
],
DMATxDscrTab
[
ETH_TXBUFNB
];
static
rt_uint8_t
Rx_Buff
[
ETH_RXBUFNB
][
ETH_MAX_PACKET_SIZE
],
Tx_Buff
[
ETH_TXBUFNB
][
ETH_MAX_PACKET_SIZE
];
static
rt_bool_t
tx_is_waiting
=
RT_FALSE
;
static
ETH_HandleTypeDef
EthHandle
;
static
struct
rt_stm32_eth
stm32_eth_device
;
static
struct
rt_semaphore
tx_wait
;
void
HAL_ETH_MspInit
(
ETH_HandleTypeDef
*
heth
)
{
GPIO_InitTypeDef
GPIO_InitStruct
;
if
(
heth
->
Instance
==
ETH
)
{
/* USER CODE BEGIN ETH_MspInit 0 */
/* USER CODE END ETH_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_ETH_CLK_ENABLE
();
__HAL_RCC_GPIOA_CLK_ENABLE
();
__HAL_RCC_GPIOC_CLK_ENABLE
();
__HAL_RCC_GPIOG_CLK_ENABLE
();
/**ETH GPIO Configuration
PC1 ------> ETH_MDC
PA1 ------> ETH_REF_CLK
PA2 ------> ETH_MDIO
PA7 ------> ETH_CRS_DV
PC4 ------> ETH_RXD0
PC5 ------> ETH_RXD1
PG11 ------> ETH_TX_EN
PG13 ------> ETH_TXD0
PB13 ------> ETH_TXD1
*/
GPIO_InitStruct
.
Pin
=
GPIO_PIN_1
|
GPIO_PIN_2
|
GPIO_PIN_7
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF11_ETH
;
HAL_GPIO_Init
(
GPIOA
,
&
GPIO_InitStruct
);
GPIO_InitStruct
.
Pin
=
GPIO_PIN_13
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF11_ETH
;
HAL_GPIO_Init
(
GPIOB
,
&
GPIO_InitStruct
);
GPIO_InitStruct
.
Pin
=
GPIO_PIN_1
|
GPIO_PIN_4
|
GPIO_PIN_5
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF11_ETH
;
HAL_GPIO_Init
(
GPIOC
,
&
GPIO_InitStruct
);
GPIO_InitStruct
.
Pin
=
GPIO_PIN_11
|
GPIO_PIN_13
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_VERY_HIGH
;
GPIO_InitStruct
.
Alternate
=
GPIO_AF11_ETH
;
HAL_GPIO_Init
(
GPIOG
,
&
GPIO_InitStruct
);
/* ETH interrupt Init */
HAL_NVIC_SetPriority
(
ETH_IRQn
,
1
,
0
);
HAL_NVIC_EnableIRQ
(
ETH_IRQn
);
}
}
/* interrupt service routine */
void
ETH_IRQHandler
(
void
)
{
...
...
@@ -213,165 +116,7 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
rt_kprintf
(
"eth err
\n
"
);
}
/**
* @brief This function handles EXTI line[9:5] interrupts.
*/
void
EXTI9_5_IRQHandler
(
void
)
{
HAL_GPIO_EXTI_IRQHandler
(
GPIO_PIN_6
);
}
void
HAL_GPIO_EXTI_Callback
(
uint16_t
GPIO_Pin
)
{
uint32_t
reg_value
=
0
;
int
i
=
10
;
if
(
GPIO_Pin
==
GPIO_PIN_6
)
{
HAL_ETH_ReadPHYRegister
(
&
EthHandle
,
PHY_REG_INTERRUPT
,
&
reg_value
);
if
(
reg_value
&
PHY_INT_LINK_CHANGE
)
{
do
{
HAL_ETH_ReadPHYRegister
(
&
EthHandle
,
PHY_REG_BMSR
,
&
reg_value
);
if
(
reg_value
&
PHY_BMSR_LINKED_STATUS
)
{
eth_device_linkchange
(
&
stm32_eth_device
.
parent
,
RT_TRUE
);
STM32_ETH_PRINTF
(
"eth phy link up
\n
"
);
return
;
}
}
while
(
i
--
);
eth_device_linkchange
(
&
stm32_eth_device
.
parent
,
RT_FALSE
);
STM32_ETH_PRINTF
(
"eth phy link down
\n
"
);
}
}
}
static
void
phy_register_read
(
int
reg
)
{
uint32_t
value
;
if
(
reg
>
0xFF
||
reg
<
0
)
rt_kprintf
(
"reg address error: %d"
,
reg
);
HAL_ETH_ReadPHYRegister
(
&
EthHandle
,
reg
,
&
value
);
rt_kprintf
(
"reg: %02X ==> %08X
\n
"
,
reg
,
value
);
}
#ifdef RT_USING_FINSH
FINSH_FUNCTION_EXPORT_ALIAS
(
phy_register_read
,
phyrd
,
read
phy
registers
);
#endif
static
void
phy_register_write
(
rt_uint16_t
reg
,
rt_uint32_t
value
)
{
if
(
reg
>
0xFF
)
rt_kprintf
(
"reg address error: %d"
,
reg
);
HAL_ETH_WritePHYRegister
(
&
EthHandle
,
reg
,
value
);
rt_kprintf
(
"reg: %02X ==> %08X
\n
"
,
reg
,
value
);
}
#ifdef RT_USING_FINSH
FINSH_FUNCTION_EXPORT_ALIAS
(
phy_register_write
,
phywr
,
write
phy
registers
);
#endif
void
eth_link_exit_config
(
void
)
{
GPIO_InitTypeDef
GPIO_InitStruct
;
__HAL_RCC_GPIOH_CLK_ENABLE
();
/*Configure GPIO pin : PH6 */
GPIO_InitStruct
.
Pin
=
GPIO_PIN_6
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_IT_FALLING
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
HAL_GPIO_Init
(
GPIOH
,
&
GPIO_InitStruct
);
/* EXTI9_5_IRQn interrupt configuration */
HAL_NVIC_SetPriority
(
EXTI9_5_IRQn
,
0
,
0
);
HAL_NVIC_EnableIRQ
(
EXTI9_5_IRQn
);
}
rt_err_t
eth_phy_init
(
void
)
{
uint32_t
reg_value
=
0
;
int
i
,
j
,
k
;
HAL_ETH_WritePHYRegister
(
&
EthHandle
,
PHY_REG_BMCR
,
PHY_RESET
);
for
(
i
=
0x10000
;
i
>
0
;
i
--
)
{
HAL_ETH_ReadPHYRegister
(
&
EthHandle
,
PHY_REG_BMCR
,
&
reg_value
);
if
(
!
(
reg_value
&
(
PHY_BMCR_RESET
|
PHY_BMCR_POWERDOWN
)))
{
STM32_ETH_PRINTF
(
"PHY Reset Finsh
\n
"
);
break
;
}
}
if
(
i
<=
0
)
{
STM32_ETH_PRINTF
(
"PHY Power Up Error: %08X
\n
"
,
reg_value
);
return
-
RT_ETIMEOUT
;
}
HAL_ETH_WritePHYRegister
(
&
EthHandle
,
PHY_REG_BMCR
,
PHY_AUTONEGOTIATION
);
for
(
j
=
0x10000
;
j
>
0
;
j
--
)
{
HAL_ETH_ReadPHYRegister
(
&
EthHandle
,
PHY_REG_BMSR
,
&
reg_value
);
if
(
reg_value
&
PHY_BMSR_AUTONEGO_COMPLETE
)
{
STM32_ETH_PRINTF
(
"Autonegotiation Complete
\n
"
);
/* Autonegotiation Complete. */
break
;
}
}
if
(
j
<=
0
)
{
STM32_ETH_PRINTF
(
"Autonegotiation failed: %08X
\n
"
,
reg_value
);
return
-
RT_ETIMEOUT
;
}
/* Check the link status. */
for
(
k
=
0x10000
;
k
>
0
;
k
--
)
{
HAL_ETH_ReadPHYRegister
(
&
EthHandle
,
PHY_REG_BMSR
,
&
reg_value
);
if
(
reg_value
&
PHY_LINKED_STATUS
)
{
/* Link */
/* Link is on, get connection info */
HAL_ETH_ReadPHYRegister
(
&
EthHandle
,
PHY_REG_DSCSR
,
&
reg_value
);
if
((
reg_value
&
(
PHY_DSCSR_100FDX
|
PHY_DSCSR_100HDX
)))
STM32_ETH_PRINTF
(
"100M "
);
else
STM32_ETH_PRINTF
(
"10M "
);
if
((
reg_value
&
(
PHY_DSCSR_100FDX
|
PHY_DSCSR_10FDX
)))
STM32_ETH_PRINTF
(
"Full"
);
else
STM32_ETH_PRINTF
(
"Half"
);
STM32_ETH_PRINTF
(
" Duplex Operation Mode
\n
"
);
break
;
}
}
if
(
k
<=
0
)
{
STM32_ETH_PRINTF
(
"check link status failed: %08X
\n
"
,
reg_value
);
return
-
RT_ETIMEOUT
;
}
HAL_ETH_WritePHYRegister
(
&
EthHandle
,
PHY_REG_INTERRUPT
,
PHY_INT_LINK_MASK
);
STM32_ETH_PRINTF
(
"Reset try: %d
\n
"
,
i
);
STM32_ETH_PRINTF
(
"Autonegotiation try: %d
\n
"
,
j
);
STM32_ETH_PRINTF
(
"Check try: %d
\n
"
,
k
);
return
RT_EOK
;
}
/* initialize the interface */
static
rt_err_t
rt_stm32_eth_init
(
rt_device_t
dev
)
...
...
@@ -380,6 +125,7 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
__HAL_RCC_ETH_CLK_ENABLE
();
/* ETHERNET Configuration --------------------------------------------------*/
EthHandle
.
Instance
=
ETH
;
EthHandle
.
Init
.
MACAddr
=
(
rt_uint8_t
*
)
&
stm32_eth_device
.
dev_addr
[
0
];
...
...
@@ -389,8 +135,7 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
EthHandle
.
Init
.
MediaInterface
=
ETH_MEDIA_INTERFACE_RMII
;
EthHandle
.
Init
.
RxMode
=
ETH_RXINTERRUPT_MODE
;
EthHandle
.
Init
.
ChecksumMode
=
ETH_CHECKSUM_BY_SOFTWARE
;
//EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
EthHandle
.
Init
.
PhyAddress
=
DM9161_PHY_ADDRESS
;
EthHandle
.
Init
.
PhyAddress
=
PHY_ADDRESS
;
HAL_ETH_DeInit
(
&
EthHandle
);
...
...
@@ -403,7 +148,7 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
{
STM32_ETH_PRINTF
(
"eth hardware init faild...
\n
"
);
}
/* Initialize Tx Descriptors list: Chain Mode */
HAL_ETH_DMATxDescListInit
(
&
EthHandle
,
DMATxDscrTab
,
&
Tx_Buff
[
0
][
0
],
ETH_TXBUFNB
);
...
...
@@ -420,8 +165,6 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev)
STM32_ETH_PRINTF
(
"eth hardware start faild...
\n
"
);
}
eth_phy_init
();
eth_link_exit_config
();
return
RT_EOK
;
}
...
...
@@ -526,9 +269,7 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
while
(
(
byteslefttocopy
+
bufferoffset
)
>
ETH_TX_BUF_SIZE
)
{
/* Copy data to Tx buffer*/
memcpy
(
(
uint8_t
*
)((
uint8_t
*
)
buffer
+
bufferoffset
),
(
uint8_t
*
)((
uint8_t
*
)
q
->
payload
+
payloadoffset
),
(
ETH_TX_BUF_SIZE
-
bufferoffset
)
);
memcpy
(
(
uint8_t
*
)((
uint8_t
*
)
buffer
+
bufferoffset
),
(
uint8_t
*
)((
uint8_t
*
)
q
->
payload
+
payloadoffset
),
(
ETH_TX_BUF_SIZE
-
bufferoffset
)
);
/* Point to next descriptor */
DmaTxDesc
=
(
ETH_DMADescTypeDef
*
)(
DmaTxDesc
->
Buffer2NextDescAddr
);
...
...
@@ -550,9 +291,7 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
}
/* Copy the remaining bytes */
memcpy
(
(
uint8_t
*
)((
uint8_t
*
)
buffer
+
bufferoffset
),
(
uint8_t
*
)((
uint8_t
*
)
q
->
payload
+
payloadoffset
),
byteslefttocopy
);
memcpy
(
(
uint8_t
*
)((
uint8_t
*
)
buffer
+
bufferoffset
),
(
uint8_t
*
)((
uint8_t
*
)
q
->
payload
+
payloadoffset
),
byteslefttocopy
);
bufferoffset
=
bufferoffset
+
byteslefttocopy
;
framelength
=
framelength
+
byteslefttocopy
;
}
...
...
@@ -627,7 +366,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
state
=
HAL_ETH_GetReceivedFrame_IT
(
&
EthHandle
);
if
(
state
!=
HAL_OK
)
{
//
STM32_ETH_PRINTF("receive frame faild\n");
STM32_ETH_PRINTF
(
"receive frame faild
\n
"
);
return
NULL
;
}
...
...
@@ -721,6 +460,72 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
return
p
;
}
static
void
NVIC_Configuration
(
void
)
{
/* Enable the Ethernet global Interrupt */
HAL_NVIC_SetPriority
(
ETH_IRQn
,
0x7
,
0
);
HAL_NVIC_EnableIRQ
(
ETH_IRQn
);
}
/*
* GPIO Configuration for ETH
*/
static
void
GPIO_Configuration
(
void
)
{
GPIO_InitTypeDef
GPIO_InitStructure
;
STM32_ETH_PRINTF
(
"GPIO_Configuration...
\n
"
);
/* Enable SYSCFG clock */
__HAL_RCC_ETH_CLK_ENABLE
();
__HAL_RCC_GPIOA_CLK_ENABLE
();
__HAL_RCC_GPIOB_CLK_ENABLE
();
__HAL_RCC_GPIOC_CLK_ENABLE
();
__HAL_RCC_GPIOG_CLK_ENABLE
();
GPIO_InitStructure
.
Speed
=
GPIO_SPEED_HIGH
;
GPIO_InitStructure
.
Mode
=
GPIO_MODE_AF_PP
;
GPIO_InitStructure
.
Alternate
=
GPIO_AF11_ETH
;
GPIO_InitStructure
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStructure
.
Pin
=
ETH_MDIO_PIN
;
HAL_GPIO_Init
(
ETH_MDIO_PORN
,
&
GPIO_InitStructure
);
GPIO_InitStructure
.
Pin
=
ETH_MDC_PIN
;
HAL_GPIO_Init
(
ETH_MDC_PORN
,
&
GPIO_InitStructure
);
GPIO_InitStructure
.
Pin
=
ETH_RMII_REF_CLK_PIN
;
HAL_GPIO_Init
(
ETH_RMII_REF_CLK_PORN
,
&
GPIO_InitStructure
);
GPIO_InitStructure
.
Pin
=
ETH_RMII_CRS_DV_PIN
;
HAL_GPIO_Init
(
ETH_RMII_CRS_DV_PORN
,
&
GPIO_InitStructure
);
GPIO_InitStructure
.
Pin
=
ETH_RMII_REF_CLK_PIN
;
HAL_GPIO_Init
(
ETH_RMII_REF_CLK_PORN
,
&
GPIO_InitStructure
);
GPIO_InitStructure
.
Pin
=
ETH_RMII_CRS_DV_PIN
;
HAL_GPIO_Init
(
ETH_RMII_CRS_DV_PORN
,
&
GPIO_InitStructure
);
GPIO_InitStructure
.
Pin
=
ETH_RMII_RXD0_PIN
;
HAL_GPIO_Init
(
ETH_RMII_RXD0_PORN
,
&
GPIO_InitStructure
);
GPIO_InitStructure
.
Pin
=
ETH_RMII_RXD1_PIN
;
HAL_GPIO_Init
(
ETH_RMII_RXD1_PORN
,
&
GPIO_InitStructure
);
GPIO_InitStructure
.
Pin
=
ETH_RMII_TX_EN_PIN
;
HAL_GPIO_Init
(
ETH_RMII_TX_EN_PORN
,
&
GPIO_InitStructure
);
GPIO_InitStructure
.
Pin
=
ETH_RMII_TXD0_PIN
;
HAL_GPIO_Init
(
ETH_RMII_TXD0_PORN
,
&
GPIO_InitStructure
);
GPIO_InitStructure
.
Pin
=
ETH_RMII_TXD1_PIN
;
HAL_GPIO_Init
(
ETH_RMII_TXD1_PORN
,
&
GPIO_InitStructure
);
HAL_NVIC_SetPriority
(
ETH_IRQn
,
1
,
0
);
HAL_NVIC_EnableIRQ
(
ETH_IRQn
);
}
void
HAL_ETH_MspInit
(
ETH_HandleTypeDef
*
heth
)
{
GPIO_Configuration
();
NVIC_Configuration
();
}
static
int
rt_hw_stm32_eth_init
(
void
)
{
rt_err_t
state
;
...
...
@@ -763,7 +568,9 @@ static int rt_hw_stm32_eth_init(void)
{
STM32_ETH_PRINTF
(
"eth_device_init faild: %d
\r\n
"
,
state
);
}
eth_device_linkchange
(
&
stm32_eth_device
.
parent
,
RT_TRUE
);
//linkup the e0 for lwip to check
return
state
;
}
INIT_DEVICE_EXPORT
(
rt_hw_stm32_eth_init
);
#endif
INIT_APP_EXPORT
(
rt_hw_stm32_eth_init
);
bsp/stm32f429-armfly/project.uvprojx
浏览文件 @
8430b832
此差异已折叠。
点击以展开。
bsp/stm32f429-armfly/rtconfig.h
浏览文件 @
8430b832
...
...
@@ -10,9 +10,7 @@
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
/* RT_THREAD_PRIORITY_8 is not set */
#define RT_THREAD_PRIORITY_32
/* RT_THREAD_PRIORITY_256 is not set */
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_DEBUG
...
...
@@ -21,7 +19,6 @@
#define RT_DEBUG_THREAD 0
#define RT_USING_HOOK
#define IDLE_THREAD_STACK_SIZE 1024
/* RT_USING_TIMER_SOFT is not set */
/* Inter-Thread communication */
...
...
@@ -30,26 +27,20 @@
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* RT_USING_SIGNALS is not set */
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
/* RT_USING_NOHEAP is not set */
/* RT_USING_SMALL_MEM is not set */
/* RT_USING_SLAB is not set */
#define RT_USING_MEMHEAP_AS_HEAP
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
/* RT_USING_INTERRUPT_INFO is not set */
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
/* RT_USING_MODULE is not set */
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M4
...
...
@@ -57,11 +48,9 @@
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
/* RT_USING_USER_MAIN is not set */
/* C++ features */
/* RT_USING_CPLUSPLUS is not set */
/* Command shell */
...
...
@@ -74,10 +63,9 @@
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
/* FINSH_USING_AUTH is not set */
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
/* FINSH_USING_MSH_ONLY is not set */
#define FINSH_ARG_MAX 10
/* Device virtual file system */
...
...
@@ -93,77 +81,41 @@
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_0
/* RT_DFS_ELM_USE_LFN_1 is not set */
/* RT_DFS_ELM_USE_LFN_2 is not set */
/* RT_DFS_ELM_USE_LFN_3 is not set */
#define RT_DFS_ELM_USE_LFN 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
/* RT_DFS_ELM_USE_ERASE is not set */
#define RT_DFS_ELM_REENTRANT
#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_NET
#define HAVE_SYS_SELECT_H
/* HAVE_SYS_SOCKET_H is not set */
/* RT_USING_DFS_ROMFS is not set */
/* RT_USING_DFS_RAMFS is not set */
/* RT_USING_DFS_UFFS is not set */
/* RT_USING_DFS_JFFS2 is not set */
/* RT_USING_DFS_NFS is not set */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_USING_SERIAL
/* RT_USING_CAN is not set */
/* RT_USING_HWTIMER is not set */
/* RT_USING_CPUTIME is not set */
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_PIN
/* RT_USING_MTD_NOR is not set */
/* RT_USING_MTD_NAND is not set */
#define RT_USING_RTC
/* RT_USING_SOFT_RTC is not set */
/* RTC_SYNC_USING_NTP is not set */
/* RT_USING_SDIO is not set */
#define RT_USING_SPI
/* RT_USING_SPI_MSD is not set */
/* RT_USING_SFUD is not set */
#define RT_USING_W25QXX
/* RT_USING_GD is not set */
/* RT_USING_ENC28J60 is not set */
/* RT_USING_SPI_WIFI is not set */
/* RT_USING_WDT is not set */
/* RT_USING_WIFI is not set */
/* Using USB */
/* RT_USING_USB_HOST is not set */
/* RT_USING_USB_DEVICE is not set */
/* POSIX layer and C standard library */
#define RT_USING_LIBC
/* RT_USING_PTHREADS is not set */
#define RT_USING_POSIX
/* RT_USING_POSIX_MMAP is not set */
/* RT_USING_POSIX_TERMIOS is not set */
/* RT_USING_POSIX_AIO is not set */
/* HAVE_SYS_SIGNALS is not set */
/* Network stack */
/* light weight TCP/IP stack */
#define RT_USING_LWIP
/* RT_USING_LWIP141 is not set */
#define RT_USING_LWIP202
/* RT_USING_LWIP_IPV6 is not set */
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
/* RT_LWIP_SNMP is not set */
#define RT_LWIP_DNS
#define RT_LWIP_DHCP
#define IP_SOF_BROADCAST 1
...
...
@@ -176,8 +128,7 @@
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
/* RT_LWIP_RAW is not set */
/* RT_LWIP_PPP is not set */
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 16
#define RT_LWIP_RAW_PCB_NUM 4
...
...
@@ -190,116 +141,69 @@
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
#define RT_LWIP_ETHTHREAD_PRIORITY 15
#define RT_LWIP_ETHTHREAD_STACKSIZE
512
#define RT_LWIP_ETHTHREAD_STACKSIZE
1024
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
/* RT_LWIP_REASSEMBLY_FRAG is not set */
#define LWIP_NETIF_STATUS_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
/* RT_LWIP_NETIF_LOOPBACK is not set */
#define LWIP_NETIF_LOOPBACK 0
/* Modbus master and slave stack */
/* RT_USING_MODBUS is not set */
/* LWIP_USING_DHCPD is not set */
/* VBUS(Virtual Software BUS) */
/* RT_USING_VBUS is not set */
/* Utilities */
/* RT_USING_LOGTRACE is not set */
/* RT_USING_RYM is not set */
/* ARM CMSIS */
/* RT_USING_CMSIS_OS is not set */
/* RT_USING_RTT_CMSIS is not set */
/* RT-Thread online packages */
/* system packages */
/* RT-Thread GUI Engine */
/* PKG_USING_GUIENGINE is not set */
/* PKG_USING_PERSIMMON is not set */
/* PKG_USING_LWEXT4 is not set */
/* PKG_USING_PARTITION is not set */
/* PKG_USING_SQLITE is not set */
/* PKG_USING_RTI is not set */
/* IoT - internet of things */
/* PKG_USING_PAHOMQTT is not set */
/* PKG_USING_WEBCLIENT is not set */
/* PKG_USING_MONGOOSE is not set */
/* PKG_USING_WEBTERMINAL is not set */
/* PKG_USING_CJSON is not set */
/* PKG_USING_LJSON is not set */
/* PKG_USING_EZXML is not set */
/* PKG_USING_NANOPB is not set */
/* PKG_USING_GAGENT_CLOUD is not set */
/* Wi-Fi */
/* Marvell WiFi */
/* PKG_USING_WLANMARVELL is not set */
/* Wiced WiFi */
/* PKG_USING_WLAN_WICED is not set */
/* PKG_USING_COAP is not set */
/* PKG_USING_NOPOLL is not set */
/* PKG_USING_NETUTILS is not set */
/* security packages */
/* PKG_USING_MBEDTLS is not set */
/* PKG_USING_libsodium is not set */
/* PKG_USING_TINYCRYPT is not set */
/* language packages */
/* PKG_USING_JERRYSCRIPT is not set */
/* PKG_USING_MICROPYTHON is not set */
/* multimedia packages */
/* PKG_USING_OPENMV is not set */
/* tools packages */
/* PKG_USING_CMBACKTRACE is not set */
/* PKG_USING_EASYLOGGER is not set */
/* PKG_USING_SYSTEMVIEW is not set */
/* PKG_USING_IPERF is not set */
/* system packages */
/* peripheral libraries and drivers */
/* miscellaneous packages */
/* PKG_USING_FASTLZ is not set */
/*
PKG_USING_MINILZO is not set
*/
/* PKG_USING_QUICKLZ is not set */
/*
sample package
*/
/* example package: hello */
/* PKG_USING_HELLO is not set */
/* PKG_USING_MULTIBUTTON is not set */
#define RT_USING_EXT_SDRAM
#define RT_USING_UART1
/* RT_USING_UART2 is not set */
/* RT_USING_UART3 is not set */
#define RT_USING_SPI1
/* RT_USING_SPI2 is not set */
/* RT_USING_SPI3 is not set */
/* RT_USING_SPI4 is not set */
/* RT_USING_SPI5 is not set */
/* RT_USING_SPI6 is not set */
#define RT_RTC_NAME "rtc"
#endif
bsp/stm32f429-armfly/template.uvprojx
浏览文件 @
8430b832
...
...
@@ -10,28 +10,30 @@
<TargetName>
rt-thread_stm32f4xx
</TargetName>
<ToolsetNumber>
0x4
</ToolsetNumber>
<ToolsetName>
ARM-ADS
</ToolsetName>
<pCCUsed>
5060750::V5.06 update 6 (build 750)::ARMCC
</pCCUsed>
<uAC6>
0
</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>
STM32F429
ZG
</Device>
<Device>
STM32F429
BITx
</Device>
<Vendor>
STMicroelectronics
</Vendor>
<PackID>
Keil.STM32F4xx_DFP.2.11.0
</PackID>
<PackURL>
http://www.keil.com/pack
</PackURL>
<Cpu>
IRAM(0x20000000,0x30000) IRAM2(0x10000000,0x10000) IROM(0x08000000,0x
1
00000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE
</Cpu>
<Cpu>
IRAM(0x20000000,0x30000) IRAM2(0x10000000,0x10000) IROM(0x08000000,0x
2
00000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE
</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>
UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_
1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F429ZG$CMSIS\Flash\STM32F4xx_1024
.FLM))
</FlashDriverDll>
<DeviceId>
7029
</DeviceId>
<RegisterFile>
$$Device:STM32F429
ZG
$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h
</RegisterFile>
<FlashDriverDll>
UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_
2048 -FS08000000 -FL0200000 -FP0($$Device:STM32F429BITx$CMSIS\Flash\STM32F4xx_2048
.FLM))
</FlashDriverDll>
<DeviceId>
0
</DeviceId>
<RegisterFile>
$$Device:STM32F429
BITx
$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h
</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc>
-DSTM32F429_439xx
</SLE66CMisc>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>
$$Device:STM32F429
ZG
$CMSIS\SVD\STM32F429x.svd
</SFDFile>
<SFDFile>
$$Device:STM32F429
BITx
$CMSIS\SVD\STM32F429x.svd
</SFDFile>
<bCustSvd>
0
</bCustSvd>
<UseEnv>
0
</UseEnv>
<BinPath></BinPath>
...
...
@@ -52,7 +54,7 @@
<CreateLib>
0
</CreateLib>
<CreateHexFile>
0
</CreateHexFile>
<DebugInformation>
1
</DebugInformation>
<BrowseInformation>
1
</BrowseInformation>
<BrowseInformation>
0
</BrowseInformation>
<ListingPath>
.\build\
</ListingPath>
<HexFormatSelection>
1
</HexFormatSelection>
<Merge32K>
0
</Merge32K>
...
...
@@ -108,11 +110,11 @@
</CommonProperty>
<DllOption>
<SimDllName>
SARMCM3.DLL
</SimDllName>
<SimDllArguments>
-MPU -REMAP
</SimDllArguments>
<SimDllArguments>
-REMAP -MPU
</SimDllArguments>
<SimDlgDll>
DCM.DLL
</SimDlgDll>
<SimDlgDllArguments>
-pCM4
</SimDlgDllArguments>
<TargetDllName>
SARMCM3.DLL
</TargetDllName>
<TargetDllArguments>
-MPU
</TargetDllArguments>
<TargetDllArguments>
-MPU
</TargetDllArguments>
<TargetDlgDll>
TCM.DLL
</TargetDlgDll>
<TargetDlgDllArguments>
-pCM4
</TargetDlgDllArguments>
</DllOption>
...
...
@@ -247,7 +249,7 @@
<IROM>
<Type>
1
</Type>
<StartAddress>
0x8000000
</StartAddress>
<Size>
0x
1
00000
</Size>
<Size>
0x
2
00000
</Size>
</IROM>
<XRAM>
<Type>
0
</Type>
...
...
@@ -272,7 +274,7 @@
<OCR_RVCT4>
<Type>
1
</Type>
<StartAddress>
0x8000000
</StartAddress>
<Size>
0x
1
00000
</Size>
<Size>
0x
2
00000
</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>
1
</Type>
...
...
@@ -322,6 +324,7 @@
<uThumb>
0
</uThumb>
<uSurpInc>
0
</uSurpInc>
<uC99>
0
</uC99>
<uGnu>
0
</uGnu>
<useXO>
0
</useXO>
<v6Lang>
1
</v6Lang>
<v6LangP>
1
</v6LangP>
...
...
@@ -385,8 +388,8 @@
<RTE>
<apis/>
<components>
<component
Cclass=
"CMSIS"
Cgroup=
"CORE"
Cvendor=
"ARM"
Cversion=
"5.
0
.1"
condition=
"ARMv6_7_8-M Device"
>
<package
name=
"CMSIS"
schemaVersion=
"1.3"
url=
"http://www.keil.com/pack/"
vendor=
"ARM"
version=
"5.
0.1
"
/>
<component
Cclass=
"CMSIS"
Cgroup=
"CORE"
Cvendor=
"ARM"
Cversion=
"5.
1
.1"
condition=
"ARMv6_7_8-M Device"
>
<package
name=
"CMSIS"
schemaVersion=
"1.3"
url=
"http://www.keil.com/pack/"
vendor=
"ARM"
version=
"5.
3.0
"
/>
<targetInfos>
<targetInfo
name=
"rt-thread_stm32f4xx"
/>
</targetInfos>
...
...
libcpu/arm/cortex-m3/context_gcc.S
浏览文件 @
8430b832
...
...
@@ -188,7 +188,7 @@ _get_sp_done:
STMFD
r0
!,
{
r4
-
r11
}
/*
push
r4
-
r11
register
*/
STMFD
r0
!,
{
lr
}
/*
push
exec_return
register
*/
TST
lr
,
#
0x04
/*
if
(!
EXC_RETURN
[
2
])
TST
lr
,
#
0x04
/*
if
(!
EXC_RETURN
[
2
])
*/
BEQ
_update_msp
MSR
psp
,
r0
/*
update
stack
pointer
to
PSP
.
*/
B
_update_done
...
...
tools/vsc.py
浏览文件 @
8430b832
...
...
@@ -46,13 +46,21 @@ def GenerateCFiles(env):
config_obj
=
{}
config_obj
[
'name'
]
=
'Win32'
config_obj
[
'includePath'
]
=
info
[
'CPPPATH'
]
config_obj
[
'defines'
]
=
info
[
'CPPDEFINES'
]
config_obj
[
'intelliSenseMode'
]
=
'clang-x64'
config_obj
[
'compilerPath'
]
=
cc
config_obj
[
'cStandard'
]
=
"c99"
config_obj
[
'cppStandard'
]
=
"c++11"
# format "a/b," to a/b. remove first quotation mark("),and remove end (",)
includePath
=
[]
for
i
in
info
[
'CPPPATH'
]:
if
i
[
0
]
==
'
\"
'
and
i
[
len
(
i
)
-
2
:
len
(
i
)]
==
'
\"
,'
:
includePath
.
append
(
i
[
1
:
len
(
i
)
-
2
])
else
:
includePath
.
append
(
i
)
config_obj
[
'includePath'
]
=
includePath
json_obj
=
{}
json_obj
[
'configurations'
]
=
[
config_obj
]
...
...
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