Update sdram (#6280)

增加1170系列SDRAM时钟配置
修复sdram中memheap自动初始化时机错误导致被assert的情况
Co-authored-by: Meco Man <920369182@qq.com>

bsp/imxrt/imxrt1170-nxp-evk/board/ports/sdram_port.h

@@ -7,6 +7,7 @@
  * Date           Author       Notes
  * 2018-12-05     zylx         The first version for STM32F4xx
  * 2019-4-25      misonyo      port to IMXRT
+ * 2022-08-15     xjy198903    add sdram config for rt1170
  */
 
 #ifndef SDRAM_PORT_H__
@@ -19,10 +20,17 @@
 #define SDRAM_REGION                    kSEMC_SDRAM_CS0
 /* CS pin: kSEMC_MUXCSX0/1/2/3 */
 #define SDRAM_CS_PIN                    kSEMC_MUXCSX0
+/* size(kbyte):64MB = 2*32*1024*1KBytes */
+#if defined(SOC_IMXRT1170_SERIES)
+#define SDRAM_SIZE                      ((uint32_t)(0x10000))
+/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize32Bit */
+#define SDRAM_DATA_WIDTH                kSEMC_PortSize32Bit
+#else
 /* size(kbyte):32MB = 32*1024*1KBytes */
 #define SDRAM_SIZE                      ((uint32_t)0x8000)
 /* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */
 #define SDRAM_DATA_WIDTH                kSEMC_PortSize16Bit
+#endif
 /* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */
 #define SDRAM_COLUMN_BITS               kSEMC_SdramColunm_9bit
 /* cas latency clock number: kSEMC_LatencyOne/Two/Three */

bsp/imxrt/libraries/MIMXRT1170/SConscript

@@ -40,6 +40,9 @@ if GetDepend(['BSP_USING_PWM']):
 if GetDepend(['BSP_USING_SDIO']):
     src += ['MIMXRT1176/drivers/fsl_usdhc.c']
 
+if GetDepend(['BSP_USING_SDRAM']):
+    src += ['MIMXRT1176/drivers/fsl_semc.c']
+
 if rtconfig.CROSS_TOOL == 'gcc':
     group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, ASFLAGS = '$ASFLAGS -D __STARTUP_CLEAR_BSS')
 else:

bsp/imxrt/libraries/drivers/drv_sdram.c

@@ -17,16 +17,21 @@
 #define LOG_TAG             "drv.sdram"
 #include <drv_log.h>
 
-#ifdef RT_USING_MEMHEAP_AS_HEAP
+#ifdef RT_USING_MEMHEAP
 static struct rt_memheap system_heap;
 #endif
 
-int rt_hw_sdram_Init(void)
+static int rt_hw_sdram_init(void)
 {
     int result = RT_EOK;
     semc_config_t config;
     semc_sdram_config_t sdramconfig;
+    
+#if defined(SOC_IMXRT1170_SERIES)
+    rt_uint32_t clockFrq = CLOCK_GetRootClockFreq(kCLOCK_Root_Semc);
+#else
     rt_uint32_t clockFrq = CLOCK_GetFreq(kCLOCK_SemcClk);
+#endif
 
     /* Initializes the MAC configure structure to zero. */
     memset(&config, 0, sizeof(semc_config_t));
@@ -67,9 +72,9 @@ int rt_hw_sdram_Init(void)
     else
     {
         LOG_D("sdram init success, mapped at 0x%X, size is %d Kbytes.", SDRAM_BANK_ADDR, SDRAM_SIZE);
-#ifdef RT_USING_MEMHEAP_AS_HEAP
+#ifdef RT_USING_MEMHEAP
     /*
-     * If RT_USING_MEMHEAP_AS_HEAP is enabled, SDRAM is initialized to the heap.
+     * If RT_USING_MEMHEAP is enabled, SDRAM is initialized to the heap.
      * The heap start address is (base + half size), and the size is (half size - 2M).
      * The reasons are:
      *      1. Reserve the half space for SDRAM link case
@@ -82,7 +87,7 @@ int rt_hw_sdram_Init(void)
 
     return result;
 }
-INIT_BOARD_EXPORT(rt_hw_sdram_Init);
+INIT_PREV_EXPORT(rt_hw_sdram_init);
 
 #ifdef DRV_DEBUG
 #ifdef FINSH_USING_MSH
@@ -92,7 +97,7 @@ rt_uint32_t sdram_writeBuffer[SEMC_DATALEN];
 rt_uint32_t sdram_readBuffer[SEMC_DATALEN];
 
 /* read write 32bit test */
-void sdram_test(void)
+static void sdram_test(void)
 {
     rt_uint32_t index;
     rt_uint32_t datalen = SEMC_DATALEN;