- 14 12月, 2012 6 次提交
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由 Alexander Graf 提交于
Now that our interrupt controller supports MSIs, let's expose that feature to the guest through the device tree! Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
This patch converts the OpenPIC device to qdev. Along the way it renames the "openpic" target to "raven" and the "mpic" target to "fsl_mpic_20", to better reflect the actual models they implement. This way we have a generic OpenPIC device now that can handle different flavors of the OpenPIC specification. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
The current openpic emulation contains half-ready code for bypass mode. Remove it, so that when someone wants to finish it they can start from a clean state. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
MPIC interrupt numbers in Linux (device tree) and in QEMU are different, because QEMU takes the sparseness of the IRQ number space into account. Remove that cleverness and instead assume a flat number space. This makes the code easier to understand, because we are actually aligned with Linux on the view of our worlds. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Bharat Bhushan 提交于
PCI Root complex have TYPE-1 configuration header while PCI endpoint have type-0 configuration header. The type-1 configuration header have a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci address space to CCSR address space. This can used for 2 purposes: 1) for MSI interrupt generation 2) Allow CCSR registers access when configured as PCI endpoint, which I am not sure is a use case with QEMU-KVM guest. What I observed is that when guest read the size of BAR0 of host controller configuration header (TYPE1 header) then it always reads it as 0. When looking into the QEMU hw/ppce500_pci.c, I do not find the PCI controller device registering BAR0. I do not find any other controller also doing so may they do not use BAR0. There are two issues when BAR0 is not there (which I can think of): 1) There should be BAR0 emulated for PCI Root complex (TYPE1 header) and when reading the size of BAR0, it should give size as per real h/w. 2) Do we need this BAR0 inbound address translation? When BAR0 is of non-zero size then it will be configured for PCI address space to local address(CCSR) space translation on inbound access. The primary use case is for MSI interrupt generation. The device is configured with an address offsets in PCI address space, which will be translated to MSI interrupt generation MPIC registers. Currently I do not understand the MSI interrupt generation mechanism in QEMU and also IIRC we do not use QEMU MSI interrupt mechanism on e500 guest machines. But this BAR0 will be used when using MSI on e500. I can see one more issue, There are ATMUs emulated in hw/ppce500_pci.c, but i do not see these being used for address translation. So far that works because pci address space and local address space are 1:1 mapped. BAR0 inbound translation + ATMU translation will complete the address translation of inbound traffic. Signed-off-by: NBharat Bhushan <bharat.bhushan@freescale.com> [agraf: fix double variable assignment w/o read] Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Bharat Bhushan 提交于
All devices are also placed under CCSR memory region. The CCSR memory region is exported to pci device. The MSI interrupt generation is the main reason to export the CCSR region to PCI device. This put the requirement to move mpic under CCSR region, but logically all devices should be under CCSR. So this patch places all emulated devices under ccsr region. Signed-off-by: NBharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 29 10月, 2012 2 次提交
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由 Alexander Graf 提交于
On PPC, we don't have PIO. So usually PIO space behind a PCI bridge is accessible via MMIO. Do this mapping explicitly by mapping the PIO space of our PCI bus into a memory region that lives in memory space. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Bharat Bhushan 提交于
it was wrongly using serial_hds[0] instead of serial_hds[1] Signed-off-by: NBharat Bhushan <bharat.bhushan@freescale.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 23 10月, 2012 2 次提交
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由 Avi Kivity 提交于
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: NAvi Kivity <avi@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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由 Gerd Hoffmann 提交于
Split serial.c into serial.c, serial.h and serial-isa.c. While being at creating a serial.h header file move the serial prototypes from pc.h to the new serial.h. The latter leads to s/pc.h/serial.h/ in tons of boards which just want the serial bits from pc.h Signed-off-by: NGerd Hoffmann <kraxel@redhat.com> Signed-off-by: NAnthony Liguori <aliguori@us.ibm.com>
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- 05 10月, 2012 4 次提交
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由 Alexander Graf 提交于
When booting our e500 machine, we automatically generate a big TLB entry in TLB1 that covers all of the code we need to run in there until the guest can handle its TLB on its own. However, e500v2 can only handle MAS1.0 sizes. However, we keep our TLB information in MAS2.0 layout, which means we have twice as many TLB sizes to choose from. That also means we can run into a situation where we try to add a TLB size that could not fit into the MAS1.0 size bits. Fix it by making sure we always have the lower bit set to 0. That way we are always guaranteed to have MAS1.0 compatible TLB size information. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Scott Wood 提交于
While investigating dtb pad issues, I noticed that initrd_base wasn't taking loadaddr into account the way dt_base was. This seems wrong. Signed-off-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Scott Wood 提交于
An allowance of 5 MiB for BSS is not enough for Linux kernels with certain debug options enabled (not sure exactly which one caused it, but I'd guess lockdep). The kernel I ran into this with had a BSS of around 6.4 MB. Unfortunately, uImage does not give us enough information to determine the actual BSS size. Increase the allowance to 18 MiB to give us plenty of room. Eventually this should be more intelligent, possibly packing initrd+dtb at the end of guest RAM. Signed-off-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
The dumpdtb code can be useful in more places than just for e500. Move it to a generic place. Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 16 8月, 2012 4 次提交
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由 Alexander Graf 提交于
This reverts commit 518c7fb4. It breaks new Linux guests with SMP, because IPIs get mapped to large vectors which our MPIC emulation does not implement. Conflicts: hw/ppc/e500.c
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由 Scott Wood 提交于
Currently the only mpc8544ds-ism that is factored out is toplevel compatible and model. In the future the generic e500 code is expected to become more generic. Signed-off-by: NScott Wood <scottwood@freescale.com> [agraf: conditionalize on CONFIG_FDT] Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Scott Wood 提交于
No functional changes -- machine is still outwardly mpc8544ds. The references that are not changed contain mpc8544 hardware details that need to be parameterized if/when a different e500 platform wants to change them. Signed-off-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Scott Wood 提交于
Rename the file (with no changes other than fixing up the header paths) in preparation for refactoring into a generic e500 platform. Also move it into the newly created ppc/ directory. Signed-off-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> [agraf: conditionalize on CONFIG_FDT] Signed-off-by: NAlexander Graf <agraf@suse.de>
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- 24 6月, 2012 22 次提交
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由 Alexander Graf 提交于
On the e500 series, accessing SPR_EPR magically turns into an access at that CPU's IACK register on the MPIC. Implement that logic to get kernels that make use of that feature work. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Device trees usually have a node /compatible, which indicate which machine type we're looking at. For quick prototyping, it can be very useful to change the contents of that node via the command line. Thus, introduce a new option to -machine called dt_compatible, which when set changes the /compatible contents to its value. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
When generating serial port device tree nodes, we duplicate quite a bit of code, because there are 2 of them in the mpc8544ds board we emulate. Shove the generating code into a function, so we duplicate less code. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We want to be able to support >= 4GB of RAM. To do so, we need to be able to tell the guest OS how much RAM it has. However, that information today is capped to 32bit. So let's extend the offset and size fields to 64bit, so we can fit in big addresses and even one day - if we wish to do so - map devices above 32bit. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Every time we use an address constant, it needs to potentially fit into a 64bit physical address space. So let's define things accordingly. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Due to popular demand, let's clean up the soc node a bit and use more recent dt notions. Requested-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Due to popular demand, we're updating the way we generate the MPIC node and interrupt lines based on what the current state of art is. Requested-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We want to be able to override the automatically created device tree by using the -dtb option. Implement this for the mpc8544ds machine. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We're passing the ram size as uint32_t, capping it to 32 bits atm. Change to target_phys_addr_t (uint64_t) to make sure we have all the bits. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
We have a nice 64bit helper to ease the device tree generation and make the code more readable when creating 64bit 2-cell parameters. Use it when generating the device tree. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Now that we are dynamically creating the dtb, it's really useful to be able to dump the created blob for debugging. This patch implements a -machine dumpdtb=<file> option for e500 that dumps the dtb exactly in the form the guest would get it to disk. It can then be analyzed by dtc to get information about the guest configuration. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Now that all of the device tree bits are generated during runtime, we can get rid of the device tree blob and instead start from scratch with an empty device tree. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Signed-off-by: NAlexander Graf <agraf@suse.de>
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