- 17 6月, 2020 2 次提交
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由 Pavel Dovgalyuk 提交于
Windows guest sometimes makes DMA requests with overlapping target addresses. This leads to the following structure of iov for the block driver: addr size1 addr size2 addr size3 It means that three adjacent disk blocks should be read into the same memory buffer. Windows does not expects anything from these bytes (should it be data from the first block, or the last one, or some mix), but uses them somehow. It leads to non-determinism of the guest execution, because block driver does not preserve any order of reading. This situation was discusses in the mailing list at least twice: https://lists.gnu.org/archive/html/qemu-devel/2010-09/msg01996.html https://lists.gnu.org/archive/html/qemu-devel/2020-02/msg05185.html This patch makes such disk reads deterministic in icount mode. It splits the whole request into several parts. Parts may overlap, but SGs inside one part do not overlap. Parts that are processed later overwrite the prior ones in case of overlapping. Examples for different SG part sequences: 1) A1 1000 A2 1000 A1 1000 A3 1000 -> One request is split into two. A1 1000 A2 1000 -- A1 1000 A3 1000 2) A1 800 A2 1000 A1 1000 -> A1 800 A2 1000 -- A1 1000 Signed-off-by: NPavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Message-Id: <159117972206.12193.12939621311413561779.stgit@pasha-ThinkPad-X280> Signed-off-by: NKevin Wolf <kwolf@redhat.com>
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由 Philippe Mathieu-Daudé 提交于
Handlers don't need to modify the IDEDMA structure. Make it const. Signed-off-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200512194917.15807-1-philmd@redhat.com> Acked-by: NJohn Snow <jsnow@redhat.com> Signed-off-by: NKevin Wolf <kwolf@redhat.com>
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- 16 6月, 2020 38 次提交
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由 Peter Maydell 提交于
Testing and plugin updates - clear up dtc warnings - add support for --enable-tsan builds - re-enable shippable cross builds - serialise cirrus check steps - fix check-tcg plugin issues - add lockstep plugin # gpg: Signature made Tue 16 Jun 2020 14:50:09 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-and-plugin-160620-2: (21 commits) plugins: new lockstep plugin for debugging TCG changes tests/tcg: ensure -cpu max also used for plugin run tests/tcg: build plugin list from contents of src directory cirrus.yml: serialise make check Revert ".shippable: temporaily disable some cross builds" tests: Disable select tests under TSan, which hit TSan issue. docs: Added details on TSan to testing.rst util: Added tsan annotate for thread name. include/qemu: Added tsan.h for annotations. tests/docker: Added docker build support for TSan. thread: add tsan annotations to QemuSpin translate-all: call qemu_spin_destroy for PageDesc tcg: call qemu_spin_destroy for tb->jmp_lock qht: call qemu_spin_destroy for head buckets cputlb: destroy CPUTLB with tlb_destroy thread: add qemu_spin_destroy cpu: convert queued work to a QSIMPLEQ configure: add --enable-tsan flag + fiber annotations for coroutine-ucontext Makefile: remove old compatibility gunks Makefile: dtc: update, build the libfdt target ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Alex Bennée 提交于
When we make changes to the TCG we sometimes cause regressions that are deep into the execution cycle of the guest. Debugging this often requires comparing large volumes of trace information to figure out where behaviour has diverged. The lockstep plugin utilises a shared socket so two QEMU's running with the plugin will write their current execution position and wait to receive the position of their partner process. When execution diverges the plugins output where they were and the previous few blocks before unloading themselves and letting execution continue. Originally I planned for this to be most useful with -icount but it turns out you can get divergence pretty quickly due to asynchronous qemu_cpu_kick_rr_cpus() events causing one side to eventually run into a short block a few cycles before the other side. For this reason I've added a bit of tracking and I think the divergence reporting could be finessed to report only if we really start to diverge in execution. An example run would be: qemu-system-sparc -monitor none -parallel none -net none \ -M SS-20 -m 256 -kernel day11/zImage.elf \ -plugin ./tests/plugin/liblockstep.so,arg=lockstep-sparc.sock \ -d plugin,nochain with an identical command in another window in the same working directory. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NRobert Foley <robert.foley@linaro.org> Tested-by: NRobert Foley <robert.foley@linaro.org> Cc: Richard Henderson <richard.henderson@linaro.org> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20200610155509.12850-3-alex.bennee@linaro.org>
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由 Alex Bennée 提交于
The check-tcg plugins build was failing because some special case tests that needed -cpu max failed because the plugin variant hadn't carried across the QEMU_OPTS tweak. Guests which globally set QEMU_OPTS=-cpu FOO where unaffected. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200615141922.18829-3-alex.bennee@linaro.org>
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由 Alex Bennée 提交于
If you jump back and forth between branches while developing plugins you end up debugging failures caused by plugins left in the build directory. Fix this by basing plugins on the source tree instead. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200615141922.18829-2-alex.bennee@linaro.org>
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由 Alex Bennée 提交于
We do this on our other platforms to make it easier to see what has broken. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NLi-Wen Hsu <lwhsu@FreeBSD.org> Message-Id: <20200612190237.30436-19-alex.bennee@linaro.org>
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由 Alex Bennée 提交于
This reverts commit 12d43b5a. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200612190237.30436-18-alex.bennee@linaro.org>
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由 Robert Foley 提交于
Disable a few tests under CONFIG_TSAN, which run into a known TSan issue that results in a hang. https://github.com/google/sanitizers/issues/1116 The disabled tests under TSan include all the qtests as well as the test-char, test-qga, and test-qdev-global-props. Signed-off-by: NRobert Foley <robert.foley@linaro.org> Reviewed-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200609200738.445-14-robert.foley@linaro.org> Message-Id: <20200612190237.30436-17-alex.bennee@linaro.org>
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由 Robert Foley 提交于
Adds TSan details to testing.rst. This includes background and reference details on TSan, and details on how to build and test with TSan both with and without docker. Signed-off-by: NRobert Foley <robert.foley@linaro.org> Reviewed-by: NEmilio G. Cota <cota@braap.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200609200738.445-13-robert.foley@linaro.org> Message-Id: <20200612190237.30436-16-alex.bennee@linaro.org>
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由 Robert Foley 提交于
This allows us to see the name of the thread in tsan warning reports such as this: Thread T7 'CPU 1/TCG' (tid=24317, running) created by main thread at: Signed-off-by: NRobert Foley <robert.foley@linaro.org> Reviewed-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200609200738.445-12-robert.foley@linaro.org> Message-Id: <20200612190237.30436-15-alex.bennee@linaro.org>
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由 Robert Foley 提交于
These annotations will allow us to give tsan additional hints. For example, we can inform tsan about reads/writes to ignore to silence certain classes of warnings. We can also annotate threads so that the proper thread naming shows up in tsan warning results. Signed-off-by: NRobert Foley <robert.foley@linaro.org> Reviewed-by: NEmilio G. Cota <cota@braap.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200609200738.445-11-robert.foley@linaro.org> Message-Id: <20200612190237.30436-14-alex.bennee@linaro.org>
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由 Robert Foley 提交于
Added a new docker for ubuntu 20.04. This docker has support for Thread Sanitizer including one patch we need in one of the header files. https://github.com/llvm/llvm-project/commit/a72dc86cd This command will build with tsan enabled: make docker-test-tsan-ubuntu2004 V=1 Also added the TSAN suppresion file to disable certain cases of TSAN warnings. Cc: Fam Zheng <fam@euphon.net> Cc: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: NRobert Foley <robert.foley@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200609200738.445-10-robert.foley@linaro.org> Message-Id: <20200612190237.30436-13-alex.bennee@linaro.org>
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由 Emilio G. Cota 提交于
Signed-off-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NRobert Foley <robert.foley@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200609200738.445-9-robert.foley@linaro.org> Message-Id: <20200612190237.30436-12-alex.bennee@linaro.org>
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由 Emilio G. Cota 提交于
The radix tree is append-only, but we can fail to insert a PageDesc if the insertion races with another thread. Signed-off-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NRobert Foley <robert.foley@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200609200738.445-8-robert.foley@linaro.org> Message-Id: <20200612190237.30436-11-alex.bennee@linaro.org>
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由 Emilio G. Cota 提交于
Signed-off-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NRobert Foley <robert.foley@linaro.org> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> [RF: minor changes + remove tb_destroy_func] Message-Id: <20200609200738.445-7-robert.foley@linaro.org> Message-Id: <20200612190237.30436-10-alex.bennee@linaro.org>
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由 Emilio G. Cota 提交于
Signed-off-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NRobert Foley <robert.foley@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> [AJB: add implied cota s-o-b c.f. github.com/cota/qemu/tree/tsan @ 1bd1209] Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200609200738.445-6-robert.foley@linaro.org> Message-Id: <20200612190237.30436-9-alex.bennee@linaro.org>
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由 Emilio G. Cota 提交于
I was after adding qemu_spin_destroy calls, but while at it I noticed that we are leaking some memory. Signed-off-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NRobert Foley <robert.foley@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200609200738.445-5-robert.foley@linaro.org> Message-Id: <20200612190237.30436-8-alex.bennee@linaro.org>
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由 Emilio G. Cota 提交于
It will be used for TSAN annotations. Signed-off-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NRobert Foley <robert.foley@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200609200738.445-4-robert.foley@linaro.org> Message-Id: <20200612190237.30436-7-alex.bennee@linaro.org>
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由 Emilio G. Cota 提交于
We convert queued work to a QSIMPLEQ, instead of open-coding it. While at it, make sure that all accesses to the list are performed while holding the list's lock. Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: NEmilio G. Cota <cota@braap.org> Signed-off-by: NRobert Foley <robert.foley@linaro.org> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200609200738.445-3-robert.foley@linaro.org> Message-Id: <20200612190237.30436-6-alex.bennee@linaro.org>
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由 Lingfeng Yang 提交于
We tried running QEMU under tsan in 2016, but tsan's lack of support for longjmp-based fibers was a blocker: https://groups.google.com/forum/#!topic/thread-sanitizer/se0YuzfWazw Fortunately, thread sanitizer gained fiber support in early 2019: https://reviews.llvm.org/D54889 This patch brings tsan support upstream by importing the patch that annotated QEMU's coroutines as tsan fibers in Android's QEMU fork: https://android-review.googlesource.com/c/platform/external/qemu/+/844675 Tested with '--enable-tsan --cc=clang-9 --cxx=clang++-9 --disable-werror' configure flags. Signed-off-by: NLingfeng Yang <lfy@google.com> Signed-off-by: NEmilio G. Cota <cota@braap.org> [cota: minor modifications + configure changes] Signed-off-by: NRobert Foley <robert.foley@linaro.org> [RF: configure changes, coroutine fix + minor modifications] Reviewed-by: NAlex Bennée <alex.bennee@linaro.org> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200609200738.445-2-robert.foley@linaro.org> Message-Id: <20200612190237.30436-5-alex.bennee@linaro.org>
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由 Claudio Fontana 提交于
Signed-off-by: NClaudio Fontana <cfontana@suse.de> Reviewed-by: NMarkus Armbruster <armbru@redhat.com> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Tested-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200518160319.18861-3-cfontana@suse.de> Message-Id: <20200612190237.30436-4-alex.bennee@linaro.org>
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由 Claudio Fontana 提交于
dtc submodule update, now call the libfdt target from the new dtc Makefile, which has been changed to not require bison, flex, etc. This removes warnings during the build. scripts/ symlink and tests directory creation are not necessary, and neither is calling the clean rule explicitly. Signed-off-by: NClaudio Fontana <cfontana@suse.de> Reviewed-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Tested-by: NPhilippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Message-Id: <20200518160319.18861-2-cfontana@suse.de> Message-Id: <20200612190237.30436-3-alex.bennee@linaro.org>
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由 Alex Bennée 提交于
We should be keeping this up to date as Fedora goes out of support quite quickly. Signed-off-by: NAlex Bennée <alex.bennee@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org> Message-Id: <20200612190237.30436-2-alex.bennee@linaro.org>
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由 Peter Maydell 提交于
* hw: arm: Set vendor property for IMX SDHCI emulations * sd: sdhci: Implement basic vendor specific register support * hw/net/imx_fec: Convert debug fprintf() to trace events * target/arm/cpu: adjust virtual time for all KVM arm cpus * Implement configurable descriptor size in ftgmac100 * hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers * target/arm: More Neon decodetree conversion work # gpg: Signature made Tue 16 Jun 2020 10:56:10 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200616: (23 commits) hw: arm: Set vendor property for IMX SDHCI emulations sd: sdhci: Implement basic vendor specific register support hw/net/imx_fec: Convert debug fprintf() to trace events target/arm/cpu: adjust virtual time for all KVM arm cpus Implement configurable descriptor size in ftgmac100 hw/misc/imx6ul_ccm: Implement non writable bits in CCM registers target/arm: Convert Neon VDUP (scalar) to decodetree target/arm: Convert Neon VTBL, VTBX to decodetree target/arm: Convert Neon VEXT to decodetree target/arm: Convert Neon 2-reg-scalar long multiplies to decodetree target/arm: Convert Neon 2-reg-scalar VQRDMLAH, VQRDMLSH to decodetree target/arm: Convert Neon 2-reg-scalar VQDMULH, VQRDMULH to decodetree target/arm: Convert Neon 2-reg-scalar float multiplies to decodetree target/arm: Convert Neon 2-reg-scalar integer multiplies to decodetree target/arm: Add missing TCG temp free in do_2shift_env_64() target/arm: Add 'static' and 'const' annotations to VSHLL function arrays target/arm: Convert Neon 3-reg-diff polynomial VMULL target/arm: Convert Neon 3-reg-diff saturating doubling multiplies target/arm: Convert Neon 3-reg-diff long multiplies target/arm: Convert Neon 3-reg-diff VABAL, VABDL to decodetree ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/arm/fsl-imx25.c # hw/arm/fsl-imx6.c # hw/arm/fsl-imx6ul.c # hw/arm/fsl-imx7.c
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由 Peter Maydell 提交于
QOM patches for 2020-06-15 # gpg: Signature made Mon 15 Jun 2020 21:07:19 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qom-2020-06-15: (84 commits) MAINTAINERS: Make section QOM cover hw/core/*bus.c as well qdev: qdev_init_nofail() is now unused, drop qdev: Convert bus-less devices to qdev_realize() with Coccinelle qdev: Use qdev_realize() in qdev_device_add() qdev: Make qdev_realize() support bus-less devices s390x/event-facility: Simplify creation of SCLP event devices microbit: Eliminate two local variables in microbit_init() sysbus: sysbus_init_child_obj() is now unused, drop sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 4 sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 3 sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2 sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1 qdev: Drop qdev_realize() support for null bus sysbus: Convert to sysbus_realize() etc. with Coccinelle sysbus: New sysbus_realize(), sysbus_realize_and_unref() sysbus: Tidy up sysbus_init_child_obj()'s @childsize arg, part 2 hw/arm/armsse: Pass correct child size to sysbus_init_child_obj() sysbus: Tidy up sysbus_init_child_obj()'s @childsize arg, part 1 microbit: Tidy up sysbus_init_child_obj() @child argument sysbus: Drop useless OBJECT() in sysbus_init_child_obj() calls ... Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
MIPS + misc queue for June 15th, 2020 # gpg: Signature made Mon 15 Jun 2020 20:05:25 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full] # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-jun-15-2020: translations: Add Swedish language MAINTAINERS: Adjust sh4 maintainership target/mips: msa: Split helpers for MULV.<B|H|W|D> target/mips: msa: Split helpers for SUBV.<B|H|W|D> target/mips: msa: Split helpers for SUBSUU_S.<B|H|W|D> target/mips: msa: Split helpers for SUBSUS_U.<B|H|W|D> target/mips: msa: Split helpers for SUBS_U.<B|H|W|D> target/mips: msa: Split helpers for SUBS_S.<B|H|W|D> target/mips: msa: Split helpers for DOTP_U.<H|W|D> target/mips: msa: Split helpers for DOTP_S.<H|W|D> target/mips: msa: Split helpers for DPSUB_U.<H|W|D> target/mips: msa: Split helpers for DPSUB_S.<H|W|D> target/mips: msa: Split helpers for DPADD_U.<H|W|D> target/mips: msa: Split helpers for DPADD_S.<H|W|D> target/mips: msa: Split helpers for MSUBV.<B|H|W|D> target/mips: msa: Split helpers for MADDV.<B|H|W|D> target/mips: Add comments for vendor-specific ASEs target/mips: Legalize Loongson insn flags Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Guenter Roeck 提交于
Set vendor property to IMX to enable IMX specific functionality in sdhci code. Tested-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200603145258.195920-3-linux@roeck-us.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Guenter Roeck 提交于
The Linux kernel's IMX code now uses vendor specific commands. This results in endless warnings when booting the Linux kernel. sdhci-esdhc-imx 2194000.usdhc: esdhc_wait_for_card_clock_gate_off: card clock still not gate off in 100us!. Implement support for the vendor specific command implemented in IMX hardware to be able to avoid this warning. Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NGuenter Roeck <linux@roeck-us.net> Message-id: 20200603145258.195920-2-linux@roeck-us.net Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Jean-Christophe Dubois 提交于
Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> [PMD: Fixed 32-bit format string using PRIx32/PRIx64] Signed-off-by: NPhilippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 fangying 提交于
Virtual time adjustment was implemented for virt-5.0 machine type, but the cpu property was enabled only for host-passthrough and max cpu model. Let's add it for any KVM arm cpu which has the generic timer feature enabled. Signed-off-by: NYing Fang <fangying1@huawei.com> Reviewed-by: NAndrew Jones <drjones@redhat.com> Message-id: 20200608121243.2076-1-fangying1@huawei.com [PMM: minor commit message tweak, removed inaccurate suggested-by tag] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Erik Smit 提交于
The hardware supports configurable descriptor sizes, configured in the DBLAC register. Most drivers use the default 4 word descriptor, which is currently hardcoded, but Aspeed SDK configures 8 words to store extra data. Signed-off-by: NErik Smit <erik.lucas.smit@gmail.com> Reviewed-by: NCédric Le Goater <clg@kaod.org> [PMM: removed unnecessary parens] Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Jean-Christophe Dubois 提交于
Some bits of the CCM registers are non writable. This was left undone in the initial commit (all bits of registers were writable). This patch adds the required code to protect the non writable bits. Signed-off-by: NJean-Christophe Dubois <jcd@tribudubois.net> Message-id: 20200608133508.550046-1-jcd@tribudubois.net Reviewed-by: NPeter Maydell <peter.maydell@linaro.org> Signed-off-by: NPeter Maydell <peter.maydell@linaro.org>
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由 Peter Maydell 提交于
Convert the Neon VDUP (scalar) insn to decodetree. (Note that we can't call this just "VDUP" as we used that already in vfp.decode for the "VDUP (general purpose register" insn.) Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
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由 Peter Maydell 提交于
Convert the Neon VTBL, VTBX instructions to decodetree. The actual implementation of the insn is copied across to the new trans function unchanged except for renaming 'tmp5' to 'tmp4'. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
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由 Peter Maydell 提交于
Convert the Neon VEXT insn to decodetree. Rather than keeping the old implementation which used fixed temporaries cpu_V0 and cpu_V1 and did the extraction with by-hand shift and logic ops, we use the TCG extract2 insn. We don't need to special case 0 or 8 immediates any more as the optimizer is smart enough to throw away the dead code. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
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由 Peter Maydell 提交于
Convert the Neon 2-reg-scalar long multiplies to decodetree. These are the last instructions in the group. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
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由 Peter Maydell 提交于
Convert the VQRDMLAH and VQRDMLSH insns in the 2-reg-scalar group to decodetree. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
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由 Peter Maydell 提交于
Convert the VQDMULH and VQRDMULH insns in the 2-reg-scalar group to decodetree. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
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由 Peter Maydell 提交于
Convert the float versions of VMLA, VMLS and VMUL in the Neon 2-reg-scalar group to decodetree. Signed-off-by: NPeter Maydell <peter.maydell@linaro.org> --- As noted in the comment on the WRAP_FP_FN macro, we could have had a do_2scalar_fp() function, but for 3 insns it seemed simpler to just do the wrapping to get hold of the fpstatus ptr. (These are the only fp insns in the group.) Reviewed-by: NRichard Henderson <richard.henderson@linaro.org>
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