Signed-off-by: Nfishpenguin <kun.yu@zilliz.com>

* Remove vector fields from output fields
Signed-off-by: Nfishpenguin <kun.yu@zilliz.com>

* Add empty_collection error_code
Signed-off-by: Nfishpenguin <kun.yu@zilliz.com>

Signed-off-by: Nsunby <bingyi.sun@zilliz.com>

* Change search result to columnBased and return target_entry
Signed-off-by: Nfishpenguin <kun.yu@zilliz.com>
Co-authored-by: Nfluorinedog <fluorinedog@gmail.com>

* synchronize the latest pymilvus-orm version
Signed-off-by: Nfishpenguin <kun.yu@zilliz.com>

* Change pymilvus-orm version to 40
Signed-off-by: Nfishpenguin <kun.yu@zilliz.com>
Co-authored-by: Nfluorinedog <fluorinedog@gmail.com>

Signed-off-by: Ndragondriver <jiquan.long@zilliz.com>

Signed-off-by: Nzhenshan.cao <zhenshan.cao@zilliz.com>

* support time travel
Signed-off-by: Nfluorinedog <fluorinedog@gmail.com>

* lint
Signed-off-by: Nfluorinedog <fluorinedog@gmail.com>

Signed-off-by: Nzhenshan.cao <zhenshan.cao@zilliz.com>

* Split segcore and plan proto for future feature
Signed-off-by: Nfluorinedog <fluorinedog@gmail.com>

* lint
Signed-off-by: Nfluorinedog <fluorinedog@gmail.com>

Signed-off-by: Nxige-16 <xi.ge@zilliz.com>
Signed-off-by: Nbigsheeper <yihao.dai@zilliz.com>
Co-authored-by: Nxige-16 <xi.ge@zilliz.com>
Co-authored-by: Nyudong.cai <yudong.cai@zilliz.com>

Signed-off-by: Nfluorinedog <fluorinedog@gmail.com>

Signed-off-by: NXiangyu Wang <xiangyu.wang@zilliz.com>

* IVF_SQ8 and IVF_PQ cannot be built on multiple GPUs
Signed-off-by: Nshengjun.li <shengjun.li@zilliz.com>

* index created by std::make_shared
Signed-off-by: Nshengjun.li <shengjun.li@zilliz.com>

Signed-off-by: Nfluorinedog <fluorinedog@gmail.com>

Signed-off-by: NXiangyu Wang <xiangyu.wang@zilliz.com>

Signed-off-by: Nfluorinedog <fluorinedog@gmail.com>

Signed-off-by: Ndragondriver <jiquan.long@zilliz.com>

Signed-off-by: Ndragondriver <jiquan.long@zilliz.com>

Signed-off-by: Nfluorinedog <fluorinedog@gmail.com>

Adding a dummy RPC makes it easier to develop new RPCs in the future.
When developing a new function, the SDK is often implemented last. 
At this time, this is helpful for debugging.
Signed-off-by: NXiangyu Wang <xiangyu.wang@zilliz.com>

Not to call getListIndex() if bitset is empty.
Signed-off-by: Nshengjun.li <shengjun.li@zilliz.com>

Signed-off-by: Nsunby <bingyi.sun@zilliz.com>

Resolves: #5257 
Signed-off-by: Nfishpenguin <kun.yu@zilliz.com>

See also: #5253 
Signed-off-by: Nfishpenguin <kun.yu@zilliz.com>

query base on timeline, add timestamp on these queries:
- ShowCollections
- HasCollection
- DescribeCollection

Resolves: #5219
Signed-off-by: Nyefu.chen <yefu.chen@zilliz.com>

Updata PhysicalChannelNames and VirtualChannelNames based
on ShardsNum when create collection, and update collVChan2Chan
map.

Resolves: #5240 
Signed-off-by: Nyudong.cai <yudong.cai@zilliz.com>

Signed-off-by: Nfishpenguin <kun.yu@zilliz.com>

Re-enable knowhere unittests and merge them all together. 
Signed-off-by: Nfluorinedog <fluorinedog@gmail.com>

Signed-off-by: Ndragondriver <jiquan.long@zilliz.com>

Pass a parameter `IsExpr` from proxy to query node, so query 
node can create search plan according to the variable `IsExpr`.
It makes `segcore` unnecessary to distinguish `dsl` or `expr`
using dynamic exception. When `IsExpr` is set to true, query
node will call `CreatePlanByExpr` according to the passed
information about expression. Otherwise query node will keep
still to use `CreatePlan` according to the `dsl` information. At
the same time, this pr adds some unittests to `CreatePlanByExpr`,
these unittests translate already exist case with `dsl` to case with
`expr`.
Signed-off-by: Ndragondriver <jiquan.long@zilliz.com>

1. Support Term, like `A in [1, 2, 3]`
2. Support Not, like `! A < 3`
3. Support logical combination, like `A < 3 && B > 5 or C == 0`

Type: Feature
Signed-off-by: Nfluorinedog <fluorinedog@gmail.com>

When the remaining space is empty, the zero size allocation will
get the pointer `end_`. However, `cudafree` the pointer `end_` will
cause to crash.

Fix: #5078 #4770 #4412 #4340 #3646
Signed-off-by: Nshengjun.li <shengjun.li@zilliz.com>

**What type of PR is this?**
- [x] Feature

**What this PR does / why we need it:**
This PR supports boolean expression as DSL.
1. The goal of this PR is to support predicates
    like `A > 3 && not B < 5 or C in [1, 2, 3]`. 
2. Defines `plan.proto`, as Intermediate Representation (IR) 
    used between go and cpp. 
3. Support expr parser, convert predicate expr to IR
    in proxynode, while doing static check there
4. Support IR to AST in cpp, enable the execution

Add get index build progress proto.
Signed-off-by: Ngodchen <qingxiang.chen@zilliz.com>

Signed-off-by: Nshengjun.li <shengjun.li@zilliz.com>

Signed-off-by: Nyefu.chen <yefu.chen@zilliz.com>

Import performance of ivf::train and hnsw, and fix bugs
Signed-off-by: Nshengjun.li <shengjun.li@zilliz.com>

* Rename module
Signed-off-by: NXiangyu Wang <xiangyu.wang@zilliz.com>

Signed-off-by: Nxige-16 <xi.ge@zilliz.com>

Signed-off-by: Ncai.zhang <cai.zhang@zilliz.com>