As all irqchips on imx have been changed to allocate their irq_descs,
and all unneeded mach/irqs.h inclusions on imx have been cleaned up,
now it's time to select SPARSE_IRQ for imx/mxc.

The SPARSE_IRQ support forces irqs allocation starting from 16.  All
those static irq number definition for SoCs need to shift 16 to keep
non-DT boot works.

With all those static IRQ number and start definitions removed from
mach/irqs.h, the header becomes just a container of a couple of
mach-imx specific irq/fiq calls.  Since mach/irqs.h is not included
by asm/irq.h now, the users of mxc_set_irq_fiq needs to explicitly
include mach/irqs.h themselves.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>

For MX50, the HW_ADADIG_DIGPROG register in the ANATOP module will
have the correct silicon revision:

Major       Minor   Description
0x50        0x0     TO1.0
0x50        0x1     TO1.1
Signed-off-by: NDinh Nguyen <Dinh.Nguyen@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Add core definitions and memory map, gpio, irq, iomux, uart device
support.
Signed-off-by: NRichard Zhao <richard.zhao@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>