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体验新版 GitCode,发现更多精彩内容 >>
提交
d6ff0fc0
编写于
9月 29, 2020
作者:
W
WangQiang
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
增加了imxrt1064-nxp-evk的BSP的以太网功能
上级
13044b1e
变更
10
隐藏空白更改
内联
并排
Showing
10 changed file
with
1028 addition
and
126 deletion
+1028
-126
bsp/imxrt/imxrt1064-nxp-evk/applications/main.c
bsp/imxrt/imxrt1064-nxp-evk/applications/main.c
+2
-0
bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig
bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig
+21
-0
bsp/imxrt/imxrt1064-nxp-evk/board/MCUX_Config/clock_config.c
bsp/imxrt/imxrt1064-nxp-evk/board/MCUX_Config/clock_config.c
+98
-122
bsp/imxrt/imxrt1064-nxp-evk/board/SConscript
bsp/imxrt/imxrt1064-nxp-evk/board/SConscript
+5
-1
bsp/imxrt/imxrt1064-nxp-evk/board/board.c
bsp/imxrt/imxrt1064-nxp-evk/board/board.c
+329
-0
bsp/imxrt/imxrt1064-nxp-evk/board/board.h
bsp/imxrt/imxrt1064-nxp-evk/board/board.h
+6
-0
bsp/imxrt/imxrt1064-nxp-evk/board/ports/phyksz8081/fsl_phy.c
bsp/imxrt/imxrt1064-nxp-evk/board/ports/phyksz8081/fsl_phy.c
+315
-0
bsp/imxrt/imxrt1064-nxp-evk/board/ports/phyksz8081/fsl_phy.h
bsp/imxrt/imxrt1064-nxp-evk/board/ports/phyksz8081/fsl_phy.h
+200
-0
bsp/imxrt/imxrt1064-nxp-evk/board/ports/sdram_port.h
bsp/imxrt/imxrt1064-nxp-evk/board/ports/sdram_port.h
+49
-0
bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py
bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py
+3
-3
未找到文件。
bsp/imxrt/imxrt1064-nxp-evk/applications/main.c
浏览文件 @
d6ff0fc0
...
...
@@ -18,6 +18,7 @@
int
main
(
void
)
{
#ifndef PHY_USING_KSZ8081
/* set LED0 pin mode to output */
rt_pin_mode
(
LED0_PIN
,
PIN_MODE_OUTPUT
);
...
...
@@ -28,6 +29,7 @@ int main(void)
rt_pin_write
(
LED0_PIN
,
PIN_LOW
);
rt_thread_mdelay
(
500
);
}
#endif
}
void
reboot
(
void
)
...
...
bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig
浏览文件 @
d6ff0fc0
...
...
@@ -37,7 +37,28 @@ menu "On-chip Peripheral Drivers"
endmenu
menu "Onboard Peripheral Drivers"
config BSP_USING_SDRAM
bool "Enable SDRAM"
default n
menuconfig BSP_USING_ETH
bool "Enable Ethernet"
select PHY_USING_KSZ8081
select RT_USING_NETDEV
default n
if BSP_USING_ETH
config PHY_USING_KSZ8081
bool "i.MX RT1064EVK uses ksz8081 phy"
default y
config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
bool "Enable the PHY ksz8081 RMII50M mode"
depends on PHY_USING_KSZ8081
default y
endif
endmenu
menu "Board extended module Drivers"
...
...
bsp/imxrt/imxrt1064-nxp-evk/board/MCUX_Config/clock_config.c
浏览文件 @
d6ff0fc0
/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* How to setup clock using clock driver functions:
*
...
...
@@ -15,15 +22,15 @@
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v
5.0
product: Clocks v
4.1
processor: MIMXRT1064xxxxA
package_id: MIMXRT1064DVL6A
mcu_data: ksdk2_0
processor_version: 5.0.1
processor_version: 0.0.0
board: MIMXRT1064-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
...
...
@@ -57,35 +64,23 @@ outputs:
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz}
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 2
64
MHz}
- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 2
880/11
MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 2880/11 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5
/7
MHz}
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
...
...
@@ -95,10 +90,10 @@ outputs:
settings:
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI2_PODF.scale, value: '1', locked: true}
- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
- {id: CCM.FLEXSPI_PODF.scale, value: '1', locked: true}
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
- {id: CCM.LCDIF_PODF.scale, value: '8', locked: true}
- {id: CCM.LCDIF_PRED.scale, value: '7', locked: true}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.SEMC_PODF.scale, value: '8'}
...
...
@@ -107,6 +102,7 @@ settings:
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
- {id: CCM_ANALOG.PLL2.div, value: '22'}
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
...
...
@@ -182,6 +178,77 @@ void BOARD_BootClockRUN(void)
while
(
DCDC_REG0_STS_DC_OK_MASK
!=
(
DCDC_REG0_STS_DC_OK_MASK
&
DCDC
->
REG0
))
{
}
/* Init ARM PLL. */
CLOCK_InitArmPll
(
&
armPllConfig_BOARD_BootClockRUN
);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Init System PLL. */
CLOCK_InitSysPll
(
&
sysPllConfig_BOARD_BootClockRUN
);
/* Init System pfd0. */
CLOCK_InitSysPfd
(
kCLOCK_Pfd0
,
27
);
/* Init System pfd1. */
CLOCK_InitSysPfd
(
kCLOCK_Pfd1
,
16
);
/* Init System pfd2. */
CLOCK_InitSysPfd
(
kCLOCK_Pfd2
,
24
);
/* Init System pfd3. */
CLOCK_InitSysPfd
(
kCLOCK_Pfd3
,
16
);
#endif
/* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll
(
&
usb1PllConfig_BOARD_BootClockRUN
);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd
(
kCLOCK_Pfd0
,
33
);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd
(
kCLOCK_Pfd1
,
16
);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd
(
kCLOCK_Pfd2
,
17
);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd
(
kCLOCK_Pfd3
,
19
);
/* Disable Usb1 PLL output for USBPHY1. */
CCM_ANALOG
->
PLL_USB1
&=
~
CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK
;
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll
();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass
(
CCM_ANALOG
,
kCLOCK_PllAudio
,
1
);
/* Set divider for Audio PLL. */
CCM_ANALOG
->
MISC2
&=
~
CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK
;
CCM_ANALOG
->
MISC2
&=
~
CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK
;
/* Enable Audio PLL output. */
CCM_ANALOG
->
PLL_AUDIO
|=
CCM_ANALOG_PLL_AUDIO_ENABLE_MASK
;
/* DeInit Video PLL. */
CLOCK_DeinitVideoPll
();
/* Bypass Video PLL. */
CCM_ANALOG
->
PLL_VIDEO
|=
CCM_ANALOG_PLL_VIDEO_BYPASS_MASK
;
/* Set divider for Video PLL. */
CCM_ANALOG
->
MISC2
=
(
CCM_ANALOG
->
MISC2
&
(
~
CCM_ANALOG_MISC2_VIDEO_DIV_MASK
))
|
CCM_ANALOG_MISC2_VIDEO_DIV
(
0
);
/* Enable Video PLL output. */
CCM_ANALOG
->
PLL_VIDEO
|=
CCM_ANALOG_PLL_VIDEO_ENABLE_MASK
;
/* DeInit Enet PLL. */
CLOCK_DeinitEnetPll
();
/* Bypass Enet PLL. */
CLOCK_SetPllBypass
(
CCM_ANALOG
,
kCLOCK_PllEnet
,
1
);
/* Set Enet output divider. */
CCM_ANALOG
->
PLL_ENET
=
(
CCM_ANALOG
->
PLL_ENET
&
(
~
CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK
))
|
CCM_ANALOG_PLL_ENET_DIV_SELECT
(
1
);
/* Enable Enet output. */
CCM_ANALOG
->
PLL_ENET
|=
CCM_ANALOG_PLL_ENET_ENABLE_MASK
;
/* Set Enet2 output divider. */
CCM_ANALOG
->
PLL_ENET
=
(
CCM_ANALOG
->
PLL_ENET
&
(
~
CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK
))
|
CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT
(
0
);
/* Enable Enet2 output. */
CCM_ANALOG
->
PLL_ENET
|=
CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK
;
/* Enable Enet25M output. */
CCM_ANALOG
->
PLL_ENET
|=
CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK
;
/* DeInit Usb2 PLL. */
CLOCK_DeinitUsb2Pll
();
/* Bypass Usb2 PLL. */
CLOCK_SetPllBypass
(
CCM_ANALOG
,
kCLOCK_PllUsb2
,
1
);
/* Enable Usb2 PLL output. */
CCM_ANALOG
->
PLL_USB2
|=
CCM_ANALOG_PLL_USB2_ENABLE_MASK
;
/* Set AHB_PODF. */
CLOCK_SetDiv
(
kCLOCK_AhbDiv
,
0
);
/* Disable IPG clock gate. */
...
...
@@ -193,8 +260,14 @@ void BOARD_BootClockRUN(void)
CLOCK_SetDiv
(
kCLOCK_IpgDiv
,
3
);
/* Set ARM_PODF. */
CLOCK_SetDiv
(
kCLOCK_ArmDiv
,
1
);
/* Set preperiph clock source. */
CLOCK_SetMux
(
kCLOCK_PrePeriphMux
,
3
);
/* Set periph clock source. */
CLOCK_SetMux
(
kCLOCK_PeriphMux
,
0
);
/* Set PERIPH_CLK2_PODF. */
CLOCK_SetDiv
(
kCLOCK_PeriphClk2Div
,
0
);
/* Set periph clock2 clock source. */
CLOCK_SetMux
(
kCLOCK_PeriphClk2Mux
,
0
);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock
(
kCLOCK_Gpt1
);
CLOCK_DisableClock
(
kCLOCK_Gpt1S
);
...
...
@@ -203,6 +276,8 @@ void BOARD_BootClockRUN(void)
CLOCK_DisableClock
(
kCLOCK_Pit
);
/* Set PERCLK_PODF. */
CLOCK_SetDiv
(
kCLOCK_PerclkDiv
,
1
);
/* Set per clock source. */
CLOCK_SetMux
(
kCLOCK_PerclkMux
,
0
);
/* Disable USDHC1 clock gate. */
CLOCK_DisableClock
(
kCLOCK_Usdhc1
);
/* Set USDHC1_PODF. */
...
...
@@ -241,9 +316,9 @@ void BOARD_BootClockRUN(void)
/* Disable Flexspi2 clock gate. */
CLOCK_DisableClock
(
kCLOCK_FlexSpi2
);
/* Set FLEXSPI2_PODF. */
CLOCK_SetDiv
(
kCLOCK_Flexspi2Div
,
1
);
CLOCK_SetDiv
(
kCLOCK_Flexspi2Div
,
0
);
/* Set Flexspi2 clock source. */
CLOCK_SetMux
(
kCLOCK_Flexspi2Mux
,
3
);
CLOCK_SetMux
(
kCLOCK_Flexspi2Mux
,
1
);
#endif
/* Disable CSI clock gate. */
CLOCK_DisableClock
(
kCLOCK_Csi
);
...
...
@@ -325,9 +400,9 @@ void BOARD_BootClockRUN(void)
/* Disable LCDIF clock gate. */
CLOCK_DisableClock
(
kCLOCK_LcdPixel
);
/* Set LCDIF_PRED. */
CLOCK_SetDiv
(
kCLOCK_LcdifPreDiv
,
6
);
CLOCK_SetDiv
(
kCLOCK_LcdifPreDiv
,
1
);
/* Set LCDIF_CLK_PODF. */
CLOCK_SetDiv
(
kCLOCK_LcdifDiv
,
7
);
CLOCK_SetDiv
(
kCLOCK_LcdifDiv
,
3
);
/* Set Lcdif pre clock source. */
CLOCK_SetMux
(
kCLOCK_LcdifPreMux
,
5
);
/* Disable SPDIF clock gate. */
...
...
@@ -356,85 +431,6 @@ void BOARD_BootClockRUN(void)
CLOCK_SetMux
(
kCLOCK_Flexio2Mux
,
3
);
/* Set Pll3 sw clock source. */
CLOCK_SetMux
(
kCLOCK_Pll3SwMux
,
0
);
/* Init ARM PLL. */
CLOCK_InitArmPll
(
&
armPllConfig_BOARD_BootClockRUN
);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Init System PLL. */
CLOCK_InitSysPll
(
&
sysPllConfig_BOARD_BootClockRUN
);
/* Init System pfd0. */
CLOCK_InitSysPfd
(
kCLOCK_Pfd0
,
27
);
/* Init System pfd1. */
CLOCK_InitSysPfd
(
kCLOCK_Pfd1
,
16
);
/* Init System pfd2. */
CLOCK_InitSysPfd
(
kCLOCK_Pfd2
,
24
);
/* Init System pfd3. */
CLOCK_InitSysPfd
(
kCLOCK_Pfd3
,
16
);
#endif
/* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll
(
&
usb1PllConfig_BOARD_BootClockRUN
);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd
(
kCLOCK_Pfd0
,
33
);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd
(
kCLOCK_Pfd1
,
16
);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd
(
kCLOCK_Pfd2
,
17
);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd
(
kCLOCK_Pfd3
,
19
);
/* Disable Usb1 PLL output for USBPHY1. */
CCM_ANALOG
->
PLL_USB1
&=
~
CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK
;
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll
();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass
(
CCM_ANALOG
,
kCLOCK_PllAudio
,
1
);
/* Set divider for Audio PLL. */
CCM_ANALOG
->
MISC2
&=
~
CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK
;
CCM_ANALOG
->
MISC2
&=
~
CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK
;
/* Enable Audio PLL output. */
CCM_ANALOG
->
PLL_AUDIO
|=
CCM_ANALOG_PLL_AUDIO_ENABLE_MASK
;
/* DeInit Video PLL. */
CLOCK_DeinitVideoPll
();
/* Bypass Video PLL. */
CCM_ANALOG
->
PLL_VIDEO
|=
CCM_ANALOG_PLL_VIDEO_BYPASS_MASK
;
/* Set divider for Video PLL. */
CCM_ANALOG
->
MISC2
=
(
CCM_ANALOG
->
MISC2
&
(
~
CCM_ANALOG_MISC2_VIDEO_DIV_MASK
))
|
CCM_ANALOG_MISC2_VIDEO_DIV
(
0
);
/* Enable Video PLL output. */
CCM_ANALOG
->
PLL_VIDEO
|=
CCM_ANALOG_PLL_VIDEO_ENABLE_MASK
;
/* DeInit Enet PLL. */
CLOCK_DeinitEnetPll
();
/* Bypass Enet PLL. */
CLOCK_SetPllBypass
(
CCM_ANALOG
,
kCLOCK_PllEnet
,
1
);
/* Set Enet output divider. */
CCM_ANALOG
->
PLL_ENET
=
(
CCM_ANALOG
->
PLL_ENET
&
(
~
CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK
))
|
CCM_ANALOG_PLL_ENET_DIV_SELECT
(
1
);
/* Enable Enet output. */
CCM_ANALOG
->
PLL_ENET
|=
CCM_ANALOG_PLL_ENET_ENABLE_MASK
;
/* Set Enet2 output divider. */
CCM_ANALOG
->
PLL_ENET
=
(
CCM_ANALOG
->
PLL_ENET
&
(
~
CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK
))
|
CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT
(
0
);
/* Enable Enet2 output. */
CCM_ANALOG
->
PLL_ENET
|=
CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK
;
/* Enable Enet25M output. */
CCM_ANALOG
->
PLL_ENET
|=
CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK
;
/* DeInit Usb2 PLL. */
CLOCK_DeinitUsb2Pll
();
/* Bypass Usb2 PLL. */
CLOCK_SetPllBypass
(
CCM_ANALOG
,
kCLOCK_PllUsb2
,
1
);
/* Enable Usb2 PLL output. */
CCM_ANALOG
->
PLL_USB2
|=
CCM_ANALOG_PLL_USB2_ENABLE_MASK
;
/* Set preperiph clock source. */
CLOCK_SetMux
(
kCLOCK_PrePeriphMux
,
3
);
/* Set periph clock source. */
CLOCK_SetMux
(
kCLOCK_PeriphMux
,
0
);
/* Set periph clock2 clock source. */
CLOCK_SetMux
(
kCLOCK_PeriphClk2Mux
,
0
);
/* Set per clock source. */
CLOCK_SetMux
(
kCLOCK_PerclkMux
,
0
);
/* Set lvds1 clock source. */
CCM_ANALOG
->
MISC1
=
(
CCM_ANALOG
->
MISC1
&
(
~
CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK
))
|
CCM_ANALOG_MISC1_LVDS1_CLK_SEL
(
0
);
/* Set clock out1 divider. */
...
...
@@ -451,26 +447,6 @@ void BOARD_BootClockRUN(void)
CCM
->
CCOSR
&=
~
CCM_CCOSR_CLKO1_EN_MASK
;
/* Disable clock out2. */
CCM
->
CCOSR
&=
~
CCM_CCOSR_CLKO2_EN_MASK
;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource
(
IOMUXC_GPR
,
kIOMUXC_GPR_SAI1MClk1Sel
,
0
);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource
(
IOMUXC_GPR
,
kIOMUXC_GPR_SAI1MClk2Sel
,
0
);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource
(
IOMUXC_GPR
,
kIOMUXC_GPR_SAI1MClk3Sel
,
0
);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource
(
IOMUXC_GPR
,
kIOMUXC_GPR_SAI2MClk3Sel
,
0
);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource
(
IOMUXC_GPR
,
kIOMUXC_GPR_SAI3MClk3Sel
,
0
);
/* Set MQS configuration. */
IOMUXC_MQSConfig
(
IOMUXC_GPR
,
kIOMUXC_MqsPwmOverSampleRate32
,
0
);
/* Set ENET1 Tx clock source. */
IOMUXC_EnableMode
(
IOMUXC_GPR
,
kIOMUXC_GPR_ENET1RefClkMode
,
false
);
/* Set ENET2 Tx clock source. */
IOMUXC_EnableMode
(
IOMUXC_GPR
,
IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK
,
false
);
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR
->
GPR5
&=
~
IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK
;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR
->
GPR5
&=
~
IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK
;
/* Set SystemCoreClock variable. */
SystemCoreClock
=
BOARD_BOOTCLOCKRUN_CORE_CLOCK
;
}
...
...
bsp/imxrt/imxrt1064-nxp-evk/board/SConscript
浏览文件 @
d6ff0fc0
...
...
@@ -13,7 +13,11 @@ MCUX_Config/pin_mux.c
CPPPATH
=
[
cwd
,
cwd
+
'/MCUX_Config'
,
cwd
+
'/ports'
]
CPPDEFINES
=
[
'CPU_MIMXRT1064DVL6A'
,
'STD=C99'
,
'SKIP_SYSCLK_INIT'
,
'EVK_MCIMXRM'
,
'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL'
,
'XIP_EXTERNAL_FLASH=1'
,
'XIP_BOOT_HEADER_ENABLE=1'
]
CPPDEFINES
=
[
'CPU_MIMXRT1064DVL6A'
,
'SKIP_SYSCLK_INIT'
,
'EVK_MCIMXRM'
,
'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1'
,
'XIP_EXTERNAL_FLASH=1'
,
'XIP_BOOT_HEADER_ENABLE=1'
,
'XIP_BOOT_HEADER_DCD_ENABLE=1'
]
if
GetDepend
([
'PHY_USING_KSZ8081'
]):
src
+=
Glob
(
'ports/phyksz8081/fsl_phy.c'
)
CPPPATH
+=
[
cwd
+
'/ports/phyksz8081'
]
if
rtconfig
.
CROSS_TOOL
==
'keil'
:
CPPDEFINES
.
append
(
'__FPU_PRESENT=1'
)
...
...
bsp/imxrt/imxrt1064-nxp-evk/board/board.c
浏览文件 @
d6ff0fc0
...
...
@@ -12,6 +12,8 @@
#include <rtthread.h>
#include "board.h"
#include "pin_mux.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#ifdef BSP_USING_DMA
#include "fsl_dmamux.h"
...
...
@@ -109,6 +111,325 @@ void imxrt_dma_init(void)
EDMA_Init
(
DMA0
,
&
config
);
}
#endif
#ifdef BSP_USING_LPUART
void
imxrt_uart_pins_init
(
void
)
{
#ifdef BSP_USING_LPUART1
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX
,
/* GPIO_AD_B0_12 is configured as LPUART1_TX */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX
,
/* GPIO_AD_B0_13 is configured as LPUART1_RX */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX
,
/* GPIO_AD_B0_12 PAD functional properties : */
0x10B0u
);
/* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX
,
/* GPIO_AD_B0_13 PAD functional properties : */
0x10B0u
);
/* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
#endif
#ifdef BSP_USING_LPUART2
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B1_02_LPUART2_TX
,
0U
);
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B1_03_LPUART2_RX
,
0U
);
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_AD_B1_02_LPUART2_TX
,
0x10B0u
);
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_AD_B1_03_LPUART2_RX
,
0x10B0u
);
#endif
#ifdef BSP_USING_LPUART3
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B1_06_LPUART3_TX
,
0U
);
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B1_07_LPUART3_RX
,
0U
);
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_AD_B1_06_LPUART3_TX
,
0x10B0u
);
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_AD_B1_07_LPUART3_RX
,
0x10B0u
);
#endif
#ifdef BSP_USING_LPUART4
IOMUXC_SetPinMux
(
IOMUXC_GPIO_B1_00_LPUART4_TX
,
0U
);
IOMUXC_SetPinMux
(
IOMUXC_GPIO_B1_01_LPUART4_RX
,
0U
);
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_B1_00_LPUART4_TX
,
0x10B0u
);
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_B1_01_LPUART4_RX
,
0x10B0u
);
#endif
#ifdef BSP_USING_LPUART5
IOMUXC_SetPinMux
(
IOMUXC_GPIO_B1_12_LPUART5_TX
,
0U
);
IOMUXC_SetPinMux
(
IOMUXC_GPIO_B1_13_LPUART5_RX
,
0U
);
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_B1_12_LPUART5_TX
,
0x10B0u
);
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_B1_13_LPUART5_RX
,
0x10B0u
);
#endif
#ifdef BSP_USING_LPUART6
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B0_02_LPUART6_TX
,
0U
);
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B0_03_LPUART6_RX
,
0U
);
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_AD_B0_02_LPUART6_TX
,
0x10B0u
);
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_AD_B0_03_LPUART6_RX
,
0x10B0u
);
#endif
#ifdef BSP_USING_LPUART7
IOMUXC_SetPinMux
(
IOMUXC_GPIO_EMC_31_LPUART7_TX
,
0U
);
IOMUXC_SetPinMux
(
IOMUXC_GPIO_EMC_32_LPUART7_RX
,
0U
);
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_EMC_31_LPUART7_TX
,
0x10B0u
);
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_EMC_32_LPUART7_RX
,
0x10B0u
);
#endif
#ifdef BSP_USING_LPUART8
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B1_10_LPUART8_TX
,
0U
);
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B1_11_LPUART8_RX
,
0U
);
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_AD_B1_10_LPUART8_TX
,
0x10B0u
);
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_AD_B1_11_LPUART8_RX
,
0x10B0u
);
#endif
}
#endif
/* BSP_USING_LPUART */
#ifdef BSP_USING_ETH
void
imxrt_enet_pins_init
(
void
)
{
CLOCK_EnableClock
(
kCLOCK_Iomuxc
);
/* iomuxc clock (iomuxc_clk_enable): 0x03u */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
,
/* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_AD_B0_10_GPIO1_IO10
,
/* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
0U
);
IOMUXC_SetPinMux
(
IOMUXC_GPIO_B1_04_ENET_RX_DATA00
,
/* GPIO_B1_04 is configured as ENET_RX_DATA00 */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_B1_05_ENET_RX_DATA01
,
/* GPIO_B1_05 is configured as ENET_RX_DATA01 */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_B1_06_ENET_RX_EN
,
/* GPIO_B1_06 is configured as ENET_RX_EN */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_B1_07_ENET_TX_DATA00
,
/* GPIO_B1_07 is configured as ENET_TX_DATA00 */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_B1_08_ENET_TX_DATA01
,
/* GPIO_B1_08 is configured as ENET_TX_DATA01 */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_B1_09_ENET_TX_EN
,
/* GPIO_B1_09 is configured as ENET_TX_EN */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_B1_10_ENET_REF_CLK
,
/* GPIO_B1_10 is configured as ENET_REF_CLK */
1U
);
/* Software Input On Field: Force input path of pad GPIO_B1_10 */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_B1_11_ENET_RX_ER
,
/* GPIO_B1_11 is configured as ENET_RX_ER */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_EMC_40_ENET_MDC
,
/* GPIO_EMC_40 is configured as ENET_MDC */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux
(
IOMUXC_GPIO_EMC_41_ENET_MDIO
,
/* GPIO_EMC_41 is configured as ENET_MDIO */
0U
);
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09
,
/* GPIO_AD_B0_09 PAD functional properties : */
0xB0A9u
);
/* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_AD_B0_10_GPIO1_IO10
,
/* GPIO_AD_B0_10 PAD functional properties : */
0xB0A9u
);
/* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_B1_04_ENET_RX_DATA00
,
/* GPIO_B1_04 PAD functional properties : */
0xB0E9u
);
/* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_B1_05_ENET_RX_DATA01
,
/* GPIO_B1_05 PAD functional properties : */
0xB0E9u
);
/* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_B1_06_ENET_RX_EN
,
/* GPIO_B1_06 PAD functional properties : */
0xB0E9u
);
/* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_B1_07_ENET_TX_DATA00
,
/* GPIO_B1_07 PAD functional properties : */
0xB0E9u
);
/* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_B1_08_ENET_TX_DATA01
,
/* GPIO_B1_08 PAD functional properties : */
0xB0E9u
);
/* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_B1_09_ENET_TX_EN
,
/* GPIO_B1_09 PAD functional properties : */
0xB0E9u
);
/* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_B1_10_ENET_REF_CLK
,
/* GPIO_B1_10 PAD functional properties : */
0x31u
);
/* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/6
Speed Field: low(50MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Disabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_B1_11_ENET_RX_ER
,
/* GPIO_B1_11 PAD functional properties : */
0xB0E9u
);
/* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_EMC_40_ENET_MDC
,
/* GPIO_EMC_40 PAD functional properties : */
0xB0E9u
);
/* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig
(
IOMUXC_GPIO_EMC_41_ENET_MDIO
,
/* GPIO_EMC_41 PAD functional properties : */
0xB829u
);
/* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: low(50MHz)
Open Drain Enable Field: Open Drain Enabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
}
void
imxrt_enet_phy_reset_by_gpio
(
void
)
{
gpio_pin_config_t
gpio_config
=
{
kGPIO_DigitalOutput
,
0
,
kGPIO_NoIntmode
};
GPIO_PinInit
(
GPIO1
,
9
,
&
gpio_config
);
GPIO_PinInit
(
GPIO1
,
10
,
&
gpio_config
);
/* pull up the ENET_INT before RESET. */
GPIO_WritePinOutput
(
GPIO1
,
10
,
1
);
GPIO_WritePinOutput
(
GPIO1
,
9
,
0
);
rt_thread_delay
(
100
);
GPIO_WritePinOutput
(
GPIO1
,
9
,
1
);
}
#endif
/* BSP_USING_ETH */
/**
* This function will initial rt1050 board.
*/
...
...
@@ -121,6 +442,14 @@ void rt_hw_board_init()
NVIC_SetPriorityGrouping
(
NVIC_PRIORITYGROUP_4
);
SysTick_Config
(
SystemCoreClock
/
RT_TICK_PER_SECOND
);
#ifdef BSP_USING_LPUART
imxrt_uart_pins_init
();
#endif
#ifdef BSP_USING_ETH
imxrt_enet_pins_init
();
#endif
#ifdef BSP_USING_DMA
imxrt_dma_init
();
#endif
...
...
bsp/imxrt/imxrt1064-nxp-evk/board/board.h
浏览文件 @
d6ff0fc0
...
...
@@ -45,5 +45,11 @@ extern int heap_end;
void
rt_hw_board_init
(
void
);
#ifdef BSP_USING_ETH
void
imxrt_enet_pins_init
(
void
);
void
imxrt_enet_phy_reset_by_gpio
(
void
);
#define PHY_ADDRESS 0x02u
#endif
#endif
bsp/imxrt/imxrt1064-nxp-evk/board/ports/phyksz8081/fsl_phy.c
0 → 100644
浏览文件 @
d6ff0fc0
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_phy.h"
#include <rtthread.h>
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Defines the timeout macro. */
#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get the ENET instance from peripheral base address.
*
* @param base ENET peripheral base address.
* @return ENET instance.
*/
extern
uint32_t
ENET_GetInstance
(
ENET_Type
*
base
);
/*******************************************************************************
* Variables
******************************************************************************/
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to enet clocks for each instance. */
extern
clock_ip_name_t
s_enetClock
[
FSL_FEATURE_SOC_ENET_COUNT
];
#endif
/* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
status_t
PHY_Init
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
uint32_t
srcClock_Hz
)
{
uint32_t
bssReg
;
uint32_t
counter
=
PHY_TIMEOUT_COUNT
;
uint32_t
idReg
=
0
;
status_t
result
=
kStatus_Success
;
uint32_t
instance
=
ENET_GetInstance
(
base
);
uint32_t
timeDelay
;
uint32_t
ctlReg
=
0
;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Set SMI first. */
CLOCK_EnableClock
(
s_enetClock
[
instance
]);
#endif
/* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
ENET_SetSMI
(
base
,
srcClock_Hz
,
false
);
/* Initialization after PHY stars to work. */
while
((
idReg
!=
PHY_CONTROL_ID1
)
&&
(
counter
!=
0
))
{
PHY_Read
(
base
,
phyAddr
,
PHY_ID1_REG
,
&
idReg
);
counter
--
;
}
if
(
!
counter
)
{
return
kStatus_Fail
;
}
/* Reset PHY. */
counter
=
PHY_TIMEOUT_COUNT
;
result
=
PHY_Write
(
base
,
phyAddr
,
PHY_BASICCONTROL_REG
,
PHY_BCTL_RESET_MASK
);
if
(
result
==
kStatus_Success
)
{
#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
uint32_t
data
=
0
;
result
=
PHY_Read
(
base
,
phyAddr
,
PHY_CONTROL2_REG
,
&
data
);
if
(
result
!=
kStatus_Success
)
{
return
result
;
}
result
=
PHY_Write
(
base
,
phyAddr
,
PHY_CONTROL2_REG
,
(
data
|
PHY_CTL2_REFCLK_SELECT_MASK
));
if
(
result
!=
kStatus_Success
)
{
return
result
;
}
#endif
/* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */
/* Set the negotiation. */
result
=
PHY_Write
(
base
,
phyAddr
,
PHY_AUTONEG_ADVERTISE_REG
,
(
PHY_100BASETX_FULLDUPLEX_MASK
|
PHY_100BASETX_HALFDUPLEX_MASK
|
PHY_10BASETX_FULLDUPLEX_MASK
|
PHY_10BASETX_HALFDUPLEX_MASK
|
0x1U
));
if
(
result
==
kStatus_Success
)
{
result
=
PHY_Write
(
base
,
phyAddr
,
PHY_BASICCONTROL_REG
,
(
PHY_BCTL_AUTONEG_MASK
|
PHY_BCTL_RESTART_AUTONEG_MASK
));
if
(
result
==
kStatus_Success
)
{
/* Check auto negotiation complete. */
while
(
counter
--
)
{
result
=
PHY_Read
(
base
,
phyAddr
,
PHY_BASICSTATUS_REG
,
&
bssReg
);
if
(
result
==
kStatus_Success
)
{
PHY_Read
(
base
,
phyAddr
,
PHY_CONTROL1_REG
,
&
ctlReg
);
if
(((
bssReg
&
PHY_BSTATUS_AUTONEGCOMP_MASK
)
!=
0
)
&&
(
ctlReg
&
PHY_LINK_READY_MASK
))
{
/* Wait a moment for Phy status stable. */
for
(
timeDelay
=
0
;
timeDelay
<
PHY_TIMEOUT_COUNT
;
timeDelay
++
)
{
__ASM
(
"nop"
);
}
break
;
}
}
if
(
!
counter
)
{
return
kStatus_PHY_AutoNegotiateFail
;
}
}
}
}
}
return
result
;
}
status_t
PHY_Write
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
uint32_t
phyReg
,
uint32_t
data
)
{
uint32_t
counter
;
/* Clear the SMI interrupt event. */
ENET_ClearInterruptStatus
(
base
,
ENET_EIR_MII_MASK
);
/* Starts a SMI write command. */
ENET_StartSMIWrite
(
base
,
phyAddr
,
phyReg
,
kENET_MiiWriteValidFrame
,
data
);
/* Wait for SMI complete. */
for
(
counter
=
PHY_TIMEOUT_COUNT
;
counter
>
0
;
counter
--
)
{
if
(
ENET_GetInterruptStatus
(
base
)
&
ENET_EIR_MII_MASK
)
{
break
;
}
}
/* Check for timeout. */
if
(
!
counter
)
{
return
kStatus_PHY_SMIVisitTimeout
;
}
/* Clear MII interrupt event. */
ENET_ClearInterruptStatus
(
base
,
ENET_EIR_MII_MASK
);
return
kStatus_Success
;
}
status_t
PHY_Read
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
uint32_t
phyReg
,
uint32_t
*
dataPtr
)
{
assert
(
dataPtr
);
uint32_t
counter
;
/* Clear the MII interrupt event. */
ENET_ClearInterruptStatus
(
base
,
ENET_EIR_MII_MASK
);
/* Starts a SMI read command operation. */
ENET_StartSMIRead
(
base
,
phyAddr
,
phyReg
,
kENET_MiiReadValidFrame
);
/* Wait for MII complete. */
for
(
counter
=
PHY_TIMEOUT_COUNT
;
counter
>
0
;
counter
--
)
{
if
(
ENET_GetInterruptStatus
(
base
)
&
ENET_EIR_MII_MASK
)
{
break
;
}
}
/* Check for timeout. */
if
(
!
counter
)
{
return
kStatus_PHY_SMIVisitTimeout
;
}
/* Get data from MII register. */
*
dataPtr
=
ENET_ReadSMIData
(
base
);
/* Clear MII interrupt event. */
ENET_ClearInterruptStatus
(
base
,
ENET_EIR_MII_MASK
);
return
kStatus_Success
;
}
status_t
PHY_EnableLoopback
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
phy_loop_t
mode
,
phy_speed_t
speed
,
bool
enable
)
{
status_t
result
;
uint32_t
data
=
0
;
/* Set the loop mode. */
if
(
enable
)
{
if
(
mode
==
kPHY_LocalLoop
)
{
if
(
speed
==
kPHY_Speed100M
)
{
data
=
PHY_BCTL_SPEED_100M_MASK
|
PHY_BCTL_DUPLEX_MASK
|
PHY_BCTL_LOOP_MASK
;
}
else
{
data
=
PHY_BCTL_DUPLEX_MASK
|
PHY_BCTL_LOOP_MASK
;
}
return
PHY_Write
(
base
,
phyAddr
,
PHY_BASICCONTROL_REG
,
data
);
}
else
{
/* First read the current status in control register. */
result
=
PHY_Read
(
base
,
phyAddr
,
PHY_CONTROL2_REG
,
&
data
);
if
(
result
==
kStatus_Success
)
{
return
PHY_Write
(
base
,
phyAddr
,
PHY_CONTROL2_REG
,
(
data
|
PHY_CTL2_REMOTELOOP_MASK
));
}
}
}
else
{
/* Disable the loop mode. */
if
(
mode
==
kPHY_LocalLoop
)
{
/* First read the current status in control register. */
result
=
PHY_Read
(
base
,
phyAddr
,
PHY_BASICCONTROL_REG
,
&
data
);
if
(
result
==
kStatus_Success
)
{
data
&=
~
PHY_BCTL_LOOP_MASK
;
return
PHY_Write
(
base
,
phyAddr
,
PHY_BASICCONTROL_REG
,
(
data
|
PHY_BCTL_RESTART_AUTONEG_MASK
));
}
}
else
{
/* First read the current status in control one register. */
result
=
PHY_Read
(
base
,
phyAddr
,
PHY_CONTROL2_REG
,
&
data
);
if
(
result
==
kStatus_Success
)
{
return
PHY_Write
(
base
,
phyAddr
,
PHY_CONTROL2_REG
,
(
data
&
~
PHY_CTL2_REMOTELOOP_MASK
));
}
}
}
return
result
;
}
status_t
PHY_GetLinkStatus
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
bool
*
status
)
{
assert
(
status
);
status_t
result
=
kStatus_Success
;
uint32_t
data
;
/* Read the basic status register. */
result
=
PHY_Read
(
base
,
phyAddr
,
PHY_BASICSTATUS_REG
,
&
data
);
if
(
result
==
kStatus_Success
)
{
if
(
!
(
PHY_BSTATUS_LINKSTATUS_MASK
&
data
))
{
/* link down. */
*
status
=
false
;
}
else
{
/* link up. */
*
status
=
true
;
}
}
return
result
;
}
status_t
PHY_GetLinkSpeedDuplex
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
phy_speed_t
*
speed
,
phy_duplex_t
*
duplex
)
{
assert
(
duplex
);
status_t
result
=
kStatus_Success
;
uint32_t
data
,
ctlReg
;
/* Read the control two register. */
result
=
PHY_Read
(
base
,
phyAddr
,
PHY_CONTROL1_REG
,
&
ctlReg
);
if
(
result
==
kStatus_Success
)
{
data
=
ctlReg
&
PHY_CTL1_SPEEDUPLX_MASK
;
if
((
PHY_CTL1_10FULLDUPLEX_MASK
==
data
)
||
(
PHY_CTL1_100FULLDUPLEX_MASK
==
data
))
{
/* Full duplex. */
*
duplex
=
kPHY_FullDuplex
;
}
else
{
/* Half duplex. */
*
duplex
=
kPHY_HalfDuplex
;
}
data
=
ctlReg
&
PHY_CTL1_SPEEDUPLX_MASK
;
if
((
PHY_CTL1_100HALFDUPLEX_MASK
==
data
)
||
(
PHY_CTL1_100FULLDUPLEX_MASK
==
data
))
{
/* 100M speed. */
*
speed
=
kPHY_Speed100M
;
}
else
{
/* 10M speed. */
*
speed
=
kPHY_Speed10M
;
}
}
return
result
;
}
bsp/imxrt/imxrt1064-nxp-evk/board/ports/phyksz8081/fsl_phy.h
0 → 100644
浏览文件 @
d6ff0fc0
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_PHY_H_
#define _FSL_PHY_H_
#include "fsl_enet.h"
/*!
* @addtogroup phy_driver
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief PHY driver version */
#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*!< Version 2.0.0. */
/*! @brief Defines the PHY registers. */
#define PHY_BASICCONTROL_REG 0x00U
/*!< The PHY basic control register. */
#define PHY_BASICSTATUS_REG 0x01U
/*!< The PHY basic status register. */
#define PHY_ID1_REG 0x02U
/*!< The PHY ID one register. */
#define PHY_ID2_REG 0x03U
/*!< The PHY ID two register. */
#define PHY_AUTONEG_ADVERTISE_REG 0x04U
/*!< The PHY auto-negotiate advertise register. */
#define PHY_CONTROL1_REG 0x1EU
/*!< The PHY control one register. */
#define PHY_CONTROL2_REG 0x1FU
/*!< The PHY control two register. */
#define PHY_CONTROL_ID1 0x22U
/*!< The PHY ID1*/
/*! @brief Defines the mask flag in basic control register. */
#define PHY_BCTL_DUPLEX_MASK 0x0100U
/*!< The PHY duplex bit mask. */
#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U
/*!< The PHY restart auto negotiation mask. */
#define PHY_BCTL_AUTONEG_MASK 0x1000U
/*!< The PHY auto negotiation bit mask. */
#define PHY_BCTL_SPEED_MASK 0x2000U
/*!< The PHY speed bit mask. */
#define PHY_BCTL_LOOP_MASK 0x4000U
/*!< The PHY loop bit mask. */
#define PHY_BCTL_RESET_MASK 0x8000U
/*!< The PHY reset bit mask. */
#define PHY_BCTL_SPEED_100M_MASK 0x2000U
/*!< The PHY 100M speed mask. */
/*!@brief Defines the mask flag of operation mode in control two register*/
#define PHY_CTL2_REMOTELOOP_MASK 0x0004U
/*!< The PHY remote loopback mask. */
#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U
/*!< The PHY RMII reference clock select. */
#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U
/*!< The PHY 10M half duplex mask. */
#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U
/*!< The PHY 100M half duplex mask. */
#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U
/*!< The PHY 10M full duplex mask. */
#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U
/*!< The PHY 100M full duplex mask. */
#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U
/*!< The PHY speed and duplex mask. */
#define PHY_CTL1_ENERGYDETECT_MASK 0x10U
/*!< The PHY signal present on rx differential pair. */
#define PHY_CTL1_LINKUP_MASK 0x100U
/*!< The PHY link up. */
#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
/*! @brief Defines the mask flag in basic status register. */
#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U
/*!< The PHY link status mask. */
#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U
/*!< The PHY auto-negotiation ability mask. */
#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U
/*!< The PHY auto-negotiation complete mask. */
/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
#define PHY_100BaseT4_ABILITY_MASK 0x200U
/*!< The PHY have the T4 ability. */
#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U
/*!< The PHY has the 100M full duplex ability.*/
#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U
/*!< The PHY has the 100M full duplex ability.*/
#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U
/*!< The PHY has the 10M full duplex ability.*/
#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U
/*!< The PHY has the 10M full duplex ability.*/
/*! @brief Defines the PHY status. */
enum
_phy_status
{
kStatus_PHY_SMIVisitTimeout
=
MAKE_STATUS
(
kStatusGroup_PHY
,
1
),
/*!< ENET PHY SMI visit timeout. */
kStatus_PHY_AutoNegotiateFail
=
MAKE_STATUS
(
kStatusGroup_PHY
,
2
)
/*!< ENET PHY AutoNegotiate Fail. */
};
/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
typedef
enum
_phy_speed
{
kPHY_Speed10M
=
0U
,
/*!< ENET PHY 10M speed. */
kPHY_Speed100M
/*!< ENET PHY 100M speed. */
}
phy_speed_t
;
/*! @brief Defines the PHY link duplex. */
typedef
enum
_phy_duplex
{
kPHY_HalfDuplex
=
0U
,
/*!< ENET PHY half duplex. */
kPHY_FullDuplex
/*!< ENET PHY full duplex. */
}
phy_duplex_t
;
/*! @brief Defines the PHY loopback mode. */
typedef
enum
_phy_loop
{
kPHY_LocalLoop
=
0U
,
/*!< ENET PHY local loopback. */
kPHY_RemoteLoop
/*!< ENET PHY remote loopback. */
}
phy_loop_t
;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern
"C"
{
#endif
/*!
* @name PHY Driver
* @{
*/
/*!
* @brief Initializes PHY.
*
* This function initialize the SMI interface and initialize PHY.
* The SMI is the MII management interface between PHY and MAC, which should be
* firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
* @retval kStatus_Success PHY initialize success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
* @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail
*/
status_t
PHY_Init
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
uint32_t
srcClock_Hz
);
/*!
* @brief PHY Write function. This function write data over the SMI to
* the specified PHY register. This function is called by all PHY interfaces.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param phyReg The PHY register.
* @param data The data written to the PHY register.
* @retval kStatus_Success PHY write success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t
PHY_Write
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
uint32_t
phyReg
,
uint32_t
data
);
/*!
* @brief PHY Read function. This interface read data over the SMI from the
* specified PHY register. This function is called by all PHY interfaces.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param phyReg The PHY register.
* @param dataPtr The address to store the data read from the PHY register.
* @retval kStatus_Success PHY read success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t
PHY_Read
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
uint32_t
phyReg
,
uint32_t
*
dataPtr
);
/*!
* @brief Enables/disables PHY loopback.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param mode The loopback mode to be enabled, please see "phy_loop_t".
* the two loopback mode should not be both set. when one loopback mode is set
* the other one should be disabled.
* @param speed PHY speed for loopback mode.
* @param enable True to enable, false to disable.
* @retval kStatus_Success PHY loopback success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t
PHY_EnableLoopback
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
phy_loop_t
mode
,
phy_speed_t
speed
,
bool
enable
);
/*!
* @brief Gets the PHY link status.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param status The link up or down status of the PHY.
* - true the link is up.
* - false the link is down.
* @retval kStatus_Success PHY get link status success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t
PHY_GetLinkStatus
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
bool
*
status
);
/*!
* @brief Gets the PHY link speed and duplex.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param speed The address of PHY link speed.
* @param duplex The link duplex of PHY.
* @retval kStatus_Success PHY get link speed and duplex success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t
PHY_GetLinkSpeedDuplex
(
ENET_Type
*
base
,
uint32_t
phyAddr
,
phy_speed_t
*
speed
,
phy_duplex_t
*
duplex
);
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif
/* _FSL_PHY_H_ */
bsp/imxrt/imxrt1064-nxp-evk/board/ports/sdram_port.h
0 → 100644
浏览文件 @
d6ff0fc0
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-05 zylx The first version for STM32F4xx
* 2019-4-25 misonyo port to IMXRT
*/
#ifndef SDRAM_PORT_H__
#define SDRAM_PORT_H__
/* parameters for sdram peripheral */
#define SDRAM_BANK_ADDR ((uint32_t)0x80000000U)
/* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */
#define SDRAM_REGION kSEMC_SDRAM_CS0
/* CS pin: kSEMC_MUXCSX0/1/2/3 */
#define SDRAM_CS_PIN kSEMC_MUXCSX0
/* size(kbyte):32MB = 32*1024*1KBytes */
#define SDRAM_SIZE ((uint32_t)0x8000)
/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */
#define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit
/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */
#define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit
/* cas latency clock number: kSEMC_LatencyOne/Two/Three */
#define SDRAM_CAS_LATENCY kSEMC_LatencyThree
/* Timing configuration for W9825G6KH */
/* TRP:precharge to active command time (ns) */
#define SDRAM_TRP 18
/* TRCD:active to read/write command delay time (ns) */
#define SDRAM_TRCD 18
/* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */
#define SDRAM_REFRESH_RECOVERY 67
/* TWR:write recovery time (ns). */
#define SDRAM_TWR 12
/* TRAS:active to precharge command time (ns). */
#define SDRAM_TRAS 42
/* TRC time (ns). */
#define SDRAM_TRC 60
/* active to active time (ns). */
#define SDRAM_ACT2ACT 60
/* refresh time (ns). 64ms */
#define SDRAM_REFRESH_ROW 64 * 1000000 / 8192
#endif
/* SDRAM_PORT_H__ */
bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py
浏览文件 @
d6ff0fc0
...
...
@@ -48,7 +48,7 @@ if PLATFORM == 'gcc':
DEVICE
=
' -mcpu='
+
CPU
+
' -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
CFLAGS
=
DEVICE
+
' -Wall -D__FPU_PRESENT -eentry'
AFLAGS
=
' -c'
+
DEVICE
+
' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry'
LFLAGS
=
DEVICE
+
' -lm -lgcc -lc'
+
' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
LFLAGS
=
DEVICE
+
' -lm -lgcc -lc'
+
' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds
-Xlinker -print-memory-usage
'
CPATH
=
''
LPATH
=
''
...
...
@@ -57,8 +57,8 @@ if PLATFORM == 'gcc':
AFLAGS
+=
' -D__STARTUP_CLEAR_BSS'
if
BUILD
==
'debug'
:
CFLAGS
+=
' -g
dwarf-2
'
AFLAGS
+=
' -g
dwarf-2
'
CFLAGS
+=
' -g'
AFLAGS
+=
' -g'
CFLAGS
+=
' -O0'
else
:
CFLAGS
+=
' -O2 -Os'
...
...
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