add support stm32wl and bsp/stm32wl55jc-st-nucleo(recommit)

update STM32WLxx_HAL to released v1.0.0

bsp/stm32/libraries/HAL_Drivers/config/wl/dma_config.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1 */
+
+/* DMA1 channel2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler          DMA1_Channel2_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
+#define SPI1_RX_DMA_REQUEST             DMA_REQUEST_1
+#define SPI1_RX_DMA_IRQ                 DMA1_Channel2_IRQn
+#endif
+
+/* DMA1 channel3 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA1_Channel3_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel3
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_1
+#define SPI1_TX_DMA_IRQ                 DMA1_Channel3_IRQn
+#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler         DMA1_Channel3_IRQHandler
+#define UART3_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE           DMA1_Channel3
+#define UART3_RX_DMA_REQUEST            DMA_REQUEST_2
+#define UART3_RX_DMA_IRQ                DMA1_Channel3_IRQn
+#endif
+
+/* DMA1 channel4 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA1_Channel4_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART1_TX_DMA_INSTANCE           DMA1_Channel4
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_2
+#define UART1_TX_DMA_IRQ                DMA1_Channel4_IRQn
+#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler          DMA1_Channel4_IRQHandler
+#define SPI2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE            DMA1_Channel4
+#define SPI2_RX_DMA_REQUEST             DMA_REQUEST_1
+#define SPI2_RX_DMA_IRQ                 DMA1_Channel4_IRQn
+#endif
+
+/* DMA1 channel5 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE           DMA1_Channel5
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_USART1_RX//DMA_REQUEST_2
+#define UART1_RX_DMA_IRQ                DMA1_Channel5_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler             DMA1_Channel5_IRQHandler
+#define QSPI_DMA_RCC                    RCC_AHB1ENR_DMA1EN
+#define QSPI_DMA_INSTANCE               DMA1_Channel5
+#define QSPI_DMA_REQUEST                DMA_REQUEST_5
+#define QSPI_DMA_IRQ                    DMA1_Channel5_IRQn
+#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler          DMA1_Channel5_IRQHandler
+#define SPI2_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE            DMA1_Channel5
+#define SPI2_TX_DMA_REQUEST             DMA_REQUEST_1
+#define SPI2_TX_DMA_IRQ                 DMA1_Channel5_IRQn
+#endif
+
+/* DMA1 channel6 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler         DMA1_Channel6_IRQHandler
+#define UART2_RX_DMA_RCC                RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE           DMA1_Channel6
+#define UART2_RX_DMA_REQUEST            DMA_REQUEST_USART2_RX//DMA_REQUEST_2
+#define UART2_RX_DMA_IRQ                DMA1_Channel6_IRQn
+#endif
+
+/* DMA1 channel7 */
+
+/* DMA2 channel1 */
+#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART5_DMA_TX_IRQHandler         DMA2_Channel1_IRQHandler
+#define UART5_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART5_TX_DMA_INSTANCE           DMA2_Channel1
+#define UART5_TX_DMA_REQUEST            DMA_REQUEST_2
+#define UART5_TX_DMA_IRQ                DMA2_Channel1_IRQn
+#endif
+
+/* DMA2 channel2 */
+#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler         DMA2_Channel2_IRQHandler
+#define UART5_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART5_RX_DMA_INSTANCE           DMA2_Channel2
+#define UART5_RX_DMA_REQUEST            DMA_REQUEST_2
+#define UART5_RX_DMA_IRQ                DMA2_Channel2_IRQn
+#endif
+
+/* DMA2 channel3 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler          DMA2_Channel3_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE            DMA2_Channel3
+#define SPI1_RX_DMA_REQUEST             DMA_REQUEST_4
+#define SPI1_RX_DMA_IRQ                 DMA2_Channel3_IRQn
+#endif
+
+/* DMA2 channel4 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA2_Channel4_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE            DMA2_Channel4
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_4
+#define SPI1_TX_DMA_IRQ                 DMA2_Channel4_IRQn
+#endif
+
+/* DMA2 channel5 */
+
+/* DMA2 channel6 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA2_Channel6_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_TX_DMA_INSTANCE           DMA2_Channel6
+#define UART1_TX_DMA_REQUEST            DMA_REQUEST_2
+#define UART1_TX_DMA_IRQ                DMA2_Channel6_IRQn
+#endif
+
+/* DMA2 channel7 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Channel7_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Channel7
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_2
+#define UART1_RX_DMA_IRQ                DMA2_Channel7_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler             DMA2_Channel7_IRQHandler
+#define QSPI_DMA_RCC                    RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE               DMA2_Channel7
+#define QSPI_DMA_REQUEST                DMA_REQUEST_3
+#define QSPI_DMA_IRQ                    DMA2_Channel7_IRQn
+#elif defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
+#define LPUART1_DMA_RX_IRQHandler       DMA2_Channel7_IRQHandler
+#define LPUART1_RX_DMA_RCC              RCC_AHB1ENR_DMA2EN
+#define LPUART1_RX_DMA_INSTANCE         DMA2_Channel7
+#define LPUART1_RX_DMA_REQUEST          DMA_REQUEST_LPUART1_RX
+#define LPUART1_RX_DMA_IRQ              DMA2_Channel7_IRQn
+#endif
+
+/* DMA2 channel6 */
+#if defined(BSP_LPUART1_TX_USING_DMA) && !defined(LPUART1_TX_DMA_INSTANCE)
+#define LPUART1_DMA_TX_IRQHandler         DMA2_Channel6_IRQHandler
+#define LPUART1_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define LPUART1_TX_DMA_INSTANCE           DMA2_Channel6
+#define LPUART1_TX_DMA_REQUEST            DMA_REQUEST_LPUART1_TX
+#define LPUART1_TX_DMA_IRQ                DMA2_Channel6_IRQn
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/wl/spi_config.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI1,                                   \
+        .bus_name = "spi1",                                 \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI1_TX_DMA_RCC,                         \
+        .Instance = SPI1_TX_DMA_INSTANCE,                   \
+        .request = SPI1_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI1_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI1_RX_DMA_RCC,                         \
+        .Instance = SPI1_RX_DMA_INSTANCE,                   \
+        .request = SPI1_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI1_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI2,                                   \
+        .bus_name = "spi2",                                 \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI2_TX_DMA_RCC,                         \
+        .Instance = SPI2_TX_DMA_INSTANCE,                   \
+        .request = SPI2_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI2_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI2_RX_DMA_RCC,                         \
+        .Instance = SPI2_RX_DMA_INSTANCE,                   \
+        .request = SPI2_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI2_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = SPI3,                                   \
+        .bus_name = "spi3",                                 \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI3_TX_DMA_RCC,                         \
+        .Instance = SPI3_TX_DMA_INSTANCE,                   \
+        .request = SPI3_TX_DMA_REQUEST,                     \
+        .dma_irq = SPI3_TX_DMA_IRQ,                         \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .dma_rcc = SPI3_RX_DMA_RCC,                         \
+        .Instance = SPI3_RX_DMA_INSTANCE,                   \
+        .request = SPI3_RX_DMA_REQUEST,                     \
+        .dma_irq = SPI3_RX_DMA_IRQ,                         \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/wl/tim_config.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-12     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#ifdef BSP_USING_TIM2
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFFFFFF,                  \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#else
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }    
+#endif    
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CONFIG
+#define TIM2_CONFIG                                        \
+    {                                                      \
+       .tim_handle.Instance     = TIM2,                    \
+       .tim_irqn                = TIM2_IRQn,               \
+       .name                    = "timer2",                \
+    }
+#endif /* TIM2_CONFIG */
+#endif /* BSP_USING_TIM2 */
+    
+#ifdef BSP_USING_TIM15
+#ifndef TIM15_CONFIG
+#define TIM15_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM15,                    \
+       .tim_irqn                = TIM1_BRK_TIM15_IRQn,      \
+       .name                    = "timer15",                \
+    }
+#endif /* TIM15_CONFIG */
+#endif /* BSP_USING_TIM15 */
+
+#ifdef BSP_USING_TIM16
+#ifndef TIM16_CONFIG
+#define TIM16_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM16,                    \
+       .tim_irqn                = TIM1_UP_TIM16_IRQn,       \
+       .name                    = "timer16",                \
+    }
+#endif /* TIM16_CONFIG */
+#endif /* BSP_USING_TIM16 */
+
+#ifdef BSP_USING_TIM17
+#ifndef TIM17_CONFIG
+#define TIM17_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM17,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM17_IRQn,  \
+       .name                    = "timer17",                \
+    }
+#endif /* TIM17_CONFIG */
+#endif /* BSP_USING_TIM17 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/wl/uart_config.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_LPUART1)
+#ifndef LPUART1_CONFIG
+#define LPUART1_CONFIG                                              \
+    {                                                               \
+        .name = "lpuart1",                                          \
+        .Instance = LPUART1,                                        \
+        .irq_type = LPUART1_IRQn,                                   \
+    }
+#endif /* LPUART1_CONFIG */
+#if defined(BSP_LPUART1_RX_USING_DMA)
+#ifndef LPUART1_DMA_RX_CONFIG
+#define LPUART1_DMA_RX_CONFIG                                          \
+    {                                                               \
+        .Instance = LPUART1_RX_DMA_INSTANCE,                        \
+        .request  = LPUART1_RX_DMA_REQUEST,                         \
+        .dma_rcc  = LPUART1_RX_DMA_RCC,                             \
+        .dma_irq  = LPUART1_RX_DMA_IRQ,                             \
+    }
+#endif /* LPUART1_DMA_CONFIG */
+#endif /* BSP_LPUART1_RX_USING_DMA */
+
+
+#if defined(BSP_LPUART1_TX_USING_DMA)
+#ifndef LPUART1_DMA_TX_CONFIG
+#define LPUART1_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = LPUART1_TX_DMA_INSTANCE,                         \
+        .dma_rcc = LPUART1_TX_DMA_RCC,                               \
+        .dma_irq = LPUART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+    
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */  
+   
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .request  = UART2_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .request  = UART3_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+    
+#ifdef __cplusplus
+}
+#endif 
+
+#endif

bsp/stm32/libraries/HAL_Drivers/drv_config.h

@@ -117,6 +117,11 @@ extern "C" {
 #include "mp1/dac_config.h"    
 #include "mp1/tim_config.h"
 #include "mp1/pwm_config.h"    
+#elif  defined(SOC_SERIES_STM32WL)
+#include "wl/dma_config.h"
+#include "wl/uart_config.h"
+#include "wl/spi_config.h"
+#include "wl/tim_config.h"
 #elif  defined(SOC_SERIES_STM32WB)
 #include "wb/adc_config.h"
 #include "wb/dma_config.h"

bsp/stm32/libraries/HAL_Drivers/drv_dma.h

@@ -20,12 +20,12 @@ extern "C" {
 #endif
 
 #if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) \
-	|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
+	|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
 #define DMA_INSTANCE_TYPE              DMA_Channel_TypeDef
 #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
 	|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
 #define DMA_INSTANCE_TYPE              DMA_Stream_TypeDef
-#endif /*  defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) */
+#endif /*  defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL)  */
 
 struct dma_config {
     DMA_INSTANCE_TYPE *Instance;
@@ -36,7 +36,7 @@ struct dma_config {
     rt_uint32_t channel;
 #endif
 
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL)  || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
     || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
     rt_uint32_t request;
 #endif

bsp/stm32/libraries/HAL_Drivers/drv_rtc.c

@@ -102,7 +102,7 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
 
 static void rt_rtc_init(void)
 {
-#if !defined(SOC_SERIES_STM32H7) && !defined(SOC_SERIES_STM32WB)
+#if !defined(SOC_SERIES_STM32H7) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32WB)
     __HAL_RCC_PWR_CLK_ENABLE();
 #endif
 
@@ -171,6 +171,10 @@ static rt_err_t rt_rtc_config(struct rt_device *dev)
 #endif
     HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
 
+#if defined(SOC_SERIES_STM32WL)
+    __HAL_RCC_RTCAPB_CLK_ENABLE();
+#endif
+
     /* Enable RTC Clock */
     __HAL_RCC_RTC_ENABLE();
 
@@ -197,7 +201,7 @@ static rt_err_t rt_rtc_config(struct rt_device *dev)
         RTC_Handler.Init.OutPut = RTC_OUTPUT_DISABLE;
         RTC_Handler.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
         RTC_Handler.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
-#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
+#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
 
         /* set the frequency division */
 #ifdef BSP_RTC_USING_LSI

bsp/stm32/libraries/HAL_Drivers/drv_usart.c

@@ -9,6 +9,7 @@
  * 2020-03-16     SummerGift   add device close feature
  * 2020-03-20     SummerGift   fix bug caused by ORE
  * 2020-05-02     whj4674672   support stm32h7 uart dma
+ * 2020-09-09     forest-rain  support stm32wl uart 
  * 2020-10-14     Dozingfiretruck   Porting for stm32wbxx
  */
 
@@ -242,7 +243,7 @@ static int stm32_putc(struct rt_serial_device *serial, char c)
 
     uart = rt_container_of(serial, struct stm32_uart, serial);
     UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
     || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
     || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
     uart->handle.Instance->TDR = c;
@@ -263,7 +264,7 @@ static int stm32_getc(struct rt_serial_device *serial)
     ch = -1;
     if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_RXNE) != RESET)
     {
-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
     || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
     || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB)
         ch = uart->handle.Instance->RDR & 0xff;
@@ -366,7 +367,7 @@ static void uart_isr(struct rt_serial_device *serial)
         {
             __HAL_UART_CLEAR_PEFLAG(&uart->handle);
         }
-#if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
+#if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32WL) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
     && !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
     && !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1) && !defined(SOC_SERIES_STM32WB)
         if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
@@ -866,7 +867,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
         /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
         SET_BIT(RCC->AHBENR, dma_config->dma_rcc);
         tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc);
-#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) \
+#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
     || defined(SOC_SERIES_STM32G4)|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32WB)
         /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
         SET_BIT(RCC->AHB1ENR, dma_config->dma_rcc);
@@ -875,14 +876,15 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
         /* enable DMA clock && Delay after an RCC peripheral clock enabling*/
         SET_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
         tmpreg = READ_BIT(RCC->MP_AHB2ENSETR, dma_config->dma_rcc);
-#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1)
+#endif
+
+#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)) && defined(DMAMUX1)
         /* enable DMAMUX clock for L4+ and G4 */
         __HAL_RCC_DMAMUX1_CLK_ENABLE();   
 #elif defined(SOC_SERIES_STM32MP1)
-    __HAL_RCC_DMAMUX_CLK_ENABLE();
+        __HAL_RCC_DMAMUX_CLK_ENABLE();
 #endif
 
-#endif
         UNUSED(tmpreg);   /* To avoid compiler warnings */
     }
 
@@ -900,7 +902,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
 #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
     DMA_Handle->Instance                 = dma_config->Instance;
     DMA_Handle->Init.Channel             = dma_config->channel;
-#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)\
     || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
     DMA_Handle->Instance                 = dma_config->Instance;
     DMA_Handle->Init.Request             = dma_config->request;

bsp/stm32/libraries/HAL_Drivers/drv_usart.h

@@ -21,15 +21,15 @@
 
 int rt_hw_usart_init(void);
 
-#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) \
+#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) \
     || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
 #define DMA_INSTANCE_TYPE              DMA_Channel_TypeDef
 #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
     || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
 #define DMA_INSTANCE_TYPE              DMA_Stream_TypeDef
-#endif /*  defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) */
+#endif /*  defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) */
 
-#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F2) \
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32F2) \
     || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \
     || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
 #define UART_INSTANCE_CLEAR_FUNCTION    __HAL_UART_CLEAR_FLAG

bsp/stm32/libraries/Kconfig

@@ -61,7 +61,14 @@ config SOC_SERIES_STM32MP1
     select ARCH_ARM_CORTEX_M4
     select SOC_FAMILY_STM32
 
+config SOC_SERIES_STM32WL
+    bool
+    select ARCH_ARM_CORTEX_M4
+    select SOC_FAMILY_STM32
+    
 config SOC_SERIES_STM32WB
     bool
     select ARCH_ARM_CORTEX_M4
     select SOC_FAMILY_STM32
+    
+

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h

+/**
+  ******************************************************************************
+  * @file    stm32wlxx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32WLxx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32WLxx device used in the target application
+  *              - To use or not the peripherals drivers in application code(i.e.
+  *                code will be based on direct access to peripherals registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32wlxx
+  * @{
+  */
+
+#ifndef __STM32WLxx_H
+#define __STM32WLxx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32WL)
+#define STM32WL
+#endif /* STM32WL */
+
+/* Uncomment the line below according to the target STM32WL device used in your
+   application
+  */
+
+#if !defined (STM32WL55xx) && !defined (STM32WL54xx) && !defined (STM32WLE5xx) && !defined (STM32WLE4xx)
+  /* #define STM32WL55xx */   /*!< STM32WL55xx Devices */
+  /* #define STM32WL54xx */   /*!< STM32WL54xx Devices */
+  /* #define STM32WLE5xx */   /*!< STM32WLE5xx Devices */
+  /* #define STM32WLE4xx */   /*!< STM32WLE4xx Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number
+  */
+#define __STM32WLxx_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
+#define __STM32WLxx_CMSIS_VERSION_SUB1   (0x00U) /*!< [23:16] sub1 version */
+#define __STM32WLxx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
+#define __STM32WLxx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32WLxx_CMSIS_DEVICE_VERSION        ((__STM32WLxx_CMSIS_VERSION_MAIN << 24)\
+                                                |(__STM32WLxx_CMSIS_VERSION_SUB1 << 16)\
+                                                |(__STM32WLxx_CMSIS_VERSION_SUB2 << 8 )\
+                                                |(__STM32WLxx_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32WL55xx)
+  #include "stm32wl55xx.h"
+#elif defined(STM32WLE5xx)
+  #include "stm32wle5xx.h"
+#elif defined(STM32WL54xx)
+  #include "stm32wl54xx.h"
+#elif defined(STM32WLE4xx)
+  #include "stm32wle4xx.h"
+#else
+ #error "Please select first the target STM32WLxx device used in your application, for instance xxx (in stm32wlxx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#if defined(CORE_CM0PLUS)
+#else
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+#endif
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32wlxx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32WLxx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h

+/**
+  ******************************************************************************
+  * @file    system_stm32wlxx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex Device System Source File for STM32WLxx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics. 
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32wlxx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32WLXX_H
+#define __SYSTEM_STM32WLXX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include <stdint.h>
+
+/** @addtogroup STM32WLxx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32WLxx_System_Exported_types
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) from within HAL_Init()
+      2) by calling CMSIS function SystemCoreClockUpdate()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+  */
+
+extern uint32_t SystemCoreClock;            /*!< System Clock Frequency */
+
+extern const uint32_t AHBPrescTable[16];    /*!< AHB prescalers table values */
+extern const uint32_t APBPrescTable[8];     /*!< APB prescalers table values */
+extern const uint32_t MSIRangeTable[16];    /*!< MSI ranges table values     */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WLxx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WLxx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32WLxx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32WLXX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/linker/stm32wl54xx_flash_cm0plus.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08020000 0x00020000  {    ; load region size_region
+  ; FLASH part dedicated to M0+
+  ER_IROM1 0x08020000 0x00020000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; Non-backup SRAM1 dedicated to M0+
+  RW_IRAM1 0x20004000 0x00004000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  ; Backup SRAM2 dedicated to M0+
+  RW_IRAM2 0x2000C000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
+  }
+}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/linker/stm32wl54xx_flash_cm4.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00020000  {    ; load region size_region
+  ; FLASH part dedicated to M4
+  ER_IROM1 0x08000000 0x00020000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; Non-backup SRAM1 dedicated to M4
+  RW_IRAM1 0x20000000 0x00004000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  ; Backup SRAM2 dedicated to M4
+  RW_IRAM2 0x20008000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
+  }
+}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/linker/stm32wl55xx_flash_cm0plus.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08020000 0x00020000  {    ; load region size_region
+  ; FLASH part dedicated to M0+
+  ER_IROM1 0x08020000 0x00020000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; Non-backup SRAM1 dedicated to M0+
+  RW_IRAM1 0x20004000 0x00004000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  ; Backup SRAM2 dedicated to M0+
+  RW_IRAM2 0x2000C000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
+  }
+}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/linker/stm32wl55xx_flash_cm4.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00020000  {    ; load region size_region
+  ; FLASH part dedicated to M4
+  ER_IROM1 0x08000000 0x00020000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; Non-backup SRAM1 dedicated to M4
+  RW_IRAM1 0x20000000 0x00004000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  ; Backup SRAM2 dedicated to M4
+  RW_IRAM2 0x20008000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
+  }
+}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/linker/stm32wle4xx_flash.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
+  ; FLASH
+  ER_IROM1 0x08000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; Non-backup SRAM1
+  RW_IRAM1 0x20000000 0x00008000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  ; Backup SRAM2
+  RW_IRAM2 0x20008000 EMPTY 0x00008000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
+  }
+}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/linker/stm32wle5xx_flash.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
+  ; FLASH
+  ER_IROM1 0x08000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  ; Non-backup SRAM1
+  RW_IRAM1 0x20000000 0x00008000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+  ; Backup SRAM2
+  RW_IRAM2 0x20008000 EMPTY 0x00008000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
+  }
+}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wl54xx_cm0plus.s

+;******************************************************************************
+;* File Name          : startup_stm32wl54xx_cm0plus.s
+;* Author             : MCD Application Team
+;* Description        : STM32WL54xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M0+ processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                     ; Top of Stack
+                DCD     Reset_Handler                    ; Reset Handler
+                DCD     NMI_Handler                      ; NMI Handler
+                DCD     HardFault_Handler                ; Hard Fault Handler
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     SVC_Handler                      ; SVCall Handler
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     PendSV_Handler                   ; PendSV Handler
+                DCD     SysTick_Handler                  ; SysTick Handler
+
+                ; External Interrupts                    
+                DCD     TZIC_ILA_IRQHandler              ; Security Interrupt controller illegal access Interrupts
+                DCD     PVD_PVM_IRQHandler               ; PVD and PVM detector
+                DCD     RTC_LSECSS_IRQHandler            ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) + SSR Underflow and LSECSS Interrupts
+                DCD     RCC_FLASH_C1SEV_IRQHandler       ; RCC1 and FLASH and CPU1 M4 SEV Interrupts
+                DCD     EXTI1_0_IRQHandler               ; EXTI Line 1:0 Interrupts
+                DCD     EXTI3_2_IRQHandler               ; XTI Line 3:2 Interrupts
+                DCD     EXTI15_4_IRQHandler              ; EXTI Line 15:4 interrupts
+                DCD     ADC_COMP_DAC_IRQHandler          ; ADC, COMP1, COMP2, DAC Interrupts
+                DCD     DMA1_Channel1_2_3_IRQHandler     ; DMA1 Channel 1 to 3 Interrupts
+                DCD     DMA1_Channel4_5_6_7_IRQHandler   ; DMA1 Channels 4, 5, 6, 7 Interrupts
+                DCD     DMA2_DMAMUX1_OVR_IRQHandler      ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts          
+                DCD     LPTIM1_IRQHandler                ; LPTIM1 global Interrupt
+                DCD     LPTIM2_IRQHandler                ; LPTIM2 global Interrupt
+                DCD     LPTIM3_IRQHandler                ; LPTIM3 global Interrupt
+                DCD     TIM1_IRQHandler                  ; TIM1 Interrupt
+                DCD     TIM2_IRQHandler                  ; TIM2 Interrupt
+                DCD     TIM16_IRQHandler                 ; TIM16 Interrupt
+                DCD     TIM17_IRQHandler                 ; TIM17 Interrupt
+                DCD     IPCC_C2_RX_C2_TX_IRQHandler      ; IPCC RX Occupied and TX Free Interrupt Interrupts
+                DCD     HSEM_IRQHandler                  ; Semaphore Interrupt
+                DCD     RNG_IRQHandler                   ; RNG Interrupt
+                DCD     AES_PKA_IRQHandler               ; AES and PKA Interrupts
+                DCD     I2C1_IRQHandler                  ; I2C1 Event and Error Interrupt
+                DCD     I2C2_IRQHandler                  ; I2C2 Event and Error Interrupt
+                DCD     I2C3_IRQHandler                  ; I2C3 Event and Error Interrupt
+                DCD     SPI1_IRQHandler                  ; SPI1 Interrupts
+                DCD     SPI2_IRQHandler                  ; SPI2 Interrupt
+                DCD     USART1_IRQHandler                ; USART1 Interrupt
+                DCD     USART2_IRQHandler                ; USART2 Interrupt
+                DCD     LPUART1_IRQHandler               ; LPUART1 Interrupt
+                DCD     SUBGHZSPI_IRQHandler             ; SUBGHZSPI Interrupt
+                DCD     SUBGHZ_Radio_IRQHandler          ; SUBGHZ Radio Interrupt
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  TZIC_ILA_IRQHandler            [WEAK]
+                EXPORT  PVD_PVM_IRQHandler             [WEAK]
+                EXPORT  RTC_LSECSS_IRQHandler          [WEAK]
+                EXPORT  RCC_FLASH_C1SEV_IRQHandler     [WEAK]
+                EXPORT  EXTI1_0_IRQHandler             [WEAK]
+                EXPORT  EXTI3_2_IRQHandler             [WEAK]
+                EXPORT  EXTI15_4_IRQHandler            [WEAK]
+                EXPORT  ADC_COMP_DAC_IRQHandler        [WEAK]
+                EXPORT  DMA1_Channel1_2_3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
+                EXPORT  DMA2_DMAMUX1_OVR_IRQHandler    [WEAK]
+                EXPORT  LPTIM1_IRQHandler              [WEAK]
+                EXPORT  LPTIM2_IRQHandler              [WEAK]
+                EXPORT  LPTIM3_IRQHandler              [WEAK]
+                EXPORT  TIM1_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                [WEAK]
+                EXPORT  TIM16_IRQHandler               [WEAK]
+                EXPORT  TIM17_IRQHandler               [WEAK]
+                EXPORT  IPCC_C2_RX_C2_TX_IRQHandler    [WEAK]
+                EXPORT  HSEM_IRQHandler                [WEAK]
+                EXPORT  RNG_IRQHandler                 [WEAK]
+                EXPORT  AES_PKA_IRQHandler             [WEAK]
+                EXPORT  I2C1_IRQHandler                [WEAK]
+                EXPORT  I2C2_IRQHandler                [WEAK]
+                EXPORT  I2C3_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                [WEAK]
+                EXPORT  SPI2_IRQHandler                [WEAK]
+                EXPORT  USART1_IRQHandler              [WEAK]
+                EXPORT  USART2_IRQHandler              [WEAK]
+                EXPORT  LPUART1_IRQHandler             [WEAK]
+                EXPORT  SUBGHZSPI_IRQHandler           [WEAK]
+                EXPORT  SUBGHZ_Radio_IRQHandler        [WEAK]
+
+TZIC_ILA_IRQHandler
+PVD_PVM_IRQHandler
+RTC_LSECSS_IRQHandler
+RCC_FLASH_C1SEV_IRQHandler
+EXTI1_0_IRQHandler
+EXTI3_2_IRQHandler
+EXTI15_4_IRQHandler
+ADC_COMP_DAC_IRQHandler
+DMA1_Channel1_2_3_IRQHandler
+DMA1_Channel4_5_6_7_IRQHandler
+DMA2_DMAMUX1_OVR_IRQHandler   
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+TIM1_IRQHandler
+TIM2_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+IPCC_C2_RX_C2_TX_IRQHandler
+HSEM_IRQHandler
+RNG_IRQHandler
+AES_PKA_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+I2C3_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+LPUART1_IRQHandler
+SUBGHZSPI_IRQHandler
+SUBGHZ_Radio_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wl54xx_cm4.s

+;******************************************************************************
+;* File Name          : startup_stm32wl54xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WL54xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                      ; Top of Stack
+                DCD     Reset_Handler                     ; Reset Handler
+                DCD     NMI_Handler                       ; NMI Handler
+                DCD     HardFault_Handler                 ; Hard Fault Handler
+                DCD     MemManage_Handler                 ; MPU Fault Handler
+                DCD     BusFault_Handler                  ; Bus Fault Handler
+                DCD     UsageFault_Handler                ; Usage Fault Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SVC_Handler                       ; SVCall Handler
+                DCD     DebugMon_Handler                  ; Debug Monitor Handler
+                DCD     0                                 ; Reserved
+                DCD     PendSV_Handler                    ; PendSV Handler
+                DCD     SysTick_Handler                   ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+                DCD     TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+                DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+                DCD     RCC_IRQHandler                    ; RCC Interrupt
+                DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+                DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+                DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+                DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+                DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+                DCD     ADC_IRQHandler                    ; ADC Interrupt
+                DCD     DAC_IRQHandler                    ; DAC Interrupt
+                DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
+                DCD     COMP_IRQHandler                   ; COMP1 and COMP2 Interrupts
+                DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupts
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Communication Interrupts
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+                DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+                DCD     TIM16_IRQHandler                  ; TIM16 Global Interrupt
+                DCD     TIM17_IRQHandler                  ; TIM17 Global Interrupt
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event Interrupt
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error Interrupt
+                DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+                DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+                DCD     USART1_IRQHandler                 ; USART1 Interrupt
+                DCD     USART2_IRQHandler                 ; USART2 Interrupt
+                DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+                DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+                DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+                DCD     LPTIM3_IRQHandler                 ; LPTIM3 Interrupt
+                DCD     SUBGHZSPI_IRQHandler              ; SUBGHZSPI Interrupt
+                DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+                DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+                DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+                DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+                DCD     SUBGHZ_Radio_IRQHandler           ; SUBGHZ Radio Interrupt
+                DCD     AES_IRQHandler                    ; AES Interrupt
+                DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+                DCD     PKA_IRQHandler                    ; PKA Interrupt
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC_IRQHandler                    [WEAK]
+                EXPORT  DAC_IRQHandler                    [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_IRQHandler                [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  TIM16_IRQHandler                  [WEAK]
+                EXPORT  TIM17_IRQHandler                  [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  USART2_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  LPTIM3_IRQHandler                 [WEAK]
+                EXPORT  SUBGHZSPI_IRQHandler              [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SUBGHZ_Radio_IRQHandler           [WEAK]
+                EXPORT  AES_IRQHandler                    [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC_IRQHandler
+DAC_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler                
+USART2_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+LPTIM3_IRQHandler
+SUBGHZSPI_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SUBGHZ_Radio_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+PKA_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wl55xx_cm0plus.s

+;******************************************************************************
+;* File Name          : startup_stm32wl55xx_cm0plus.s
+;* Author             : MCD Application Team
+;* Description        : STM32WL55xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M0+ processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                     ; Top of Stack
+                DCD     Reset_Handler                    ; Reset Handler
+                DCD     NMI_Handler                      ; NMI Handler
+                DCD     HardFault_Handler                ; Hard Fault Handler
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     SVC_Handler                      ; SVCall Handler
+                DCD     0                                ; Reserved
+                DCD     0                                ; Reserved
+                DCD     PendSV_Handler                   ; PendSV Handler
+                DCD     SysTick_Handler                  ; SysTick Handler
+
+                ; External Interrupts                    
+                DCD     TZIC_ILA_IRQHandler              ; Security Interrupt controller illegal access Interrupts
+                DCD     PVD_PVM_IRQHandler               ; PVD and PVM detector
+                DCD     RTC_LSECSS_IRQHandler            ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) + SSR Underflow and LSECSS Interrupts
+                DCD     RCC_FLASH_C1SEV_IRQHandler       ; RCC1 and FLASH and CPU1 M4 SEV Interrupts
+                DCD     EXTI1_0_IRQHandler               ; EXTI Line 1:0 Interrupts
+                DCD     EXTI3_2_IRQHandler               ; XTI Line 3:2 Interrupts
+                DCD     EXTI15_4_IRQHandler              ; EXTI Line 15:4 interrupts
+                DCD     ADC_COMP_DAC_IRQHandler          ; ADC, COMP1, COMP2, DAC Interrupts
+                DCD     DMA1_Channel1_2_3_IRQHandler     ; DMA1 Channel 1 to 3 Interrupts
+                DCD     DMA1_Channel4_5_6_7_IRQHandler   ; DMA1 Channels 4, 5, 6, 7 Interrupts
+                DCD     DMA2_DMAMUX1_OVR_IRQHandler      ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts          
+                DCD     LPTIM1_IRQHandler                ; LPTIM1 global Interrupt
+                DCD     LPTIM2_IRQHandler                ; LPTIM2 global Interrupt
+                DCD     LPTIM3_IRQHandler                ; LPTIM3 global Interrupt
+                DCD     TIM1_IRQHandler                  ; TIM1 Interrupt
+                DCD     TIM2_IRQHandler                  ; TIM2 Interrupt
+                DCD     TIM16_IRQHandler                 ; TIM16 Interrupt
+                DCD     TIM17_IRQHandler                 ; TIM17 Interrupt
+                DCD     IPCC_C2_RX_C2_TX_IRQHandler      ; IPCC RX Occupied and TX Free Interrupt Interrupts
+                DCD     HSEM_IRQHandler                  ; Semaphore Interrupt
+                DCD     RNG_IRQHandler                   ; RNG Interrupt
+                DCD     AES_PKA_IRQHandler               ; AES and PKA Interrupts
+                DCD     I2C1_IRQHandler                  ; I2C1 Event and Error Interrupt
+                DCD     I2C2_IRQHandler                  ; I2C2 Event and Error Interrupt
+                DCD     I2C3_IRQHandler                  ; I2C3 Event and Error Interrupt
+                DCD     SPI1_IRQHandler                  ; SPI1 Interrupts
+                DCD     SPI2_IRQHandler                  ; SPI2 Interrupt
+                DCD     USART1_IRQHandler                ; USART1 Interrupt
+                DCD     USART2_IRQHandler                ; USART2 Interrupt
+                DCD     LPUART1_IRQHandler               ; LPUART1 Interrupt
+                DCD     SUBGHZSPI_IRQHandler             ; SUBGHZSPI Interrupt
+                DCD     SUBGHZ_Radio_IRQHandler          ; SUBGHZ Radio Interrupt
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT  TZIC_ILA_IRQHandler            [WEAK]
+                EXPORT  PVD_PVM_IRQHandler             [WEAK]
+                EXPORT  RTC_LSECSS_IRQHandler          [WEAK]
+                EXPORT  RCC_FLASH_C1SEV_IRQHandler     [WEAK]
+                EXPORT  EXTI1_0_IRQHandler             [WEAK]
+                EXPORT  EXTI3_2_IRQHandler             [WEAK]
+                EXPORT  EXTI15_4_IRQHandler            [WEAK]
+                EXPORT  ADC_COMP_DAC_IRQHandler        [WEAK]
+                EXPORT  DMA1_Channel1_2_3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
+                EXPORT  DMA2_DMAMUX1_OVR_IRQHandler    [WEAK]
+                EXPORT  LPTIM1_IRQHandler              [WEAK]
+                EXPORT  LPTIM2_IRQHandler              [WEAK]
+                EXPORT  LPTIM3_IRQHandler              [WEAK]
+                EXPORT  TIM1_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                [WEAK]
+                EXPORT  TIM16_IRQHandler               [WEAK]
+                EXPORT  TIM17_IRQHandler               [WEAK]
+                EXPORT  IPCC_C2_RX_C2_TX_IRQHandler    [WEAK]
+                EXPORT  HSEM_IRQHandler                [WEAK]
+                EXPORT  RNG_IRQHandler                 [WEAK]
+                EXPORT  AES_PKA_IRQHandler             [WEAK]
+                EXPORT  I2C1_IRQHandler                [WEAK]
+                EXPORT  I2C2_IRQHandler                [WEAK]
+                EXPORT  I2C3_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                [WEAK]
+                EXPORT  SPI2_IRQHandler                [WEAK]
+                EXPORT  USART1_IRQHandler              [WEAK]
+                EXPORT  USART2_IRQHandler              [WEAK]
+                EXPORT  LPUART1_IRQHandler             [WEAK]
+                EXPORT  SUBGHZSPI_IRQHandler           [WEAK]
+                EXPORT  SUBGHZ_Radio_IRQHandler        [WEAK]
+
+TZIC_ILA_IRQHandler
+PVD_PVM_IRQHandler
+RTC_LSECSS_IRQHandler
+RCC_FLASH_C1SEV_IRQHandler
+EXTI1_0_IRQHandler
+EXTI3_2_IRQHandler
+EXTI15_4_IRQHandler
+ADC_COMP_DAC_IRQHandler
+DMA1_Channel1_2_3_IRQHandler
+DMA1_Channel4_5_6_7_IRQHandler
+DMA2_DMAMUX1_OVR_IRQHandler   
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+TIM1_IRQHandler
+TIM2_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+IPCC_C2_RX_C2_TX_IRQHandler
+HSEM_IRQHandler
+RNG_IRQHandler
+AES_PKA_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+I2C3_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+LPUART1_IRQHandler
+SUBGHZSPI_IRQHandler
+SUBGHZ_Radio_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wl55xx_cm4.s

+;******************************************************************************
+;* File Name          : startup_stm32wl55xx_cm4.s
+;* Author             : MCD Application Team
+;* Description        : STM32WL55xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                      ; Top of Stack
+                DCD     Reset_Handler                     ; Reset Handler
+                DCD     NMI_Handler                       ; NMI Handler
+                DCD     HardFault_Handler                 ; Hard Fault Handler
+                DCD     MemManage_Handler                 ; MPU Fault Handler
+                DCD     BusFault_Handler                  ; Bus Fault Handler
+                DCD     UsageFault_Handler                ; Usage Fault Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SVC_Handler                       ; SVCall Handler
+                DCD     DebugMon_Handler                  ; Debug Monitor Handler
+                DCD     0                                 ; Reserved
+                DCD     PendSV_Handler                    ; PendSV Handler
+                DCD     SysTick_Handler                   ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+                DCD     TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+                DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+                DCD     RCC_IRQHandler                    ; RCC Interrupt
+                DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+                DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+                DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+                DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+                DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+                DCD     ADC_IRQHandler                    ; ADC Interrupt
+                DCD     DAC_IRQHandler                    ; DAC Interrupt
+                DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
+                DCD     COMP_IRQHandler                   ; COMP1 and COMP2 Interrupts
+                DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupts
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Communication Interrupts
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+                DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+                DCD     TIM16_IRQHandler                  ; TIM16 Global Interrupt
+                DCD     TIM17_IRQHandler                  ; TIM17 Global Interrupt
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event Interrupt
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error Interrupt
+                DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+                DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+                DCD     USART1_IRQHandler                 ; USART1 Interrupt
+                DCD     USART2_IRQHandler                 ; USART2 Interrupt
+                DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+                DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+                DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+                DCD     LPTIM3_IRQHandler                 ; LPTIM3 Interrupt
+                DCD     SUBGHZSPI_IRQHandler              ; SUBGHZSPI Interrupt
+                DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
+                DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
+                DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+                DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+                DCD     SUBGHZ_Radio_IRQHandler           ; SUBGHZ Radio Interrupt
+                DCD     AES_IRQHandler                    ; AES Interrupt
+                DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+                DCD     PKA_IRQHandler                    ; PKA Interrupt
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC_IRQHandler                    [WEAK]
+                EXPORT  DAC_IRQHandler                    [WEAK]
+                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_IRQHandler                [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  TIM16_IRQHandler                  [WEAK]
+                EXPORT  TIM17_IRQHandler                  [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  USART2_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  LPTIM3_IRQHandler                 [WEAK]
+                EXPORT  SUBGHZSPI_IRQHandler              [WEAK]
+                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
+                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SUBGHZ_Radio_IRQHandler           [WEAK]
+                EXPORT  AES_IRQHandler                    [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC_IRQHandler
+DAC_IRQHandler
+C2SEV_PWR_C2H_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler                
+USART2_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+LPTIM3_IRQHandler
+SUBGHZSPI_IRQHandler
+IPCC_C1_RX_IRQHandler
+IPCC_C1_TX_IRQHandler
+HSEM_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SUBGHZ_Radio_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+PKA_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wle4xx.s

+;******************************************************************************
+;* File Name          : startup_stm32wle4xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32WLE4xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                      ; Top of Stack
+                DCD     Reset_Handler                     ; Reset Handler
+                DCD     NMI_Handler                       ; NMI Handler
+                DCD     HardFault_Handler                 ; Hard Fault Handler
+                DCD     MemManage_Handler                 ; MPU Fault Handler
+                DCD     BusFault_Handler                  ; Bus Fault Handler
+                DCD     UsageFault_Handler                ; Usage Fault Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SVC_Handler                       ; SVCall Handler
+                DCD     DebugMon_Handler                  ; Debug Monitor Handler
+                DCD     0                                 ; Reserved
+                DCD     PendSV_Handler                    ; PendSV Handler
+                DCD     SysTick_Handler                   ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+                DCD     TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+                DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+                DCD     RCC_IRQHandler                    ; RCC Interrupt
+                DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+                DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+                DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+                DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+                DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+                DCD     ADC_IRQHandler                    ; ADC Interrupt
+                DCD     DAC_IRQHandler                    ; DAC Interrupt
+                DCD     0                                 ; Reserved
+                DCD     COMP_IRQHandler                   ; COMP1 and COMP2 Interrupts
+                DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupts
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Communication Interrupts
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+                DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+                DCD     TIM16_IRQHandler                  ; TIM16 Global Interrupt
+                DCD     TIM17_IRQHandler                  ; TIM17 Global Interrupt
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event Interrupt
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error Interrupt
+                DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+                DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+                DCD     USART1_IRQHandler                 ; USART1 Interrupt
+                DCD     USART2_IRQHandler                 ; USART2 Interrupt
+                DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+                DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+                DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+                DCD     LPTIM3_IRQHandler                 ; LPTIM3 Interrupt
+                DCD     SUBGHZSPI_IRQHandler              ; SUBGHZSPI Interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+                DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+                DCD     SUBGHZ_Radio_IRQHandler           ; SUBGHZ Radio Interrupt
+                DCD     AES_IRQHandler                    ; AES Interrupt
+                DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+                DCD     PKA_IRQHandler                    ; PKA Interrupt
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC_IRQHandler                    [WEAK]
+                EXPORT  DAC_IRQHandler                    [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_IRQHandler                [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  TIM16_IRQHandler                  [WEAK]
+                EXPORT  TIM17_IRQHandler                  [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  USART2_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  LPTIM3_IRQHandler                 [WEAK]
+                EXPORT  SUBGHZSPI_IRQHandler              [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SUBGHZ_Radio_IRQHandler           [WEAK]
+                EXPORT  AES_IRQHandler                    [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC_IRQHandler
+DAC_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler                
+USART2_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+LPTIM3_IRQHandler
+SUBGHZSPI_IRQHandler
+HSEM_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SUBGHZ_Radio_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+PKA_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wle5xx.s

+;******************************************************************************
+;* File Name          : startup_stm32wle5xx.s
+;* Author             : MCD Application Team
+;* Description        : STM32WLE5xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 STMicroelectronics. All rights reserved.
+;*
+;* This software component is licensed by ST under Apache License, Version 2.0,
+;* the "License"; You may not use this file except in compliance with the 
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/Apache-2.0
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                      ; Top of Stack
+                DCD     Reset_Handler                     ; Reset Handler
+                DCD     NMI_Handler                       ; NMI Handler
+                DCD     HardFault_Handler                 ; Hard Fault Handler
+                DCD     MemManage_Handler                 ; MPU Fault Handler
+                DCD     BusFault_Handler                  ; Bus Fault Handler
+                DCD     UsageFault_Handler                ; Usage Fault Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SVC_Handler                       ; SVCall Handler
+                DCD     DebugMon_Handler                  ; Debug Monitor Handler
+                DCD     0                                 ; Reserved
+                DCD     PendSV_Handler                    ; PendSV Handler
+                DCD     SysTick_Handler                   ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog
+                DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
+                DCD     TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
+                DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
+                DCD     RCC_IRQHandler                    ; RCC Interrupt
+                DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
+                DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
+                DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
+                DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
+                DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
+                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
+                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
+                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
+                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
+                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
+                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
+                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
+                DCD     ADC_IRQHandler                    ; ADC Interrupt
+                DCD     DAC_IRQHandler                    ; DAC Interrupt
+                DCD     0                                 ; Reserved
+                DCD     COMP_IRQHandler                   ; COMP1 and COMP2 Interrupts
+                DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
+                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
+                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupts
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Communication Interrupts
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
+                DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
+                DCD     TIM16_IRQHandler                  ; TIM16 Global Interrupt
+                DCD     TIM17_IRQHandler                  ; TIM17 Global Interrupt
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event Interrupt
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error Interrupt
+                DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
+                DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
+                DCD     USART1_IRQHandler                 ; USART1 Interrupt
+                DCD     USART2_IRQHandler                 ; USART2 Interrupt
+                DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
+                DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
+                DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
+                DCD     LPTIM3_IRQHandler                 ; LPTIM3 Interrupt
+                DCD     SUBGHZSPI_IRQHandler              ; SUBGHZSPI Interrupt
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
+                DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
+                DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
+                DCD     SUBGHZ_Radio_IRQHandler           ; SUBGHZ Radio Interrupt
+                DCD     AES_IRQHandler                    ; AES Interrupt
+                DCD     RNG_IRQHandler                    ; RNG1 Interrupt
+                DCD     PKA_IRQHandler                    ; PKA Interrupt
+                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
+                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
+                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
+                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
+                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
+                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
+                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                 [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                    [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler              [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler              [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler               [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler             [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                    [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                 [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
+                EXPORT  ADC_IRQHandler                    [WEAK]
+                EXPORT  DAC_IRQHandler                    [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_IRQHandler                [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  TIM16_IRQHandler                  [WEAK]
+                EXPORT  TIM17_IRQHandler                  [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  USART2_IRQHandler                 [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  LPTIM3_IRQHandler                 [WEAK]
+                EXPORT  SUBGHZSPI_IRQHandler              [WEAK]
+                EXPORT  HSEM_IRQHandler                   [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  SUBGHZ_Radio_IRQHandler           [WEAK]
+                EXPORT  AES_IRQHandler                    [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  PKA_IRQHandler                    [WEAK]
+                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
+                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+TAMP_STAMP_LSECSS_SSRU_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC_IRQHandler
+DAC_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler                
+USART2_IRQHandler
+LPUART1_IRQHandler
+LPTIM1_IRQHandler
+LPTIM2_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+LPTIM3_IRQHandler
+SUBGHZSPI_IRQHandler
+HSEM_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+SUBGHZ_Radio_IRQHandler
+AES_IRQHandler
+RNG_IRQHandler
+PKA_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+DMAMUX1_OVR_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/linker/STM32WL54XX_FLASH_CM0PLUS.ld

+/*
+** LinkerScript
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
+
+_Min_Heap_Size  = 0x200; /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  ROM    (rx)    : ORIGIN = 0x08020000, LENGTH = 128K   /* Flash memory dedicated to CM0+ */
+  RAM1   (xrw)   : ORIGIN = 0x20004000, LENGTH = 16K    /* Non-backup SRAM1 dedicated to CM0+ */
+  RAM2   (xrw)   : ORIGIN = 0x2000C000, LENGTH = 16K    /* Backup SRAM2 dedicated to CM0+ */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "ROM" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(8);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(8);
+  } >ROM
+
+  /* The program code and other data into "ROM" Rom type memory */
+  .text :
+  {
+    . = ALIGN(8);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(8);
+    _etext = .;        /* define a global symbols at end of code */
+  } >ROM
+
+  /* Constant data into "ROM" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(8);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(8);
+  } >ROM
+
+  .ARM.extab   : { 
+    . = ALIGN(8);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(8);
+  } >ROM
+  
+  .ARM : {
+    . = ALIGN(8);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(8);
+  } >ROM
+
+  .preinit_array     :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .init_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .fini_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "SRAM1" Ram type memory */
+  .data : 
+  {
+    . = ALIGN(8);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(8);
+    _edata = .;        /* define a global symbol at data end */
+    
+  } >RAM1 AT> ROM
+
+  /* Uninitialized data section into "SRAM1" Ram type memory */
+  . = ALIGN(8);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(8);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM0+ */
+  . = ALIGN(8);
+  RAM1_region :
+  {
+    _sRAM1_region = .;         /* define a global symbol at section start */
+    *(.RAM1_region)
+
+    . = ALIGN(8);
+    _eRAM1_region = .;         /* define a global symbol at section end */
+  } >RAM1
+
+  /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM0+ */
+  . = ALIGN(8);
+  RAM2_region :
+  {
+    _sRAM2_region = .;         /* define a global symbol at section start */
+    *(.RAM2_region)
+
+    . = ALIGN(8);
+    _eRAM2_region = .;         /* define a global symbol at section end */
+  } >RAM2
+
+  /* User_heap_stack section, used to check that there is enough "SRAM1" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/linker/STM32WL54XX_FLASH_CM4.ld

+/*
+** LinkerScript
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
+
+_Min_Heap_Size  = 0x200; /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  ROM    (rx)    : ORIGIN = 0x08000000, LENGTH = 128K   /* Flash memory dedicated to CM4 */
+  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 16K    /* Non-backup SRAM1 dedicated to CM4 */
+  RAM2   (xrw)   : ORIGIN = 0x20008000, LENGTH = 16K    /* Backup SRAM2 dedicated to CM4 */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "ROM" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(8);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(8);
+  } >ROM
+
+  /* The program code and other data into "ROM" Rom type memory */
+  .text :
+  {
+    . = ALIGN(8);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(8);
+    _etext = .;        /* define a global symbols at end of code */
+  } >ROM
+
+  /* Constant data into "ROM" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(8);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(8);
+  } >ROM
+
+  .ARM.extab   : { 
+    . = ALIGN(8);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(8);
+  } >ROM
+  
+  .ARM : {
+    . = ALIGN(8);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(8);
+  } >ROM
+
+  .preinit_array     :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .init_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .fini_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "SRAM1" Ram type memory */
+  .data : 
+  {
+    . = ALIGN(8);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(8);
+    _edata = .;        /* define a global symbol at data end */
+    
+  } >RAM1 AT> ROM
+
+  /* Uninitialized data section into "SRAM1" Ram type memory */
+  . = ALIGN(8);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(8);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
+  . = ALIGN(8);
+  RAM1_region :
+  {
+    _sRAM1_region = .;         /* define a global symbol at section start */
+    *(.RAM1_region)
+
+    . = ALIGN(8);
+    _eRAM1_region = .;         /* define a global symbol at section end */
+  } >RAM1
+
+  /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
+  . = ALIGN(8);
+  RAM2_region :
+  {
+    _sRAM2_region = .;         /* define a global symbol at section start */
+    *(.RAM2_region)
+
+    . = ALIGN(8);
+    _eRAM2_region = .;         /* define a global symbol at section end */
+  } >RAM2
+
+  /* User_heap_stack section, used to check that there is enough "SRAM1" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/linker/STM32WL55XX_FLASH_CM0PLUS.ld

+/*
+** LinkerScript
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
+
+_Min_Heap_Size  = 0x200; /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  ROM    (rx)    : ORIGIN = 0x08020000, LENGTH = 128K   /* Flash memory dedicated to CM0+ */
+  RAM1   (xrw)   : ORIGIN = 0x20004000, LENGTH = 16K    /* Non-backup SRAM1 dedicated to CM0+ */
+  RAM2   (xrw)   : ORIGIN = 0x2000C000, LENGTH = 16K    /* Backup SRAM2 dedicated to CM0+ */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "ROM" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(8);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(8);
+  } >ROM
+
+  /* The program code and other data into "ROM" Rom type memory */
+  .text :
+  {
+    . = ALIGN(8);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(8);
+    _etext = .;        /* define a global symbols at end of code */
+  } >ROM
+
+  /* Constant data into "ROM" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(8);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(8);
+  } >ROM
+
+  .ARM.extab   : { 
+    . = ALIGN(8);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(8);
+  } >ROM
+  
+  .ARM : {
+    . = ALIGN(8);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(8);
+  } >ROM
+
+  .preinit_array     :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .init_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .fini_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "SRAM1" Ram type memory */
+  .data : 
+  {
+    . = ALIGN(8);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(8);
+    _edata = .;        /* define a global symbol at data end */
+    
+  } >RAM1 AT> ROM
+
+  /* Uninitialized data section into "SRAM1" Ram type memory */
+  . = ALIGN(8);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(8);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM0+ */
+  . = ALIGN(8);
+  RAM1_region :
+  {
+    _sRAM1_region = .;         /* define a global symbol at section start */
+    *(.RAM1_region)
+
+    . = ALIGN(8);
+    _eRAM1_region = .;         /* define a global symbol at section end */
+  } >RAM1
+
+  /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM0+ */
+  . = ALIGN(8);
+  RAM2_region :
+  {
+    _sRAM2_region = .;         /* define a global symbol at section start */
+    *(.RAM2_region)
+
+    . = ALIGN(8);
+    _eRAM2_region = .;         /* define a global symbol at section end */
+  } >RAM2
+
+  /* User_heap_stack section, used to check that there is enough "SRAM1" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/linker/STM32WL55XX_FLASH_CM4.ld

+/*
+** LinkerScript
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
+
+_Min_Heap_Size  = 0x200; /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  ROM    (rx)    : ORIGIN = 0x08000000, LENGTH = 128K   /* Flash memory dedicated to CM4 */
+  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 16K    /* Non-backup SRAM1 dedicated to CM4 */
+  RAM2   (xrw)   : ORIGIN = 0x20008000, LENGTH = 16K    /* Backup SRAM2 dedicated to CM4 */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "ROM" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(8);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(8);
+  } >ROM
+
+  /* The program code and other data into "ROM" Rom type memory */
+  .text :
+  {
+    . = ALIGN(8);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(8);
+    _etext = .;        /* define a global symbols at end of code */
+  } >ROM
+
+  /* Constant data into "ROM" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(8);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(8);
+  } >ROM
+
+  .ARM.extab   : { 
+    . = ALIGN(8);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(8);
+  } >ROM
+  
+  .ARM : {
+    . = ALIGN(8);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(8);
+  } >ROM
+
+  .preinit_array     :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .init_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .fini_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "SRAM1" Ram type memory */
+  .data : 
+  {
+    . = ALIGN(8);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(8);
+    _edata = .;        /* define a global symbol at data end */
+    
+  } >RAM1 AT> ROM
+
+  /* Uninitialized data section into "SRAM1" Ram type memory */
+  . = ALIGN(8);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(8);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
+  . = ALIGN(8);
+  RAM1_region :
+  {
+    _sRAM1_region = .;         /* define a global symbol at section start */
+    *(.RAM1_region)
+
+    . = ALIGN(8);
+    _eRAM1_region = .;         /* define a global symbol at section end */
+  } >RAM1
+
+  /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
+  . = ALIGN(8);
+  RAM2_region :
+  {
+    _sRAM2_region = .;         /* define a global symbol at section start */
+    *(.RAM2_region)
+
+    . = ALIGN(8);
+    _eRAM2_region = .;         /* define a global symbol at section end */
+  } >RAM2
+
+  /* User_heap_stack section, used to check that there is enough "SRAM1" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/linker/STM32WLE4XX_FLASH.ld

+/*
+** LinkerScript
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
+
+_Min_Heap_Size  = 0x200; /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  ROM    (rx)    : ORIGIN = 0x08000000, LENGTH = 256K
+  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 32K    /* Non-backup SRAM1 */
+  RAM2   (xrw)   : ORIGIN = 0x20008000, LENGTH = 32K    /* Backup SRAM2 */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "ROM" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(8);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(8);
+  } >ROM
+
+  /* The program code and other data into "ROM" Rom type memory */
+  .text :
+  {
+    . = ALIGN(8);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(8);
+    _etext = .;        /* define a global symbols at end of code */
+  } >ROM
+
+  /* Constant data into "ROM" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(8);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(8);
+  } >ROM
+
+  .ARM.extab   : { 
+    . = ALIGN(8);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(8);
+  } >ROM
+  
+  .ARM : {
+    . = ALIGN(8);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(8);
+  } >ROM
+
+  .preinit_array     :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .init_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .fini_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "SRAM1" Ram type memory */
+  .data : 
+  {
+    . = ALIGN(8);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(8);
+    _edata = .;        /* define a global symbol at data end */
+    
+  } >RAM1 AT> ROM
+
+  /* Uninitialized data section into "SRAM1" Ram type memory */
+  . = ALIGN(8);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(8);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
+  . = ALIGN(8);
+  RAM1_region :
+  {
+    _sRAM1_region = .;         /* define a global symbol at section start */
+    *(.RAM1_region)
+
+    . = ALIGN(8);
+    _eRAM1_region = .;         /* define a global symbol at section end */
+  } >RAM1
+
+  /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
+  . = ALIGN(8);
+  RAM2_region :
+  {
+    _sRAM2_region = .;         /* define a global symbol at section start */
+    *(.RAM2_region)
+
+    . = ALIGN(8);
+    _eRAM2_region = .;         /* define a global symbol at section end */
+  } >RAM2
+
+  /* User_heap_stack section, used to check that there is enough "SRAM1" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/linker/STM32WLE5XX_FLASH.ld

+/*
+** LinkerScript
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
+
+_Min_Heap_Size  = 0x200; /* required amount of heap  */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+  ROM    (rx)    : ORIGIN = 0x08000000, LENGTH = 256K
+  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 32K    /* Non-backup SRAM1 */
+  RAM2   (xrw)   : ORIGIN = 0x20008000, LENGTH = 32K    /* Backup SRAM2 */
+}
+
+/* Sections */
+SECTIONS
+{
+  /* The startup code into "ROM" Rom type memory */
+  .isr_vector :
+  {
+    . = ALIGN(8);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(8);
+  } >ROM
+
+  /* The program code and other data into "ROM" Rom type memory */
+  .text :
+  {
+    . = ALIGN(8);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(8);
+    _etext = .;        /* define a global symbols at end of code */
+  } >ROM
+
+  /* Constant data into "ROM" Rom type memory */
+  .rodata :
+  {
+    . = ALIGN(8);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(8);
+  } >ROM
+
+  .ARM.extab   : { 
+    . = ALIGN(8);
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(8);
+  } >ROM
+  
+  .ARM : {
+    . = ALIGN(8);
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+    . = ALIGN(8);
+  } >ROM
+
+  .preinit_array     :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .init_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+  
+  .fini_array :
+  {
+    . = ALIGN(8);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    . = ALIGN(8);
+  } >ROM
+
+  /* Used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections into "SRAM1" Ram type memory */
+  .data : 
+  {
+    . = ALIGN(8);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(8);
+    _edata = .;        /* define a global symbol at data end */
+    
+  } >RAM1 AT> ROM
+
+  /* Uninitialized data section into "SRAM1" Ram type memory */
+  . = ALIGN(8);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss section */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(8);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM1
+
+  /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
+  . = ALIGN(8);
+  RAM1_region :
+  {
+    _sRAM1_region = .;         /* define a global symbol at section start */
+    *(.RAM1_region)
+
+    . = ALIGN(8);
+    _eRAM1_region = .;         /* define a global symbol at section end */
+  } >RAM1
+
+  /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
+  . = ALIGN(8);
+  RAM2_region :
+  {
+    _sRAM2_region = .;         /* define a global symbol at section start */
+    *(.RAM2_region)
+
+    . = ALIGN(8);
+    _eRAM2_region = .;         /* define a global symbol at section end */
+  } >RAM2
+
+  /* User_heap_stack section, used to check that there is enough "SRAM1" Ram  type memory left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(8);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(8);
+  } >RAM1
+
+  /* Remove information from the compiler libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wl54xx_cm0plus.s

+/**
+  ******************************************************************************
+  * @file      startup_stm32wl54xx_cm0plus.s
+  * @author    MCD Application Team
+  * @brief     STM32WL54xx devices Cortex-M0+ vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M0+ processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+.syntax unified
+.cpu cortex-m0plus
+.fpu softvfp
+.thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+  bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+  bl main
+
+LoopForever:
+    b LoopForever
+
+  .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32WL54xx Cortex-M0+ vector table.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+  .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word	0
+  .word	0
+  .word	0
+  .word	0
+  .word	0
+  .word	0
+  .word	0
+  .word	SVC_Handler
+  .word	0
+  .word	0
+  .word	PendSV_Handler
+  .word	SysTick_Handler
+  .word	TZIC_ILA_IRQHandler                  			/* TZIC ILA Interrupt                                 */
+  .word	PVD_PVM_IRQHandler                   			/* PVD and PVM interrupt through EXTI                 */
+  .word	RTC_LSECSS_IRQHandler                			/* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
+  .word	RCC_FLASH_C1SEV_IRQHandler           			/* RCC and FLASH and CPU1 M4 SEV Interrupt            */
+  .word	EXTI1_0_IRQHandler                   			/* EXTI Line 1:0 Interrupt                            */
+  .word	EXTI3_2_IRQHandler                   			/* EXTI Line 3:2 Interrupt                            */
+  .word	EXTI15_4_IRQHandler                  			/* EXTI Line 15:4 interrupt                           */
+  .word	ADC_COMP_DAC_IRQHandler              			/* ADC, COMP1, COMP2, DAC Interrupt                   */
+  .word	DMA1_Channel1_2_3_IRQHandler         			/* DMA1 Channel 1 to 3 Interrupt                      */
+  .word	DMA1_Channel4_5_6_7_IRQHandler       			/* DMA1 Channels 4,5,6,7 Interrupt                    */
+  .word	DMA2_DMAMUX1_OVR_IRQHandler          			/* DMA2 Channels[1..7] and DMAMUX Overrun Interrupts  */
+  .word	LPTIM1_IRQHandler                    			/* LPTIM1 Global Interrupt                            */
+  .word	LPTIM2_IRQHandler                    			/* LPTIM2 Global Interrupt                            */
+  .word	LPTIM3_IRQHandler                    			/* LPTIM3 Global Interrupt                            */
+  .word	TIM1_IRQHandler                      			/* TIM1 Global Interrupt                              */
+  .word	TIM2_IRQHandler                      			/* TIM2 Global Interrupt                              */
+  .word	TIM16_IRQHandler                     			/* TIM16 Global Interrupt                             */
+  .word	TIM17_IRQHandler                     			/* TIM17 Global Interrupt                             */
+  .word	IPCC_C2_RX_C2_TX_IRQHandler          			/* IPCC RX Occupied and TX Free Interrupt Interrupt   */
+  .word	HSEM_IRQHandler                      			/* Semaphore Interrupt                                */
+  .word	RNG_IRQHandler                       			/* RNG Interrupt                                      */
+  .word	AES_PKA_IRQHandler                   			/* COMP1 and COMP2 interrupt through EXTI             */
+  .word	I2C1_IRQHandler                      			/* I2C1 Event and Error Interrupt                     */
+  .word	I2C2_IRQHandler                      			/* I2C2 Event and Error Interrupt                     */
+  .word	I2C3_IRQHandler                      			/* I2C3 Event and Error Interrupt                     */
+  .word	SPI1_IRQHandler                      			/* SPI1 Interrupt                                     */
+  .word	SPI2_IRQHandler                      			/* SPI2 Interrupt                                     */
+  .word	USART1_IRQHandler                    			/* USART1 Interrupt                                   */
+  .word	USART2_IRQHandler                    			/* USART2 Interrupt                                   */
+  .word	LPUART1_IRQHandler                   			/* LPUART1 Interrupt                                  */
+  .word	SUBGHZSPI_IRQHandler                 			/* SUBGHZSPI Interrupt                                */
+  .word	SUBGHZ_Radio_IRQHandler              			/* SUBGHZ Radio Interrupt                             */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+	.weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+	.weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	TZIC_ILA_IRQHandler
+	.thumb_set TZIC_ILA_IRQHandler,Default_Handler
+
+	.weak	PVD_PVM_IRQHandler
+	.thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+	.weak	RTC_LSECSS_IRQHandler
+	.thumb_set RTC_LSECSS_IRQHandler,Default_Handler
+
+	.weak	RCC_FLASH_C1SEV_IRQHandler
+	.thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
+
+	.weak	EXTI1_0_IRQHandler
+	.thumb_set EXTI1_0_IRQHandler,Default_Handler
+
+	.weak	EXTI3_2_IRQHandler
+	.thumb_set EXTI3_2_IRQHandler,Default_Handler
+
+	.weak	EXTI15_4_IRQHandler
+	.thumb_set EXTI15_4_IRQHandler,Default_Handler
+
+	.weak	ADC_COMP_DAC_IRQHandler
+	.thumb_set ADC_COMP_DAC_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_2_3_IRQHandler
+	.thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_5_6_7_IRQHandler
+	.thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
+
+	.weak	DMA2_DMAMUX1_OVR_IRQHandler
+	.thumb_set DMA2_DMAMUX1_OVR_IRQHandler,Default_Handler
+
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler
+
+	.weak	LPTIM3_IRQHandler
+	.thumb_set LPTIM3_IRQHandler,Default_Handler
+
+	.weak	TIM1_IRQHandler
+	.thumb_set TIM1_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM16_IRQHandler
+	.thumb_set TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM17_IRQHandler
+	.thumb_set TIM17_IRQHandler,Default_Handler
+
+	.weak	IPCC_C2_RX_C2_TX_IRQHandler
+	.thumb_set IPCC_C2_RX_C2_TX_IRQHandler,Default_Handler
+
+	.weak	HSEM_IRQHandler
+	.thumb_set HSEM_IRQHandler,Default_Handler
+
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+
+	.weak	AES_PKA_IRQHandler
+	.thumb_set AES_PKA_IRQHandler,Default_Handler
+
+	.weak	I2C1_IRQHandler
+	.thumb_set I2C1_IRQHandler,Default_Handler
+
+	.weak	I2C2_IRQHandler
+	.thumb_set I2C2_IRQHandler,Default_Handler
+
+	.weak	I2C3_IRQHandler
+	.thumb_set I2C3_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler
+
+	.weak	SUBGHZSPI_IRQHandler
+	.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
+
+	.weak	SUBGHZ_Radio_IRQHandler
+	.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
+
+	.weak	SystemInit
+
+/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wl54xx_cm4.s

+/**
+  ******************************************************************************
+  * @file      startup_stm32wl54xx_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32WL54xx devices Cortex-M4 vector table for GCC toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address,
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Apache License, Version 2.0,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/Apache-2.0
+  *
+  ******************************************************************************
+  */
+
+.syntax unified
+.cpu cortex-m4
+.fpu softvfp
+.thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   r0, =_estack
+  mov   sp, r0          /* set stack pointer */
+
+/* Call the clock system initialization function.*/
+  bl  SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+  ldr r0, =_sdata
+  ldr r1, =_edata
+  ldr r2, =_sidata
+  movs r3, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r4, [r2, r3]
+  str r4, [r0, r3]
+  adds r3, r3, #4
+
+LoopCopyDataInit:
+  adds r4, r0, r3
+  cmp r4, r1
+  bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+  ldr r2, =_sbss
+  ldr r4, =_ebss
+  movs r3, #0
+  b LoopFillZerobss
+
+FillZerobss:
+  str  r3, [r2]
+  adds r2, r2, #4
+
+LoopFillZerobss:
+  cmp r2, r4
+  bcc FillZerobss
+
+/* Call static constructors */
+  bl __libc_init_array
+/* Call the application's entry point.*/
+  bl main
+
+LoopForever:
+    b LoopForever
+
+  .size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+  .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+
+/******************************************************************************
+*
+* The STM32WL54xx Cortex-M4 vector table.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+  .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word	MemManage_Handler
+  .word	BusFault_Handler
+  .word	UsageFault_Handler
+  .word	0
+  .word	0
+  .word	0
+  .word	0
+  .word	SVC_Handler
+  .word	DebugMon_Handler
+  .word	0
+  .word	PendSV_Handler
+  .word	SysTick_Handler
+  .word	WWDG_IRQHandler                      			/* Window Watchdog interrupt                          */
+  .word	PVD_PVM_IRQHandler                   			/* PVD and PVM interrupt through EXTI                 */
+  .word	TAMP_STAMP_LSECSS_SSRU_IRQHandler    			/* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
+  .word	RTC_WKUP_IRQHandler                  			/* RTC wakeup interrupt through EXTI[19]              */
+  .word	FLASH_IRQHandler                     			/* Flash memory global interrupt and Flash memory ECC */
+  .word	RCC_IRQHandler                       			/* RCC global interrupt                               */
+  .word	EXTI0_IRQHandler                     			/* EXTI line 0 interrupt                              */
+  .word	EXTI1_IRQHandler                     			/* EXTI line 1 interrupt                              */
+  .word	EXTI2_IRQHandler                     			/* EXTI line 2 interrupt                              */
+  .word	EXTI3_IRQHandler                     			/* EXTI line 3 interrupt                              */
+  .word	EXTI4_IRQHandler                     			/* EXTI line 4 interrupt                              */
+  .word	DMA1_Channel1_IRQHandler             			/* DMA1 channel 1 interrupt                           */
+  .word	DMA1_Channel2_IRQHandler             			/* DMA1 channel 2 interrupt                           */
+  .word	DMA1_Channel3_IRQHandler             			/* DMA1 channel 3 interrupt                           */
+  .word	DMA1_Channel4_IRQHandler             			/* DMA1 channel 4 interrupt                           */
+  .word	DMA1_Channel5_IRQHandler             			/* DMA1 channel 5 interrupt                           */
+  .word	DMA1_Channel6_IRQHandler             			/* DMA1 channel 6 interrupt                           */
+  .word	DMA1_Channel7_IRQHandler             			/* DMA1 channel 7 interrupt                           */
+  .word	ADC_IRQHandler                       			/* ADC interrupt                                      */
+  .word	DAC_IRQHandler                       			/* DAC interrupt                                      */
+  .word	C2SEV_PWR_C2H_IRQHandler             			/* CPU M0+ SEV Interrupt                              */
+  .word	COMP_IRQHandler                      			/* COMP1 and COMP2 interrupt through EXTI             */
+  .word	EXTI9_5_IRQHandler                   			/* EXTI line 9_5 interrupt                            */
+  .word	TIM1_BRK_IRQHandler                  			/* Timer 1 break interrupt                            */
+  .word	TIM1_UP_IRQHandler                   			/* Timer 1 Update                                     */
+  .word	TIM1_TRG_COM_IRQHandler              			/* Timer 1 trigger and communication                  */
+  .word	TIM1_CC_IRQHandler                   			/* Timer 1 capture compare interrupt                  */
+  .word	TIM2_IRQHandler                      			/* TIM2 global interrupt                              */
+  .word	TIM16_IRQHandler                     			/* Timer 16 global interrupt                          */
+  .word	TIM17_IRQHandler                     			/* Timer 17 global interrupt                          */
+  .word	I2C1_EV_IRQHandler                   			/* I2C1 event interrupt                               */
+  .word	I2C1_ER_IRQHandler                   			/* I2C1 event interrupt                               */
+  .word	I2C2_EV_IRQHandler                   			/* I2C2 error interrupt                               */
+  .word	I2C2_ER_IRQHandler                   			/* I2C2 error interrupt                               */
+  .word	SPI1_IRQHandler                      			/* SPI1 global interrupt                              */
+  .word	SPI2_IRQHandler                      			/* SPI2 global interrupt                              */
+  .word	USART1_IRQHandler                    			/* USART1 global interrupt                            */
+  .word	USART2_IRQHandler                    			/* USART2 global interrupt                            */
+  .word	LPUART1_IRQHandler                   			/* LPUART1 global interrupt                           */
+  .word	LPTIM1_IRQHandler                    			/* LPtimer 1 global interrupt                         */
+  .word	LPTIM2_IRQHandler                    			/* LPtimer 2 global interrupt                         */
+  .word	EXTI15_10_IRQHandler                 			/* EXTI line 15_10] interrupt through EXTI            */
+  .word	RTC_Alarm_IRQHandler                 			/* RTC Alarms A & B interrupt                         */
+  .word	LPTIM3_IRQHandler                    			/* LPtimer 3 global interrupt                         */
+  .word	SUBGHZSPI_IRQHandler                 			/* SUBGHZSPI global interrupt                         */
+  .word	IPCC_C1_RX_IRQHandler                			/* IPCC CPU1 RX occupied interrupt                    */
+  .word	IPCC_C1_TX_IRQHandler                			/* IPCC CPU1 RX free interrupt                        */
+  .word	HSEM_IRQHandler                      			/* Semaphore interrupt 0 to CPU1                      */
+  .word	I2C3_EV_IRQHandler                   			/* I2C3 event interrupt                               */
+  .word	I2C3_ER_IRQHandler                   			/* I2C3 error interrupt                               */
+  .word	SUBGHZ_Radio_IRQHandler              			/* Radio IRQs RFBUSY interrupt through EXTI           */
+  .word	AES_IRQHandler                       			/* AES global interrupt                               */
+  .word	RNG_IRQHandler                       			/* RNG interrupt                                      */
+  .word	PKA_IRQHandler                       			/* PKA interrupt                                      */
+  .word	DMA2_Channel1_IRQHandler             			/* DMA2 channel 1 interrupt                           */
+  .word	DMA2_Channel2_IRQHandler             			/* DMA2 channel 2 interrupt                           */
+  .word	DMA2_Channel3_IRQHandler             			/* DMA2 channel 3 interrupt                           */
+  .word	DMA2_Channel4_IRQHandler             			/* DMA2 channel 4 interrupt                           */
+  .word	DMA2_Channel5_IRQHandler             			/* DMA2 channel 5 interrupt                           */
+  .word	DMA2_Channel6_IRQHandler             			/* DMA2 channel 6 interrupt                           */
+  .word	DMA2_Channel7_IRQHandler             			/* DMA2 channel 7 interrupt                           */
+  .word	DMAMUX1_OVR_IRQHandler               			/* DMAMUX overrun interrupt                           */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+	.weak	NMI_Handler
+	.thumb_set NMI_Handler,Default_Handler
+
+	.weak	HardFault_Handler
+	.thumb_set HardFault_Handler,Default_Handler
+
+	.weak	MemManage_Handler
+	.thumb_set MemManage_Handler,Default_Handler
+
+	.weak	BusFault_Handler
+	.thumb_set BusFault_Handler,Default_Handler
+
+	.weak	UsageFault_Handler
+	.thumb_set UsageFault_Handler,Default_Handler
+
+	.weak	SVC_Handler
+	.thumb_set SVC_Handler,Default_Handler
+
+	.weak	DebugMon_Handler
+	.thumb_set DebugMon_Handler,Default_Handler
+
+	.weak	PendSV_Handler
+	.thumb_set PendSV_Handler,Default_Handler
+
+	.weak	SysTick_Handler
+	.thumb_set SysTick_Handler,Default_Handler
+
+	.weak	WWDG_IRQHandler
+	.thumb_set WWDG_IRQHandler,Default_Handler
+
+	.weak	PVD_PVM_IRQHandler
+	.thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+	.weak	TAMP_STAMP_LSECSS_SSRU_IRQHandler
+	.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
+
+	.weak	RTC_WKUP_IRQHandler
+	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+	.weak	FLASH_IRQHandler
+	.thumb_set FLASH_IRQHandler,Default_Handler
+
+	.weak	RCC_IRQHandler
+	.thumb_set RCC_IRQHandler,Default_Handler
+
+	.weak	EXTI0_IRQHandler
+	.thumb_set EXTI0_IRQHandler,Default_Handler
+
+	.weak	EXTI1_IRQHandler
+	.thumb_set EXTI1_IRQHandler,Default_Handler
+
+	.weak	EXTI2_IRQHandler
+	.thumb_set EXTI2_IRQHandler,Default_Handler
+
+	.weak	EXTI3_IRQHandler
+	.thumb_set EXTI3_IRQHandler,Default_Handler
+
+	.weak	EXTI4_IRQHandler
+	.thumb_set EXTI4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel1_IRQHandler
+	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel2_IRQHandler
+	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel3_IRQHandler
+	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel4_IRQHandler
+	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel5_IRQHandler
+	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel6_IRQHandler
+	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA1_Channel7_IRQHandler
+	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+	.weak	ADC_IRQHandler
+	.thumb_set ADC_IRQHandler,Default_Handler
+
+	.weak	DAC_IRQHandler
+	.thumb_set DAC_IRQHandler,Default_Handler
+
+	.weak	C2SEV_PWR_C2H_IRQHandler
+	.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
+
+	.weak	COMP_IRQHandler
+	.thumb_set COMP_IRQHandler,Default_Handler
+
+	.weak	EXTI9_5_IRQHandler
+	.thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+	.weak	TIM1_BRK_IRQHandler
+	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+	.weak	TIM1_UP_IRQHandler
+	.thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+	.weak	TIM1_TRG_COM_IRQHandler
+	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+	.weak	TIM1_CC_IRQHandler
+	.thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+	.weak	TIM2_IRQHandler
+	.thumb_set TIM2_IRQHandler,Default_Handler
+
+	.weak	TIM16_IRQHandler
+	.thumb_set TIM16_IRQHandler,Default_Handler
+
+	.weak	TIM17_IRQHandler
+	.thumb_set TIM17_IRQHandler,Default_Handler
+
+	.weak	I2C1_EV_IRQHandler
+	.thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+	.weak	I2C1_ER_IRQHandler
+	.thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+	.weak	I2C2_EV_IRQHandler
+	.thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+	.weak	I2C2_ER_IRQHandler
+	.thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+	.weak	SPI1_IRQHandler
+	.thumb_set SPI1_IRQHandler,Default_Handler
+
+	.weak	SPI2_IRQHandler
+	.thumb_set SPI2_IRQHandler,Default_Handler
+
+	.weak	USART1_IRQHandler
+	.thumb_set USART1_IRQHandler,Default_Handler
+
+	.weak	USART2_IRQHandler
+	.thumb_set USART2_IRQHandler,Default_Handler
+
+	.weak	LPUART1_IRQHandler
+	.thumb_set LPUART1_IRQHandler,Default_Handler
+
+	.weak	LPTIM1_IRQHandler
+	.thumb_set LPTIM1_IRQHandler,Default_Handler
+
+	.weak	LPTIM2_IRQHandler
+	.thumb_set LPTIM2_IRQHandler,Default_Handler
+
+	.weak	EXTI15_10_IRQHandler
+	.thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+	.weak	RTC_Alarm_IRQHandler
+	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+	.weak	LPTIM3_IRQHandler
+	.thumb_set LPTIM3_IRQHandler,Default_Handler
+
+	.weak	SUBGHZSPI_IRQHandler
+	.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
+
+	.weak	IPCC_C1_RX_IRQHandler
+	.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
+
+	.weak	IPCC_C1_TX_IRQHandler
+	.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
+
+	.weak	HSEM_IRQHandler
+	.thumb_set HSEM_IRQHandler,Default_Handler
+
+	.weak	I2C3_EV_IRQHandler
+	.thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+	.weak	I2C3_ER_IRQHandler
+	.thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+	.weak	SUBGHZ_Radio_IRQHandler
+	.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
+
+	.weak	AES_IRQHandler
+	.thumb_set AES_IRQHandler,Default_Handler
+
+	.weak	RNG_IRQHandler
+	.thumb_set RNG_IRQHandler,Default_Handler
+
+	.weak	PKA_IRQHandler
+	.thumb_set PKA_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel1_IRQHandler
+	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel2_IRQHandler
+	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel3_IRQHandler
+	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel4_IRQHandler
+	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel5_IRQHandler
+	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel6_IRQHandler
+	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+	.weak	DMA2_Channel7_IRQHandler
+	.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+	.weak	DMAMUX1_OVR_IRQHandler
+	.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+	.weak	SystemInit
+
+/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm0plus.icf

+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08020000;
+
+/*-Memory Regions-*/
+/***** FLASH part dedicated to M0+ *****/
+define symbol __ICFEDIT_region_ROM_start__    = 0x08020000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0803FFFF;
+/***** Non-backup SRAM1 dedicated to M0+ *****/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20004000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
+/***** Backup SRAM2 dedicated to M0+ *****/
+define symbol __ICFEDIT_region_RAM2_start__   = 0x2000C000;
+define symbol __ICFEDIT_region_RAM2_end__     = 0x2000FFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM2_region     = mem:[from __ICFEDIT_region_RAM2_start__  to __ICFEDIT_region_RAM2_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+place in RAM2_region  { };
\ No newline at end of file

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm4.icf

+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+
+/*-Memory Regions-*/
+/***** FLASH part dedicated to M4 *****/
+define symbol __ICFEDIT_region_ROM_start__    = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__      = 0x0801FFFF;
+/***** Non-backup SRAM1 dedicated to M4 *****/
+define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
+/***** Backup SRAM2 dedicated to M4 *****/
+define symbol __ICFEDIT_region_RAM2_start__   = 0x20008000;
+define symbol __ICFEDIT_region_RAM2_end__     = 0x2000BFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM2_region     = mem:[from __ICFEDIT_region_RAM2_start__  to __ICFEDIT_region_RAM2_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+place in RAM2_region  { };
\ No newline at end of file

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_sram_cm0plus.icf

+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x2000C000;
+
+/*-Memory Regions-*/
+/***** Non-backup SRAM1 dedicated to M0+ code *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x2000C000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x2000FFFF;
+/***** Backup SRAM2 dedicated to M0+ data *****/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20004000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
\ No newline at end of file

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_sram_cm4.icf

+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x20008000;
+/*-Memory Regions-*/
+/***** Non-backup SRAM1 dedicated to M4 code *****/
+define symbol __ICFEDIT_region_ROM_start__ = 0x20008000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x2000BFFF;
+/***** Backup SRAM2 dedicated to M4 data *****/
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x200;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };