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3e32b36c
编写于
12月 15, 2021
作者:
H
Huang bo
浏览文件
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修改格式
上级
b8db37f5
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
49 addition
and
49 deletion
+49
-49
bsp/ti-tms320c6678/common/common.c
bsp/ti-tms320c6678/common/common.c
+34
-34
bsp/ti-tms320c6678/common/common.h
bsp/ti-tms320c6678/common/common.h
+12
-12
bsp/ti-tms320c6678/driver/drv_timer.c
bsp/ti-tms320c6678/driver/drv_timer.c
+3
-3
未找到文件。
bsp/ti-tms320c6678/common/common.c
浏览文件 @
3e32b36c
...
...
@@ -10,9 +10,9 @@
#include "common.h"
CSL_BootcfgRegs
*
gp
BootCfgR
egs
=
(
CSL_BootcfgRegs
*
)
CSL_BOOT_CFG_REGS
;
CSL_CgemRegs
*
gp
CGEM
_regs
=
(
CSL_CgemRegs
*
)
CSL_CGEM0_5_REG_BASE_ADDRESS_REGS
;
CSL_TmrPlusRegs
*
gp
TimerR
egs
[
9
]
=
{
CSL_BootcfgRegs
*
gp
_bootcfg_r
egs
=
(
CSL_BootcfgRegs
*
)
CSL_BOOT_CFG_REGS
;
CSL_CgemRegs
*
gp
_cgem
_regs
=
(
CSL_CgemRegs
*
)
CSL_CGEM0_5_REG_BASE_ADDRESS_REGS
;
CSL_TmrPlusRegs
*
gp
_timer_r
egs
[
9
]
=
{
(
CSL_TmrPlusRegs
*
)
CSL_TIMER_0_REGS
,
(
CSL_TmrPlusRegs
*
)
CSL_TIMER_1_REGS
,
(
CSL_TmrPlusRegs
*
)
CSL_TIMER_2_REGS
,
...
...
@@ -29,22 +29,22 @@ void cpu_interrupt_init(void)
//clear interrupt and excpetion events
ICR
=
IFR
;
ECR
=
EFR
;
IER
=
3
;
//disable all interrupts
IER
=
3
;
//disable all interrupts
/* disable event combine */
gp
CGEM
_regs
->
EVTMASK
[
0
]
=
0xffffffff
;
gp
CGEM
_regs
->
EVTMASK
[
1
]
=
0xffffffff
;
gp
CGEM
_regs
->
EVTMASK
[
2
]
=
0xffffffff
;
gp
CGEM
_regs
->
EVTMASK
[
3
]
=
0xffffffff
;
gp
_cgem
_regs
->
EVTMASK
[
0
]
=
0xffffffff
;
gp
_cgem
_regs
->
EVTMASK
[
1
]
=
0xffffffff
;
gp
_cgem
_regs
->
EVTMASK
[
2
]
=
0xffffffff
;
gp
_cgem
_regs
->
EVTMASK
[
3
]
=
0xffffffff
;
/*Clear all CPU events*/
gp
CGEM_regs
->
EVTCLR
[
0
]
=
0xFFFFFFFF
;
gp
CGEM_regs
->
EVTCLR
[
1
]
=
0xFFFFFFFF
;
gp
CGEM_regs
->
EVTCLR
[
2
]
=
0xFFFFFFFF
;
gp
CGEM_regs
->
EVTCLR
[
3
]
=
0xFFFFFFFF
;
gp
_cgem_regs
->
EVTCLR
[
0
]
=
0xFFFFFFFF
;
gp
_cgem_regs
->
EVTCLR
[
1
]
=
0xFFFFFFFF
;
gp
_cgem_regs
->
EVTCLR
[
2
]
=
0xFFFFFFFF
;
gp
_cgem_regs
->
EVTCLR
[
3
]
=
0xFFFFFFFF
;
/*Interrupt Service Table Pointer to begining of LL2 memory*/
ISTP
=
0x800000
;
ISTP
=
0x800000
;
}
void
keystone_cpu_init
(
void
)
...
...
@@ -56,10 +56,10 @@ void keystone_cpu_init(void)
/*===============================Timer=================================*/
void
reset_timer
(
int
timer_num
)
{
if
(
gp
TimerR
egs
[
timer_num
]
->
TGCR
)
if
(
gp
_timer_r
egs
[
timer_num
]
->
TGCR
)
{
gp
TimerR
egs
[
timer_num
]
->
TGCR
=
0
;
gp
TimerR
egs
[
timer_num
]
->
TCR
=
0
;
gp
_timer_r
egs
[
timer_num
]
->
TGCR
=
0
;
gp
_timer_r
egs
[
timer_num
]
->
TCR
=
0
;
}
}
...
...
@@ -67,8 +67,8 @@ void timer64_init(Timer64_Config * tmrCfg)
{
reset_timer
(
tmrCfg
->
timer_num
);
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
CNTLO
=
0
;
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
CNTHI
=
0
;
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
CNTLO
=
0
;
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
CNTHI
=
0
;
/*please note, in clock mode, two timer periods generate a clock,
one timer period output high voltage level, the other timer period
...
...
@@ -80,17 +80,17 @@ void timer64_init(Timer64_Config * tmrCfg)
}
/*the value written into period register is the expected value minus one*/
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
PRDLO
=
_loll
(
tmrCfg
->
period
-
1
);
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
PRDHI
=
_hill
(
tmrCfg
->
period
-
1
);
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
PRDLO
=
_loll
(
tmrCfg
->
period
-
1
);
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
PRDHI
=
_hill
(
tmrCfg
->
period
-
1
);
if
(
tmrCfg
->
reload_period
>
1
)
{
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
RELLO
=
_loll
(
tmrCfg
->
reload_period
-
1
);
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
RELHI
=
_hill
(
tmrCfg
->
reload_period
-
1
);
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
RELLO
=
_loll
(
tmrCfg
->
reload_period
-
1
);
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
RELHI
=
_hill
(
tmrCfg
->
reload_period
-
1
);
}
if
(
TIMER_WATCH_DOG
==
tmrCfg
->
timerMode
)
{
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
TGCR
=
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
TGCR
=
/*Select watch-dog mode*/
(
CSL_TMR_TIMMODE_WDT
<<
CSL_TMR_TGCR_TIMMODE_SHIFT
)
/*Remove the timer from reset*/
...
...
@@ -99,18 +99,18 @@ void timer64_init(Timer64_Config * tmrCfg)
}
else
if
(
TIMER_PERIODIC_WAVE
==
tmrCfg
->
timerMode
)
{
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
TGCR
=
TMR_TGCR_PLUSEN_MASK
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
TGCR
=
TMR_TGCR_PLUSEN_MASK
/*for plus featuers, dual 32-bit unchained timer mode should be used*/
|
(
CSL_TMR_TIMMODE_DUAL_UNCHAINED
<<
CSL_TMR_TGCR_TIMMODE_SHIFT
)
/*Remove the timer from reset*/
|
(
CSL_TMR_TGCR_TIMLORS_MASK
);
//in plus mode, interrupt/event must be enabled manually
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
INTCTL_STAT
=
TMR_INTCTLSTAT_EN_ALL_CLR_ALL
;
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
INTCTL_STAT
=
TMR_INTCTLSTAT_EN_ALL_CLR_ALL
;
}
else
{
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
TGCR
=
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
TGCR
=
/*Select 64-bit general timer mode*/
(
CSL_TMR_TIMMODE_GPT
<<
CSL_TMR_TGCR_TIMMODE_SHIFT
)
/*Remove the timer from reset*/
...
...
@@ -119,16 +119,16 @@ void timer64_init(Timer64_Config * tmrCfg)
}
/*make timer stop with emulation*/
gp
TimerRegs
[
tmrCfg
->
timer_num
]
->
EMUMGT_CLKSPD
=
(
gpTimerR
egs
[
tmrCfg
->
timer_num
]
->
EMUMGT_CLKSPD
&
gp
_timer_regs
[
tmrCfg
->
timer_num
]
->
EMUMGT_CLKSPD
=
(
gp_timer_r
egs
[
tmrCfg
->
timer_num
]
->
EMUMGT_CLKSPD
&
~
(
CSL_TMR_EMUMGT_CLKSPD_FREE_MASK
|
CSL_TMR_EMUMGT_CLKSPD_SOFT_MASK
));
if
(
TIMER_WATCH_DOG
==
tmrCfg
->
timerMode
)
{
/*enable watchdog timer*/
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
WDTCR
=
CSL_TMR_WDTCR_WDEN_MASK
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
WDTCR
=
CSL_TMR_WDTCR_WDEN_MASK
|
(
CSL_TMR_WDTCR_WDKEY_CMD1
<<
CSL_TMR_WDTCR_WDKEY_SHIFT
);
gp
TimerRegs
[
tmrCfg
->
timer_num
]
->
TCR
=
gp
_timer_regs
[
tmrCfg
->
timer_num
]
->
TCR
=
(
CSL_TMR_CLOCK_INP_NOGATE
<<
CSL_TMR_TCR_TIEN_LO_SHIFT
)
|
(
CSL_TMR_CLKSRC_INTERNAL
<<
CSL_TMR_TCR_CLKSRC_LO_SHIFT
)
/*The timer is enabled continuously*/
...
...
@@ -141,12 +141,12 @@ void timer64_init(Timer64_Config * tmrCfg)
|
(
0
<<
CSL_TMR_TCR_TSTAT_LO_SHIFT
);
/*active watchdog timer*/
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
WDTCR
=
CSL_TMR_WDTCR_WDEN_MASK
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
WDTCR
=
CSL_TMR_WDTCR_WDEN_MASK
|
(
CSL_TMR_WDTCR_WDKEY_CMD2
<<
CSL_TMR_WDTCR_WDKEY_SHIFT
);
}
else
if
(
TIMER_ONE_SHOT_PULSE
==
tmrCfg
->
timerMode
)
{
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
TCR
=
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
TCR
=
(
CSL_TMR_CLOCK_INP_NOGATE
<<
CSL_TMR_TCR_TIEN_LO_SHIFT
)
|
(
CSL_TMR_CLKSRC_INTERNAL
<<
CSL_TMR_TCR_CLKSRC_LO_SHIFT
)
/*The timer is enabled one-shot*/
...
...
@@ -160,7 +160,7 @@ void timer64_init(Timer64_Config * tmrCfg)
}
else
if
(
TIMER_PERIODIC_CLOCK
==
tmrCfg
->
timerMode
)
{
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
TCR
=
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
TCR
=
(
CSL_TMR_CLOCK_INP_NOGATE
<<
CSL_TMR_TCR_TIEN_LO_SHIFT
)
|
(
CSL_TMR_CLKSRC_INTERNAL
<<
CSL_TMR_TCR_CLKSRC_LO_SHIFT
)
/*The timer is enabled continuously*/
...
...
@@ -174,7 +174,7 @@ void timer64_init(Timer64_Config * tmrCfg)
}
else
if
(
TIMER_PERIODIC_WAVE
==
tmrCfg
->
timerMode
)
{
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
TCR
=
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
TCR
=
(
CSL_TMR_CLOCK_INP_NOGATE
<<
CSL_TMR_TCR_TIEN_LO_SHIFT
)
|
(
CSL_TMR_CLKSRC_INTERNAL
<<
CSL_TMR_TCR_CLKSRC_LO_SHIFT
)
/*The timer is enabled continuously with period reload*/
...
...
@@ -188,7 +188,7 @@ void timer64_init(Timer64_Config * tmrCfg)
}
else
/*TIMER_PERIODIC_PULSE*/
{
gp
TimerR
egs
[
tmrCfg
->
timer_num
]
->
TCR
=
gp
_timer_r
egs
[
tmrCfg
->
timer_num
]
->
TCR
=
(
CSL_TMR_CLOCK_INP_NOGATE
<<
CSL_TMR_TCR_TIEN_LO_SHIFT
)
|
(
CSL_TMR_CLKSRC_INTERNAL
<<
CSL_TMR_TCR_CLKSRC_LO_SHIFT
)
/*The timer is enabled continuously*/
...
...
bsp/ti-tms320c6678/common/common.h
浏览文件 @
3e32b36c
...
...
@@ -21,8 +21,8 @@
/* DSP core clock speed in Hz */
#define DSP_CORE_SPEED_HZ 1000000000
extern
CSL_CgemRegs
*
gp
CGEM
_regs
;
extern
CSL_BootcfgRegs
*
gp
BootCfgR
egs
;
extern
CSL_CgemRegs
*
gp
_cgem
_regs
;
extern
CSL_BootcfgRegs
*
gp
_bootcfg_r
egs
;
/*----------------------Timer plus registers definition----------------*/
typedef
struct
{
...
...
@@ -69,16 +69,16 @@ typedef struct {
#define CSL_TMR_ENAMODE_CONT_RELOAD 3
extern
CSL_TmrPlusRegs
*
gp
Timer0R
egs
;
extern
CSL_TmrPlusRegs
*
gp
Timer1R
egs
;
extern
CSL_TmrPlusRegs
*
gp
Timer2R
egs
;
extern
CSL_TmrPlusRegs
*
gp
Timer3R
egs
;
extern
CSL_TmrPlusRegs
*
gp
Timer4R
egs
;
extern
CSL_TmrPlusRegs
*
gp
Timer5R
egs
;
extern
CSL_TmrPlusRegs
*
gp
Timer6R
egs
;
extern
CSL_TmrPlusRegs
*
gp
Timer7R
egs
;
extern
CSL_TmrPlusRegs
*
gp
Timer8R
egs
;
extern
CSL_TmrPlusRegs
*
gp
TimerR
egs
[];
extern
CSL_TmrPlusRegs
*
gp
_timer0_r
egs
;
extern
CSL_TmrPlusRegs
*
gp
_timer1_r
egs
;
extern
CSL_TmrPlusRegs
*
gp
_timer2_r
egs
;
extern
CSL_TmrPlusRegs
*
gp
_timer3_r
egs
;
extern
CSL_TmrPlusRegs
*
gp
_timer4_r
egs
;
extern
CSL_TmrPlusRegs
*
gp
_timer5_r
egs
;
extern
CSL_TmrPlusRegs
*
gp
_timer6_r
egs
;
extern
CSL_TmrPlusRegs
*
gp
_timer7_r
egs
;
extern
CSL_TmrPlusRegs
*
gp
_timer8_r
egs
;
extern
CSL_TmrPlusRegs
*
gp
_timer_r
egs
[];
typedef
enum
{
...
...
bsp/ti-tms320c6678/driver/drv_timer.c
浏览文件 @
3e32b36c
...
...
@@ -36,7 +36,7 @@ void rt_hw_systick_isr(void)
void
rt_hw_system_timer_init
(
void
)
{
// initial system timer interrupt, map local timer interrupt to INT14
gpCGEM
_regs
->
INTMUX3
=
(
CSL_GEM_TINTLN
<<
CSL_CGEM_INTMUX3_INTSEL14_SHIFT
);
gp_cgem
_regs
->
INTMUX3
=
(
CSL_GEM_TINTLN
<<
CSL_CGEM_INTMUX3_INTSEL14_SHIFT
);
// enable CPU INT14
rt_hw_interrupt_umask
(
1
<<
14
);
...
...
@@ -45,7 +45,7 @@ void rt_hw_system_timer_init(void)
/**
* The function initial system timer.
* Use local timer (==DNUM of a core) to generate a clock on TIMO0,interrupts are generated as well
* Use local timer (==
DNUM of a core) to generate a clock on TIMO0,interrupts are generated as well
*
*/
void
rt_hw_system_timer_start
(
void
)
...
...
@@ -53,7 +53,7 @@ void rt_hw_system_timer_start(void)
Timer64_Config
tmrCfg
;
// select output on TIMO0 from local timer.
gp
BootCfgR
egs
->
TOUTSEL
=
(
DNUM
*
2
)
<<
CSL_BOOTCFG_TOUTSEL_TOUTSEL0_SHIFT
;
gp
_bootcfg_r
egs
->
TOUTSEL
=
(
DNUM
*
2
)
<<
CSL_BOOTCFG_TOUTSEL_TOUTSEL0_SHIFT
;
// configure the timer to generate clocks and interrupts
tmrCfg
.
timer_num
=
DNUM
;
...
...
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