添加 APM32F103ZE MINI 板 bsp

bsp/apm32/apm32f103xe-minibroard/.config

+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40001
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M3=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+
+#
+# Using WiFi
+#
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_LWP is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+CONFIG_SOC_FAMILY_STM32=y
+CONFIG_SOC_SERIES_STM32F1=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_STM32F103ZE=y
+
+#
+# Onboard Peripheral Drivers
+#
+# CONFIG_BSP_USING_SDCARD is not set
+# CONFIG_BSP_USING_SPI_FLASH is not set
+# CONFIG_BSP_USING_EEPROM is not set
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_I2C2 is not set
+# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
+# CONFIG_BSP_USING_SDIO is not set
+
+#
+# Board extended module Drivers
+#

bsp/apm32/apm32f103xe-minibroard/.gitignore

+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h

bsp/apm32/apm32f103xe-minibroard/Kconfig

+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"
+

bsp/apm32/apm32f103xe-minibroard/README.md

+# APM32F103ZE MINI BOARD BSP 说明
+
+## 简介
+
+本文档为 APM32F103ZE MINI 开发板（MINI BOARD）的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+## 开发板介绍
+
+APM32F103ZE MINI BOARD，采用标准JTAG/SWD调试接口，引出了全部的IO。开发板外观如下图所示：
+
+![board](figures/APM32F103ZE.png)
+
+
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：STM32F103C8T6，主频 96MHz，512KB FLASH ，128KB RAM
+- 外部 RAM：无
+- 外部 FLASH：无
+- 常用外设
+  - LED：2个，（黄色，PE5/PE6）
+  - 按键：2个，K1（兼具唤醒功能，PA0），K2（PC13）
+- 常用接口：RS232转串口、、USB SLAVE
+- 调试接口：标准 JTAG/SWD
+
+
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设** | **支持情况** | **备注**                              |
+| :----------- | :----------: | :------------------------------------ |
+| RS232转串口  |     支持     | 使用 UART1/ UART2(通过跳线选择)       |
+| **片上外设** | **支持情况** | **备注**                              |
+| GPIO         |     支持     | PA0, PA1... PG15 ---> PIN: 0, 1...143 |
+| UART         |     支持     | UART1/2                               |
+
+## 使用说明
+
+本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+
+### 快速上手
+
+本 BSP 为开发者提供MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 J-Link 仿真器下载程序，在通过 J-Link 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，LED 闪烁
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.4 build Aug 20 2021
+ 2006 - 2021 Copyright by rt-thread team
+msh >
+```
+## 注意事项
+
+- 可在极海官方网站进行所需资料下载，如pack安装包和MINI开发板原理图等（www.geehy.com）;
+
+## 联系人信息
+
+-
\ No newline at end of file

bsp/apm32/apm32f103xe-minibroard/SConscript

+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/apm32/apm32f103xe-minibroard/SConstruct

+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+apm32_library = 'APM32F10x_Library'
+rtconfig.BSP_LIBRARY_TYPE = apm32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, apm32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/apm32/apm32f103xe-minibroard/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/apm32/apm32f103xe-minibroard/applications/main.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     Abbcc        first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+/* defined the LED0 pin: PC0 */
+#define LED2_PIN    GET_PIN(E, 6)
+
+int main(void)
+{
+    /* set LED0 pin mode to output */
+    rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED2_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED2_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}

bsp/apm32/apm32f103xe-minibroard/board/Kconfig

+menu "Hardware Drivers Config"
+
+config SOC_APM32F103ZE
+    bool
+    select SOC_SERIES_APM32F1
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "On-chip Peripheral Drivers"
+
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default y
+
+        endif
+
+    source "../libraries/HAL_Drivers/Kconfig"
+    
+endmenu
+
+endmenu

bsp/apm32/apm32f103xe-minibroard/board/SConscript

+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+''')
+
+path =  [cwd]
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.CROSS_TOOL == 'keil':
+    src += [startup_path_prefix + '/APM32F10x_Library/Device/Geehy/APM32F10x/Source/ARM/startup_apm32f10x_hd.s']
+
+# You can select chips from the list above
+CPPDEFINES = ['APM32F103xE']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+Return('group')

bsp/apm32/apm32f103xe-minibroard/board/board.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     Abbcc        first version
+ */
+
+#include "board.h"
+
+void apm32_usart_init(void)
+{
+    GPIO_Config_T GPIO_ConfigStruct;
+    
+#ifdef BSP_USING_UART1
+    RCM_EnableAPB2PeriphClock((RCM_APB2_PERIPH_T)(RCM_APB2_PERIPH_GPIOA | RCM_APB2_PERIPH_USART1));
+    
+    GPIO_ConfigStruct.mode = GPIO_MODE_AF_PP;
+    GPIO_ConfigStruct.pin = GPIO_PIN_9;
+    GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
+    GPIO_Config(GPIOA, &GPIO_ConfigStruct);
+    
+    GPIO_ConfigStruct.mode = GPIO_MODE_IN_PU;
+    GPIO_ConfigStruct.pin = GPIO_PIN_10;
+    GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
+    GPIO_Config(GPIOA, &GPIO_ConfigStruct);
+#endif
+
+#ifdef BSP_USING_UART2
+    RCM_EnableAPB2PeriphClock(RCM_APB2_PERIPH_GPIOA);
+    RCM_EnableAPB1PeriphClock(RCM_APB1_PERIPH_USART2);
+    
+    GPIO_ConfigStruct.mode = GPIO_MODE_AF_PP;
+    GPIO_ConfigStruct.pin = GPIO_PIN_2;
+    GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
+    GPIO_Config(GPIOA, &GPIO_ConfigStruct);
+    
+    GPIO_ConfigStruct.mode = GPIO_MODE_IN_PU;
+    GPIO_ConfigStruct.pin = GPIO_PIN_3;
+    GPIO_ConfigStruct.speed = GPIO_SPEED_50MHz;
+    GPIO_Config(GPIOA, &GPIO_ConfigStruct);
+#endif
+}

bsp/apm32/apm32f103xe-minibroard/board/board.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     Abbcc        first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include <apm32f10x.h>
+
+#include "apm32f10x_gpio.h"
+#include "apm32f10x_rcm.h"
+#include "apm32f10x_misc.h"
+#include "apm32f10x_rcm.h"
+#include "apm32f10x_eint.h"
+#include "apm32f10x_usart.h"
+
+#include "drv_common.h"
+#include "drv_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define APM32_FLASH_START_ADRESS     ((uint32_t)0x08000000)
+#define APM32_FLASH_SIZE             (512 * 1024)
+#define APM32_FLASH_END_ADDRESS      ((uint32_t)(APM32_FLASH_START_ADRESS + APM32_FLASH_SIZE))
+
+/* Internal SRAM memory size[Kbytes] <6-128>, Default: 128 */
+#define APM32_SRAM_SIZE      128
+#define APM32_SRAM_END       (0x20000000 + APM32_SRAM_SIZE * 1024)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN      ((void *)&__bss_end)
+#endif
+
+#define HEAP_END        APM32_SRAM_END
+
+void SystemClock_Config(void);
+
+void apm32_usart_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_H__ */

bsp/apm32/apm32f103xe-minibroard/board/linker_scripts/link.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00020000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
+

bsp/apm32/apm32f103xe-minibroard/rtconfig.h

+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40001
+#define ARCH_ARM
+#define ARCH_ARM_CORTEX_M
+#define ARCH_ARM_CORTEX_M3
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_USING_MSH_ONLY
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using WiFi */
+
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* Modbus master and slave stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+#define SOC_FAMILY_APM32
+#define SOC_SERIES_APM32F1
+
+/* Hardware Drivers Config */
+
+#define SOC_APM32F103ZE
+
+/* Onboard Peripheral Drivers */
+
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART1
+
+/* Board extended module Drivers */
+
+
+#endif

bsp/apm32/apm32f103xe-minibroard/rtconfig.py

+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m3'
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armcc'
+    EXEC_PATH   = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM    = 'iar'
+    EXEC_PATH   = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    CXX = PREFIX + 'g++'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE + ' -Dgcc'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS 
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    CXX = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M3 '
+    CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+    LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+    CFLAGS += ' -D__MICROLIB '
+    AFLAGS += ' --pd "__MICROLIB SETA 1" '
+    LFLAGS += ' --library_type=microlib '
+    EXEC_PATH += '/ARM/ARMCC/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS 
+    CFLAGS += ' -std=c99'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    CXX = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = '-Dewarm'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-M3'
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=None'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --silent'
+
+    AFLAGS = DEVICE
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-M3'
+    AFLAGS += ' --fpu None'
+    AFLAGS += ' -S'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    LFLAGS = ' --config "board/linker_scripts/link.icf"'
+    LFLAGS += ' --entry __iar_program_start'
+
+    CXXFLAGS = CFLAGS
+    
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)

bsp/apm32/apm32f103xe-minibroard/template.uvprojx

+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rt-thread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>APM32F103ZE</Device>
+          <Vendor>Geehy</Vendor>
+          <PackID>Geehy.APM32F1xx_DFP.1.0.7</PackID>
+          <PackURL>https://www.geehy.com/uploads/tool/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:APM32F103ZE$Device\Include\apm32f10x.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:APM32F103ZE$SVD\APM32F103xx.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\keil\Obj\</OutputDirectory>
+          <OutputName>rtthread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\build\keil\List\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x80000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>1</v6Lang>
+            <v6LangP>1</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>4</ClangAsOpt>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Source Group 1</GroupName>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+</Project>

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_adc.h

+/*!
+ * @file        apm32f10x_adc.h
+ *
+ * @brief       This file contains all the functions prototypes for the ADC firmware library
+ *
+ * @version     V1.0.1
+ *
+ * @date        2021-03-23
+ *
+ */
+
+#ifndef __APM32F10X_ADC_H
+#define __APM32F10X_ADC_H
+
+#include "apm32f10x.h"
+
+#ifdef __cplusplus
+  extern "C" {
+#endif
+
+/** @addtogroup Peripherals_Library Standard Peripheral Library
+  @{
+*/
+
+/** @addtogroup ADC_Driver ADC Driver
+  @{
+*/
+
+/** @addtogroup ADC_Enumerations Enumerations
+  @{
+*/
+
+/**
+ * @brief    ADC configuration Mode
+ */
+typedef enum
+{
+    ADC_MODE_INDEPENDENT              = ((uint32_t)0x00000000), //!< Independent mode
+    ADC_MODE_REG_INJEC_SIMULT         = ((uint32_t)0x00010000), //!< Combined regular simultaneous and injected simultaneous mode
+    ADC_MODE_REG_SIMULT_ALTER_TRIG    = ((uint32_t)0x00020000), //!< Combined regular simultaneous and alternate trigger mode
+    ADC_MODE_INJEC_SIMULT_FAST_TNTERL = ((uint32_t)0x00030000), //!< Combined injected simultaneous and fast interleaved mode
+    ADC_MODE_INJEC_SIMULT_SLOW_INTERL = ((uint32_t)0x00040000), //!< Combined injected simultaneous and slow interleaved mode
+    ADC_MODE_INJEC_SIMULT             = ((uint32_t)0x00050000), //!< Injected simultaneous mode
+    ADC_MODE_REG_SIMULT               = ((uint32_t)0x00060000), //!< Regular simultaneous mode
+    ADC_MODE_FAST_INTERL              = ((uint32_t)0x00070000), //!< Fast interleaved mode
+    ADC_MODE_SLOW_INTERL              = ((uint32_t)0x00080000), //!< Slow interleaved mode
+    ADC_MODE_ALTER_TRIG               = ((uint32_t)0x00090000)  //!< Alternate trigger mode
+} ADC_MODE_T;
+
+/**
+ * @brief    ADC external trigger sources for regular channels conversion enumeration
+ */
+typedef enum
+{
+    ADC_EXT_TRIG_CONV_TMR1_CC1        = ((uint32_t)0x00000000),
+    ADC_EXT_TRIG_CONV_TMR1_CC2        = ((uint32_t)0x00020000),
+    ADC_EXT_TRIG_CONV_TMR2_CC2        = ((uint32_t)0x00060000),
+    ADC_EXT_TRIG_CONV_TMR3_TRGO       = ((uint32_t)0x00080000),
+    ADC_EXT_TRIG_CONV_TMR4_CC4        = ((uint32_t)0x000A0000),
+    ADC_EXT_TRIG_CONV_EINT9_T8_TRGO   = ((uint32_t)0x000C0000),
+    ADC_EXT_TRIG_CONV_TMR1_CC3        = ((uint32_t)0x00040000),
+    ADC_EXT_TRIG_CONV_None            = ((uint32_t)0x000E0000),
+
+    ADC_EXT_TRIG_CONV_TMR3_CC1        = ((uint32_t)0x00000000),
+    ADC_EXT_TRIG_CONV_TMR2_CC3        = ((uint32_t)0x00030000),
+    ADC_EXT_TRIG_CONV_TMR8_CC1        = ((uint32_t)0x00060000),
+    ADC_EXT_TRIG_CONV_TMR8_TRGO       = ((uint32_t)0x00080000),
+    ADC_EXT_TRIG_CONV_TMR5_CC1        = ((uint32_t)0x000A0000),
+    ADC_EXT_TRIG_CONV_TMR5_CC3        = ((uint32_t)0x000C0000)
+} ADC_EXT_TRIG_CONV_T;
+
+/**
+ * @brief    ADC Data Align
+ */
+typedef enum
+{
+    ADC_DATA_ALIGN_RIGHT = 0x00000000,
+    ADC_DATA_ALIGN_LEFT  = 0x00000800
+} ADC_DATA_ALIGN_T;
+
+/**
+ * @brief    ADC Channels
+ */
+typedef enum
+{
+    ADC_CHANNEL_0           = ((uint8_t)0x00),
+    ADC_CHANNEL_1           = ((uint8_t)0x01),
+    ADC_CHANNEL_2           = ((uint8_t)0x02),
+    ADC_CHANNEL_3           = ((uint8_t)0x03),
+    ADC_CHANNEL_4           = ((uint8_t)0x04),
+    ADC_CHANNEL_5           = ((uint8_t)0x05),
+    ADC_CHANNEL_6           = ((uint8_t)0x06),
+    ADC_CHANNEL_7           = ((uint8_t)0x07),
+    ADC_CHANNEL_8           = ((uint8_t)0x08),
+    ADC_CHANNEL_9           = ((uint8_t)0x09),
+    ADC_CHANNEL_10          = ((uint8_t)0x0A),
+    ADC_CHANNEL_11          = ((uint8_t)0x0B),
+    ADC_CHANNEL_12          = ((uint8_t)0x0C),
+    ADC_CHANNEL_13          = ((uint8_t)0x0D),
+    ADC_CHANNEL_14          = ((uint8_t)0x0E),
+    ADC_CHANNEL_15          = ((uint8_t)0x0F),
+    ADC_CHANNEL_16          = ((uint8_t)0x10),
+    ADC_CHANNEL_TEMP_SENSOR = ((uint8_t)0x10),
+    ADC_CHANNEL_17          = ((uint8_t)0x11),
+    ADC_CHANNEL_V_REFINT    = ((uint8_t)0x11)
+} ADC_CHANNEL_T;
+
+/**
+ * @brief    ADC Sampling Time
+ */
+typedef enum
+{
+    ADC_SAMPLE_TIME_1_5   = ((uint8_t)0x00),
+    ADC_SAMPLE_TIME_7_5   = ((uint8_t)0x01),
+    ADC_SAMPLE_TIME_13_5  = ((uint8_t)0x02),
+    ADC_SAMPLE_TIME_28_5  = ((uint8_t)0x03),
+    ADC_SAMPLE_TIME_41_5  = ((uint8_t)0x04),
+    ADC_SAMPLE_TIME_55_5  = ((uint8_t)0x05),
+    ADC_SAMPLE_TIME_71_5  = ((uint8_t)0x06),
+    ADC_SAMPLE_TIME_239_5 = ((uint8_t)0x07)
+} ADC_SAMPLE_TIME_T;
+
+/**
+ * @brief    ADC external trigger sources for injected channels conversion
+ */
+typedef enum
+{
+    /** for ADC1 and ADC2 */
+    ADC_EXT_TRIG_INJEC_CONV_TMR2_TRGO       = ((uint8_t)0x02),
+    ADC_EXT_TRIG_INJEC_CONV_TMR2_CC1        = ((uint8_t)0x03),
+    ADC_EXT_TRIG_INJEC_CONV_TMR3_CC4        = ((uint8_t)0x04),
+    ADC_EXT_TRIG_INJEC_CONV_TMR4_TRGO       = ((uint8_t)0x05),
+    ADC_EXT_TRIG_INJEC_CONV_EINT15_T8_CC4   = ((uint8_t)0x06),
+
+    /** for ADC1, ADC2 and ADC3 */
+    ADC_EXT_TRIG_INJEC_CONV_TMR1_TRGO       = ((uint8_t)0x00),
+    ADC_EXT_TRIG_INJEC_CONV_TMR1_CC4        = ((uint8_t)0x01),
+    ADC_EXT_TRIG_INJEC_CONV_NONE            = ((uint8_t)0x07),
+
+    /** for ADC3 only */
+    ADC_EXT_TRIG_INJEC_CONV_TMR4_CC3        = ((uint8_t)0x02),
+    ADC_EXT_TRIG_INJEC_CONV_TMR8_CC2        = ((uint8_t)0x03),
+    ADC_EXT_TRIG_INJEC_CONV_TMR8_CC4        = ((uint8_t)0x04),
+    ADC_EXT_TRIG_INJEC_CONV_TMR5_TRGO       = ((uint8_t)0x05),
+    ADC_EXT_TRIG_INJEC_CONV_TMR5_CC4        = ((uint8_t)0x06)
+} ADC_EXT_TRIG_INJEC_CONV_T;
+
+/**
+ * @brief    ADC Injected channels
+ */
+typedef enum
+{
+    ADC_INJEC_CHANNEL_1 = ((uint8_t)0x14),
+    ADC_INJEC_CHANNEL_2 = ((uint8_t)0x18),
+    ADC_INJEC_CHANNEL_3 = ((uint8_t)0x1C),
+    ADC_INJEC_CHANNEL_4 = ((uint8_t)0x20)
+} ADC_INJEC_CHANNEL_T;
+
+/**
+ * @brief    ADC Analog Watchdog Selection
+ */
+typedef enum
+{
+    ADC_ANALOG_WATCHDOG_SINGLE_REG        = ((uint32_t)0x00800200),
+    ADC_ANALOG_WATCHDOG_SINGLE_INJEC      = ((uint32_t)0x00400200),
+    ADC_ANALOG_WATCHDOG_SINGLE_REG_INJEC  = ((uint32_t)0x00C00200),
+    ADC_ANALOG_WATCHDOG_ALL_REG           = ((uint32_t)0x00800000),
+    ADC_ANALOG_WATCHDOG_ALL_INJEC         = ((uint32_t)0x00400000),
+    ADC_ANALOG_WATCHDOG_ALL_REG_ALL_INJEC = ((uint32_t)0x00C00000),
+    ADC_ANALOG_WATCHDOG_NONE              = ((uint32_t)0x00000000)
+} ADC_ANALOG_WATCHDOG_T;
+
+/**
+ * @brief    ADC Interrupt definition
+ */
+typedef enum
+{
+    ADC_INT_AWD    = ((uint16_t)0x0140), //!<  Analog Watchdog interrupt
+    ADC_INT_EOC    = ((uint16_t)0x0220), //!<  End Of Conversion interrupt
+    ADC_INT_INJEOC = ((uint16_t)0x0480)  //!<  Injected Channel End Of Conversion interrupt
+} ADC_INT_T;
+
+/**
+ * @brief    ADC Flag
+ */
+typedef enum
+{
+    ADC_FLAG_AWD    = ((uint8_t)0x01), //!<  Analog Watchdog event occur flag
+    ADC_FLAG_EOC    = ((uint8_t)0x02), //!<  End Of Conversion flag
+    ADC_FLAG_INJEOC = ((uint8_t)0x04), //!<  Injected Channel End Of Conversion flag
+    ADC_FLAG_INJCS  = ((uint8_t)0x08), //!<  Injected Channel Conversion Start flag
+    ADC_FLAG_REGCS  = ((uint8_t)0x10)  //!<  Regular Channel Conversion Start flag
+} ADC_FLAG_T;
+
+/**@} end of group ADC_Enumerations*/
+
+
+/** @addtogroup ADC_Macros Macros
+  @{
+*/
+
+/** ADC_IJD Offset */
+#define INJDATA_OFFSET          ((uint8_t)0x28)
+
+/** ADC_RDG register address */
+#define RDG_ADDRESS             ((uint32_t)0x4001244C)
+
+/** INJSEQ register config */
+#define INJSEQ_SET_INJSEQC      ((uint32_t)0x0000001F)
+#define INJSEQ_SET_INJSEQLEN    ((uint32_t)0x00300000)
+
+/** SMPTIM register SET */
+#define SMPCYCCFG_SET_SMPTIM1   ((uint32_t)0x00000007)
+#define SMPCYCCFG_SET_SMPTIM2   ((uint32_t)0x00000007)
+
+/** REGSEQ register SET  */
+#define REGSEQC_SET_REGSEQ3     ((uint32_t)0x0000001F)
+#define REGSEQC_SET_REGSEQ2     ((uint32_t)0x0000001F)
+#define REGSEQC_SET_REGSEQ1     ((uint32_t)0x0000001F)
+
+/**@} end of group ADC_Macros*/
+
+
+/** @addtogroup ADC_Structure Data Structure
+  @{
+*/
+
+/**
+ * @brief    ADC Config structure definition
+ */
+typedef struct
+{
+    ADC_MODE_T          mode;
+    uint8_t             scanConvMode;       //!< This parameter can be ENABLE or DISABLE.
+    uint8_t             continuosConvMode;  //!< This parameter can be ENABLE or DISABLE.
+    ADC_EXT_TRIG_CONV_T externalTrigConv;
+    ADC_DATA_ALIGN_T    dataAlign;
+    uint8_t             nbrOfChannel;       //!< This parameter must range from 1 to 16.
+} ADC_Config_T;
+
+/**@} end of group ADC_Structure*/
+
+
+/** @addtogroup ADC_Fuctions Fuctions
+  @{
+*/
+
+/** ADC reset and common configuration */
+void ADC_Reset(ADC_T* adc);
+void ADC_Config(ADC_T* adc, ADC_Config_T* adcConfig);
+void ADC_ConfigStructInit(ADC_Config_T* adcConfig);
+void ADC_ConfigRegularChannel(ADC_T* adc, uint8_t channel,uint8_t rank, uint8_t sampleTime);
+void ADC_Enable(ADC_T* adc);
+void ADC_Disable(ADC_T* adc);
+
+/** ADC for DMA */
+void ADC_EnableDMA(ADC_T* adc);
+void ADC_DisableDMA(ADC_T* adc);
+
+/** ADC Calibration */
+void ADC_ResetCalibration(ADC_T* adc);
+uint8_t ADC_ReadResetCalibrationStatus(ADC_T* adc);
+void ADC_StartCalibration(ADC_T* adc);
+uint8_t ADC_ReadCalibrationStartFlag(ADC_T* adc);
+
+/** ADC software start conversion */
+void ADC_EnableSoftwareStartConv(ADC_T* adc);
+void ADC_DisableSoftwareStartConv(ADC_T* adc);
+uint8_t ADC_ReadSoftwareStartConvStatus(ADC_T* adc);
+
+/** ADC Discontinuous mode */
+void ADC_ConfigDiscModeChannel(ADC_T* adc, uint8_t number);
+void ADC_EnableDiscMode(ADC_T* adc);
+void ADC_DisableDiscMode(ADC_T* adc);
+
+/** ADC External trigger conversion */
+void ADC_EnableExternalTrigConv(ADC_T* adc);
+void ADC_DisableExternalTrigConv(ADC_T* adc);
+
+/** ADC Conversion result */
+uint16_t ADC_ReadConversionValue(ADC_T* adc);
+uint32_t ADC_ReadDualModeConversionValue(ADC_T* adc);
+
+/** ADC Automatic injected group */
+void ADC_EnableInjectedConv(ADC_T* adc);
+void ADC_DisableInjectedConv(ADC_T* adc);
+void ADC_EnableInjectedDiscMode(ADC_T* adc);
+void ADC_DisableInjectedDiscMode(ADC_T* adc);
+
+/** ADC External trigger for injected channels conversion */
+void ADC_ConfigExternalTrigInjectedConv(ADC_T* adc, ADC_EXT_TRIG_INJEC_CONV_T extTrigInjecConv);
+void ADC_EnableExternalTrigInjectedConv(ADC_T* adc);
+void ADC_DisableExternalTrigInjectedConv(ADC_T* adc);
+
+/** ADC Start of the injected channels conversion */
+void ADC_EnableSoftwareStartInjectedConv(ADC_T* adc);
+void ADC_DisableSoftwareStartInjectedConv(ADC_T* adc);
+uint8_t ADC_ReadSoftwareStartInjectedConvStatus(ADC_T* adc);
+
+/** ADC injected channel */
+void ADC_ConfigInjectedChannel(ADC_T* adc, uint8_t channel, uint8_t rank, uint8_t sampleTime);
+void ADC_ConfigInjectedSequencerLength(ADC_T* adc, uint8_t length);
+void ADC_ConfigInjectedOffset(ADC_T* adc, ADC_INJEC_CHANNEL_T channel, uint16_t offSet);
+uint16_t ADC_ReadInjectedConversionValue(ADC_T* adc, ADC_INJEC_CHANNEL_T channel);
+
+/** ADC analog watchdog */
+void ADC_EnableAnalogWatchdog(ADC_T* adc, uint32_t analogWatchdog);
+void ADC_DisableAnalogWatchdog(ADC_T* adc);
+void ADC_ConfigAnalogWatchdogThresholds(ADC_T* adc, uint16_t highThreshold, uint16_t lowThreshold);
+void ADC_ConfigAnalogWatchdogSingleChannel(ADC_T* adc, uint8_t channel);
+
+/** ADC temperature sensor */
+void ADC_EnableTempSensorVrefint(ADC_T* adc);
+void ADC_DisableTempSensorVrefint(ADC_T* adc);
+
+/** Interrupt and flag */
+void ADC_EnableInterrupt(ADC_T* adc, uint16_t interrupt);
+void ADC_DisableInterrupt(ADC_T* adc, uint16_t interrupt);
+uint8_t ADC_ReadStatusFlag(ADC_T* adc, ADC_FLAG_T flag);
+void ADC_ClearStatusFlag(ADC_T* adc, uint8_t flag);
+uint8_t ADC_ReadIntFlag(ADC_T* adc, ADC_INT_T interrupt);
+void ADC_ClearIntFlag(ADC_T* adc, uint16_t interrupt);
+
+/**@} end of group ADC_Fuctions*/
+/**@} end of group ADC_Driver*/
+/**@} end of group Peripherals_Library*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /** __APM32F10X_ADC_H */

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_bakpr.h

+/*!
+ * @file        apm32f10x_bakr.h
+ *
+ * @brief       This file contains all the functions prototypes for the BAKPR firmware library.
+ *
+ * @version     V1.0.1
+ *
+ * @date        2021-03-23
+ *
+ */
+
+#ifndef __APM32F10X_BAKPR_H
+#define __APM32F10X_BAKPR_H
+
+#include "apm32f10x.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup Peripherals_Library Standard Peripheral Library
+  @{
+*/
+
+/** @addtogroup BAKPR_Driver BAKPR Driver
+  @{
+*/
+
+/** @addtogroup BAKPR_Enumerations Enumerations
+  @{
+*/
+
+/**
+ * @brief BAKPR TAMPER Pin Active Level
+ */
+typedef enum
+{
+    BAKPR_TAMPER_PIN_LEVEL_HIGH,
+    BAKPR_TAMPER_PIN_LEVEL_LOW
+} BAKPR_TAMPER_PIN_LEVEL_T;
+
+/**
+ * @brief BAKPR RTC output source
+ */
+typedef enum
+{
+    BAKPR_RTC_OUTPUT_SOURCE_NONE,
+    BAKPR_RTC_OUTPUT_SOURCE_CALIBRATION_CLOCK,
+    BAKPR_RTC_OUTPUT_SOURCE_ALARM,
+    BAKPR_RTC_OUTPUT_SOURCE_SECOND
+} BAKPR_RTC_OUTPUT_SOURCE_T;
+
+/**
+ * @brief BAKPR DATA register Addr
+ */
+typedef enum
+{
+    BAKPR_DATA1  = ((uint16_t)0x0004),
+    BAKPR_DATA2  = ((uint16_t)0x0008),
+    BAKPR_DATA3  = ((uint16_t)0x000C),
+    BAKPR_DATA4  = ((uint16_t)0x0010),
+    BAKPR_DATA5  = ((uint16_t)0x0014),
+    BAKPR_DATA6  = ((uint16_t)0x0018),
+    BAKPR_DATA7  = ((uint16_t)0x001C),
+    BAKPR_DATA8  = ((uint16_t)0x0020),
+    BAKPR_DATA9  = ((uint16_t)0x0024),
+    BAKPR_DATA10 = ((uint16_t)0x0028),
+    BAKPR_DATA11 = ((uint16_t)0x0040),
+    BAKPR_DATA12 = ((uint16_t)0x0044),
+    BAKPR_DATA13 = ((uint16_t)0x0048),
+    BAKPR_DATA14 = ((uint16_t)0x004C),
+    BAKPR_DATA15 = ((uint16_t)0x0050),
+    BAKPR_DATA16 = ((uint16_t)0x0054),
+    BAKPR_DATA17 = ((uint16_t)0x0058),
+    BAKPR_DATA18 = ((uint16_t)0x005C),
+    BAKPR_DATA19 = ((uint16_t)0x0060),
+    BAKPR_DATA20 = ((uint16_t)0x0064),
+    BAKPR_DATA21 = ((uint16_t)0x0068),
+    BAKPR_DATA22 = ((uint16_t)0x006C),
+    BAKPR_DATA23 = ((uint16_t)0x0070),
+    BAKPR_DATA24 = ((uint16_t)0x0074),
+    BAKPR_DATA25 = ((uint16_t)0x0078),
+    BAKPR_DATA26 = ((uint16_t)0x007C),
+    BAKPR_DATA27 = ((uint16_t)0x0080),
+    BAKPR_DATA28 = ((uint16_t)0x0084),
+    BAKPR_DATA29 = ((uint16_t)0x0088),
+    BAKPR_DATA30 = ((uint16_t)0x008C),
+    BAKPR_DATA31 = ((uint16_t)0x0090),
+    BAKPR_DATA32 = ((uint16_t)0x0094),
+    BAKPR_DATA33 = ((uint16_t)0x0098),
+    BAKPR_DATA34 = ((uint16_t)0x009C),
+    BAKPR_DATA35 = ((uint16_t)0x00A0),
+    BAKPR_DATA36 = ((uint16_t)0x00A4),
+    BAKPR_DATA37 = ((uint16_t)0x00A8),
+    BAKPR_DATA38 = ((uint16_t)0x00AC),
+    BAKPR_DATA39 = ((uint16_t)0x00B0),
+    BAKPR_DATA40 = ((uint16_t)0x00B4),
+    BAKPR_DATA41 = ((uint16_t)0x00B8),
+    BAKPR_DATA42 = ((uint16_t)0x00BC)
+} BAKPR_DATA_T;
+
+/**@} end of group BAKPR_Enumerations*/
+
+
+/** @addtogroup BAKPR_Fuctions Fuctions
+  @{
+*/
+
+/** BAKPR reset and configuration */
+void BAKPR_Reset(void);
+void BAKPR_ConfigTamperPinLevel(BAKPR_TAMPER_PIN_LEVEL_T value);
+void BAKPR_EnableTamperPin(void);
+void BAKPR_DisableTamperPin(void);
+void BAKPR_ConfigRTCOutput(BAKPR_RTC_OUTPUT_SOURCE_T soure);
+void BAKPR_ConfigRTCCalibrationValue(uint8_t calibrationValue);
+void BAKPR_ConfigBackupRegister(BAKPR_DATA_T bakrData, uint16_t data);
+uint16_t BAKPR_ReadBackupRegister(BAKPR_DATA_T bakrData);
+
+/** Interrupts and flags */
+void BAKPR_EnableInterrupt(void);
+void BAKPR_DisableInterrupt(void);
+uint8_t BAKPR_ReadStatusFlag(void);
+void BAKPR_ClearStatusFlag(void);
+uint8_t BAKPR_ReadIntFlag(void);
+void BAKPR_ClearIntFlag(void);
+
+/**@} end of group BAKPR_Fuctions*/
+/**@} end of group BAKPR_Driver */
+/**@} end of group Peripherals_Library*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __APM32F10X_BAKPR_H */

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_can.h

+/*!
+ * @file       apm32f10x_can.h
+ *
+ * @brief      This file contains all the functions prototypes for the CAN firmware library
+ *
+ * @version    V1.0.1
+ *
+ * @date       2021-03-23
+ *
+ */
+
+#ifndef __APM32F10X_CAN_H
+#define __APM32F10X_CAN_H
+
+#include "apm32f10x.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup Peripherals_Library Standard Peripheral Library
+  @{
+*/
+
+/** @addtogroup CAN_Driver CAN Driver
+  @{
+*/
+
+/** @addtogroup CAN_Enumerations Enumerations
+  @{
+*/
+
+/**
+ * @brief CAN mode
+ */
+typedef enum
+{
+    CAN_MODE_NORMAL          = ((uint8_t)00),  //!< normal mode
+    CAN_MODE_LOOPBACK        = ((uint8_t)01),  //!< loopback mode
+    CAN_MODE_SILENT          = ((uint8_t)02),  //!< silent mode
+    CAN_MODE_SILENT_LOOPBACK = ((uint8_t)03),  //!< loopback combined with silent mode
+} CAN_MODE_T;
+
+/**
+ * @brief CAN synchronisation jump width
+ */
+typedef enum
+{
+    CAN_SJW_1 = ((uint8_t)00),  //!< 1 time quantum
+    CAN_SJW_2 = ((uint8_t)01),  //!< 2 time quantum
+    CAN_SJW_3 = ((uint8_t)02),  //!< 3 time quantum
+    CAN_SJW_4 = ((uint8_t)03)   //!< 4 time quantum
+} CAN_SJW_T;
+
+/**
+ * @brief CAN time quantum in bit segment 1
+ */
+typedef enum
+{
+    CAN_TIME_SEGMENT1_1  = ((uint8_t)0x00),  //!< 1  time quanta
+    CAN_TIME_SEGMENT1_2  = ((uint8_t)0x01),  //!< 2  time quanta
+    CAN_TIME_SEGMENT1_3  = ((uint8_t)0x02),  //!< 3  time quanta
+    CAN_TIME_SEGMENT1_4  = ((uint8_t)0x03),  //!< 4  time quanta
+    CAN_TIME_SEGMENT1_5  = ((uint8_t)0x04),  //!< 5  time quanta
+    CAN_TIME_SEGMENT1_6  = ((uint8_t)0x05),  //!< 6  time quanta
+    CAN_TIME_SEGMENT1_7  = ((uint8_t)0x06),  //!< 7  time quanta
+    CAN_TIME_SEGMENT1_8  = ((uint8_t)0x07),  //!< 8  time quanta
+    CAN_TIME_SEGMENT1_9  = ((uint8_t)0x08),  //!< 9  time quanta
+    CAN_TIME_SEGMENT1_10 = ((uint8_t)0x09),  //!< 10 time quanta
+    CAN_TIME_SEGMENT1_11 = ((uint8_t)0x0A),  //!< 11 time quanta
+    CAN_TIME_SEGMENT1_12 = ((uint8_t)0x0B),  //!< 12 time quanta
+    CAN_TIME_SEGMENT1_13 = ((uint8_t)0x0C),  //!< 13 time quanta
+    CAN_TIME_SEGMENT1_14 = ((uint8_t)0x0D),  //!< 14 time quanta
+    CAN_TIME_SEGMENT1_15 = ((uint8_t)0x0E),  //!< 15 time quanta
+    CAN_TIME_SEGMENT1_16 = ((uint8_t)0x0F)   //!< 16 time quanta
+} CAN_TIME_SEGMENT1_T;
+
+/**
+ * @brief CAN time quantum in bit segment 2
+ */
+typedef enum
+{
+    CAN_TIME_SEGMENT2_1 = (uint8_t)0x00,     //!< 1  time quanta
+    CAN_TIME_SEGMENT2_2 = (uint8_t)0x01,     //!< 2  time quanta
+    CAN_TIME_SEGMENT2_3 = (uint8_t)0x02,     //!< 3  time quanta
+    CAN_TIME_SEGMENT2_4 = (uint8_t)0x03,     //!< 4  time quanta
+    CAN_TIME_SEGMENT2_5 = (uint8_t)0x04,     //!< 5  time quanta
+    CAN_TIME_SEGMENT2_6 = (uint8_t)0x05,     //!< 6  time quanta
+    CAN_TIME_SEGMENT2_7 = (uint8_t)0x06,     //!< 7  time quanta
+    CAN_TIME_SEGMENT2_8 = (uint8_t)0x07,     //!< 8  time quanta
+} CAN_TIME_SEGMENT2_T;
+
+/**
+ * @brief CAN filter FIFO
+ */
+typedef enum
+{
+    CAN_FILTER_FIFO_0 = ((uint8_t)0x00),     //!< filter FIFO 0
+    CAN_FILTER_FIFO_1 = ((uint8_t)0x01),     //!< filter FIFO 1
+} CAN_FILTER_FIFO_T;
+
+/**
+ * @brief CAN filter mode
+ */
+typedef enum
+{
+    CAN_FILTER_MODE_IDMASK = ((uint8_t)00),  //!< identifier/mask mode
+    CAN_FILTER_MODE_IDLIST = ((uint8_t)01)   //!< identifier list mode
+} CAN_FILTER_MODE_T;
+
+/**
+ * @brief CAN filter scale
+ */
+typedef enum
+{
+    CAN_FILTER_SCALE_16BIT = ((uint8_t)0x00), //!< Two 16-bit filters
+    CAN_FILTER_SCALE_32BIT = ((uint8_t)0x01), //!< One 32-bit filter
+} CAN_FILTER_SCALE_T;
+
+/**
+ * @brief CAN identifier type
+ */
+typedef enum
+{
+    CAN_TYPEID_STD = ((uint32_t)0x00000000), //!< Standard Id
+    CAN_TYPEID_EXT = ((uint32_t)0x00000004)  //!< Extended Id
+} CAN_TYPEID_T;
+
+/**
+ * @brief CAN_remote_transmission_request
+ */
+typedef enum
+{
+    CAN_RTXR_DATA   = ((uint32_t)0x00000000), //!< Data frame
+    CAN_RTXR_REMOTE = ((uint32_t)0x00000002)  //!< Remote frame
+} CAN_RTXR_T;
+
+/**
+ * @brief Mailboxes definition
+ */
+typedef enum
+{
+    CAN_TX_MAILBIX_0 = ((uint8_t)0x00), //!< Tx mailbox0
+    CAN_TX_MAILBIX_1 = ((uint8_t)0x01), //!< Tx mailbox1
+    CAN_TX_MAILBIX_2 = ((uint8_t)0x02), //!< Tx mailbox2
+} CAN_TX_MAILBIX_T;
+
+/**
+ * @brief CAN receive FIFO number constants
+ */
+typedef enum
+{
+    CAN_RX_FIFO_0 = ((uint8_t)0x00), //!< receive FIFO 0
+    CAN_RX_FIFO_1 = ((uint8_t)0x01), //!< receive FIFO 1
+} CAN_RX_FIFO_T;
+
+/**
+ * @brief CAN Operating Mode
+ */
+typedef enum
+{
+    CAN_OPERATING_MODE_INIT   = ((uint8_t)00), //!< Initialization mode
+    CAN_OPERATING_MODE_NORMAL = ((uint8_t)01), //!< Normal mode
+    CAN_OPERATING_MODE_SLEEP  = ((uint8_t)02), //!< sleep mode
+} CAN_OPERATING_MODE_T;
+
+/**
+ * @brief CAN Interrupts
+ */
+typedef enum
+{
+    CAN_INT_TXME   = ((uint32_t)0x00000001), //!< Transmit mailbox empty Interrupt
+    CAN_INT_F0MP   = ((uint32_t)0x00000002), //!< FIFO 0 message pending Interrupt
+    CAN_INT_F0FULL = ((uint32_t)0x00000004), //!< FIFO 0 full Interrupt
+    CAN_INT_F0OVR  = ((uint32_t)0x00000008), //!< FIFO 0 overrun Interrupt
+    CAN_INT_F1MP   = ((uint32_t)0x00000010), //!< FIFO 1 message pending Interrupt
+    CAN_INT_F1FULL = ((uint32_t)0x00000020), //!< FIFO 1 full Interrupt
+    CAN_INT_F1OVR  = ((uint32_t)0x00000040), //!< FIFO 1 overrun Interrupt
+    CAN_INT_ERRW   = ((uint32_t)0x00000100), //!< Error warning Interrupt
+    CAN_INT_ERRP   = ((uint32_t)0x00000200), //!< Error passive Interrupt
+    CAN_INT_BOF    = ((uint32_t)0x00000400), //!< Bus-off Interrupt
+    CAN_INT_LEC    = ((uint32_t)0x00000800), //!< Last error record code Interrupt
+    CAN_INT_ERR    = ((uint32_t)0x00008000), //!< Error Interrupt
+    CAN_INT_WUP    = ((uint32_t)0x00010000), //!< Wake-up Interrupt
+    CAN_INT_SLEEP  = ((uint32_t)0x00020000)  //!< Sleep acknowledge Interrupt
+} CAN_INT_T;
+
+/**
+ * @brief CAN Flags
+ */
+typedef enum
+{
+    /** Error flag*/
+    CAN_FLAG_ERRW   = ((uint32_t)0x10F00001),  //!< Error Warning Flag
+    CAN_FLAG_ERRP   = ((uint32_t)0x10F00002),  //!< Error Passive Flag
+    CAN_FLAG_BOF    = ((uint32_t)0x10F00004),  //!< Bus-Off Flag
+    CAN_FLAG_LERRC  = ((uint32_t)0x30F00070),  //!< Last error record code Flag
+    /** Operating Mode Flags */
+    CAN_FLAG_WUPI   = ((uint32_t)0x31000008),  //!< Wake up Flag
+    CAN_FLAG_SLEEP  = ((uint32_t)0x31000012),  //!< Sleep acknowledge Flag
+    /** Receive Flags */
+    CAN_FLAG_F0MP   = ((uint32_t)0x12000003),  //!< FIFO 0 Message Pending Flag
+    CAN_FLAG_F0FULL = ((uint32_t)0x32000008),  //!< FIFO 0 Full Flag
+    CAN_FLAG_F0OVR  = ((uint32_t)0x32000010),  //!< FIFO 0 Overrun Flag
+    CAN_FLAG_F1MP   = ((uint32_t)0x14000003),  //!< FIFO 1 Message Pending Flag
+    CAN_FLAG_F1FULL = ((uint32_t)0x34000008),  //!< FIFO 1 Full Flag
+    CAN_FLAG_F1OVR  = ((uint32_t)0x34000010),  //!< FIFO 1 Overrun Flag
+    /** Transmit Flags */
+    CAN_FLAG_REQC0  = ((uint32_t)0x38000001),  //!< Request MailBox0 Flag
+    CAN_FLAG_REQC1  = ((uint32_t)0x38000100),  //!< Request MailBox1 Flag
+    CAN_FLAG_REQC2  = ((uint32_t)0x38010000)   //!< Request MailBox2 Flag
+} CAN_FLAG_T;
+
+/**@} end of group CAN_Enumerations*/
+
+
+/**
+ * @brief    CAN Config structure definition
+ */
+
+/**
+ * @brief CAN config structure definition
+ */
+typedef struct
+{
+    uint8_t      timeTrigComMode;     //!< Enable or disable the time triggered communication mode.
+    uint8_t      autoBusOffManage;    //!< Enable or disable the automatic bus-off management.
+    uint8_t      autoWakeUpMode;      //!< Enable or disable the automatic wake-up mode.
+    uint8_t      nonAutoRetran;       //!< Enable or disable the non-automatic retransmission mode.
+    uint8_t      rxFIFOLockMode;      //!< Enable or disable the Receive FIFO Locked mode.
+    uint8_t      txFIFOPriority;      //!< Enable or disable the transmit FIFO priority.
+    CAN_MODE_T   mode;                //!< Specifies the CAN operating mode.
+    CAN_SJW_T    syncJumpWidth;       /** Specifies the maximum number of time quanta the CAN hardware
+                                       *  is allowed to lengthen or shorten a bit to perform resynchronization.
+                                       */
+    CAN_TIME_SEGMENT1_T timeSegment1; //!< Specifies the number of time quanta in Bit Segment 1.
+    CAN_TIME_SEGMENT2_T timeSegment2; //!< Specifies the number of time quanta in Bit Segment 2.
+    uint16_t            prescaler;    //!< Specifies the length of a time quantum. It can be 1 to 1024.
+} CAN_Config_T;
+
+/**
+ * @brief  CAN Tx message structure definition
+ */
+typedef struct
+{
+    uint32_t            stdID;         //!< Specifies the standard identifier. It can be 0 to 0x7FF.
+    uint32_t            extID;         //!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF.
+    CAN_TYPEID_T        typeID;
+    CAN_RTXR_T          remoteTxReq;
+    uint8_t             dataLengthCode;//!< Specifies the data length code.       It can be 0 to 8.
+    uint8_t             data[8];       //!< Specifies the data to be transmitted. It can be 0 to 0xFF.
+} CAN_TX_MESSAGE_T;
+
+/**
+ * @brief  CAN Rx message structure definition
+ */
+typedef struct
+{
+    uint32_t            stdID;           //!< Specifies the standard identifier. It can be 0 to 0x7FF.
+    uint32_t            extID;           //!< Specifies the extended identifier. It can be 0 to 0x1FFFFFFF.
+    uint32_t            typeID;
+    uint32_t            remoteTxReq;
+    uint8_t             dataLengthCode;  //!< Specifies the data length code.       It can be 0 to 8.
+    uint8_t             data[8];         //!< Specifies the data to be transmitted. It can be 0 to 0xFF.
+    uint8_t             filterMatchIndex;//!< Specifies the filter match index.     It can be 0 to 0xFF.
+} CAN_RX_MESSAGE_T;
+
+/**
+ * @brief     CAN filter config structure definition
+ */
+typedef struct
+{
+    uint8_t             filterNumber;      //!< Specifies the filter number. It can be 0 to 13.
+    uint16_t            filterIdHigh;      //!< Specifies the filter identification number.It can be 0 to 0xFFFF.
+    uint16_t            filterIdLow;       //!< Specifies the filter identification number.It can be 0 to 0xFFFF.
+    uint16_t            filterMaskIdHigh;  //!< Specifies the filter mask identification.  It can be 0 to 0xFFFF.
+    uint16_t            filterMaskIdLow;   //!< Specifies the filter mask identification.  It can be 0 to 0xFFFF.
+    uint16_t            filterActivation;  //!< Specifies the filter Activation. It can be ENABLE or DISABLE.
+    CAN_FILTER_FIFO_T   filterFIFO;
+    CAN_FILTER_MODE_T   filterMode;
+    CAN_FILTER_SCALE_T  filterScale;
+} CAN_FILTER_CONFIG_T;
+
+/**@} end of group CAN_Structure*/
+
+
+/** @addtogroup CAN_Fuctions Fuctions
+  @{
+*/
+
+/** CAN reset and configuration */
+void CAN_Reset(CAN_T* can);
+uint8_t CAN_Config(CAN_T* can, CAN_Config_T* canConfig);
+void CAN_ConfigFilter(CAN_T* can, CAN_FILTER_CONFIG_T* filterConfig);
+void CAN_ConfigStructInit(CAN_Config_T* canConfig);
+void CAN_EnableDBGFreeze(CAN_T* can);
+void CAN_DisableDBGFreeze(CAN_T* can);
+void CAN_EnableTTCComMode(CAN_T* can);
+void CAN_DisableTTCComMode(CAN_T* can);
+
+/** CAN frames transmit */
+uint8_t CAN_TxMessage(CAN_T* can, CAN_TX_MESSAGE_T* TxMessage);
+uint8_t CAN_TxMessageStatus(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox);
+void CAN_CancelTxMailbox(CAN_T* can, CAN_TX_MAILBIX_T TxMailbox);
+
+/** CAN frames receive */
+void CAN_RxMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber, CAN_RX_MESSAGE_T* RxMessage);
+void CAN_ReleaseFIFO(CAN_T* can, CAN_RX_FIFO_T FIFONumber);
+uint8_t CAN_PendingMessage(CAN_T* can, CAN_RX_FIFO_T FIFONumber);
+
+/** CAN operation modes */
+uint8_t CAN_OperatingMode(CAN_T* can, CAN_OPERATING_MODE_T operatingMode);
+uint8_t CAN_SleepMode(CAN_T* can);
+uint8_t CAN_WakeUpMode(CAN_T* can);
+
+/** CAN bus error management */
+uint8_t CAN_ReadLastErrorCode(CAN_T* can);
+uint8_t CAN_ReadRxErrorCounter(CAN_T* can);
+uint8_t CAN_ReadLSBTxErrorCounter(CAN_T* can);
+
+/** CAN interrupt and flag */
+void CAN_EnableInterrupt(CAN_T* can, uint32_t interrupt);
+void CAN_DisableInterrupt(CAN_T* can, uint32_t interrupt);
+uint8_t CAN_ReadStatusFlag(CAN_T* can, CAN_FLAG_T flag);
+void CAN_ClearStatusFlag(CAN_T* can, CAN_FLAG_T flag);
+uint8_t CAN_ReadIntFlag(CAN_T* can, CAN_INT_T flag);
+void CAN_ClearIntFlag(CAN_T* can, CAN_INT_T flag);
+
+/**@} end of group CAN_Fuctions*/
+/**@} end of group CAN_Driver */
+/**@} end of group Peripherals_Library*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __APM32F10X_CAN_H */

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_crc.h

+/*!
+ * @file       apm32f10x_crc.h
+ *
+ * @brief      This file contains all the functions prototypes for the CRC firmware library
+ *
+ * @version    V1.0.1
+ *
+ * @date       2021-03-23
+ *
+ */
+
+#ifndef __APM32F10X_CRC_H
+#define __APM32F10X_CRC_H
+
+#include "apm32f10x.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup Peripherals_Library Standard Peripheral Library
+  @{
+*/
+
+/** @addtogroup CRC_Driver CRC Driver
+  @{
+*/
+
+/** @addtogroup CRC_Fuctions Fuctions
+  @{
+*/
+
+/** Reset DATA */
+void CRC_ResetDATA(void);
+
+/** Operation functions */
+uint32_t CRC_CalculateCRC(uint32_t data);
+uint32_t CRC_CalculateBlockCRC(uint32_t *buf, uint32_t bufLen);
+uint32_t CRC_ReadCRC(void);
+void CRC_WriteIDRegister(uint8_t inData);
+uint8_t CRC_ReadIDRegister(void);
+
+/**@} end of group CRC_Fuctions*/
+/**@} end of group CRC_Driver */
+/**@} end of group Peripherals_Library*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __APM32F10X_CRC_H */
+

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dac.h

+/*!
+ * @file        apm32f10x_dac.h
+ *
+ * @brief       This file contains all the functions prototypes for the DAC firmware library
+ *
+ * @version     V1.0.1
+ *
+ * @date        2021-03-23
+ *
+ */
+
+#ifndef __APM32F10X_DAC_H
+#define __APM32F10X_DAC_H
+
+#include "apm32f10x.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Peripherals_Library Standard Peripheral Library
+  @{
+*/
+
+/** @addtogroup DAC_Driver DAC Driver
+  @{
+*/
+
+/** @addtogroup DAC_Enumerations Enumerations
+  @{
+*/
+
+/**
+ * @brief    DAC Channel selection
+ */
+typedef enum
+{
+    DAC_CHANNEL_1 = 0x00000000,
+    DAC_CHANNEL_2 = 0x00000010
+}DAC_CHANNEL_T;
+
+/**
+ * @brief    DAC trigger selection
+ */
+typedef enum
+{
+    DAC_TRIGGER_NONE       = 0x00000000,
+    DAC_TRIGGER_TMR6_TRGO  = 0x00000004,
+    DAC_TRIGGER_TMR8_TRGO  = 0x0000000C,
+    DAC_TRIGGER_TMR7_TRGO  = 0x00000014,
+    DAC_TRIGGER_TMR5_TRGO  = 0x0000001C,
+    DAC_TRIGGER_TMR2_TRGO  = 0x00000024,
+    DAC_TRIGGER_TMR4_TRGO  = 0x0000002C,
+    DAC_TRIGGER_EINT9      = 0x00000034,
+    DAC_TRIGGER_SOFT       = 0x0000003C
+}DAC_TRIGGER_T;
+
+/**
+ * @brief    DAC wave generation
+ */
+typedef enum
+{
+    DAC_WAVE_GENERATION_NONE     = 0x00000000,
+    DAC_WAVE_GENERATION_NOISE    = 0x00000040,
+    DAC_WAVE_GENERATION_TRIANGLE = 0x00000080
+}DAC_WAVE_GENERATION_T;
+
+/**
+ * @brief    DAC channelx mask/amplitude selector
+ */
+typedef enum
+{
+    DAC_LFSR_MASK_BIT11_1  = 0x00000000, //!< Mask bit[11:1] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_2  = 0x00001000, //!< Mask bit[11:2] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_3  = 0x00002000, //!< Mask bit[11:3] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_4  = 0x00003000, //!< Mask bit[11:4] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_5  = 0x00004000, //!< Mask bit[11:5] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_6  = 0x00005000, //!< Mask bit[11:6] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_7  = 0x00006000, //!< Mask bit[11:7] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_8  = 0x00007000, //!< Mask bit[11:8] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_9  = 0x00008000, //!< Mask bit[11:9] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11_10 = 0x00009000, //!< Mask bit[11:10] of LFSR for noise wave generation
+    DAC_LFSR_MASK_BIT11    = 0x0000A000, //!< Mask bit11 of LFSR for noise wave generation
+    DAC_LFSR_MASK_NONE     = 0x0000B000, //!< Mask none bit of LFSR for noise wave generation
+
+    DAC_TRIANGLE_AMPLITUDE_1    = 0x00000000, //!< Triangle amplitude equal to 1
+    DAC_TRIANGLE_AMPLITUDE_3    = 0x00001000, //!< Triangle amplitude equal to 3
+    DAC_TRIANGLE_AMPLITUDE_7    = 0x00002000, //!< Triangle amplitude equal to 7
+    DAC_TRIANGLE_AMPLITUDE_15   = 0x00003000, //!< Triangle amplitude equal to 15
+    DAC_TRIANGLE_AMPLITUDE_31   = 0x00004000, //!< Triangle amplitude equal to 31
+    DAC_TRIANGLE_AMPLITUDE_63   = 0x00005000, //!< Triangle amplitude equal to 63
+    DAC_TRIANGLE_AMPLITUDE_127  = 0x00006000, //!< Triangle amplitude equal to 127
+    DAC_TRIANGLE_AMPLITUDE_255  = 0x00007000, //!< Triangle amplitude equal to 255
+    DAC_TRIANGLE_AMPLITUDE_511  = 0x00008000, //!< Triangle amplitude equal to 511
+    DAC_TRIANGLE_AMPLITUDE_1023 = 0x00009000, //!< Triangle amplitude equal to 1023
+    DAC_TRIANGLE_AMPLITUDE_2047 = 0x0000A000, //!< Triangle amplitude equal to 2047
+    DAC_TRIANGLE_AMPLITUDE_4095 = 0x0000B000  //!< Triangle amplitude equal to 4095
+}DAC_MASK_AMPLITUDE_SEL_T;
+
+/**
+ * @brief    DAC output buffer
+ */
+typedef enum
+{
+    DAC_OUTPUT_BUFFER_ENBALE  = 0x00000000,
+    DAC_OUTPUT_BUFFER_DISABLE = 0x00000002
+}DAC_OUTPUT_BUFFER_T;
+
+/**
+ * @brief    DAC data align
+ */
+typedef enum
+{
+    DAC_ALIGN_12BIT_R = 0x00000000,
+    DAC_ALIGN_12BIT_L = 0x00000004,
+    DAC_ALIGN_8BIT_R  = 0x00000008
+}DAC_ALIGN_T;
+
+/**@} end of group DAC_Enumerations*/
+
+
+/** @addtogroup DAC_Structure Data Structure
+  @{
+*/
+
+/**
+ * @brief    DAC Config structure definition
+ */
+typedef struct
+{
+    DAC_TRIGGER_T               trigger;
+    DAC_OUTPUT_BUFFER_T         outputBuffer;
+    DAC_WAVE_GENERATION_T       waveGeneration;
+    DAC_MASK_AMPLITUDE_SEL_T    maskAmplitudeSelect;
+}DAC_ConfigStruct_T;
+
+/**@} end of group DAC_Structure*/
+
+
+/** @addtogroup DAC_Fuctions Fuctions
+  @{
+*/
+
+/** DAC Reset and Configuration */
+void DAC_Reset(void);
+void DAC_Config(uint32_t channel, DAC_ConfigStruct_T* configStruct);
+void DAC_ConfigStructInit(DAC_ConfigStruct_T* configStruct);
+void DAC_Enable(DAC_CHANNEL_T channel);
+void DAC_Disable(DAC_CHANNEL_T channel);
+
+/** DAC channel for DAM */
+void DAC_DMA_Enable(DAC_CHANNEL_T channel);
+void DAC_DMA_Disable(DAC_CHANNEL_T channel);
+
+/** DAC channel software trigger */
+void DAC_EnableSoftwareTrigger(DAC_CHANNEL_T channel);
+void DAC_DisableSoftwareTrigger(DAC_CHANNEL_T channel);
+void DAC_EnableDualSoftwareTrigger(void);
+void DAC_DisableDualSoftwareTrigger(void);
+
+/** DAC channel wave generation */
+void DAC_EnableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave);
+void DAC_DisableWaveGeneration(DAC_CHANNEL_T channel, DAC_WAVE_GENERATION_T wave);
+
+/** DAC set channel data */
+void DAC_ConfigChannel1Data(DAC_ALIGN_T align, uint16_t data);
+void DAC_ConfigChannel2Data(DAC_ALIGN_T align, uint16_t data);
+void DAC_ConfigDualChannelData(DAC_ALIGN_T align, uint16_t data2, uint16_t data1);
+
+/** DAC read data output value */
+uint16_t DAC_ReadDataOutputValue(DAC_CHANNEL_T channel);
+
+/**@} end of group DAC_Fuctions*/
+/**@} end of group DAC_Driver */
+/**@} end of group Peripherals_Library*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __APM32F10X_DAC_H */

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dbgmcu.h

+/*!
+ * @file        apm32f10x_dbgmcu.h
+ *
+ * @brief       This file contains all the functions prototypes for the DBUGMCU firmware library
+ *
+ * @version     V1.0.1
+ *
+ * @date        2021-03-23
+ *
+ */
+
+#ifndef __APM32F10X_DBGMCU_H
+#define __APM32F10X_DBGMCU_H
+
+#include "apm32f10x.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Peripherals_Library Standard Peripheral Library
+  @{
+*/
+
+/** @addtogroup DBGMCU_Driver DBGMCU Driver
+  @{
+*/
+
+/** @addtogroup DBGMCU_Enumerations Enumerations
+  @{
+*/
+
+enum
+{
+    DBGMCU_SLEEP                = ((uint32_t)0x00000001),
+    DBGMCU_STOP                 = ((uint32_t)0x00000002),
+    DBGMCU_STANDBY              = ((uint32_t)0x00000004),
+    DBGMCU_IWDT_STOP            = ((uint32_t)0x00000100),
+    DBGMCU_WWDT_STOP            = ((uint32_t)0x00000200),
+    DBGMCU_TMR1_STOP            = ((uint32_t)0x00000400),
+    DBGMCU_TMR2_STOP            = ((uint32_t)0x00000800),
+    DBGMCU_TMR3_STOP            = ((uint32_t)0x00001000),
+    DBGMCU_TMR4_STOP            = ((uint32_t)0x00002000),
+    DBGMCU_CAN1_STOP            = ((uint32_t)0x00004000),
+    DBGMCU_I2C1_SMBUS_TIMEOUT   = ((uint32_t)0x00008000),
+    DBGMCU_I2C2_SMBUS_TIMEOUT   = ((uint32_t)0x00010000),
+    DBGMCU_TMR8_STOP            = ((uint32_t)0x00020000),
+    DBGMCU_TMR5_STOP            = ((uint32_t)0x00040000),
+    DBGMCU_TMR6_STOP            = ((uint32_t)0x00080000),
+    DBGMCU_TMR7_STOP            = ((uint32_t)0x00100000),
+    DBGMCU_CAN2_STOP            = ((uint32_t)0x00200000),
+    DBGMCU_TMR15_STOP           = ((uint32_t)0x00400000),
+    DBGMCU_TMR16_STOP           = ((uint32_t)0x00800000),
+    DBGMCU_TMR17_STOP           = ((uint32_t)0x01000000),
+    DBGMCU_TMR12_STOP           = ((uint32_t)0x02000000),
+    DBGMCU_TMR13_STOP           = ((uint32_t)0x04000000),
+    DBGMCU_TMR14_STOP           = ((uint32_t)0x08000000),
+    DBGMCU_TMR9_STOP            = ((uint32_t)0x10000000),
+    DBGMCU_TMR10_STOP           = ((uint32_t)0x20000000),
+    DBGMCU_TMR11_STOP           = ((uint32_t)0x40000000),
+};
+
+/**@} end of group DBGMCU_Enumerations*/
+
+
+/** @addtogroup DBGMCU_Fuctions Fuctions
+  @{
+*/
+
+uint32_t DBGMCU_ReadDEVID(void);
+uint32_t DBGMCU_ReadREVID(void);
+void DBGMCU_Enable(uint32_t periph);
+void DBGMCU_Disable(uint32_t periph);
+
+/**@} end of group DBGMCU_Fuctions*/
+/**@} end of group DBGMCU_Driver */
+/**@} end of group Peripherals_Library*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __APM32F10X_DBGMCU_H */

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dma.h

+/*!
+ * @file       apm32f10x_dma.h
+ *
+ * @brief      This file contains all the functions prototypes for the DMA firmware library
+ *
+ * @version     V1.0.1
+ *
+ * @date        2021-03-23
+ *
+ */
+
+#ifndef __APM32F10X_DMA_H
+#define __APM32F10X_DMA_H
+
+#include "apm32f10x.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup Peripherals_Library Standard Peripheral Library
+  @{
+*/
+
+/** @addtogroup DMA_Driver DMA Driver
+  @{
+*/
+
+/** @addtogroup DMA_Enumerations Enumerations
+  @{
+*/
+
+/**
+ * @brief   DMA Transmission direction
+ */
+typedef enum
+{
+    DMA_DIR_PERIPHERAL_SRC,
+    DMA_DIR_PERIPHERAL_DST
+} DMA_DIR_T;
+
+/**
+ * @brief   DMA Peripheral address increment
+ */
+typedef enum
+{
+    DMA_PERIPHERAL_INC_DISABLE,
+    DMA_PERIPHERAL_INC_ENABLE
+} DMA_PERIPHERAL_INC_T;
+
+/**
+ * @brief   DMA Memory address increment
+ */
+typedef enum
+{
+    DMA_MEMORY_INC_DISABLE,
+    DMA_MEMORY_INC_ENABLE
+} DMA_MEMORY_INC_T;
+
+/**
+ * @brief   DMA Peripheral Data Size
+ */
+typedef enum
+{
+    DMA_PERIPHERAL_DATA_SIZE_BYTE,
+    DMA_PERIPHERAL_DATA_SIZE_HALFWORD,
+    DMA_PERIPHERAL_DATA_SIZE_WOED
+} DMA_PERIPHERAL_DATA_SIZE_T;
+
+/**
+ * @brief   DMA Memory Data Size
+ */
+typedef enum
+{
+    DMA_MEMORY_DATA_SIZE_BYTE,
+    DMA_MEMORY_DATA_SIZE_HALFWORD,
+    DMA_MEMORY_DATA_SIZE_WOED
+} DMA_MEMORY_DATA_SIZE_T;
+
+/**
+ * @brief   DMA Mode
+ */
+typedef enum
+{
+    DMA_MODE_NORMAL,
+    DMA_MODE_CIRCULAR
+} DMA_LOOP_MODE_T;
+
+/**
+ * @brief   DMA priority level
+ */
+typedef enum
+{
+    DMA_PRIORITY_LOW,
+    DMA_PRIORITY_MEDIUM,
+    DMA_PRIORITY_HIGH,
+    DMA_PRIORITY_VERYHIGH
+} DMA_PRIORITY_T;
+
+/**
+ * @brief   DMA Memory to Memory
+ */
+typedef enum
+{
+    DMA_M2MEN_DISABLE,
+    DMA_M2MEN_ENABLE
+} DMA_M2MEN_T;
+
+/**
+ * @brief   DMA interrupt
+ */
+typedef enum
+{
+    DMA_INT_TC   = 0x00000002,
+    DMA_INT_HT   = 0x00000004,
+    DMA_INT_TERR = 0x00000008
+} DMA_INT_T;
+
+/**
+ * @brief   DMA Flag
+ */
+typedef enum
+{
+    DMA1_FLAG_GINT1 = 0x00000001,
+    DMA1_FLAG_TC1   = 0x00000002,
+    DMA1_FLAG_HT1   = 0x00000004,
+    DMA1_FLAG_TERR1 = 0x00000008,
+    DMA1_FLAG_GINT2 = 0x00000010,
+    DMA1_FLAG_TC2   = 0x00000020,
+    DMA1_FLAG_HT2   = 0x00000040,
+    DMA1_FLAG_TERR2 = 0x00000080,
+    DMA1_FLAG_GINT3 = 0x00000100,
+    DMA1_FLAG_TC3   = 0x00000200,
+    DMA1_FLAG_HT3   = 0x00000400,
+    DMA1_FLAG_TERR3 = 0x00000800,
+    DMA1_FLAG_GINT4 = 0x00001000,
+    DMA1_FLAG_TC4   = 0x00002000,
+    DMA1_FLAG_HT4   = 0x00004000,
+    DMA1_FLAG_TERR4 = 0x00008000,
+    DMA1_FLAG_GINT5 = 0x00010000,
+    DMA1_FLAG_TC5   = 0x00020000,
+    DMA1_FLAG_HT5   = 0x00040000,
+    DMA1_FLAG_TERR5 = 0x00080000,
+    DMA1_FLAG_GINT6 = 0x00100000,
+    DMA1_FLAG_TC6   = 0x00200000,
+    DMA1_FLAG_HT6   = 0x00400000,
+    DMA1_FLAG_TERR6 = 0x00800000,
+    DMA1_FLAG_GINT7 = 0x01000000,
+    DMA1_FLAG_TC7   = 0x02000000,
+    DMA1_FLAG_HT7   = 0x04000000,
+    DMA1_FLAG_TERR7 = 0x08000000,
+
+    DMA2_FLAG_GINT1 = 0x10000001,
+    DMA2_FLAG_TC1   = 0x10000002,
+    DMA2_FLAG_HT1   = 0x10000004,
+    DMA2_FLAG_TERR1 = 0x10000008,
+    DMA2_FLAG_GINT2 = 0x10000010,
+    DMA2_FLAG_TC2   = 0x10000020,
+    DMA2_FLAG_HT2   = 0x10000040,
+    DMA2_FLAG_TERR2 = 0x10000080,
+    DMA2_FLAG_GINT3 = 0x10000100,
+    DMA2_FLAG_TC3   = 0x10000200,
+    DMA2_FLAG_HT3   = 0x10000400,
+    DMA2_FLAG_TERR3 = 0x10000800,
+    DMA2_FLAG_GINT4 = 0x10001000,
+    DMA2_FLAG_TC4   = 0x10002000,
+    DMA2_FLAG_HT4   = 0x10004000,
+    DMA2_FLAG_TERR4 = 0x10008000,
+    DMA2_FLAG_GINT5 = 0x10010000,
+    DMA2_FLAG_TC5   = 0x10020000,
+    DMA2_FLAG_HT5   = 0x10040000,
+    DMA2_FLAG_TERR5 = 0x10080000
+} DMA_FLAG_T;
+
+/**
+ * @brief   DMA Flag
+ */
+typedef enum
+{
+    DMA1_INT_FLAG_GINT1   = 0x00000001,
+    DMA1_INT_FLAG_TC1     = 0x00000002,
+    DMA1_INT_FLAG_HT1     = 0x00000004,
+    DMA1_INT_FLAG_TERR1   = 0x00000008,
+    DMA1_INT_FLAG_GINT2   = 0x00000010,
+    DMA1_INT_FLAG_TC2     = 0x00000020,
+    DMA1_INT_FLAG_HT2     = 0x00000040,
+    DMA1_INT_FLAG_TERR2   = 0x00000080,
+    DMA1_INT_FLAG_GINT3   = 0x00000100,
+    DMA1_INT_FLAG_TC3     = 0x00000200,
+    DMA1_INT_FLAG_HT3     = 0x00000400,
+    DMA1_INT_FLAG_TERR3   = 0x00000800,
+    DMA1_INT_FLAG_GINT4   = 0x00001000,
+    DMA1_INT_FLAG_TC4     = 0x00002000,
+    DMA1_INT_FLAG_HT4     = 0x00004000,
+    DMA1_INT_FLAG_TERR4   = 0x00008000,
+    DMA1_INT_FLAG_GINT5   = 0x00010000,
+    DMA1_INT_FLAG_TC5     = 0x00020000,
+    DMA1_INT_FLAG_HT5     = 0x00040000,
+    DMA1_INT_FLAG_TERR5   = 0x00080000,
+    DMA1_INT_FLAG_GINT6   = 0x00100000,
+    DMA1_INT_FLAG_TC6     = 0x00200000,
+    DMA1_INT_FLAG_HT6     = 0x00400000,
+    DMA1_INT_FLAG_TERR6   = 0x00800000,
+    DMA1_INT_FLAG_GINT7   = 0x01000000,
+    DMA1_INT_FLAG_TC7     = 0x02000000,
+    DMA1_INT_FLAG_HT7     = 0x04000000,
+    DMA1_INT_FLAG_TERR7   = 0x08000000,
+
+    DMA2_INT_FLAG_GINT1   = 0x10000001,
+    DMA2_INT_FLAG_TC1     = 0x10000002,
+    DMA2_INT_FLAG_HT1     = 0x10000004,
+    DMA2_INT_FLAG_TERR1   = 0x10000008,
+    DMA2_INT_FLAG_GINT2   = 0x10000010,
+    DMA2_INT_FLAG_TC2     = 0x10000020,
+    DMA2_INT_FLAG_HT2     = 0x10000040,
+    DMA2_INT_FLAG_TERR2   = 0x10000080,
+    DMA2_INT_FLAG_GINT3   = 0x10000100,
+    DMA2_INT_FLAG_TC3     = 0x10000200,
+    DMA2_INT_FLAG_HT3     = 0x10000400,
+    DMA2_INT_FLAG_TERR3   = 0x10000800,
+    DMA2_INT_FLAG_GINT4   = 0x10001000,
+    DMA2_INT_FLAG_TC4     = 0x10002000,
+    DMA2_INT_FLAG_HT4     = 0x10004000,
+    DMA2_INT_FLAG_TERR4   = 0x10008000,
+    DMA2_INT_FLAG_GINT5   = 0x10010000,
+    DMA2_INT_FLAG_TC5     = 0x10020000,
+    DMA2_INT_FLAG_HT5     = 0x10040000,
+    DMA2_INT_FLAG_TERR5   = 0x10080000
+} DMA_INT_FLAG_T;
+
+/**@} end of group DMA_Enumerations*/
+
+
+/** @addtogroup DMA_Structure Data Structure
+  @{
+*/
+
+/**
+ * @brief    DMA Config struct definition
+ */
+typedef struct
+{
+    uint32_t                   peripheralBaseAddr;
+    uint32_t                   memoryBaseAddr;
+    DMA_DIR_T                  dir;
+    uint32_t                   bufferSize;
+    DMA_PERIPHERAL_INC_T       peripheralInc;
+    DMA_MEMORY_INC_T           memoryInc;
+    DMA_PERIPHERAL_DATA_SIZE_T peripheralDataSize;
+    DMA_MEMORY_DATA_SIZE_T     memoryDataSize;
+    DMA_LOOP_MODE_T            loopMode;
+    DMA_PRIORITY_T             priority;
+    DMA_M2MEN_T                M2M;
+} DMA_Config_T;
+
+/**@} end of group DMA_Structure*/
+
+
+/** @addtogroup DMA_Fuctions Fuctions
+  @{
+*/
+
+/** Reset and configuration */
+void DMA_Reset(DMA_Channel_T *channel);
+void DMA_Config(DMA_Channel_T* channel, DMA_Config_T* dmaConfig);
+void DMA_ConfigStructInit( DMA_Config_T* dmaConfig);
+void DMA_Enable(DMA_Channel_T *channel);
+void DMA_Disable(DMA_Channel_T *channel);
+
+/** Data number */
+void DMA_ConfigDataNumber(DMA_Channel_T *channel, uint16_t dataNumber);
+uint16_t DMA_ReadDataNumber(DMA_Channel_T *channel);
+
+/** Interrupt and flag */
+void DMA_EnableInterrupt(DMA_Channel_T *channel, uint32_t interrupt);
+void DMA_DisableInterrupt(DMA_Channel_T *channel, uint32_t interrupt);
+uint8_t DMA_ReadStatusFlag(DMA_FLAG_T flag);
+void DMA_ClearStatusFlag(uint32_t flag);
+uint8_t DMA_ReadIntFlag(DMA_INT_FLAG_T flag);
+void DMA_ClearIntFlag(uint32_t flag);
+
+/**@} end of group DMA_Fuctions*/
+/**@} end of group DMA_Driver */
+/**@} end of group Peripherals_Library*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __APM32F10X_DMA_H */

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_dmc.h

+/*!
+ * @file        apm32f10x_dmc.h
+ *
+ * @brief       This file contains all the prototypes,enumeration and macros for the DMC peripheral
+ *
+ * @version     V1.0.1
+ *
+ * @date        2021-03-23
+ *
+ */
+#ifndef __APM32F10X_DMC_H
+#define __APM32F10X_DMC_H
+
+#include "apm32f10x.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Peripherals_Library Standard Peripheral Library
+  @{
+*/
+
+/** @addtogroup DMC_Driver DMC Driver
+  @{
+*/
+
+/** @addtogroup DMC_Enumerations Enumerations
+  @{
+*/
+
+
+/**
+ * @brief   Bank Address Width
+ */
+typedef enum
+{
+    DMC_BANK_WIDTH_1,
+    DMC_BANK_WIDTH_2
+}DMC_BANK_WIDTH_T;
+
+/**
+ * @brief   Row Address Width
+ */
+typedef enum
+{
+    DMC_ROW_WIDTH_11 = 0x0A,
+    DMC_ROW_WIDTH_12,
+    DMC_ROW_WIDTH_13,
+    DMC_ROW_WIDTH_14,
+    DMC_ROW_WIDTH_15,
+    DMC_ROW_WIDTH_16
+}DMC_ROW_WIDTH_T;
+
+/**
+ * @brief   Column Address Width
+ */
+typedef enum
+{
+    DMC_COL_WIDTH_8 = 0x07,
+    DMC_COL_WIDTH_9,
+    DMC_COL_WIDTH_10,
+    DMC_COL_WIDTH_11,
+    DMC_COL_WIDTH_12,
+    DMC_COL_WIDTH_13,
+    DMC_COL_WIDTH_14,
+    DMC_COL_WIDTH_15
+}DMC_COL_WIDTH_T;
+
+/**
+ * @brief   CAS Latency Select
+ */
+typedef enum
+{
+    DMC_CAS_LATENCY_1,
+    DMC_CAS_LATENCY_2,
+    DMC_CAS_LATENCY_3,
+    DMC_CAS_LATENCY_4
+}DMC_CAS_LATENCY_T;
+
+/**
+ * @brief   RAS Minimun Time Select
+ */
+typedef enum
+{
+    DMC_RAS_MINIMUM_1,
+    DMC_RAS_MINIMUM_2,
+    DMC_RAS_MINIMUM_3,
+    DMC_RAS_MINIMUM_4,
+    DMC_RAS_MINIMUM_5,
+    DMC_RAS_MINIMUM_6,
+    DMC_RAS_MINIMUM_7,
+    DMC_RAS_MINIMUM_8,
+    DMC_RAS_MINIMUM_9,
+    DMC_RAS_MINIMUM_10,
+    DMC_RAS_MINIMUM_11,
+    DMC_RAS_MINIMUM_12,
+    DMC_RAS_MINIMUM_13,
+    DMC_RAS_MINIMUM_14,
+    DMC_RAS_MINIMUM_15,
+    DMC_RAS_MINIMUM_16
+}DMC_RAS_MINIMUM_T;
+
+/**
+ * @brief   RAS To CAS Delay Time Select
+ */
+typedef enum
+{
+    DMC_DELAY_TIME_1,
+    DMC_DELAY_TIME_2,
+    DMC_DELAY_TIME_3,
+    DMC_DELAY_TIME_4,
+    DMC_DELAY_TIME_5,
+    DMC_DELAY_TIME_6,
+    DMC_DELAY_TIME_7,
+    DMC_DELAY_TIME_8
+}DMC_DELAY_TIME_T;
+
+/**
+ * @brief   Precharge Period Select
+ */
+typedef enum
+{
+    DMC_PRECHARGE_1,
+    DMC_PRECHARGE_2,
+    DMC_PRECHARGE_3,
+    DMC_PRECHARGE_4,
+    DMC_PRECHARGE_5,
+    DMC_PRECHARGE_6,
+    DMC_PRECHARGE_7,
+    DMC_PRECHARGE_8
+}DMC_PRECHARGE_T;
+
+/**
+ * @brief   Last Data Next Precharge For Write Time Select 
+ */
+typedef enum
+{
+    DMC_NEXT_PRECHARGE_1,
+    DMC_NEXT_PRECHARGE_2,
+    DMC_NEXT_PRECHARGE_3,
+    DMC_NEXT_PRECHARGE_4
+}DMC_NEXT_PRECHARGE_T;
+
+/**
+ * @brief   Auto-Refresh Period Select
+ */
+typedef enum
+{
+    DMC_AUTO_REFRESH_1,
+    DMC_AUTO_REFRESH_2,
+    DMC_AUTO_REFRESH_3,
+    DMC_AUTO_REFRESH_4,
+    DMC_AUTO_REFRESH_5,
+    DMC_AUTO_REFRESH_6,
+    DMC_AUTO_REFRESH_7,
+    DMC_AUTO_REFRESH_8,
+    DMC_AUTO_REFRESH_9,
+    DMC_AUTO_REFRESH_10,
+    DMC_AUTO_REFRESH_11,
+    DMC_AUTO_REFRESH_12,
+    DMC_AUTO_REFRESH_13,
+    DMC_AUTO_REFRESH_14,
+    DMC_AUTO_REFRESH_15,
+    DMC_AUTO_REFRESH_16,
+}DMC_AUTO_REFRESH_T;
+
+/**
+ * @brief   Active-to-active Command Period Select
+ */
+typedef enum
+{
+    DMC_ATA_CMD_1,
+    DMC_ATA_CMD_2,
+    DMC_ATA_CMD_3,
+    DMC_ATA_CMD_4,
+    DMC_ATA_CMD_5,
+    DMC_ATA_CMD_6,
+    DMC_ATA_CMD_7,
+    DMC_ATA_CMD_8,
+    DMC_ATA_CMD_9,
+    DMC_ATA_CMD_10,
+    DMC_ATA_CMD_11,
+    DMC_ATA_CMD_12,
+    DMC_ATA_CMD_13,
+    DMC_ATA_CMD_14,
+    DMC_ATA_CMD_15,
+    DMC_ATA_CMD_16,
+}DMC_ATA_CMD_T;
+
+/**
+ * @brief   Clock PHASE
+ */
+typedef enum
+{
+    DMC_CLK_PHASE_NORMAL,
+    DMC_CLK_PHASE_REVERSE
+}DMC_CLK_PHASE_T;
+
+/**
+ * @brief   DMC Memory Size
+ */
+typedef enum
+{
+    DMC_MEMORY_SIZE_0,
+    DMC_MEMORY_SIZE_64KB,
+    DMC_MEMORY_SIZE_128KB,
+    DMC_MEMORY_SIZE_256KB,
+    DMC_MEMORY_SIZE_512KB,
+    DMC_MEMORY_SIZE_1MB,
+    DMC_MEMORY_SIZE_2MB,
+    DMC_MEMORY_SIZE_4MB,
+    DMC_MEMORY_SIZE_8MB,
+    DMC_MEMORY_SIZE_16MB,
+    DMC_MEMORY_SIZE_32MB,
+    DMC_MEMORY_SIZE_64MB,
+    DMC_MEMORY_SIZE_128MB,
+    DMC_MEMORY_SIZE_256MB,
+}DMC_MEMORY_SIZE_T;
+
+/**
+ * @brief    Open Banks Of Number 
+ */
+typedef enum
+{
+    DMC_BANK_NUMBER_1,
+    DMC_BANK_NUMBER_2,
+    DMC_BANK_NUMBER_3,
+    DMC_BANK_NUMBER_4,
+    DMC_BANK_NUMBER_5,
+    DMC_BANK_NUMBER_6,
+    DMC_BANK_NUMBER_7,
+    DMC_BANK_NUMBER_8,
+    DMC_BANK_NUMBER_9,
+    DMC_BANK_NUMBER_10,
+    DMC_BANK_NUMBER_11,
+    DMC_BANK_NUMBER_12,
+    DMC_BANK_NUMBER_13,
+    DMC_BANK_NUMBER_14,
+    DMC_BANK_NUMBER_15,
+    DMC_BANK_NUMBER_16,
+}DMC_BANK_NUMBER_T;
+
+/**
+ * @brief   Full refresh type
+ */
+typedef enum
+{
+    DMC_REFRESH_ROW_ONE,        //!< Refresh one row
+    DMC_REFRESH_ROW_ALL,        //!< Refresh all row
+}DMC_REFRESH_T;
+
+/**
+ * @brief   Precharge type
+ */
+typedef enum
+{
+    DMC_PRECHARGE_IM,        //!< Immediate precharge
+    DMC_PRECHARGE_DELAY,     //!< Delayed precharge
+}DMC_PRECHARE_T;
+
+
+/**@} end of group DMC_Enumerations*/
+
+
+/** @addtogroup DMC_Structure Data Structure
+  @{
+*/
+
+/**
+ * @brief   Timing config definition
+ */
+typedef struct
+{
+    uint32_t    latencyCAS  : 2;       //!< DMC_CAS_LATENCY_T
+    uint32_t    tRAS        : 4;       //!< DMC_RAS_MINIMUM_T
+    uint32_t    tRCD        : 3;       //!< DMC_DELAY_TIME_T
+    uint32_t    tRP         : 3;       //!< DMC_PRECHARGE_T
+    uint32_t    tWR         : 2;       //!< DMC_NEXT_PRECHARGE_T
+    uint32_t    tARP        : 4;       //!< DMC_AUTO_REFRESH_T
+    uint32_t    tCMD        : 4;       //!< DMC_ATA_CMD_T
+    uint32_t    tXSR        : 9;       //!< auto-refresh commands, can be 0x000 to 0x1FF
+    uint16_t    tRFP        : 16;      //!< Refresh period, can be 0x0000 to 0xFFFF
+}DMC_TimingConfig_T;
+
+/**
+ * @brief   Config struct definition
+ */
+typedef struct
+{
+    DMC_MEMORY_SIZE_T       memorySize;    //!< Memory size(byte)
+    DMC_BANK_WIDTH_T        bankWidth;     //!< Number of bank bits
+    DMC_ROW_WIDTH_T         rowWidth;      //!< Number of row address bits
+    DMC_COL_WIDTH_T         colWidth;      //!< Number of col address bits
+    DMC_CLK_PHASE_T         clkPhase;      //!< Clock phase
+    DMC_TimingConfig_T      timing;        //!< Timing
+}DMC_Config_T;
+
+/**@} end of group DMC_Structure*/
+
+
+/** @addtogroup DMC_Fuctions Fuctions
+  @{
+*/
+
+ /** Enable / Disable */
+void DMC_Enable(void);
+void DMC_Disable(void);
+void DMC_EnableInit(void);
+
+/** Global config */
+void DMC_Config(DMC_Config_T *dmcConfig);
+void DMC_ConfigStructInit(DMC_Config_T *dmcConfig);
+
+/** Address */
+void DMC_ConfigBankWidth(DMC_BANK_WIDTH_T bankWidth);
+void DMC_ConfigAddrWidth(DMC_ROW_WIDTH_T rowWidth, DMC_COL_WIDTH_T colWidth);
+
+/** Timing */
+void DMC_ConfigTiming(DMC_TimingConfig_T *timingConfig);
+void DMC_ConfigTimingStructInit(DMC_TimingConfig_T *timingConfig);
+void DMC_ConfigStableTimePowerup(uint16_t stableTime);
+void DMC_ConfigAutoRefreshNumDuringInit(DMC_AUTO_REFRESH_T num);
+void DMC_ConfigRefreshPeriod(uint16_t period);
+
+/** Refresh mode */
+void DMC_EixtSlefRefreshMode(void);
+void DMC_EnterSlefRefreshMode(void);
+
+/** Config */
+void DMC_ConfigOpenBank(DMC_BANK_NUMBER_T num);
+void DMC_EnableUpdateMode(void);
+void DMC_EnterPowerdownMode(void);
+void DMC_ConfigFullRefreshBeforeSR(DMC_REFRESH_T refresh);
+void DMC_ConfigFullRefreshAfterSR(DMC_REFRESH_T refresh);
+void DMC_ConfigPrechargeType(DMC_PRECHARE_T precharge);
+void DMC_ConfigMemorySize(DMC_MEMORY_SIZE_T memorySize);
+void DMC_ConfigClockPhase(DMC_CLK_PHASE_T clkPhase);
+
+/** read flag */
+uint8_t DMC_ReadSelfRefreshStatus(void);
+
+/**@} end of group DMC_Fuctions*/
+/**@} end of group DMC_Driver*/
+/**@} end of group Peripherals_Library*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __APM32F10X_DMC_H */

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_eint.h

+/*!
+ * @file       apm32f10x_eint.h
+ *
+ * @brief      This file contains all the functions prototypes for the EINT firmware library
+ *
+ * @version    V1.0.1
+ *
+ * @date       2021-03-23
+ *
+ */
+
+#ifndef __APM32F10X_EINT_H
+#define __APM32F10X_EINT_H
+
+#include "apm32f10x.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup Peripherals_Library Standard Peripheral Library
+  @{
+*/
+
+/** @addtogroup EINT_Driver EINT Driver
+  @{
+*/
+
+/** @addtogroup EINT_Enumerations Enumerations
+  @{
+*/
+
+/**
+ * @brief    EINT mode enumeration
+ */
+typedef enum
+{
+    EINT_MODE_INTERRUPT = 0x00,
+    EINT_MODE_EVENT     = 0x04
+} EINT_MODE_T;
+
+/**
+ * @brief    EINT Trigger enumeration
+ */
+typedef enum
+{
+    EINT_TRIGGER_RISING         = 0x08,
+    EINT_TRIGGER_FALLING        = 0x0C,
+    EINT_TRIGGER_RISING_FALLING = 0x10
+} EINT_TRIGGER_T;
+
+typedef enum
+{
+    EINT_LINE_0   = 0x00001,  //!< External interrupt line 0
+    EINT_LINE_1   = 0x00002,  //!< External interrupt line 1
+    EINT_LINE_2   = 0x00004,  //!< External interrupt line 2
+    EINT_LINE_3   = 0x00008,  //!< External interrupt line 3
+    EINT_LINE_4   = 0x00010,  //!< External interrupt line 4
+    EINT_LINE_5   = 0x00020,  //!< External interrupt line 5
+    EINT_LINE_6   = 0x00040,  //!< External interrupt line 6
+    EINT_LINE_7   = 0x00080,  //!< External interrupt line 7
+    EINT_LINE_8   = 0x00100,  //!< External interrupt line 8
+    EINT_LINE_9   = 0x00200,  //!< External interrupt line 9
+    EINT_LINE_10  = 0x00400,  //!< External interrupt line 10
+    EINT_LINE_11  = 0x00800,  //!< External interrupt line 11
+    EINT_LINE_12  = 0x01000,  //!< External interrupt line 12
+    EINT_LINE_13  = 0x02000,  //!< External interrupt line 13
+    EINT_LINE_14  = 0x04000,  //!< External interrupt line 14
+    EINT_LINE_15  = 0x08000,  //!< External interrupt line 15
+    EINT_LINE_16  = 0x10000,  //!< External interrupt line 16 Connected to the PVD Output
+    EINT_LINE_17  = 0x20000,  //!< External interrupt line 17 Connected to the RTC Alarm event
+    EINT_LINE_18  = 0x40000,  //!< External interrupt line 18 Connected to the USB Device
+} EINT_LINE_T;
+
+/**@} end of group EINT_Enumerations*/
+
+
+/** @addtogroup EINT_Structure Data Structure
+  @{
+*/
+
+/**
+ * @brief    EINT Config structure definition
+ */
+typedef struct
+{
+    uint32_t        line;
+    EINT_MODE_T     mode;
+    EINT_TRIGGER_T  trigger;
+    uint8_t         lineCmd;
+} EINT_Config_T;
+
+/**@} end of group EINT_Structure*/
+
+
+/** @addtogroup EINT_Fuctions Fuctions
+  @{
+*/
+
+/** Reset and configuration */
+void EINT_Reset(void);
+void EINT_Config( EINT_Config_T* eintConfig);
+
+/** Interrupt and flag */
+void EINT_SelectSWInterrupt(uint32_t line);
+uint8_t EINT_ReadStatusFlag(EINT_LINE_T line);
+void EINT_ClearStatusFlag(uint32_t line);
+uint8_t EINT_ReadIntFlag(EINT_LINE_T line);
+void EINT_ClearIntFlag(uint32_t line);
+
+/**@} end of group EINT_Fuctions*/
+/**@} end of group EINT_Driver */
+/**@} end of group Peripherals_Library*/
+
+#ifdef __APM32F10X_cplusplus
+}
+#endif
+
+#endif /* __EINT_H */

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_emmc.h

+/*!
+ * @file       apm32f10x_emmc.h
+ *
+ * @brief      This file contains all the functions prototypes for the EMMC firmware library
+ *
+ * @version    V1.0.1
+ *
+ * @date       2021-03-23
+ *
+ */
+
+#ifndef __APM32F10X_EMMC_H
+#define __APM32F10X_EMMC_H
+
+#include "apm32f10x.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup Peripherals_Library Standard Peripheral Library
+  @{
+*/
+
+/** @addtogroup EMMC_Driver EMMC Driver
+  @{
+*/
+
+/** @addtogroup EMMC_Enumerations Enumerations
+  @{
+*/
+
+/**
+ * @brief EMMC NORSRAM_Bank
+ */
+typedef enum
+{
+    EMMC_BANK1_NORSRAM_1 = 0x00000000,
+    EMMC_BANK1_NORSRAM_2 = 0x00000002,
+    EMMC_BANK1_NORSRAM_3 = 0x00000004,
+    EMMC_BANK1_NORSRAM_4 = 0x00000006
+} EMMC_BANK1_NORSRAM_T;
+
+/**
+ * @brief EMMC NAND and PC Card Bank
+ */
+typedef enum
+{
+    EMMC_BANK2_NAND   = 0x00000010,
+    EMMC_BANK3_NAND   = 0x00000100,
+    EMMC_BANK4_PCCARD = 0x00001000
+} EMMC_BANK_NAND_T;
+
+/**
+ * @brief EMMC_Data_Address_Bus_Multiplexing
+ */
+typedef enum
+{
+    EMMC_DATA_ADDRESS_MUX_DISABLE = 0x00000000,
+    EMMC_DATA_ADDRESS_MUX_ENABLE  = 0x00000002
+} EMMC_DATA_ADDRESS_MUX_T;
+
+/**
+ * @brief EMMC_Memory_Type
+ */
+typedef enum
+{
+    EMMC_MEMORY_TYPE_SRAM  = 0x00000000,
+    EMMC_MEMORY_TYPE_PARAM = 0x00000004,
+    EMMC_MEMORY_TYPE_NOR   = 0x00000008
+} EMMC_MEMORY_TYPE_T;
+
+/**
+ * @brief EMMC_Data_Width
+ */
+typedef enum
+{
+    EMMC_MEMORY_DATA_WIDTH_8BIT  = 0x00000000,
+    EMMC_MEMORY_DATA_WIDTH_16BIT = 0x00000010
+} EMMC_MEMORY_DATA_WIDTH_T;
+
+/**
+ * @brief EMMC_Burst_Access_Mode
+ */
+typedef enum
+{
+    EMMC_BURST_ACCESS_MODE_DISABLE = 0x00000000,
+    EMMC_BURST_ACCESS_MODE_ENABLE  = 0x00000100
+} EMMC_BURST_ACCESS_MODE_T;
+
+/**
+ * @brief EMMC_AsynchronousWait
+ */
+typedef enum
+{
+    EMMC_ASYNCHRONOUS_WAIT_DISABLE = 0x00000000,
+    EMMC_ASYNCHRONOUS_WAIT_ENABLE  = 0x00008000
+} EMMC_ASYNCHRONOUS_WAIT_T;
+
+/**
+ * @brief EMMC_Wait_Signal_Polarity
+ */
+typedef enum
+{
+    EMMC_WAIT_SIGNAL_POLARITY_LOW  = 0x00000000,
+    EMMC_WAIT_SIGNAL_POLARITY_HIGH = 0x00000200
+} EMMC_WAIT_SIGNAL_POLARITY_T;
+
+/**
+ * @brief EMMC_Wrap_Mode
+ */
+typedef enum
+{
+    EMMC_WRAP_MODE_DISABLE = 0x00000000,
+    EMMC_WRAP_MODE_ENABLE  = 0x00000400
+} EMMC_WRAP_MODE_T;
+
+/**
+ * @brief EMMC_Wait_Timing
+ */
+typedef enum
+{
+    EMMC_WAIT_SIGNAL_ACTIVE_BEFORE_WAIT = 0x00000000,
+    EMMC_WAIT_SIGNAL_ACTIVE_DURING_WAIT = 0x00000800
+} EMMC_WAIT_SIGNAL_ACTIVE_T;
+
+/**
+ * @brief EMMC_Write_Operation
+ */
+typedef enum
+{
+    EMMC_WRITE_OPERATION_DISABLE = 0x00000000,
+    EMMC_WRITE_OPERATION_ENABLE  = 0x00001000
+} EMMC_WRITE_OPERATION_T;
+
+/**
+ * @brief EMMC_Wait_Signal
+ */
+typedef enum
+{
+    EMMC_WAITE_SIGNAL_DISABLE = 0x00000000,
+    EMMC_WAITE_SIGNAL_ENABLE  = 0x00002000
+} EMMC_WAITE_SIGNAL_T;
+
+/**
+ * @brief EMMC_Extended_Mode
+ */
+typedef enum
+{
+    EMMC_EXTENDEN_MODE_DISABLE = 0x00000000,
+    EMMC_EXTENDEN_MODE_ENABLE  = 0x00004000
+} EMMC_EXTENDEN_MODE_T;
+
+/**
+ * @brief EMMC_Write_Burst
+ */
+typedef enum
+{
+    EMMC_WRITE_BURST_DISABLE = 0x00000000,
+    EMMC_WRITE_BURST_ENABLE  = 0x00080000
+} EMMC_WRITE_BURST_T;
+
+/**
+ * @brief   EMMC_WAIT_FEATURE
+ */
+typedef enum
+{
+    EMMC_WAIT_FEATURE_DISABLE = 0x00000000,
+    EMMC_WAIT_FEATURE_ENABLE  = 0x00000002
+} EMMC_WAIT_FEATURE_T;
+
+/**
+ * @brief EMMC_ECC
+ */
+typedef enum
+{
+    EMMC_ECC_DISABLE = 0x00000000,
+    EMMC_ECC_ENABLE  = 0x00000040
+} EMMC_ECC_T;
+
+/**
+ * @brief EMMC_ECC_Page_Size
+ */
+typedef enum
+{
+    EMMC_ECC_PAGE_SIZE_BYTE_256  = 0x00000000,
+    EMMC_ECC_PAGE_SIZE_BYTE_512  = 0x00020000,
+    EMMC_ECC_PAGE_SIZE_BYTE_1024 = 0x00040000,
+    EMMC_ECC_PAGE_SIZE_BYTE_2048 = 0x00060000,
+    EMMC_ECC_PAGE_SIZE_BYTE_4096 = 0x00080000,
+    EMMC_ECC_PAGE_SIZE_BYTE_8192 = 0x000A0000
+} EMMC_ECC_PAGE_SIZE_BYTE_T;
+
+/**
+ * @brief EMMC_Access_Mode
+ */
+typedef enum
+{
+    EMMC_ACCESS_MODE_A = 0x00000000,
+    EMMC_ACCESS_MODE_B = 0x10000000,
+    EMMC_ACCESS_MODE_C = 0x20000000,
+    EMMC_ACCESS_MODE_D = 0x30000000
+} EMMC_ACCESS_MODE_T;
+
+/**
+ * @brief  EMMC_Interrupt_sources
+ */
+typedef enum
+{
+    EMMC_INT_EDGE_RISING  = 0x00000008,
+    EMMC_INT_LEVEL_HIGH   = 0x00000010,
+    EMMC_INT_EDGE_FALLING = 0x00000020
+} EMMC_INT_T;
+
+/**
+ * @brief  EMMC_Flags
+ */
+typedef enum
+{
+    EMMC_FLAG_EDGE_RISING  = 0x00000001,
+    EMMC_FLAG_LEVEL_HIGH   = 0x00000002,
+    EMMC_FLAG_EDGE_FALLING = 0x00000004,
+    EMMC_FLAG_FIFO_EMPTY   = 0x00000040
+} EMMC_FLAG_T;
+
+/**@} end of group EMMC_Enumerations*/
+
+
+/** @addtogroup EMMC_Structure Data Structure
+  @{
+*/
+
+/**
+ * @brief Timing parameters for NOR/SRAM Banks
+ */
+typedef struct
+{
+    uint32_t           addressSetupTime;
+    uint32_t           addressHodeTime;
+    uint32_t           dataSetupTime;
+    uint32_t           busTurnaroundTime;
+    uint32_t           clockDivision;
+    uint32_t           dataLatency;
+    EMMC_ACCESS_MODE_T accessMode;
+} EMMC_NORSRAMTimingConfig_T;
+
+/**
+ * @brief EMMC NOR/SRAM Config structure
+ */
+typedef struct
+{
+    EMMC_BANK1_NORSRAM_T        bank;
+    EMMC_DATA_ADDRESS_MUX_T     dataAddressMux;
+    EMMC_MEMORY_TYPE_T          memoryType;
+    EMMC_MEMORY_DATA_WIDTH_T    memoryDataWidth;
+    EMMC_BURST_ACCESS_MODE_T    burstAcceesMode;
+    EMMC_ASYNCHRONOUS_WAIT_T    asynchronousWait;
+    EMMC_WAIT_SIGNAL_POLARITY_T waitSignalPolarity;
+    EMMC_WRAP_MODE_T            wrapMode;
+    EMMC_WAIT_SIGNAL_ACTIVE_T   waitSignalActive;
+    EMMC_WRITE_OPERATION_T      writeOperation;
+    EMMC_WAITE_SIGNAL_T         waiteSignal;
+    EMMC_EXTENDEN_MODE_T        extendedMode;
+    EMMC_WRITE_BURST_T          writeBurst;
+    EMMC_NORSRAMTimingConfig_T*   readWriteTimingStruct;
+    EMMC_NORSRAMTimingConfig_T*   writeTimingStruct;
+} EMMC_NORSRAMConfig_T;
+
+/**
+ * @brief Timing parameters for NAND and PCCARD Banks
+ */
+typedef struct
+{
+    uint32_t setupTime;
+    uint32_t waitSetupTime;
+    uint32_t holdSetupTime;
+    uint32_t HiZSetupTime;
+} EMMC_NAND_PCCARDTimingConfig_T;
+
+/**
+ * @brief EMMC NAND Config structure
+ */
+typedef struct
+{
+    EMMC_BANK_NAND_T          bank;
+    EMMC_WAIT_FEATURE_T       waitFeature;
+    EMMC_MEMORY_DATA_WIDTH_T  memoryDataWidth;
+    EMMC_ECC_T                ECC;
+    EMMC_ECC_PAGE_SIZE_BYTE_T ECCPageSize;
+    uint32_t                  TCLRSetupTime;
+    uint32_t                  TARSetupTime;
+    EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
+    EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
+} EMMC_NANDConfig_T;
+
+/**
+ * @brief EMMC PCCARD Config structure
+ */
+typedef struct
+{
+    EMMC_WAIT_FEATURE_T waitFeature;
+    uint32_t            TCLRSetupTime;
+    uint32_t            TARSetupTime;
+    EMMC_NAND_PCCARDTimingConfig_T* commonSpaceTimingStruct;
+    EMMC_NAND_PCCARDTimingConfig_T* attributeSpaceTimingStruct;
+    EMMC_NAND_PCCARDTimingConfig_T* IOSpaceTimingStruct;
+} EMMC_PCCARDConfig_T;
+
+/**@} end of group EMMC_Structure*/
+
+/** @addtogroup EMMC_Fuctions Fuctions
+  @{
+*/
+
+/** EMMC reset */
+void EMMC_ResetNORSRAM(EMMC_BANK1_NORSRAM_T bank);
+void EMMC_ResetNAND(EMMC_BANK_NAND_T bank);
+void EMMC_ResetPCCard(void);
+
+/** EMMC Configuration */
+void EMMC_ConfigNORSRAM(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
+void EMMC_ConfigNAND(EMMC_NANDConfig_T* emmcNANDConfig);
+void EMMC_ConfigPCCard(EMMC_PCCARDConfig_T* emmcPCCardConfig);
+void EMMC_ConfigNORSRAMStructInit(EMMC_NORSRAMConfig_T* emmcNORSRAMConfig);
+void EMMC_ConfigNANDStructInit(EMMC_NANDConfig_T* emmcNANDConfig);
+void EMMC_ConfigPCCardStructInit(EMMC_PCCARDConfig_T* emmcPCCardConfig);
+
+/** EMMC bank control */
+void EMMC_EnableNORSRAM(EMMC_BANK1_NORSRAM_T bank);
+void EMMC_DisableNORSRAM(EMMC_BANK1_NORSRAM_T bank);
+void EMMC_EnableNAND(EMMC_BANK_NAND_T bank);
+void EMMC_DisableNAND(EMMC_BANK_NAND_T bank);
+void EMMC_EnablePCCARD(void);
+void EMMC_DisablePCCARD(void);
+void EMMC_EnableNANDECC(EMMC_BANK_NAND_T bank);
+void EMMC_DisableNANDECC(EMMC_BANK_NAND_T bank);
+uint32_t EMMC_ReadECC(EMMC_BANK_NAND_T bank);
+
+/** Interrupt and flag */
+void EMMC_EnableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt);
+void EMMC_DisableInterrupt(EMMC_BANK_NAND_T bank, uint32_t interrupt);
+uint8_t EMMC_ReadStatusFlag(EMMC_BANK_NAND_T bank, EMMC_FLAG_T flag);
+void EMMC_ClearStatusFlag(EMMC_BANK_NAND_T bank, uint32_t flag);
+uint8_t EMMC_ReadIntFlag(EMMC_BANK_NAND_T bank, EMMC_INT_T flag);
+void EMMC_ClearIntFlag(EMMC_BANK_NAND_T bank, uint32_t flag);
+
+/**@} end of group EMMC_Fuctions*/
+/**@} end of group EMMC_Driver */
+/**@} end of group Peripherals_Library*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __APM32F10X_EMMC_H */

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_fmc.h

+/*!
+ * @file       apm32f10x_fmc.h
+ *
+ * @brief      This file contains all the functions prototypes for the FMC firmware library
+ *
+ * @version    V1.0.1
+ *
+ * @date       2021-03-23
+ *
+ */
+
+#ifndef __APM32F10X_FMC_H
+#define __APM32F10X_FMC_H
+
+#include "apm32f10x.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup Peripherals_Library Standard Peripheral Library
+  @{
+*/
+
+/** @addtogroup FMC_Driver FMC Driver
+  @{
+*/
+
+/** @addtogroup FMC_Enumerations Enumerations
+  @{
+*/
+
+/**
+ * @brief Flash Latency
+ */
+typedef enum
+{
+    FMC_LATENCY_0,
+    FMC_LATENCY_1,
+    FMC_LATENCY_2
+} FMC_LATENCY_T;
+
+/**
+ * @brief FMC Status
+ */
+typedef enum
+{
+    FMC_STATUS_BUSY = 1,   //!< flash busy
+    FMC_STATUS_ERROR_PG,   //!< flash programming error
+    FMC_STATUS_ERROR_WRP,  //!< flash write protection error
+    FMC_STATUS_COMPLETE,   //!< flash operation complete
+    FMC_STATUS_TIMEOUT     //!< flash time out
+} FMC_STATUS_T;
+
+/**
+ * @brief Option Bytes IWatchdog
+ */
+typedef enum
+{
+    OB_IWDT_HARD   = 0x0000,
+    OB_IWDT_SOTF   = 0x0001
+} OB_IWDT_T;
+
+/**
+ * @brief Option Bytes nRST STOP
+ */
+typedef enum
+{
+    OB_STOP_RST    = 0x0000,
+    OB_STOP_NORST  = 0x0002
+} OB_STOP_T;
+
+/**
+ * @brief Option Bytes nRST STDBY
+ */
+typedef enum
+{
+    OB_STDBY_RST   = 0x0000,
+    OB_STDBY_NORST = 0x0004
+} OB_STDBY_T;
+
+/**
+ * @brief  FMC Interrupts
+ */
+typedef enum
+{
+    FMC_INT_ERR,
+    FMC_INT_OC
+} FMC_INT_T;
+
+/**
+ * @brief FMC flag
+ */
+typedef enum
+{
+    FMC_FLAG_BUSY = 0x00000001,  //!< FMC Busy flag
+    FMC_FLAG_OC   = 0x00000020,  //!< FMC End of Operation flag
+    FMC_FLAG_PE   = 0x00000004,  //!< FMC Program error flag
+    FMC_FLAG_WPE  = 0x00000010,  //!< FMC Write protected error flag
+    FMC_FLAG_OBE  = 0x10000001,  //!< FMC Option Byte error flag
+} FMC_FLAG_T;
+
+/**@} end of group FMC_Enumerations*/
+
+/** @addtogroup FMC_Macros Macros
+  @{
+*/
+
+/** Macros description */
+
+/** Values for APM32 Low and Medium density devices */
+#define FLASH_WRP_PAGE_0_3               ((uint32_t)BIT0) //!< Write protection of page 0 to 3
+#define FLASH_WRP_PAGE_4_7               ((uint32_t)BIT1) //!< Write protection of page 4 to 7
+#define FLASH_WRP_PAGE_8_11              ((uint32_t)BIT2) //!< Write protection of page 8 to 11
+#define FLASH_WRP_PAGE_12_15             ((uint32_t)BIT3) //!< Write protection of page 12 to 15
+#define FLASH_WRP_PAGE_16_19             ((uint32_t)BIT4) //!< Write protection of page 16 to 19
+#define FLASH_WRP_PAGE_20_23             ((uint32_t)BIT5) //!< Write protection of page 20 to 23
+#define FLASH_WRP_PAGE_24_27             ((uint32_t)BIT6) //!< Write protection of page 24 to 27
+#define FLASH_WRP_PAGE_28_31             ((uint32_t)BIT7) //!< Write protection of page 28 to 31
+
+/** Values for APM32 Medium-density devices */
+#define FLASH_WRP_PAGE_32_35             ((uint32_t)BIT8)  //!< Write protection of page 32 to 35
+#define FLASH_WRP_PAGE_36_39             ((uint32_t)BIT9)  //!< Write protection of page 36 to 39
+#define FLASH_WRP_PAGE_40_43             ((uint32_t)BIT10) //!< Write protection of page 40 to 43
+#define FLASH_WRP_PAGE_44_47             ((uint32_t)BIT11) //!< Write protection of page 44 to 47
+#define FLASH_WRP_PAGE_48_51             ((uint32_t)BIT12) //!< Write protection of page 48 to 51
+#define FLASH_WRP_PAGE_52_55             ((uint32_t)BIT13) //!< Write protection of page 52 to 55
+#define FLASH_WRP_PAGE_56_59             ((uint32_t)BIT14) //!< Write protection of page 56 to 59
+#define FLASH_WRP_PAGE_60_63             ((uint32_t)BIT15) //!< Write protection of page 60 to 63
+#define FLASH_WRP_PAGE_64_67             ((uint32_t)BIT16) //!< Write protection of page 64 to 67
+#define FLASH_WRP_PAGE_68_71             ((uint32_t)BIT17) //!< Write protection of page 68 to 71
+#define FLASH_WRP_PAGE_72_75             ((uint32_t)BIT18) //!< Write protection of page 72 to 75
+#define FLASH_WRP_PAGE_76_79             ((uint32_t)BIT19) //!< Write protection of page 76 to 79
+#define FLASH_WRP_PAGE_80_83             ((uint32_t)BIT20) //!< Write protection of page 80 to 83
+#define FLASH_WRP_PAGE_84_87             ((uint32_t)BIT21) //!< Write protection of page 84 to 87
+#define FLASH_WRP_PAGE_88_91             ((uint32_t)BIT22) //!< Write protection of page 88 to 91
+#define FLASH_WRP_PAGE_92_95             ((uint32_t)BIT23) //!< Write protection of page 92 to 95
+#define FLASH_WRP_PAGE_96_99             ((uint32_t)BIT24) //!< Write protection of page 96 to 99
+#define FLASH_WRP_PAGE_100_103           ((uint32_t)BIT25) //!< Write protection of page 100 to 103
+#define FLASH_WRP_PAGE_104_107           ((uint32_t)BIT26) //!< Write protection of page 104 to 107
+#define FLASH_WRP_PAGE_108_111           ((uint32_t)BIT27) //!< Write protection of page 108 to 111
+#define FLASH_WRP_PAGE_112_115           ((uint32_t)BIT28) //!< Write protection of page 112 to 115
+#define FLASH_WRP_PAGE_116_119           ((uint32_t)BIT29) //!< Write protection of page 116 to 119
+#define FLASH_WRP_PAGE_120_123           ((uint32_t)BIT30) //!< Write protection of page 120 to 123
+#define FLASH_WRP_PAGE_124_127           ((uint32_t)BIT31) //!< Write protection of page 124 to 127
+
+/** Values only for APM32 High-density devices */
+#define FLASH_WRP_PAGE_0_1             ((uint32_t)BIT0)  //!< Write protection of page 0 to 1
+#define FLASH_WRP_PAGE_2_3             ((uint32_t)BIT1)  //!< Write protection of page 2 to 3
+#define FLASH_WRP_PAGE_4_5             ((uint32_t)BIT2)  //!< Write protection of page 4 to 5
+#define FLASH_WRP_PAGE_6_7             ((uint32_t)BIT3)  //!< Write protection of page 6 to 7
+#define FLASH_WRP_PAGE_8_9             ((uint32_t)BIT4)  //!< Write protection of page 8 to 9
+#define FLASH_WRP_PAGE_10_11           ((uint32_t)BIT5)  //!< Write protection of page 10 to 11
+#define FLASH_WRP_PAGE_12_13           ((uint32_t)BIT6)  //!< Write protection of page 12 to 13
+#define FLASH_WRP_PAGE_14_15           ((uint32_t)BIT7)  //!< Write protection of page 14 to 15
+#define FLASH_WRP_PAGE_16_17           ((uint32_t)BIT8)  //!< Write protection of page 16 to 17
+#define FLASH_WRP_PAGE_18_19           ((uint32_t)BIT9)  //!< Write protection of page 18 to 19
+#define FLASH_WRP_PAGE_20_21           ((uint32_t)BIT10) //!< Write protection of page 20 to 21
+#define FLASH_WRP_PAGE_22_23           ((uint32_t)BIT11) //!< Write protection of page 22 to 23
+#define FLASH_WRP_PAGE_24_25           ((uint32_t)BIT12) //!< Write protection of page 24 to 25
+#define FLASH_WRP_PAGE_26_27           ((uint32_t)BIT13) //!< Write protection of page 26 to 27
+#define FLASH_WRP_PAGE_28_29           ((uint32_t)BIT14) //!< Write protection of page 28 to 29
+#define FLASH_WRP_PAGE_30_31           ((uint32_t)BIT15) //!< Write protection of page 30 to 31
+#define FLASH_WRP_PAGE_32_33           ((uint32_t)BIT16) //!< Write protection of page 32 to 33
+#define FLASH_WRP_PAGE_34_35           ((uint32_t)BIT17) //!< Write protection of page 34 to 35
+#define FLASH_WRP_PAGE_36_37           ((uint32_t)BIT18) //!< Write protection of page 36 to 37
+#define FLASH_WRP_PAGE_38_39           ((uint32_t)BIT19) //!< Write protection of page 38 to 39
+#define FLASH_WRP_PAGE_40_41           ((uint32_t)BIT20) //!< Write protection of page 40 to 41
+#define FLASH_WRP_PAGE_42_43           ((uint32_t)BIT21) //!< Write protection of page 42 to 43
+#define FLASH_WRP_PAGE_44_45           ((uint32_t)BIT22) //!< Write protection of page 44 to 45
+#define FLASH_WRP_PAGE_46_47           ((uint32_t)BIT23) //!< Write protection of page 46 to 47
+#define FLASH_WRP_PAGE_48_49           ((uint32_t)BIT24) //!< Write protection of page 48 to 49
+#define FLASH_WRP_PAGE_50_51           ((uint32_t)BIT25) //!< Write protection of page 50 to 51
+#define FLASH_WRP_PAGE_52_53           ((uint32_t)BIT26) //!< Write protection of page 52 to 53
+#define FLASH_WRP_PAGE_54_55           ((uint32_t)BIT27) //!< Write protection of page 54 to 55
+#define FLASH_WRP_PAGE_56_57           ((uint32_t)BIT28) //!< Write protection of page 56 to 57
+#define FLASH_WRP_PAGE_58_59           ((uint32_t)BIT29) //!< Write protection of page 58 to 59
+#define FLASH_WRP_PAGE_60_61           ((uint32_t)BIT30) //!< Write protection of page 60 to 61
+#define FLASH_WRP_PAGE_62_127          ((uint32_t)BIT31) //!< Write protection of page 62 to 127
+#define FMC_WRP_PAGE_ALL               ((uint32_t)0xFFFFFFFF) //!< Write protection of page all */
+
+/**@} end of group FMC_Macros*/
+
+/** @addtogroup FMC_Structure Data Structure
+  @{
+*/
+
+/**
+ * @brief   User Option byte config struct definition
+ */
+typedef struct
+{
+    OB_IWDT_T  iwdtSet;
+    OB_STOP_T  stopSet;
+    OB_STDBY_T stdbySet;
+} FMC_UserConfig_T;
+
+/**@} end of group FMC_Structure*/
+
+/** @addtogroup FMC_Fuctions Fuctions
+  @{
+*/
+
+/** Initialization and Configuration */
+void FMC_ConfigLatency(FMC_LATENCY_T latency);
+void FMC_EnableHalfCycleAccess(void);
+void FMC_DisableHalfCycleAccess(void);
+void FMC_EnablePrefetchBuffer(void);
+void FMC_DisablePrefetchBuffer(void);
+
+/** Lock management */
+void FMC_Unlock(void);
+void FMC_Lock(void);
+
+/** Erase management */
+FMC_STATUS_T FMC_ErasePage(uint32_t pageAddr);
+FMC_STATUS_T FMC_EraseAllPage(void);
+FMC_STATUS_T FMC_EraseOptionBytes(void);
+
+/** Read Write management */
+FMC_STATUS_T FMC_ProgramWord(uint32_t address, uint32_t data);
+FMC_STATUS_T FMC_ProgramHalfWord(uint32_t address, uint16_t data);
+FMC_STATUS_T FMC_ProgramOptionByteData(uint32_t address, uint8_t data);
+FMC_STATUS_T FMC_EnableWriteProtection(uint32_t page);
+FMC_STATUS_T FMC_EnableReadOutProtection(void);
+FMC_STATUS_T FMC_DisableReadOutProtection(void);
+FMC_STATUS_T FMC_ConfigUserOptionByte(FMC_UserConfig_T* userConfig);
+uint32_t FMC_ReadUserOptionByte(void);
+uint32_t FMC_ReadOptionByteWriteProtection(void);
+uint8_t FMC_GetReadProtectionStatus(void);
+uint8_t FMC_ReadPrefetchBufferStatus(void);
+
+/** Interrupts and flags */
+void FMC_EnableInterrupt(FMC_INT_T interrupt);
+void FMC_DisableInterrupt(FMC_INT_T interrupt);
+uint8_t FMC_ReadStatusFlag(FMC_FLAG_T flag);
+void FMC_ClearStatusFlag(FMC_FLAG_T flag);
+
+/** Status management */
+FMC_STATUS_T FMC_ReadStatus(void);
+FMC_STATUS_T FMC_WaitForLastOperation(uint32_t timeOut);
+
+/**@} end of group FMC_Fuctions*/
+/**@} end of group FMC_Driver*/
+/**@} end of group Peripherals_Library*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __APM32F10X_FMC_H */

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_gpio.h

+/*!
+ * @file       apm32f10x_gpio.h
+ *
+ * @brief      This file contains all the functions prototypes for the GPIO firmware library
+ *
+ * @version    V1.0.1
+ *
+ * @date       2021-03-23
+ *
+ */
+
+#ifndef __APM32F10X_GPIO_H
+#define __APM32F10X_GPIO_H
+
+#include "apm32f10x.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Peripherals_Library Standard Peripheral Library
+  @{
+*/
+
+/** @addtogroup GPIO_Driver GPIO Driver
+  @{
+*/
+
+/** @addtogroup GPIO_Enumerations Enumerations
+  @{
+*/
+
+/**
+ * @brief   GPIO Output Maximum frequency selection
+ */
+typedef enum
+{
+   GPIO_SPEED_10MHz = 1,
+   GPIO_SPEED_2MHz,
+   GPIO_SPEED_50MHz
+}GPIO_SPEED_T;
+
+/**
+ * @brief   Configuration Mode enumeration
+ */
+typedef enum
+{
+    GPIO_MODE_ANALOG      = 0x0,   //!< Analog mode
+    GPIO_MODE_IN_FLOATING = 0x04,  //!< Floating input
+    GPIO_MODE_IN_PD       = 0x28,  //!< Input with pull-down
+    GPIO_MODE_IN_PU       = 0x48,  //!< Input with pull-up
+    GPIO_MODE_OUT_PP      = 0x80,  //!< General purpose output push-pull
+    GPIO_MODE_OUT_OD      = 0x84,  //!< General purpose output Open-drain
+    GPIO_MODE_AF_PP       = 0x88,  //!< Alternate function output Push-pull
+    GPIO_MODE_AF_OD       = 0x8C,  //!< Alternate function output Open-drain
+}GPIO_MODE_T;
+
+/**
+ * @brief    Definition of the GPIO pins
+ */
+typedef enum
+{
+    GPIO_PIN_0   = ((uint16_t)BIT0),
+    GPIO_PIN_1   = ((uint16_t)BIT1),
+    GPIO_PIN_2   = ((uint16_t)BIT2),
+    GPIO_PIN_3   = ((uint16_t)BIT3),
+    GPIO_PIN_4   = ((uint16_t)BIT4),
+    GPIO_PIN_5   = ((uint16_t)BIT5),
+    GPIO_PIN_6   = ((uint16_t)BIT6),
+    GPIO_PIN_7   = ((uint16_t)BIT7),
+    GPIO_PIN_8   = ((uint16_t)BIT8),
+    GPIO_PIN_9   = ((uint16_t)BIT9),
+    GPIO_PIN_10  = ((uint16_t)BIT10),
+    GPIO_PIN_11  = ((uint16_t)BIT11),
+    GPIO_PIN_12  = ((uint16_t)BIT12),
+    GPIO_PIN_13  = ((uint16_t)BIT13),
+    GPIO_PIN_14  = ((uint16_t)BIT14),
+    GPIO_PIN_15  = ((uint16_t)BIT15),
+    GPIO_PIN_ALL = ((uint32_t)0XFFFF),
+} GPIO_PIN_T;
+
+/**
+ * @brief   GPIO remap type define
+ */
+typedef enum
+{
+   GPIO_NO_REMAP_SPI1          = 0x00000010,
+   GPIO_REMAP_SPI1             = 0x00000011,
+
+   GPIO_NO_REMAP_I2C1          = 0x00000110,
+   GPIO_REMAP_I2C1             = 0x00000111,
+
+   GPIO_NO_REMAP_USART1        = 0x00000210,
+   GPIO_REMAP_USART1           = 0x00000211,
+
+   GPIO_NO_REMAP_USART2        = 0x00000310,
+   GPIO_REMAP_USART2           = 0x00000311,
+
+   GPIO_NO_REMAP_USART3        = 0x00000430,
+   GPIO_PARTIAL_REMAP_USART3   = 0x00000431,
+   GPIO_FULL_REMAP_USART3      = 0x00000433,
+
+   GPIO_NO_REMAP_TMR1          = 0x00000630,
+   GPIO_PARTIAL_REMAP_TMR1     = 0x00000631,
+   GPIO_FULL_REMAP_TMR1        = 0x00000633,
+
+   GPIO_NO_REMAP_TMR2          = 0x00000830,
+   GPIO_PARTIAL_REMAP1_TMR2    = 0x00000831,
+   GPIO_PARTIAL_REMAP2_TMR2    = 0x00000832,
+   GPIO_FULL_REMAP_TMR2        = 0x00000833,
+
+   GPIO_NO_REMAP_TMR3          = 0x00000A30,
+   GPIO_PARTIAL_REMAP_TMR3     = 0x00000A32,
+   GPIO_FULL_REMAP_TMR3        = 0x00000A33,
+
+   GPIO_NO_REMAP_TMR4          = 0x00000C10,
+   GPIO_REMAP_TMR4             = 0x00000C11,
+
+   GPIO_NO_REMAP_CAN1          = 0x00000D30,
+   GPIO_REMAP1_CAN1            = 0x00000D32,
+   GPIO_REMAP2_CAN1            = 0x00000D33,
+
+   GPIO_NO_REMAP_PD01          = 0x00000F10,
+   GPIO_REMAP_PD01             = 0x00000F11,
+
+   GPIO_NO_REMAP_TMR5CH4_LSI   = 0x00001010,
+   GPIO_REMAP_TMR5CH4_LSI      = 0x00001011,
+
+   GPIO_NO_REMAP_ADC1_ETRGINJ  = 0x00001110,
+   GPIO_REMAP_ADC1_ETRGINJ     = 0x00001111,
+
+   GPIO_NO_REMAP_ADC1_ETRGREG  = 0x00001210,
+   GPIO_REMAP_ADC1_ETRGREG     = 0x00001211,
+
+   GPIO_NO_REMAP_ADC2_ETRGINJ  = 0x00001310,
+   GPIO_REMAP_ADC2_ETRGINJ     = 0x00001311,
+
+   GPIO_NO_REMAP_ADC2_ETRGREG  = 0x00001410,
+   GPIO_REMAP_ADC2_ETRGREG     = 0x00001411,
+
+   GPIO_NO_REMAP_CAN2          = 0x00001610,
+   GPIO_REMAP_CAN2             = 0x00001611,
+
+   GPIO_NO_REMAP_SWJ           = 0x00001870,
+   GPIO_REMAP_SWJ_NOJTRST      = 0x00001871,
+   GPIO_REMAP_SWJ_JTAGDISABLE  = 0x00001872,
+   GPIO_REMAP_SWJ_DISABLE      = 0x00001874,
+
+   GPIO_NO_REMAP_EMMC_NADV     = 0x00010A10,
+   GPIO_REMAP_EMMC_NADV        = 0x00010A11,
+}GPIO_REMAP_T;
+
+/**
+ * @brief   gpio port source define
+ */
+typedef enum
+{
+   GPIO_PORT_SOURCE_A,
+   GPIO_PORT_SOURCE_B,
+   GPIO_PORT_SOURCE_C,
+   GPIO_PORT_SOURCE_D,
+   GPIO_PORT_SOURCE_E,
+   GPIO_PORT_SOURCE_F,
+   GPIO_PORT_SOURCE_G,
+}GPIO_PORT_SOURCE_T;
+
+/**
+ * @brief   gpio pin source define
+ */
+typedef enum
+{
+   GPIO_PIN_SOURCE_0,
+   GPIO_PIN_SOURCE_1,
+   GPIO_PIN_SOURCE_2,
+   GPIO_PIN_SOURCE_3,
+   GPIO_PIN_SOURCE_4,
+   GPIO_PIN_SOURCE_5,
+   GPIO_PIN_SOURCE_6,
+   GPIO_PIN_SOURCE_7,
+   GPIO_PIN_SOURCE_8,
+   GPIO_PIN_SOURCE_9,
+   GPIO_PIN_SOURCE_10,
+   GPIO_PIN_SOURCE_11,
+   GPIO_PIN_SOURCE_12,
+   GPIO_PIN_SOURCE_13,
+   GPIO_PIN_SOURCE_14,
+   GPIO_PIN_SOURCE_15,
+}GPIO_PIN_SOURCE_T;
+
+/**@} end of group GPIO_Enumerations*/
+
+
+/** @addtogroup GPIO_Structure Data Structure
+  @{
+*/
+
+/**
+ * @brief   GPIO Config structure definition
+ */
+typedef struct
+{
+   uint16_t         pin;
+   GPIO_SPEED_T     speed;
+   GPIO_MODE_T      mode;
+}GPIO_Config_T;
+
+/**@} end of group GPIO_Structure*/
+
+/** @addtogroup GPIO_Fuctions Fuctions
+  @{
+*/
+
+/** Reset and common Configuration */
+void GPIO_Reset(GPIO_T* port);
+void GPIO_AFIOReset(void);
+void GPIO_Config(GPIO_T* port, GPIO_Config_T* gpioConfig);
+void GPIO_StructInit(GPIO_Config_T* gpioConfig);
+
+/** Read */
+uint8_t GPIO_ReadInputBit(GPIO_T* port, uint16_t pin);
+uint16_t GPIO_ReadInputPort(GPIO_T* port);
+uint8_t GPIO_ReadOutputBit(GPIO_T* port, uint16_t pin);
+uint16_t GPIO_ReadOutputPort(GPIO_T* port);
+
+/** Write */
+void GPIO_SetBits(GPIO_T* port, uint16_t pin);
+void GPIO_ResetBits(GPIO_T* port, uint16_t pin);
+void GPIO_WriteOutputPort(GPIO_T* port, uint16_t portValue);
+void GPIO_WriteBitValue(GPIO_T* port, uint16_t pin, uint8_t bitVal);
+
+/** GPIO Configuration */
+void GPIO_ConfigPinLock(GPIO_T* port, uint16_t pin);
+void GPIO_ConfigEventOutput(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource);
+void GPIO_EnableEventOutput(void);
+void GPIO_DisableEventOutput(void);
+void GPIO_ConfigPinRemap(GPIO_REMAP_T remap);
+void GPIO_ConfigEINTLine(GPIO_PORT_SOURCE_T portSource, GPIO_PIN_SOURCE_T pinSource);
+
+/**@} end of group GPIO_Fuctions*/
+/**@} end of group GPIO_Driver */
+/**@} end of group Peripherals_Library*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __APM32F10X_GPIO_H */

bsp/apm32/libraries/APM32F10x_Library/APM32F10x_StdPeriphDriver/inc/apm32f10x_rtc.h

+/*!
+ * @file       apm32f10x_rtc.h
+ *
+ * @brief      This file contains all the functions prototypes for the RTC firmware library
+ *
+ * @version    V1.0.1
+ *
+ * @date       2021-03-23
+ *
+ */
+
+#ifndef __APM32F10X_RTC_H
+#define __APM32F10X_RTC_H
+
+#include "apm32f10x.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup Peripherals_Library Standard Peripheral Library
+  @{
+*/
+
+/** @addtogroup RTC_Driver RTC Driver
+  @{
+*/
+
+/** @addtogroup RTC_Enumerations Enumerations
+  @{
+*/
+
+typedef enum
+{
+    RTC_FLAG_OC    = 0x0020,    //!< RTC Operation Complete flag
+    RTC_FLAG_RSYNC = 0x0008,    //!< Registers Synchronized flag
+    RTC_FLAG_OVR   = 0x0004,    //!< Overflow flag
+    RTC_FLAG_ALR   = 0x0002,    //!< Alarm flag
+    RTC_FLAG_SEC   = 0x0001     //!< Second flag
+} RTC_FLAG_T;
+
+typedef enum
+{
+    RTC_INT_OVR = 0x0004,       //!< Overflow interrupt
+    RTC_INT_ALR = 0x0002,       //!< Alarm interrupt
+    RTC_INT_SEC = 0x0001        //!< Second interrupt
+} RTC_INT_T;
+
+/**@} end of group RTC_Enumerations*/
+
+
+/** @addtogroup RTC_Fuctions Fuctions
+  @{
+*/
+
+/** Operation modes */
+void RTC_EnableConfigMode(void);
+void RTC_DisableConfigMode(void);
+
+/** Configuration */
+uint32_t RTC_ReadCounter(void);
+void RTC_ConfigCounter(uint32_t value);
+void RTC_ConfigPrescaler(uint32_t value);
+void RTC_ConfigAlarm(uint32_t value);
+uint32_t RTC_ReadDivider(void);
+void RTC_WaitForLastTask(void);
+void RTC_WaitForSynchor(void);
+
+/** Interrupts and flags */
+void RTC_EnableInterrupt(uint16_t interrupt);
+void RTC_DisableInterrupt(uint16_t interrupt);
+uint8_t RTC_ReadStatusFlag(RTC_FLAG_T flag);
+void RTC_ClearStatusFlag(uint16_t flag);
+uint8_t RTC_ReadIntFlag(RTC_INT_T flag);
+void RTC_ClearIntFlag(uint16_t flag);
+
+/**@} end of group RTC_Fuctions*/
+/**@} end of group RTC_Driver*/
+/**@} end of group Peripherals_Library*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __APM32F10X_RTC_H */