Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
逝缘~
rt-thread
提交
1f114ec2
R
rt-thread
项目概览
逝缘~
/
rt-thread
与 Fork 源项目一致
Fork自
RT-Thread / rt-thread
通知
1
Star
0
Fork
0
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
0
列表
看板
标记
里程碑
合并请求
0
DevOps
流水线
流水线任务
计划
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
R
rt-thread
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
0
Issue
0
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
DevOps
DevOps
流水线
流水线任务
计划
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
流水线任务
提交
Issue看板
体验新版 GitCode,发现更多精彩内容 >>
提交
1f114ec2
编写于
7月 10, 2019
作者:
E
Ernest
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
[bsp][stm32]upgrade menuconfig about crypto
上级
2aaa7d06
变更
9
隐藏空白更改
内联
并排
Showing
9 changed file
with
102 addition
and
48 deletion
+102
-48
bsp/stm32/libraries/HAL_Drivers/Kconfig.crypto
bsp/stm32/libraries/HAL_Drivers/Kconfig.crypto
+20
-0
bsp/stm32/libraries/HAL_Drivers/drv_crypto.c
bsp/stm32/libraries/HAL_Drivers/drv_crypto.c
+67
-46
bsp/stm32/stm32f091-st-nucleo/board/Kconfig
bsp/stm32/stm32f091-st-nucleo/board/Kconfig
+1
-0
bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig
bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig
+2
-1
bsp/stm32/stm32f407-atk-explorer/board/Kconfig
bsp/stm32/stm32f407-atk-explorer/board/Kconfig
+2
-0
bsp/stm32/stm32f767-atk-apollo/board/Kconfig
bsp/stm32/stm32f767-atk-apollo/board/Kconfig
+2
-0
bsp/stm32/stm32h743-atk-apollo/board/Kconfig
bsp/stm32/stm32h743-atk-apollo/board/Kconfig
+3
-0
bsp/stm32/stm32l475-atk-pandora/board/Kconfig
bsp/stm32/stm32l475-atk-pandora/board/Kconfig
+3
-1
bsp/stm32/stm32l496-ali-developer/board/Kconfig
bsp/stm32/stm32l496-ali-developer/board/Kconfig
+2
-0
未找到文件。
bsp/stm32/libraries/HAL_Drivers/Kconfig.crypto
0 → 100644
浏览文件 @
1f114ec2
config BSP_USING_CRC
bool "Enable CRC (CRC-32 0x04C11DB7 polynomial)"
select RT_USING_HWCRYPTO
select RT_HWCRYPTO_USING_CRC
default n
config BSP_USING_RNG
bool "Enable RNG"
select RT_USING_HWCRYPTO
select RT_HWCRYPTO_USING_RNG
depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \
SOC_SERIES_STM32H7)
default n
config BSP_USING_UDID
bool "Enable unique device identifier"
select RT_USING_HWCRYPTO
default n
bsp/stm32/libraries/HAL_Drivers/drv_crypto.c
浏览文件 @
1f114ec2
...
@@ -15,43 +15,22 @@
...
@@ -15,43 +15,22 @@
#include "drv_crypto.h"
#include "drv_crypto.h"
#include "board.h"
#include "board.h"
#if !defined(SOC_SERIES_STM32F0)&& !defined(SOC_SERIES_STM32F1) && !defined(SOC_SERIES_STM32F4) \
&& !defined(SOC_SERIES_STM32F7)&& !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32H7)
#error "Please define at least one SOC_SERIES"
#endif
#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
static
struct
hwcrypto_crc_cfg
crc_backup_cfg
;
#endif
struct
stm32_hwcrypto_device
struct
stm32_hwcrypto_device
{
{
struct
rt_hwcrypto_device
dev
;
struct
rt_hwcrypto_device
dev
;
struct
rt_mutex
mutex
;
struct
rt_mutex
mutex
;
};
};
#if defined(BSP_USING_CRC)
struct
hash_ctx_des
struct
hash_ctx_des
{
{
CRC_HandleTypeDef
contex
;
CRC_HandleTypeDef
contex
;
};
};
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
static
rt_uint32_t
_rng_rand
(
struct
hwcrypto_rng
*
ctx
)
static
struct
hwcrypto_crc_cfg
crc_backup_cfg
;
{
rt_uint32_t
gen_random
=
0
;
RNG_HandleTypeDef
*
HW_TypeDef
=
(
RNG_HandleTypeDef
*
)(
ctx
->
parent
.
contex
);
if
(
HAL_OK
==
HAL_RNG_GenerateRandomNumber
(
HW_TypeDef
,
&
gen_random
))
{
return
gen_random
;
}
return
0
;
}
#endif
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
static
int
reverse_bit
(
rt_uint32_t
n
)
static
int
reverse_bit
(
rt_uint32_t
n
)
{
{
n
=
((
n
>>
1
)
&
0x55555555
)
|
((
n
<<
1
)
&
0xaaaaaaaa
);
n
=
((
n
>>
1
)
&
0x55555555
)
|
((
n
<<
1
)
&
0xaaaaaaaa
);
...
@@ -68,12 +47,13 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
...
@@ -68,12 +47,13 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
{
{
rt_uint32_t
result
=
0
;
rt_uint32_t
result
=
0
;
struct
stm32_hwcrypto_device
*
stm32_hw_dev
=
(
struct
stm32_hwcrypto_device
*
)
ctx
->
parent
.
device
->
user_data
;
struct
stm32_hwcrypto_device
*
stm32_hw_dev
=
(
struct
stm32_hwcrypto_device
*
)
ctx
->
parent
.
device
->
user_data
;
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
CRC_HandleTypeDef
*
HW_TypeDef
=
(
CRC_HandleTypeDef
*
)(
ctx
->
parent
.
contex
);
CRC_HandleTypeDef
*
HW_TypeDef
=
(
CRC_HandleTypeDef
*
)(
ctx
->
parent
.
contex
);
#endif
#endif
rt_mutex_take
(
&
stm32_hw_dev
->
mutex
,
RT_WAITING_FOREVER
);
rt_mutex_take
(
&
stm32_hw_dev
->
mutex
,
RT_WAITING_FOREVER
);
#if defined(SOC_SERIES_STM32L4)
|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
if
(
0
!=
memcmp
(
&
crc_backup_cfg
,
&
ctx
->
crc_cfg
,
sizeof
(
struct
hwcrypto_crc_cfg
)))
if
(
0
!=
memcmp
(
&
crc_backup_cfg
,
&
ctx
->
crc_cfg
,
sizeof
(
struct
hwcrypto_crc_cfg
)))
{
{
if
(
HW_TypeDef
->
Init
.
DefaultPolynomialUse
==
DEFAULT_POLYNOMIAL_DISABLE
)
if
(
HW_TypeDef
->
Init
.
DefaultPolynomialUse
==
DEFAULT_POLYNOMIAL_DISABLE
)
...
@@ -122,8 +102,9 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
...
@@ -122,8 +102,9 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
{
{
goto
_exit
;
goto
_exit
;
}
}
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F1)
#else
if
(
length
%
4
!=
0
)
if
(
ctx
->
crc_cfg
.
flags
==
0
&&
ctx
->
crc_cfg
.
last_val
==
0xFFFFFFFF
&&
\
ctx
->
crc_cfg
.
xorout
==
0
&&
length
%
4
!=
0
)
{
{
goto
_exit
;
goto
_exit
;
}
}
...
@@ -132,7 +113,7 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
...
@@ -132,7 +113,7 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
result
=
HAL_CRC_Accumulate
(
ctx
->
parent
.
contex
,
(
rt_uint32_t
*
)
in
,
length
);
result
=
HAL_CRC_Accumulate
(
ctx
->
parent
.
contex
,
(
rt_uint32_t
*
)
in
,
length
);
#if defined(SOC_SERIES_STM32L4)
|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
if
(
HW_TypeDef
->
Init
.
OutputDataInversionMode
)
if
(
HW_TypeDef
->
Init
.
OutputDataInversionMode
)
{
{
ctx
->
crc_cfg
.
last_val
=
reverse_bit
(
result
);
ctx
->
crc_cfg
.
last_val
=
reverse_bit
(
result
);
...
@@ -143,32 +124,48 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
...
@@ -143,32 +124,48 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r
}
}
crc_backup_cfg
.
last_val
=
ctx
->
crc_cfg
.
last_val
;
crc_backup_cfg
.
last_val
=
ctx
->
crc_cfg
.
last_val
;
result
=
(
result
?
result
^
(
ctx
->
crc_cfg
.
xorout
)
:
result
);
result
=
(
result
?
result
^
(
ctx
->
crc_cfg
.
xorout
)
:
result
);
#endif
#endif
_exit:
_exit:
rt_mutex_release
(
&
stm32_hw_dev
->
mutex
);
rt_mutex_release
(
&
stm32_hw_dev
->
mutex
);
return
result
;
return
result
;
}
}
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
static
const
struct
hwcrypto_crc_ops
crc_ops
=
static
const
struct
hwcrypto_rng_ops
rng_ops
=
{
{
.
update
=
_
rng_rand
,
.
update
=
_
crc_update
,
};
};
#endif
#endif
/* BSP_USING_CRC */
static
const
struct
hwcrypto_crc_ops
crc_ops
=
#if defined(BSP_USING_RNG)
static
rt_uint32_t
_rng_rand
(
struct
hwcrypto_rng
*
ctx
)
{
{
.
update
=
_crc_update
,
rt_uint32_t
gen_random
=
0
;
RNG_HandleTypeDef
*
HW_TypeDef
=
(
RNG_HandleTypeDef
*
)(
ctx
->
parent
.
contex
);
if
(
HAL_OK
==
HAL_RNG_GenerateRandomNumber
(
HW_TypeDef
,
&
gen_random
))
{
return
gen_random
;
}
return
0
;
}
static
const
struct
hwcrypto_rng_ops
rng_ops
=
{
.
update
=
_rng_rand
,
};
};
#endif
/* BSP_USING_RNG */
static
rt_err_t
_crypto_create
(
struct
rt_hwcrypto_ctx
*
ctx
)
static
rt_err_t
_crypto_create
(
struct
rt_hwcrypto_ctx
*
ctx
)
{
{
rt_err_t
res
=
RT_EOK
;
rt_err_t
res
=
RT_EOK
;
switch
(
ctx
->
type
&
HWCRYPTO_MAIN_TYPE_MASK
)
switch
(
ctx
->
type
&
HWCRYPTO_MAIN_TYPE_MASK
)
{
{
#if defined(
SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7
)
#if defined(
BSP_USING_RNG
)
case
HWCRYPTO_TYPE_RNG
:
case
HWCRYPTO_TYPE_RNG
:
{
{
RNG_HandleTypeDef
*
hrng
=
rt_calloc
(
1
,
sizeof
(
RNG_HandleTypeDef
));
RNG_HandleTypeDef
*
hrng
=
rt_calloc
(
1
,
sizeof
(
RNG_HandleTypeDef
));
...
@@ -180,7 +177,9 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
...
@@ -180,7 +177,9 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
break
;
break
;
}
}
#endif
#endif
/* BSP_USING_RNG */
#if defined(BSP_USING_CRC)
case
HWCRYPTO_TYPE_CRC
:
case
HWCRYPTO_TYPE_CRC
:
{
{
CRC_HandleTypeDef
*
hcrc
=
rt_calloc
(
1
,
sizeof
(
CRC_HandleTypeDef
));
CRC_HandleTypeDef
*
hcrc
=
rt_calloc
(
1
,
sizeof
(
CRC_HandleTypeDef
));
...
@@ -191,13 +190,13 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
...
@@ -191,13 +190,13 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
}
}
hcrc
->
Instance
=
CRC
;
hcrc
->
Instance
=
CRC
;
#if defined(SOC_SERIES_STM32L4)
|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
#if defined(SOC_SERIES_STM32L4)|| defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
hcrc
->
Init
.
DefaultPolynomialUse
=
DEFAULT_POLYNOMIAL_ENABLE
;
hcrc
->
Init
.
DefaultPolynomialUse
=
DEFAULT_POLYNOMIAL_ENABLE
;
hcrc
->
Init
.
DefaultInitValueUse
=
DEFAULT_INIT_VALUE_DISABLE
;
hcrc
->
Init
.
DefaultInitValueUse
=
DEFAULT_INIT_VALUE_DISABLE
;
hcrc
->
Init
.
InputDataInversionMode
=
CRC_INPUTDATA_INVERSION_BYTE
;
hcrc
->
Init
.
InputDataInversionMode
=
CRC_INPUTDATA_INVERSION_BYTE
;
hcrc
->
Init
.
OutputDataInversionMode
=
CRC_OUTPUTDATA_INVERSION_ENABLE
;
hcrc
->
Init
.
OutputDataInversionMode
=
CRC_OUTPUTDATA_INVERSION_ENABLE
;
hcrc
->
InputDataFormat
=
CRC_INPUTDATA_FORMAT_BYTES
;
hcrc
->
InputDataFormat
=
CRC_INPUTDATA_FORMAT_BYTES
;
#el
if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F1)
#el
se
if
(
HAL_CRC_Init
(
hcrc
)
!=
HAL_OK
)
if
(
HAL_CRC_Init
(
hcrc
)
!=
HAL_OK
)
{
{
res
=
-
RT_ERROR
;
res
=
-
RT_ERROR
;
...
@@ -207,11 +206,11 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
...
@@ -207,11 +206,11 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
((
struct
hwcrypto_crc
*
)
ctx
)
->
ops
=
&
crc_ops
;
((
struct
hwcrypto_crc
*
)
ctx
)
->
ops
=
&
crc_ops
;
break
;
break
;
}
}
#endif
/* BSP_USING_CRC */
default:
default:
res
=
-
RT_ERROR
;
res
=
-
RT_ERROR
;
break
;
break
;
}
}
return
res
;
return
res
;
}
}
...
@@ -219,11 +218,16 @@ static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx)
...
@@ -219,11 +218,16 @@ static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx)
{
{
switch
(
ctx
->
type
&
HWCRYPTO_MAIN_TYPE_MASK
)
switch
(
ctx
->
type
&
HWCRYPTO_MAIN_TYPE_MASK
)
{
{
#if defined(BSP_USING_RNG)
case
HWCRYPTO_TYPE_RNG
:
case
HWCRYPTO_TYPE_RNG
:
break
;
break
;
#endif
/* BSP_USING_RNG */
#if defined(BSP_USING_CRC)
case
HWCRYPTO_TYPE_CRC
:
case
HWCRYPTO_TYPE_CRC
:
HAL_CRC_DeInit
((
CRC_HandleTypeDef
*
)(
ctx
->
contex
));
HAL_CRC_DeInit
((
CRC_HandleTypeDef
*
)(
ctx
->
contex
));
break
;
break
;
#endif
/* BSP_USING_CRC */
default:
default:
break
;
break
;
}
}
...
@@ -237,14 +241,23 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry
...
@@ -237,14 +241,23 @@ static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcry
switch
(
src
->
type
&
HWCRYPTO_MAIN_TYPE_MASK
)
switch
(
src
->
type
&
HWCRYPTO_MAIN_TYPE_MASK
)
{
{
#if defined(BSP_USING_RNG)
case
HWCRYPTO_TYPE_RNG
:
case
HWCRYPTO_TYPE_RNG
:
if
(
des
->
contex
&&
src
->
contex
)
{
rt_memcpy
(
des
->
contex
,
src
->
contex
,
sizeof
(
struct
hash_ctx_des
));
}
break
;
break
;
#endif
/* BSP_USING_RNG */
#if defined(BSP_USING_CRC)
case
HWCRYPTO_TYPE_CRC
:
case
HWCRYPTO_TYPE_CRC
:
if
(
des
->
contex
&&
src
->
contex
)
if
(
des
->
contex
&&
src
->
contex
)
{
{
rt_memcpy
(
des
->
contex
,
src
->
contex
,
sizeof
(
struct
hash_ctx_des
));
rt_memcpy
(
des
->
contex
,
src
->
contex
,
sizeof
(
struct
hash_ctx_des
));
}
}
break
;
break
;
#endif
/* BSP_USING_CRC */
default:
default:
res
=
-
RT_ERROR
;
res
=
-
RT_ERROR
;
break
;
break
;
...
@@ -256,11 +269,16 @@ static void _crypto_reset(struct rt_hwcrypto_ctx *ctx)
...
@@ -256,11 +269,16 @@ static void _crypto_reset(struct rt_hwcrypto_ctx *ctx)
{
{
switch
(
ctx
->
type
&
HWCRYPTO_MAIN_TYPE_MASK
)
switch
(
ctx
->
type
&
HWCRYPTO_MAIN_TYPE_MASK
)
{
{
#if defined(BSP_USING_RNG)
case
HWCRYPTO_TYPE_RNG
:
case
HWCRYPTO_TYPE_RNG
:
break
;
break
;
#endif
/* BSP_USING_RNG */
#if defined(BSP_USING_CRC)
case
HWCRYPTO_TYPE_CRC
:
case
HWCRYPTO_TYPE_CRC
:
__HAL_CRC_DR_RESET
((
CRC_HandleTypeDef
*
)
ctx
->
contex
);
__HAL_CRC_DR_RESET
((
CRC_HandleTypeDef
*
)
ctx
->
contex
);
break
;
break
;
#endif
/* BSP_USING_CRC */
default:
default:
break
;
break
;
}
}
...
@@ -277,9 +295,11 @@ static const struct rt_hwcrypto_ops _ops =
...
@@ -277,9 +295,11 @@ static const struct rt_hwcrypto_ops _ops =
int
stm32_hw_crypto_device_init
(
void
)
int
stm32_hw_crypto_device_init
(
void
)
{
{
static
struct
stm32_hwcrypto_device
_crypto_dev
;
static
struct
stm32_hwcrypto_device
_crypto_dev
;
rt_uint32_t
cpuid
[
3
]
=
{
0
};
rt_uint32_t
cpuid
[
3
]
=
{
0
};
_crypto_dev
.
dev
.
ops
=
&
_ops
;
#if defined(BSP_USING_UDID)
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F7)
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F7)
cpuid
[
0
]
=
HAL_GetUIDw0
();
cpuid
[
0
]
=
HAL_GetUIDw0
();
cpuid
[
1
]
=
HAL_GetUIDw1
();
cpuid
[
1
]
=
HAL_GetUIDw1
();
...
@@ -289,14 +309,15 @@ int stm32_hw_crypto_device_init(void)
...
@@ -289,14 +309,15 @@ int stm32_hw_crypto_device_init(void)
cpuid
[
0
]
=
HAL_GetREVID
();
cpuid
[
0
]
=
HAL_GetREVID
();
cpuid
[
1
]
=
HAL_GetDEVID
();
cpuid
[
1
]
=
HAL_GetDEVID
();
#endif
#endif
_crypto_dev
.
dev
.
ops
=
&
_ops
;
#endif
/* BSP_USING_UDID */
_crypto_dev
.
dev
.
id
=
0
;
_crypto_dev
.
dev
.
id
=
0
;
rt_memcpy
(
&
_crypto_dev
.
dev
.
id
,
cpuid
,
8
);
rt_memcpy
(
&
_crypto_dev
.
dev
.
id
,
cpuid
,
8
);
_crypto_dev
.
dev
.
user_data
=
&
_crypto_dev
;
_crypto_dev
.
dev
.
user_data
=
&
_crypto_dev
;
if
(
rt_hwcrypto_register
(
&
_crypto_dev
.
dev
,
if
(
rt_hwcrypto_register
(
&
_crypto_dev
.
dev
,
RT_HWCRYPTO_DEFAULT_NAME
)
!=
RT_EOK
)
RT_HWCRYPTO_DEFAULT_NAME
)
!=
RT_EOK
)
{
{
return
-
1
;
return
-
1
;
}
}
...
...
bsp/stm32/stm32f091-st-nucleo/board/Kconfig
浏览文件 @
1f114ec2
...
@@ -156,6 +156,7 @@ menu "On-chip Peripheral Drivers"
...
@@ -156,6 +156,7 @@ menu "On-chip Peripheral Drivers"
select RT_USING_WDT
select RT_USING_WDT
default n
default n
source "../libraries/HAL_Drivers/Kconfig.crypto"
endmenu
endmenu
menu "Board extended module Drivers"
menu "Board extended module Drivers"
...
...
bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig
浏览文件 @
1f114ec2
...
@@ -200,7 +200,8 @@ menu "On-chip Peripheral Drivers"
...
@@ -200,7 +200,8 @@ menu "On-chip Peripheral Drivers"
bool "Enable Watchdog Timer"
bool "Enable Watchdog Timer"
select RT_USING_WDT
select RT_USING_WDT
default n
default n
source "../libraries/HAL_Drivers/Kconfig.crypto"
endmenu
endmenu
menu "Board extended module Drivers"
menu "Board extended module Drivers"
...
...
bsp/stm32/stm32f407-atk-explorer/board/Kconfig
浏览文件 @
1f114ec2
...
@@ -294,6 +294,8 @@ menu "On-chip Peripheral Drivers"
...
@@ -294,6 +294,8 @@ menu "On-chip Peripheral Drivers"
select RT_USING_DFS
select RT_USING_DFS
default n
default n
source "../libraries/HAL_Drivers/Kconfig.crypto"
endmenu
endmenu
menu "Board extended module Drivers"
menu "Board extended module Drivers"
...
...
bsp/stm32/stm32f767-atk-apollo/board/Kconfig
浏览文件 @
1f114ec2
...
@@ -245,6 +245,8 @@ menu "On-chip Peripheral Drivers"
...
@@ -245,6 +245,8 @@ menu "On-chip Peripheral Drivers"
select RT_USING_DFS
select RT_USING_DFS
default n
default n
source "../libraries/HAL_Drivers/Kconfig.crypto"
endmenu
endmenu
menu "Board extended module Drivers"
menu "Board extended module Drivers"
...
...
bsp/stm32/stm32h743-atk-apollo/board/Kconfig
浏览文件 @
1f114ec2
...
@@ -67,6 +67,9 @@ menu "On-chip Peripheral Drivers"
...
@@ -67,6 +67,9 @@ menu "On-chip Peripheral Drivers"
bool "Enable Watchdog Timer"
bool "Enable Watchdog Timer"
select RT_USING_WDT
select RT_USING_WDT
default n
default n
source "../libraries/HAL_Drivers/Kconfig.crypto"
endmenu
endmenu
...
...
bsp/stm32/stm32l475-atk-pandora/board/Kconfig
浏览文件 @
1f114ec2
...
@@ -250,7 +250,9 @@ menu "On-chip Peripheral Drivers"
...
@@ -250,7 +250,9 @@ menu "On-chip Peripheral Drivers"
bool "Enable OTGFS as USB device"
bool "Enable OTGFS as USB device"
select RT_USING_USB_DEVICE
select RT_USING_USB_DEVICE
default n
default n
source "../libraries/HAL_Drivers/Kconfig.crypto"
endmenu
endmenu
menu "Board extended module Drivers"
menu "Board extended module Drivers"
...
...
bsp/stm32/stm32l496-ali-developer/board/Kconfig
浏览文件 @
1f114ec2
...
@@ -218,6 +218,8 @@ menu "On-chip Peripheral Drivers"
...
@@ -218,6 +218,8 @@ menu "On-chip Peripheral Drivers"
bool "Enable Watchdog Timer"
bool "Enable Watchdog Timer"
select RT_USING_WDT
select RT_USING_WDT
default n
default n
source "../libraries/HAL_Drivers/Kconfig.crypto"
endmenu
endmenu
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录