Merge branch 'VeriSilicon' into 'master'

up VeriSilicon projects

See merge request codechina/mirrors-settings!534

projects/VeriSilicon/imports.yml

@@ -7,47 +7,43 @@ group:
     description: ''
     mirrorRelease: false
     topic: ''
-- name: 'tensorflow'
+  - name: 'tflite-vx-delegate'
     description: ''
     mirrorRelease: false
     topic: ''
-- name: 'tflite-vx-delegate'
+  - name: 'acuitylite'
     description: ''
     mirrorRelease: false
     topic: ''
-- name: 'acuitylite'
+  - name: 'tvm'
     description: ''
     mirrorRelease: false
     topic: ''
-- name: 'tvm'
+  - name: 'mlcommons-inference'
     description: ''
     mirrorRelease: false
     topic: ''
-- name: 'mlcommons-inference'
+  - name: 'ffmpeg'
     description: ''
     mirrorRelease: false
     topic: ''
-- name: 'ffmpeg'
+  - name: 'acuity-models'
     description: ''
     mirrorRelease: false
     topic: ''
-- name: 'acuity-models'
+  - name: 'solios-x-device-plugin'
     description: ''
     mirrorRelease: false
     topic: ''
-- name: 'solios-x-device-plugin'
+  - name: 'vpe'
     description: ''
     mirrorRelease: false
     topic: ''
-- name: 'vpe'
+  - name: 'acuity-dataset'
     description: ''
     mirrorRelease: false
     topic: ''
-- name: 'acuity-dataset'
-    description: ''
-    mirrorRelease: false
-    topic: ''
-- name: 'caffe'
+  - name: 'caffe'
     description: ''
     mirrorRelease: false
     topic: ''
\ No newline at end of file