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提交 f665c5f3 编写于 作者: 饶先宏's avatar 饶先宏
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202106062137

上级 15a51de0
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Showing with 6829 addition and 5691 deletion
examples/counter/verilog/main_asm.v
浏览文件 @ f665c5f3
......@@ -261,16 +261,16 @@ assign wCounterin9 = wCounterin8;
hdl4se_binop #(1, 1, 1, BINOP_AND) binop_resetcounter(wButton0NotPressed, nwReset, nwResetCount);
/* 以下是译码器连接，十个计数器的输出对应到十个译码器 */
wire code0[7:0];
wire code1[7:0];
wire code2[7:0];
wire code3[7:0];
wire code4[7:0];
wire code5[7:0];
wire code6[7:0];
wire code7[7:0];
wire code8[7:0];
wire code9[7:0];
wire [7:0] code0;
wire [7:0] code1;
wire [7:0] code2;
wire [7:0] code3;
wire [7:0] code4;
wire [7:0] code5;
wire [7:0] code6;
wire [7:0] code7;
wire [7:0] code8;
wire [7:0] code9;
dec2seg dec0(bCount0, code0);
dec2seg dec1(bCount1, code1);
dec2seg dec2(bCount2, code2);
......
hdl4secell/verilog/hdl4secell.v
浏览文件 @ f665c5f3
......@@ -129,22 +129,8 @@ module hdl4se_mux16
#(parameter WIDTH=8)
(
input [3:0] sel,
input [WIDTH-1:0] in0,
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
input [WIDTH-1:0] in3,
input [WIDTH-1:0] in4,
input [WIDTH-1:0] in5,
input [WIDTH-1:0] in6,
input [WIDTH-1:0] in7,
input [WIDTH-1:0] in8,
input [WIDTH-1:0] in9,
input [WIDTH-1:0] in10,
input [WIDTH-1:0] in11,
input [WIDTH-1:0] in12,
input [WIDTH-1:0] in13,
input [WIDTH-1:0] in14,
input [WIDTH-1:0] in15,
input [WIDTH-1:0] in0,in1,in2, in3,in4,in5,in6,in7, in8,in9,
in10, in11, in12, in13, in14, in15,
output [WIDTH-1:0] data
);
reg [WIDTH-1:0] data;
......@@ -240,7 +226,7 @@ module hdl4se_bind2
wire [INPUTWIDTH0-1:0] wirein0;
wire [INPUTWIDTH1-1:0] wirein1;
wire [INPUTWIDTH0+INPUTWIDTH1-1:0] wireout;
assign wireout = {wirein1, wirein0};
/* assign wireout = {wirein1, wirein0}; */
endmodule
(*
......@@ -263,7 +249,7 @@ module hdl4se_bind3
wire [INPUTWIDTH1-1:0] wirein1;
wire [INPUTWIDTH2-1:0] wirein2;
wire [INPUTWIDTH0+INPUTWIDTH1+INPUTWIDTH2-1:0] wireout;
assign wireout = {wirein2, wirein1, wirein0};
/*assign wireout = {wirein2, wirein1, wirein0};*/
endmodule
(*
......@@ -289,7 +275,7 @@ module hdl4se_bind4
wire [WIDTH2-1:0] wirein2;
wire [WIDTH3-1:0] wirein3;
wire [WIDTH0+WIDTH1+WIDTH2+WIDTH3-1:0] wireout;
assign wireout = {wirein3, wirein2, wirein1, wirein0};
/*assign wireout = {wirein3, wirein2, wirein1, wirein0};*/
endmodule
(*
......
parser/CMakeLists.txt
浏览文件 @ f665c5f3
......@@ -18,9 +18,16 @@ add_library (verilog_parser STATIC
"verilog_root.h"
"verilog_scanner.c"
"verilog_keyword.h"
"verilog_constexpr.h"
"verilog_constexpr.c"
"verilog_port.h" "verilog_port.c" "verilog_vardecl.h" "verilog_vardecl.c")
"verilog_expr.h"
"verilog_expr.c"
"verilog_port.h"
"verilog_port.c"
"verilog_vardecl.h"
"verilog_vardecl.c"
"verilog_paraminst.h"
"verilog_paraminst.c"
"verilog_moduleinst.h"
"verilog_moduleinst.c")
include_directories("../../lcom/include")
include_directories("../hdl4secell/include")
......
parser/verilog_constexpr.c → parser/verilog_expr.c
浏览文件 @ f665c5f3
......@@ -30,9 +30,10 @@
*/
/*
* verilog_constexpr.c
* verilog_expr.c
修改记录：
202106021610: rxh, initial version
202106061502: rxh, modify from expr to expr
*/
#include "stdio.h"
#include "stdlib.h"
......@@ -42,10 +43,10 @@
#include "dlist.h"
#include "verilog_parsetree.h"
#define IMPLEMENT_GUID
#include "verilog_constexpr.h"
#include "verilog_expr.h"
#undef IMPLEMENT_GUID
typedef struct _sConstExpr {
typedef struct _sExpr {
OBJECT_HEADER
INTERFACE_DECLARE(IVerilogNode)
VERILOGNODE_VARDECLARE
......@@ -60,48 +61,49 @@ typedef struct _sConstExpr {
IVerilogNode** expr1;
IVerilogNode** expr2;
IDListVarPtr attributes;
}sConstExpr;
IDListVarPtr elementselect;
}sExpr;
OBJECT_FUNCDECLARE(constexpr, CLSID_VERILOG_CONSTEXPR);
OBJECT_FUNCDECLARE(expr, CLSID_VERILOG_EXPR);
VERILOGNODE_FUNCDECLARE(constexpr, CLSID_VERILOG_CONSTEXPR, sConstExpr);
DLIST_FUNCIMPL(constexpr, CLSID_VERILOG_CONSTEXPR, sConstExpr);
OBJECT_FUNCIMPL(constexpr, sConstExpr, CLSID_VERILOG_CONSTEXPR);
VERILOGNODE_FUNCDECLARE(expr, CLSID_VERILOG_EXPR, sExpr);
DLIST_FUNCIMPL(expr, CLSID_VERILOG_EXPR, sExpr);
OBJECT_FUNCIMPL(expr, sExpr, CLSID_VERILOG_EXPR);
QUERYINTERFACE_BEGIN(constexpr, CLSID_VERILOG_CONSTEXPR)
QUERYINTERFACE_ITEM(IID_VERILOG_NODE, IVerilogNode, sConstExpr)
QUERYINTERFACE_ITEM(IID_DLIST, IDList, sConstExpr)
QUERYINTERFACE_BEGIN(expr, CLSID_VERILOG_EXPR)
QUERYINTERFACE_ITEM(IID_VERILOG_NODE, IVerilogNode, sExpr)
QUERYINTERFACE_ITEM(IID_DLIST, IDList, sExpr)
QUERYINTERFACE_END
static const char *constexprModuleInfo()
static const char *exprModuleInfo()
{
return "1.0.0-20210602.1612 Constant Expression ";
return "1.1.0-20210606.1504 Expression ";
}
static int constexprCreate(const PARAMITEM * pParams, int paramcount, HOBJECT * pObject)
static int exprCreate(const PARAMITEM * pParams, int paramcount, HOBJECT * pObject)
{
sConstExpr * pobj;
pobj = (sConstExpr *)malloc(sizeof(sConstExpr));
sExpr * pobj;
pobj = (sExpr *)malloc(sizeof(sExpr));
if (pobj == NULL)
return -1;
memset(pobj, 0, sizeof(sConstExpr));
memset(pobj, 0, sizeof(sExpr));
*pObject = 0;
DLIST_VARINIT(pobj, constexpr);
VERILOGNODE_VARINIT(pobj, CLSID_VERILOG_CONSTEXPR);
INTERFACE_INIT(IVerilogNode, pobj, constexpr, verilognode);
DLIST_VARINIT(pobj, expr);
VERILOGNODE_VARINIT(pobj, CLSID_VERILOG_EXPR);
INTERFACE_INIT(IVerilogNode, pobj, expr, verilognode);
/*返回生成的对象*/
OBJECT_RETURN_GEN(constexpr, pobj, pObject, CLSID_VERILOG_CONSTEXPR);
OBJECT_RETURN_GEN(expr, pobj, pObject, CLSID_VERILOG_EXPR);
return EIID_OK;
}
static void constexprDestroy(HOBJECT object)
static void exprDestroy(HOBJECT object)
{
sConstExpr * pobj;
pobj = (sConstExpr *)objectThis(object);
sExpr * pobj;
pobj = (sExpr *)objectThis(object);
if (pobj->value)
free(pobj->value);
objectRelease(pobj->expr0);
......@@ -111,6 +113,8 @@ static void constexprDestroy(HOBJECT object)
objectRelease(pobj->range1);
dlistRemoveAll(pobj->attributes);
objectRelease(pobj->attributes);
dlistRemoveAll(pobj->elementselect);
objectRelease(pobj->elementselect);
free(pobj);
}
......@@ -122,50 +126,18 @@ static void constexprDestroy(HOBJECT object)
0 -- 对象是无效的
1 -- 对象是有效的
*/
static int constexprValid(HOBJECT object)
static int exprValid(HOBJECT object)
{
return 1;
}
static const char* operator_name[] =
{
"!", /*_L_NOT */
"~", /*_B_NOT */
"&", /*_B_AND */
"&~", /*_B_NAND */
"|", /*_B_OR */
"|~", /*_B_NOR */
"^", /*_B_XOR */
"^~", /*_B_EQU */
"+", /*_PLUS */
"-", /*_MINUS */
"*", /*_MUL */
"/", /*_DIV */
"%", /*_MOD */
"**", /*_POW */
"==", /*_L_EQ */
"!=", /*_L_NEQ */
"===", /*_C_EQ */
"!==", /*_C_NEQ */
"&&", /*_L_AND */
"||", /*_L_OR */
"<", /*_LT */
"<=", /*_LTE */
">", /*_GT */
">=", /*_GTE */
">>", /*_LSR */
"<<", /*_LSL */
">>>", /*_ASR */
"<<<", /*_ASL */
};
static int output_operator(FILE* pFile, int opt, int op)
{
fprintf(pFile, operator_name[op]);
}
static int output_attributes(FILE* pFile, int opt, sConstExpr* pobj)
static int output_attributes(FILE* pFile, int opt, sExpr* pobj)
{
if (dlistItemCount(pobj->attributes) > 0) {
fprintf(pFile, "(* ");
......@@ -175,31 +147,31 @@ static int output_attributes(FILE* pFile, int opt, sConstExpr* pobj)
return 0;
}
static int constexpr_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
static int expr_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
{
sConstExpr * pobj;
pobj = (sConstExpr *)objectThis(object);
sExpr * pobj;
pobj = (sExpr *)objectThis(object);
switch (pobj->exprtype) {
case CONSTEXPRTYPE_NUMBER:
case CONSTEXPRTYPE_STRING:
case EXPRTYPE_NUMBER:
case EXPRTYPE_STRING:
fprintf(pFile, pobj->value);
break;
case CONSTEXPRTYPE_PARAM:
case CONSTEXPRTYPE_LOCALPARAM:
case EXPRTYPE_PARAM:
case EXPRTYPE_LOCALPARAM:
fprintf(pFile, pobj->value);
break;
case CONSTEXPRTYPE_BINOP:
case EXPRTYPE_BINOP:
objectCall2(pobj->expr0, dump, pFile, opt);
output_operator(pFile, opt, pobj->op);
output_attributes(pFile, opt, pobj);
objectCall2(pobj->expr1, dump, pFile, opt);
break;
case CONSTEXPRTYPE_UNOP:
case EXPRTYPE_UNOP:
output_operator(pFile, opt, pobj->op);
output_attributes(pFile, opt, pobj);
objectCall2(pobj->expr0, dump, pFile, opt);
break;
case CONSTEXPRTYPE_IFOP:
case EXPRTYPE_IFOP:
objectCall2(pobj->expr0, dump, pFile, opt);
fprintf(pFile, "?");
output_attributes(pFile, opt, pobj);
......@@ -214,7 +186,7 @@ static int constexpr_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
return 0;
}
HOBJECT verilogparseCreateConstExpr(
HOBJECT verilogparseCreateExpr(
int exprtype,
const char* value,
HOBJECT range0,
......@@ -223,16 +195,17 @@ HOBJECT verilogparseCreateConstExpr(
HOBJECT expr0,
HOBJECT expr1,
HOBJECT expr2,
IDListVarPtr attributes
IDListVarPtr attributes,
IDListVarPtr elementselect
)
{
HOBJECT constexpr = NULL;
sConstExpr * pobj;
A_u_t_o_registor_constexpr();
objectCreate(CLSID_VERILOG_CONSTEXPR, NULL, 0, &constexpr);
if (constexpr == NULL)
HOBJECT expr = NULL;
sExpr * pobj;
A_u_t_o_registor_expr();
objectCreate(CLSID_VERILOG_EXPR, NULL, 0, &expr);
if (expr == NULL)
return NULL;
pobj = (sConstExpr *)objectThis(constexpr);
pobj = (sExpr *)objectThis(expr);
if (value != NULL)
pobj->value = strdup(value);
else
......@@ -240,6 +213,7 @@ HOBJECT verilogparseCreateConstExpr(
pobj->exprtype = exprtype;
pobj->op = op;
pobj->attributes = attributes;
pobj->elementselect = elementselect;
objectQueryInterface(expr0, IID_VERILOG_NODE, (void**)&pobj->expr0);
objectRelease(expr0);
objectQueryInterface(expr1, IID_VERILOG_NODE, (void**)&pobj->expr1);
......@@ -250,7 +224,7 @@ HOBJECT verilogparseCreateConstExpr(
objectRelease(range0);
objectQueryInterface(range1, IID_VERILOG_NODE, (void**)&pobj->range1);
objectRelease(range1);
return constexpr;
return expr;
}
parser/verilog_constexpr.h → parser/verilog_expr.h
浏览文件 @ f665c5f3
......@@ -30,13 +30,14 @@
*/
/*
* verilog_constexpr.h
* verilog_expr.h
修改记录：
202106021601: rxh, initial version
202106061459: rxh, modify from constexpr to expr
*/
#ifndef __VERILOG_CONSTEXPR_H
#define __VERILOG_CONSTEXPR_H
#ifndef __VERILOG_EXPR_H
#define __VERILOG_EXPR_H
#ifdef __cplusplus
extern "C" {
......@@ -46,18 +47,19 @@ extern "C" {
#include "guid.h"
DEFINE_GUID(CLSID_VERILOG_CONSTEXPR, 0xa74d1de6, 0x2c4d, 0x42a6, 0x91, 0xd4, 0x77, 0xf5, 0x62, 0x76, 0x7a, 0x1e);
DEFINE_GUID(CLSID_VERILOG_EXPR, 0xa74d1de6, 0x2c4d, 0x42a6, 0x91, 0xd4, 0x77, 0xf5, 0x62, 0x76, 0x7a, 0x1e);
HOBJECT verilogparseCreateConstExpr(
int exprtype,
const char * value,
HOBJECT range0,
HOBJECT range1,
int op,
HOBJECT expr0,
HOBJECT expr1,
HOBJECT expr2,
IDListVarPtr attributes
HOBJECT verilogparseCreateExpr(
int exprtype,
const char* value,
HOBJECT range0,
HOBJECT range1,
int op,
HOBJECT expr0,
HOBJECT expr1,
HOBJECT expr2,
IDListVarPtr attributes,
IDListVarPtr elementselect
);
#endif
......
parser/verilog_module.c
浏览文件 @ f665c5f3
......@@ -56,22 +56,24 @@ typedef struct _sVerilogModule {
IDListVar * attributes;
IDListVar * module_parameters;
IDListVar * module_ports;
IDListVar * net_declarations;
IDListVar * always_blocks;
IDListVar * reg_declarations;
IDListVar * continuous_assignments;
IDListVar * event_declarations;
IDListVar * module_instantiations;
IDListVar * initial_blocks;
IDListVar * always_blocks;
IDListVar * event_declarations;
IDListVar * function_declarations;
IDListVar * gate_instantiations;
IDListVar * genvar_declarations;
IDListVar * generate_blocks;
IDListVar * initial_blocks;
IDListVar * integer_declarations;
IDListVar * local_parameters;
IDListVar * module_instantiations;
IDListVar * parameter_overrides;
IDListVar * real_declarations;
IDListVar * realtime_declarations;
IDListVar * reg_declarations;
IDListVar * specify_blocks;
IDListVar * specparams;
IDListVar * task_declarations;
......@@ -159,9 +161,26 @@ static int verilogmodule_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
fprintf(pFile, "\n)\n");
}
fprintf(pFile, ";\n");
/*module items*/
#define dump_module_items(item) \
if (dlistItemCount(pModule->item) > 0) { \
verilog_dump_node_list(pModule->item, pFile, opt, ""); \
}
dump_module_items(net_declarations);
dump_module_items(reg_declarations);
dump_module_items(event_declarations);
dump_module_items(function_declarations);
dump_module_items(task_declarations);
dump_module_items(continuous_assignments);
dump_module_items(module_instantiations);
dump_module_items(initial_blocks);
dump_module_items(always_blocks);
fprintf(pFile, "endmodule\n");
return 0;
}
......@@ -185,122 +204,6 @@ HOBJECT verilogparseCreateModuleDeclaration(
pModule->module_parameters = parameters;
pModule->module_ports = ports;
/*
for(i = 0; i < constructs -> items; i++)
{
ast_module_item * construct = ast_list_get(constructs, i);
if(construct -> type == MOD_ITEM_PORT_DECLARATION && ports == NULL){
// Only accept ports declared this way iff the ports argument to
// this function is NULL, signifying the old style of port
// declaration.
ast_list_append(tr -> module_ports,
construct -> port_declaration);
}
else if(construct -> type == MOD_ITEM_GENERATED_INSTANTIATION){
ast_list_append(tr -> generate_blocks,
construct -> generated_instantiation);
}
else if(construct -> type == MOD_ITEM_PARAMETER_DECLARATION) {
ast_list_append(tr -> module_parameters,
construct -> parameter_declaration);
}
else if(construct -> type == MOD_ITEM_SPECIFY_BLOCK){
ast_list_append(tr -> specify_blocks,
construct -> specify_block);
}
else if(construct -> type == MOD_ITEM_SPECPARAM_DECLARATION){
ast_list_append(tr -> specparams,
construct -> specparam_declaration);
}
else if(construct -> type == MOD_ITEM_PARAMETER_OVERRIDE){
ast_list_append(tr -> parameter_overrides,
construct -> parameter_override);
}
else if(construct -> type == MOD_ITEM_CONTINOUS_ASSIGNMENT){
ast_list_append(tr -> continuous_assignments,
construct -> continuous_assignment);
}
else if(construct -> type == MOD_ITEM_GATE_INSTANTIATION){
ast_list_append(tr -> gate_instantiations,
construct -> gate_instantiation);
}
else if(construct -> type == MOD_ITEM_UDP_INSTANTIATION){
ast_list_append(tr -> udp_instantiations,
construct -> udp_instantiation);
}
else if(construct -> type == MOD_ITEM_MODULE_INSTANTIATION){
ast_list_append(tr -> module_instantiations,
construct -> module_instantiation);
}
else if(construct -> type == MOD_ITEM_INITIAL_CONSTRUCT){
ast_statement_block * toadd = ast_extract_statement_block(
BLOCK_SEQUENTIAL_INITIAL, construct -> initial_construct);
ast_list_append(tr -> initial_blocks ,toadd);
}
else if(construct -> type == MOD_ITEM_ALWAYS_CONSTRUCT){
ast_statement_block * toadd = ast_extract_statement_block(
BLOCK_SEQUENTIAL_ALWAYS, construct -> always_construct);
ast_list_append(tr -> always_blocks,toadd);
}
else if(construct -> type == MOD_ITEM_NET_DECLARATION){
tr -> net_declarations = ast_list_concat(
tr -> net_declarations,
ast_new_net_declaration(construct -> net_declaration));
}
else if(construct -> type == MOD_ITEM_REG_DECLARATION){
tr -> reg_declarations = ast_list_concat(
tr -> reg_declarations,
ast_new_reg_declaration(construct -> reg_declaration));
}
else if(construct -> type == MOD_ITEM_INTEGER_DECLARATION){
tr -> integer_declarations = ast_list_concat(
tr -> integer_declarations,
ast_new_var_declaration(construct -> integer_declaration));
}
else if(construct -> type == MOD_ITEM_REAL_DECLARATION){
tr -> real_declarations = ast_list_concat(
tr -> real_declarations,
ast_new_var_declaration(construct -> real_declaration));
}
else if(construct -> type == MOD_ITEM_TIME_DECLARATION){
tr -> time_declarations = ast_list_concat(
tr -> time_declarations,
ast_new_var_declaration(construct -> time_declaration));
}
else if(construct -> type == MOD_ITEM_REALTIME_DECLARATION){
tr -> realtime_declarations = ast_list_concat(
tr -> realtime_declarations,
ast_new_var_declaration(construct -> realtime_declaration));
}
else if(construct -> type == MOD_ITEM_EVENT_DECLARATION){
tr -> event_declarations = ast_list_concat(
tr -> event_declarations,
ast_new_var_declaration(construct -> event_declaration));
}
else if(construct -> type == MOD_ITEM_GENVAR_DECLARATION){
tr -> genvar_declarations = ast_list_concat(
tr -> genvar_declarations,
ast_new_var_declaration(construct -> genvar_declaration));
}
else if(construct -> type == MOD_ITEM_TASK_DECLARATION){
ast_list_append(tr -> task_declarations,
construct -> task_declaration);
}
else if(construct -> type == MOD_ITEM_FUNCTION_DECLARATION){
ast_list_append(tr -> function_declarations,
construct -> function_declaration);
}
else
{
printf("ERROR: Unsupported module construct type: %d\n",
construct -> type);
assert(0); // Fail out because this should *never* happen
}
}
return tr;
}*/
return module;
}
......@@ -316,6 +219,12 @@ int verilogparseAddModuleItems(HOBJECT object, IDListVarPtr itemlist, int type)
dlistConcat(pModule->net_declarations, itemlist);
return 0;
}
if (type == MODULE_ITEM_TYPE_MODULE_INSTANCE) {
if (pModule->module_instantiations == NULL)
pModule->module_instantiations = dlistCreate();
dlistConcat(pModule->module_instantiations, itemlist);
return 0;
}
return -2;
}
......
parser/verilog_module.h
浏览文件 @ f665c5f3
......@@ -57,6 +57,7 @@ HOBJECT verilogparseCreateModuleDeclaration(
enum MODULE_ITEM_TYPE {
MODULE_ITEM_TYPE_NET_DECLARATION,
MODULE_ITEM_TYPE_MODULE_INSTANCE,
};
int verilogparseAddModuleItems(HOBJECT object, IDListVarPtr itemlist, int type);
......
parser/verilog_moduleinst.c 0 → 100644
浏览文件 @ f665c5f3
/*
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
** derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY moduleinstESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* verilog_moduleinst.c
修改记录：
202106062114: rxh, initial version
*/
#include "stdio.h"
#include "stdlib.h"
#include "string.h"
#include "object.h"
#include "dlist.h"
#include "verilog_parsetree.h"
#define IMPLEMENT_GUID
#include "verilog_moduleinst.h"
#undef IMPLEMENT_GUID
typedef struct _sModuleInst {
OBJECT_HEADER
INTERFACE_DECLARE(IVerilogNode)
VERILOGNODE_VARDECLARE
DLIST_VARDECLARE
const char* instname;
int range_type;
HOBJECT range_msb;
HOBJECT range_lsb;
IDListVarPtr port_connections;
IDListVarPtr attributes;
const char* modulename;
IDListVarPtr parameter_value_assignment;
}sModuleInst;
OBJECT_FUNCDECLARE(moduleinst, CLSID_VERILOG_MODULEINST);
VERILOGNODE_FUNCDECLARE(moduleinst, CLSID_VERILOG_MODULEINST, sModuleInst);
DLIST_FUNCIMPL(moduleinst, CLSID_VERILOG_MODULEINST, sModuleInst);
OBJECT_FUNCIMPL(moduleinst, sModuleInst, CLSID_VERILOG_MODULEINST);
QUERYINTERFACE_BEGIN(moduleinst, CLSID_VERILOG_MODULEINST)
QUERYINTERFACE_ITEM(IID_VERILOG_NODE, IVerilogNode, sModuleInst)
QUERYINTERFACE_ITEM(IID_DLIST, IDList, sModuleInst)
QUERYINTERFACE_END
static const char *moduleinstModuleInfo()
{
return "1.0.0-20210606.2115 module instance ";
}
static int moduleinstCreate(const PARAMITEM * pParams, int paramcount, HOBJECT * pObject)
{
sModuleInst * pobj;
pobj = (sModuleInst *)malloc(sizeof(sModuleInst));
if (pobj == NULL)
return -1;
memset(pobj, 0, sizeof(sModuleInst));
*pObject = 0;
DLIST_VARINIT(pobj, moduleinst);
VERILOGNODE_VARINIT(pobj, CLSID_VERILOG_MODULEINST);
INTERFACE_INIT(IVerilogNode, pobj, moduleinst, verilognode);
/*返回生成的对象*/
OBJECT_RETURN_GEN(moduleinst, pobj, pObject, CLSID_VERILOG_MODULEINST);
return EIID_OK;
}
static void moduleinstDestroy(HOBJECT object)
{
sModuleInst * pobj;
pobj = (sModuleInst *)objectThis(object);
if (pobj->instname)
free(pobj->instname);
if (pobj->modulename)
free(pobj->modulename);
objectRelease(pobj->range_msb);
objectRelease(pobj->range_lsb);
dlistRemoveAll(pobj->attributes);
objectRelease(pobj->attributes);
dlistRemoveAll(pobj->port_connections);
objectRelease(pobj->port_connections);
dlistRemoveAll(pobj->parameter_value_assignment);
objectRelease(pobj->parameter_value_assignment);
free(pobj);
}
/*
功能：判断对象是否是一个有效对象
参数：
object -- 对象数据指针
返回值：
0 -- 对象是无效的
1 -- 对象是有效的
*/
static int moduleinstValid(HOBJECT object)
{
return 1;
}
static int output_attributes(FILE* pFile, int opt, sModuleInst* pobj)
{
if (dlistItemCount(pobj->attributes) > 0) {
fprintf(pFile, "(* ");
verilog_dump_node_list(pobj->attributes, pFile, opt, ", ");
fprintf(pFile, " *) ");
}
return 0;
}
static int moduleinst_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
{
sModuleInst * pobj;
pobj = (sModuleInst *)objectThis(object);
fprintf(pFile, " %s", pobj->modulename);
fprintf(pFile, " %s", pobj->instname);
fprintf(pFile, ";\n");
return 0;
}
HOBJECT verilogparseCreateModuleInstance(
const char* instname,
int range_type,
HOBJECT range_msb,
HOBJECT range_lsb,
IDListVarPtr port_connections
)
{
HOBJECT moduleinst = NULL;
sModuleInst * pobj;
A_u_t_o_registor_moduleinst();
objectCreate(CLSID_VERILOG_MODULEINST, NULL, 0, &moduleinst);
if (moduleinst == NULL)
return NULL;
pobj = (sModuleInst *)objectThis(moduleinst);
if (instname != NULL)
pobj->instname = strdup(instname);
objectQueryInterface(range_msb, IID_VERILOG_NODE, (void**)&pobj->range_msb);
objectRelease(range_msb);
objectQueryInterface(range_lsb, IID_VERILOG_NODE, (void**)&pobj->range_lsb);
objectRelease(range_lsb);
pobj->port_connections = port_connections;
return moduleinst;
}
;
int verilogparseSetModuleInstanceOption(
HOBJECT inst,
IDListVarPtr attributes,
const char* modulename,
IDListVarPtr parameter_value_assignment
) {
sModuleInst* pobj;
if (!objectIsClass(inst, CLSID_VERILOG_MODULEINST)) {
return -1;
}
pobj = (sModuleInst*)objectThis(inst);
pobj->attributes = attributes;
pobj->modulename = strdup(modulename);
pobj->parameter_value_assignment = parameter_value_assignment;
objectAddRef(attributes);
objectAddRef(parameter_value_assignment);
return 0;
}
\ No newline at end of file
parser/verilog_moduleinst.h 0 → 100644
浏览文件 @ f665c5f3
/*
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
** derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* verilog_moduleinst.h
修改记录：
202106062103: rxh, initial version
*/
#ifndef __VERILOG_MODULEINST_H
#define __VERILOG_MODULEINST_H
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
#include "guid.h"
DEFINE_GUID(CLSID_VERILOG_MODULEINST, 0xcbf438d3, 0x81d6, 0x4289, 0xb5, 0x89, 0xae, 0x11, 0x2e, 0x22, 0x97, 0x6d);
HOBJECT verilogparseCreateModuleInstance(
const char * instname,
int range_type,
HOBJECT range_msb,
HOBJECT range_lsb,
IDListVarPtr port_connections
);
int verilogparseSetModuleInstanceOption(
HOBJECT inst,
IDListVarPtr attributes,
const char * modulename,
IDListVarPtr parameter_value_assignment
);
#endif
#ifdef __cplusplus
}
#endif
#endif
parser/verilog_paraminst.c 0 → 100644
浏览文件 @ f665c5f3
/*
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
** derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY paraminstESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* verilog_paraminst.c
修改记录：
202106061905: rxh, initial version
*/
#include "stdio.h"
#include "stdlib.h"
#include "string.h"
#include "object.h"
#include "dlist.h"
#include "verilog_parsetree.h"
#define IMPLEMENT_GUID
#include "verilog_paraminst.h"
#undef IMPLEMENT_GUID
typedef struct _sParamInst {
OBJECT_HEADER
INTERFACE_DECLARE(IVerilogNode)
VERILOGNODE_VARDECLARE
DLIST_VARDECLARE
int index;
const char* name;
int exprcount;
IVerilogNode** expr0;
IVerilogNode** expr1;
IVerilogNode** expr2;
IDListVarPtr attributes;
}sParamInst;
OBJECT_FUNCDECLARE(paraminst, CLSID_VERILOG_PARAMINST);
VERILOGNODE_FUNCDECLARE(paraminst, CLSID_VERILOG_PARAMINST, sParamInst);
DLIST_FUNCIMPL(paraminst, CLSID_VERILOG_PARAMINST, sParamInst);
OBJECT_FUNCIMPL(paraminst, sParamInst, CLSID_VERILOG_PARAMINST);
QUERYINTERFACE_BEGIN(paraminst, CLSID_VERILOG_PARAMINST)
QUERYINTERFACE_ITEM(IID_VERILOG_NODE, IVerilogNode, sParamInst)
QUERYINTERFACE_ITEM(IID_DLIST, IDList, sParamInst)
QUERYINTERFACE_END
static const char *paraminstModuleInfo()
{
return "1.0.0-20210606.1905 param instance ";
}
static int paraminstCreate(const PARAMITEM * pParams, int paramcount, HOBJECT * pObject)
{
sParamInst * pobj;
pobj = (sParamInst *)malloc(sizeof(sParamInst));
if (pobj == NULL)
return -1;
memset(pobj, 0, sizeof(sParamInst));
*pObject = 0;
DLIST_VARINIT(pobj, paraminst);
VERILOGNODE_VARINIT(pobj, CLSID_VERILOG_PARAMINST);
INTERFACE_INIT(IVerilogNode, pobj, paraminst, verilognode);
/*返回生成的对象*/
OBJECT_RETURN_GEN(paraminst, pobj, pObject, CLSID_VERILOG_PARAMINST);
return EIID_OK;
}
static void paraminstDestroy(HOBJECT object)
{
sParamInst * pobj;
pobj = (sParamInst *)objectThis(object);
if (pobj->name)
free(pobj->name);
objectRelease(pobj->expr0);
objectRelease(pobj->expr1);
objectRelease(pobj->expr2);
dlistRemoveAll(pobj->attributes);
objectRelease(pobj->attributes);
free(pobj);
}
/*
功能：判断对象是否是一个有效对象
参数：
object -- 对象数据指针
返回值：
0 -- 对象是无效的
1 -- 对象是有效的
*/
static int paraminstValid(HOBJECT object)
{
return 1;
}
static int output_attributes(FILE* pFile, int opt, sParamInst* pobj)
{
if (dlistItemCount(pobj->attributes) > 0) {
fprintf(pFile, "(* ");
verilog_dump_node_list(pobj->attributes, pFile, opt, ", ");
fprintf(pFile, " *) ");
}
return 0;
}
static int paraminst_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
{
sParamInst * pobj;
pobj = (sParamInst *)objectThis(object);
return 0;
}
HOBJECT verilogparseCreateParamInstance(
const char* name,
int exprcount,
HOBJECT expr0,
HOBJECT expr1,
HOBJECT expr2,
IDListVarPtr attributes
)
{
HOBJECT paraminst = NULL;
sParamInst * pobj;
A_u_t_o_registor_paraminst();
objectCreate(CLSID_VERILOG_PARAMINST, NULL, 0, &paraminst);
if (paraminst == NULL)
return NULL;
pobj = (sParamInst *)objectThis(paraminst);
if (name != NULL)
pobj->name = strdup(name);
else
pobj->name = NULL;
pobj->index = -1;
pobj->exprcount = exprcount;
pobj->attributes = attributes;
objectQueryInterface(expr0, IID_VERILOG_NODE, (void**)&pobj->expr0);
objectRelease(expr0);
objectQueryInterface(expr1, IID_VERILOG_NODE, (void**)&pobj->expr1);
objectRelease(expr1);
objectQueryInterface(expr2, IID_VERILOG_NODE, (void**)&pobj->expr2);
objectRelease(expr2);
return paraminst;
}
int verilogparseSetParamInstanceIndex(
HOBJECT paraminst,
int index
) {
sParamInst* pobj;
if (!objectIsClass(paraminst, CLSID_VERILOG_PARAMINST)) {
return -1;
}
pobj = (sParamInst*)objectThis(paraminst);
pobj->index = index;
return 0;
}
\ No newline at end of file
parser/verilog_paraminst.h 0 → 100644
浏览文件 @ f665c5f3
/*
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
** derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* verilog_paraminst.h
修改记录：
202106061856: rxh, initial version
*/
#ifndef __VERILOG_PARAMINST_H
#define __VERILOG_PARAMINST_H
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
#include "guid.h"
DEFINE_GUID(CLSID_VERILOG_PARAMINST, 0xf3d79b55, 0xfd54, 0x40fd, 0x8d, 0xa0, 0x5d, 0xbb, 0x4b, 0x7c, 0xfb, 0x97);
HOBJECT verilogparseCreateParamInstance(
const char* name,
int exprcount,
HOBJECT expr0,
HOBJECT expr1,
HOBJECT expr2,
IDListVarPtr attributes
);
int verilogparseSetParamInstanceIndex(
HOBJECT paraminst,
int index
);
#endif
#ifdef __cplusplus
}
#endif
#endif
parser/verilog_parser.c
浏览文件 @ f665c5f3
此差异已折叠。
parser/verilog_parser.h
浏览文件 @ f665c5f3
......@@ -57,11 +57,13 @@ extern int yydebug;
#include "verilog_keyword.h"
#include "verilog_attrspec.h"
#include "verilog_parameter.h"
#include "verilog_constexpr.h"
#include "verilog_expr.h"
#include "verilog_port.h"
#include "verilog_vardecl.h"
#include "verilog_paraminst.h"
#include "verilog_moduleinst.h"
#line 65 "D:/gitwork/hdl4se/parser/verilog_parser.h"
#line 67 "D:/gitwork/hdl4se/parser/verilog_parser.h"
/* Token kinds. */
#ifndef YYTOKENTYPE
......@@ -265,14 +267,15 @@ extern int yydebug;
#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
union YYSTYPE
{
#line 92 "D:/gitwork/hdl4se/parser/verilog_parser.y"
#line 94 "D:/gitwork/hdl4se/parser/verilog_parser.y"
HOBJECT treenode;
HOBJECT obj;
struct _two_obj {
int type;
HOBJECT obj[2];
}two_obj;
struct _mul_obj {
int type;
int objcount;
HOBJECT obj[16];
}mul_obj;
struct _str_bind_obj {
const char * key;
HOBJECT obj;
......@@ -283,7 +286,7 @@ union YYSTYPE
int ival;
IDListVar* list;
#line 287 "D:/gitwork/hdl4se/parser/verilog_parser.h"
#line 290 "D:/gitwork/hdl4se/parser/verilog_parser.h"
};
typedef union YYSTYPE YYSTYPE;
......
parser/verilog_parser.y
浏览文件 @ f665c5f3
此差异已折叠。
parser/verilog_parsetree.h
浏览文件 @ f665c5f3
......@@ -103,20 +103,40 @@ enum VAR_TYPE {
VAR_TYPE_REG,
};
static const char* var_type_name[] = {
"",
"supply0",
"supply1",
"tri",
"triand",
"trior",
"tri0",
"tri1",
"uwire",
"wire",
"wand",
"wor",
"integer",
"time",
"reg",
};
enum VECT_OR_SCALAR {
VS_NONE,
VS_VECTORED,
VS_SCALARED,
};
enum constexprtype {
CONSTEXPRTYPE_NUMBER,
CONSTEXPRTYPE_PARAM,
CONSTEXPRTYPE_LOCALPARAM,
CONSTEXPRTYPE_STRING,
CONSTEXPRTYPE_UNOP,
CONSTEXPRTYPE_BINOP,
CONSTEXPRTYPE_IFOP,
enum exprtype {
EXPRTYPE_NUMBER,
EXPRTYPE_PARAM,
EXPRTYPE_LOCALPARAM,
EXPRTYPE_STRING,
EXPRTYPE_UNOP,
EXPRTYPE_BINOP,
EXPRTYPE_IFOP,
EXPRTYPE_IDENT,
EXPRTYPE_HIERARCHICAL_IDENT,
};
enum RANGE_TYPE {
......@@ -127,6 +147,13 @@ enum RANGE_TYPE {
RANGE_TYPE_STARTMINUSWIDTH,
};
typedef struct _ident_part {
const char* name;
int type;
HOBJECT msb;
HOBJECT lsb;
}ident_part;
enum PORT_DIRECT {
PORT_DIRECT_INPUT,
PORT_DIRECT_INOUT,
......@@ -135,6 +162,14 @@ enum PORT_DIRECT {
PORT_DIRECT_ASPRE,
};
static const char* port_direct_name[] = {
"input ",
"inout ",
"output ",
"", /* UNKOWN */
"error aspre not handled",
};
enum PARAM_TYPE {
PARAM_TYPE_PARAM,
PARAM_TYPE_LOCAL,
......@@ -180,6 +215,38 @@ enum OPERATOR {
OP_ASL,
};
static const char* operator_name[] =
{
"!", /*_L_NOT */
"~", /*_B_NOT */
"&", /*_B_AND */
"&~", /*_B_NAND */
"|", /*_B_OR */
"|~", /*_B_NOR */
"^", /*_B_XOR */
"^~", /*_B_EQU */
"+", /*_PLUS */
"-", /*_MINUS */
"*", /*_MUL */
"/", /*_DIV */
"%", /*_MOD */
"**", /*_POW */
"==", /*_L_EQ */
"!=", /*_L_NEQ */
"===", /*_C_EQ */
"!==", /*_C_NEQ */
"&&", /*_L_AND */
"||", /*_L_OR */
"<", /*_LT */
"<=", /*_LTE */
">", /*_GT */
">=", /*_GTE */
">>", /*_LSR */
"<<", /*_LSL */
">>>", /*_ASR */
"<<<", /*_ASL */
};
#endif
#ifdef __cplusplus
......
parser/verilog_port.c
浏览文件 @ f665c5f3
......@@ -125,34 +125,9 @@ static int portValid(HOBJECT object)
return 1;
}
static const char* port_direct_name[] = {
"input ",
"inout ",
"output ",
"" /* UNKOWN */
};
static const char* port_type_name[] = {
"",
"supply0",
"supply1",
"tri",
"triand",
"trior",
"tri0",
"tri1",
"uwire",
"wire",
"wand",
"wor",
"integer",
"time",
"reg",
};
static int output_port_type(FILE* pFile, int ptype)
{
fprintf(pFile, port_type_name[ptype]);
fprintf(pFile, var_type_name[ptype]);
}
static int output_range(FILE* pFile, int opt, int type, IVerilogNode **msb, IVerilogNode ** lsb)
......
parser/verilog_vardecl.c
浏览文件 @ f665c5f3
......@@ -56,7 +56,6 @@ typedef struct _sVarDecl {
IVerilogNode** assignexpr;
IDListVar* attributes;
IDListVar* dimensions;
int drive_strength;
int vectored_or_scalared;
int issigned;
int range_type;
......@@ -136,11 +135,47 @@ static int vardeclValid(HOBJECT object)
return 1;
}
static int output_range(FILE* pFile, int opt, int type, IVerilogNode** msb, IVerilogNode** lsb)
{
if (type == RANGE_TYPE_NONE)
return 0;
if (type == RANGE_TYPE_BITSELECT) {
fprintf(pFile, " [");
objectCall2(msb, dump, pFile, opt);
fprintf(pFile, "] ");
return 0;
}
fprintf(pFile, " [");
objectCall2(msb, dump, pFile, opt);
if (type == RANGE_TYPE_PARTSELECT)
fprintf(pFile, ":");
else if (type == RANGE_TYPE_STARTPLUSWIDTH)
fprintf(pFile, "+:");
else if (type == RANGE_TYPE_STARTMINUSWIDTH)
fprintf(pFile, "-:");
objectCall2(lsb, dump, pFile, opt);
fprintf(pFile, "] ");
return 0;
}
static int vardecl_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
{
sVarDecl * pobj;
pobj = (sVarDecl *)objectThis(object);
fprintf(pFile, "%s", pobj->name);
/*
attribute_instance_list net_type drive_strength_option vectored_or_scalared_option signed_option
range_option delay3_option list_of_net
*/
fprintf(pFile, " ");
if (dlistItemCount(pobj->attributes) > 0) {
fprintf(pFile, "(* ");
verilog_dump_node_list(pobj->attributes, pFile, opt, ", ");
fprintf(pFile, " *) ");
}
fprintf(pFile, var_type_name[pobj->type]);
output_range(pFile, opt, pobj->range_type, pobj->range_msb, pobj->range_lsb);
fprintf(pFile, " %s", pobj->name);
if (pobj->assignexpr != NULL) {
fprintf(pFile, " = ");
objectCall2(pobj->assignexpr, dump, pFile, opt);
......@@ -187,7 +222,6 @@ int verilogparseVarDeclSetDimensions(HOBJECT object, IDListVar* dimensions)
int verilogparseVarDeclSetOptions(HOBJECT object,
int type,
IDListVar* attributes,
int drive_strength,
int vectored_or_scalared,
int issigned,
int range_type,
......@@ -209,7 +243,6 @@ int verilogparseVarDeclSetOptions(HOBJECT object,
pobj = (sVarDecl*)objectThis(object);
pobj->attributes = attributes;
objectAddRef(pobj->attributes);
pobj->drive_strength = drive_strength;
pobj->type = type;
pobj->vectored_or_scalared = vectored_or_scalared;
pobj->issigned = issigned;
......
parser/verilog_vardecl.h
浏览文件 @ f665c5f3
......@@ -48,14 +48,12 @@ extern "C" {
DEFINE_GUID(CLSID_VERILOG_VARDECL, 0x71990979, 0xc02a, 0x44af, 0xa2, 0x49, 0xd7, 0x2, 0xec, 0x6d, 0x7a, 0x4d);
HOBJECT verilogparseCreateVarDecl(const char * name);
int verilogparseVarDeclSetAssignExpr(HOBJECT object, HOBJECT expr);
int verilogparseVarDeclSetDimensions(HOBJECT object, IDListVar * dimensions);
int verilogparseVarDeclSetOptions(HOBJECT object,
int type,
IDListVar* attributes,
int drive_strength,
int vectored_or_scalared,
int issigned,
int range_type,
......
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