202108250635

examples/hdl4se_riscv/hdl4se_riscv_sim/CMakeLists.txt

@@ -7,7 +7,7 @@ add_executable(riscv_sim
    "hdl4se_riscv_core.c"
    "riscv_sim_main.c"
    "main.c"
-   )
+    "hdl4se_riscv_core_v2.c" "hdl4se_riscv_ram8k.c")
 
 add_definitions(-D_CRT_SECURE_NO_WARNINGS)
   

examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv.h

@@ -46,6 +46,8 @@ extern "C" {
 #include "guid.h"
 
 DEFINE_GUID(CLSID_HDL4SE_RISCV_CORE, 0x638e8bc3, 0xb0e0, 0x41dc, 0x9e, 0xdd, 0xd3, 0x5a, 0x39, 0xfd, 0x80, 0x51);
+// {EE3409B2-6D04-42B3-A44D-7F2444DDC00D}
+DEFINE_GUID(CLSID_HDL4SE_RISCV_RAM, 0xee3409b2, 0x6d04, 0x42b3, 0xa4, 0x4d, 0x7f, 0x24, 0x44, 0xdd, 0xc0, 0xd);
 
 #endif
 

examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_ram8k.c

+/*
+** HDL4SE: 软件Verilog综合仿真平台
+** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
+** LCOM: 轻量级组件对象模型
+** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without
+** modification, are permitted provided that the following conditions are met:
+**
+** * Redistributions of source code must retain the above copyright notice,
+**   this list of conditions and the following disclaimer.
+** * Redistributions in binary form must reproduce the above copyright notice,
+**   this list of conditions and the following disclaimer in the documentation
+**   and/or other materials provided with the distribution.
+** * The name of the author may be used to endorse or promote products
+**   derived from this software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+** THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+* hdl4se_riscv_ram8k.c
+    202108250608: rxh, initial version
+*/
+
+#include "stdlib.h" 
+#include "stdio.h"
+#include "object.h"
+#include "dlist.h"
+#include "string.h"
+#include "stdarg.h"
+#include "bignumber.h"
+#include "hdl4secell.h"
+
+#define IMPLEMENT_GUID
+#include "hdl4se_riscv.h"
+#undef IMPLEMENT_GUID
+
+#ifdef WIN32
+#define DATADIR "d:/gitwork/hdl4se/examples/hdl4se_riscv/"
+#else
+#define DATADIR "/media/raoxianhong/_dde_data/gitwork/hdl4se/examples/hdl4se_riscv/"
+#endif
+
+
+#define riscv_ram_MODULE_VERSION_STRING "0.4.0-20210825.0610 RISCV RAM cell"
+#define riscv_ram_MODULE_CLSID CLSID_HDL4SE_RISCV_RAM
+
+#define M_ID(id) riscv_ram##id
+
+/* 
+    跟alter生成的端口一致 
+module ram8kb (
+    address,
+    byteena,
+    clock,
+    data,
+    wren,
+    q);
+
+    input	[10:0]  address;
+    input	[3:0]  byteena;
+    input	  clock;
+    input	[31:0]  data;
+    input	  wren;
+    output	[31:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+    tri1	[3:0]  byteena;
+    tri1	  clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+endmodule
+*/
+
+#define RAMSIZE  2048
+
+IDLIST
+    VID(address),
+    VID(byteena),
+    VID(clock),
+    VID(data),
+    VID(wren),
+    VID(q),
+    VID(lastaddr),
+END_IDLIST
+
+MODULE_DECLARE(riscv_ram)
+    unsigned int* ram;
+    unsigned int ramaddr;
+    unsigned int ramwrdata;
+    unsigned int ramwren;
+    unsigned int rambyteena;
+END_MODULE_DECLARE(riscv_ram)
+
+DEFINE_FUNC(riscv_ram_gen_q, "address, byteena, data, wren, lastaddr") {
+    unsigned int lastaddr;
+    lastaddr = vget(lastaddr);
+    if (lastaddr < RAMSIZE)
+        vput(q, pobj->ram[vget(lastaddr)]);
+    else
+        vput(q, 0xdeadbeef);
+} END_DEFINE_FUNC
+
+
+DEFINE_FUNC(riscv_ram_clktick, "") {
+    pobj->ramwren = vget(wren);
+    pobj->ramwrdata = vget(data);
+    pobj->rambyteena = vget(byteena);
+    pobj->ramaddr = vget(address);
+    vput(lastaddr, vget(address));
+} END_DEFINE_FUNC
+
+DEFINE_FUNC(riscv_ram_deinit, "") {
+    if (pobj->ram != NULL)
+        free(pobj->ram);
+} END_DEFINE_FUNC
+
+DEFINE_FUNC(riscv_ram_setup, "") {
+    if (pobj->ramwren) {
+        unsigned int mask =
+              (pobj->rambyteena & 1 ? 0x000000ff : 0)
+            | (pobj->rambyteena & 2 ? 0x0000ff00 : 0)
+            | (pobj->rambyteena & 4 ? 0x00ff0000 : 0)
+            | (pobj->rambyteena & 8 ? 0xff000000 : 0);
+        pobj->ram[pobj->ramaddr] =  (pobj->ram[pobj->ramaddr] & (~mask))
+                                    | (pobj->ramwrdata & mask);
+    }
+    pobj->ramwren = 0;
+} END_DEFINE_FUNC
+
+int loadExecImage(unsigned char* data, int maxlen)
+{
+    unsigned int addr;
+    FILE* pFile = fopen(DATADIR"test_code/test.cod", "rt");
+    if (pFile == NULL) {
+        printf("File %s can not open\n", DATADIR"test_code/test.bin");
+        exit(-1);
+    }
+    addr = 0;
+    while (!feof(pFile)) {
+        char line[256];
+        fgets(line, 256, pFile);
+        if (strlen(line) < 2)
+            break;
+        if (line[0] == '@') {
+            sscanf(line + 1, "%08x", &addr);
+        }
+        else {
+            int len;
+            if (addr >= maxlen - 16) {
+                printf("loadExecImage failed, address [%08x] overflow\n", addr);
+                exit(-5);
+            }
+            len = sscanf(line, "%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X",
+                data + addr + 0,
+                data + addr + 1,
+                data + addr + 2,
+                data + addr + 3,
+                data + addr + 4,
+                data + addr + 5,
+                data + addr + 6,
+                data + addr + 7,
+                data + addr + 8,
+                data + addr + 9,
+                data + addr + 10,
+                data + addr + 11,
+                data + addr + 12,
+                data + addr + 13,
+                data + addr + 14,
+                data + addr + 15
+            );
+            addr += len;
+        }
+    }
+    fclose(pFile);
+}
+
+MODULE_INIT(riscv_ram)
+    pobj->ram = malloc(RAMSIZE * 4);
+    loadExecImage(pobj->ram, RAMSIZE * 4);
+    pobj->ramwren = 0;
+    PORT_IN(clock, 1);
+    PORT_IN(wren, 1);
+    PORT_IN(address, 11);
+    PORT_IN(data, 32);
+    PORT_IN(byteena, 4);
+    GPORT_OUT(q, 32, riscv_ram_gen_q);
+    REG(lastaddr, 11);
+    CLKTICK_FUNC(riscv_ram_clktick);
+    SETUP_FUNC(riscv_ram_setup);
+    DEINIT_FUNC(riscv_ram_deinit);
+END_MODULE_INIT(riscv_ram)