202107191818 中间版本，还没有就绪

hdl4secell/src/hdl4se_general.c

@@ -182,6 +182,8 @@ unsigned int hdl4se_module_GetVarUint32(sGeneralModule* pobj, int varindex)
 int hdl4se_module_GetVarInt32(sGeneralModule* pobj, int varindex) 
 { 
 	func_UpdateVariableData(pobj, varindex);
+	if (pobj->variables.array[varindex] == NULL)
+		return 0;
 	return objectCall0(((ModuleVariable*)pobj->variables.array[varindex])->data, ReadInt32); 
 } 
 
@@ -430,6 +432,8 @@ int hdl4se_module_ClkTick(sGeneralModule * pobj)
 		pobj->clktick_func(pobj->func_param); 
 	for (i = 0; i < pobj->variables.itemcount; i++) {
 		ModuleVariable * var = (ModuleVariable *)pobj->variables.array[i]; 
+		if (var == NULL)
+			continue;
 		if (var->type == VTYPE_REG) {
 			if (var->genfunc != NULL) {
 				var->genfunc(pobj->func_param);
@@ -449,7 +453,9 @@ int hdl4se_module_Setup(sGeneralModule * pobj)
 	if (pobj->setup_func != 0) 
 		pobj->setup_func(pobj->func_param); 
 	for (i = 0; i < pobj->variables.itemcount; i++) {
-		ModuleVariable * var = (ModuleVariable *)pobj->variables.array[i]; 
+		ModuleVariable * var = (ModuleVariable *)pobj->variables.array[i];
+		if (var == NULL)
+			continue;
 		if (var->type == VTYPE_REG) { 
 			objectCall1(var->data, Clone, var->data_reg); 
 		} 

hdl4sesim/src/hdl4sesim.c

@@ -214,6 +214,8 @@ static void hdl4se_module_UpdateVariableData(sGeneralModule* pobj, int varindex)
 {
 	if (varindex >= 0 && varindex < pobj->variables.itemcount) {
 		ModuleVariable* var = (ModuleVariable*)pobj->variables.array[varindex];
+		if (var == NULL)
+			return;
 		var->func_UpdateVariable(var, pobj->func_param);
 	}
 }

parser/verilog_expr.c

@@ -868,9 +868,9 @@ static int expr_verilognode_procheck(HOBJECT object, HOBJECT module, void * para
 		IBigNumber** left = NULL;
 		verilogExpr* pexpr;
 		pobj->data.isconst = 0;
-		objectCall2(pobj->data.expr0, procheck, module, param);
+		objectCall2(pobj->data.expr, procheck, module, param);
 		left = bigintegerCreate(32);
-		pexpr = verilogExprGetData(pobj->data.expr0);
+		pexpr = verilogExprGetData(pobj->data.expr);
 		if (pexpr == NULL)
 			goto endofunop;
 		pobj->data.width = pexpr->width;
@@ -1706,22 +1706,56 @@ int verilogparseGenConstExpr(FILE* pFile, const char* pre, HOBJECT expr, HOBJECT
 	return count;
 }
 
-const char * verilogparseGenConstExprStr(HOBJECT expr, HOBJECT module)
+const char * verilogparseGenExprStr(HOBJECT expr, HOBJECT module)
 {
-	int count;
+	int width;
 	sExpr* pobj;
 	pobj = (sExpr*)objectThis(expr);
 	if (pobj == NULL)
 		return 0;
+	width = verilogparseGenExprWidth(expr, module);
 	switch (pobj->data.exprtype) {
 	case EXPRTYPE_NUMBER:
 	{
-		return pobj->data.value->string;
+		IBigNumber** number;
+		int width;
+		int isunsigned;
+		long long v;
+		number = bigintegerCreate(0);
+		objectCall3(number, AssignStr, pobj->data.value->string, NULL, 1);
+		objectCall1(number, GetInt64, &v);
+		width = objectCall0(number, GetWidth);
+		isunsigned = objectCall0(number, IsUnsigned);
+		if (isunsigned == 0) {
+			sprintf(hdl4se_parse_logbuf(), "%lld", v);
+		} 
+		else if (width <= 8){
+			sprintf(hdl4se_parse_logbuf(), "%d", (int)v);
+		}
+		else {
+			sprintf(hdl4se_parse_logbuf(), "0x%llx", v);
+		}
+		objectRelease(number);
+		return hdl4se_parse_logbuf();
 		break;
 	}
 	case EXPRTYPE_BIGNUMBER:
 	{
-		objectCall3(pobj->data.bignumber, GetStr, 10, hdl4se_parse_logbuf(), 1024);
+		int width;
+		int isunsigned;
+		long long v;
+		objectCall1(pobj->data.bignumber, GetInt64, &v);
+		width = objectCall0(pobj->data.bignumber, GetWidth);
+		isunsigned = objectCall0(pobj->data.bignumber, IsUnsigned);
+		if (isunsigned == 0) {
+			sprintf(hdl4se_parse_logbuf(), "%lld", v);
+		}
+		else if (v < 256) {
+			sprintf(hdl4se_parse_logbuf(), "%d", (int)v);
+		}
+		else {
+			sprintf(hdl4se_parse_logbuf(), "0x%llx", v);
+		}
 		return hdl4se_parse_logbuf();
 		break;
 	}
@@ -1746,8 +1780,8 @@ const char * verilogparseGenConstExprStr(HOBJECT expr, HOBJECT module)
 	{
 		char * src0;
 		char * src1;
-		src0 = strdup(verilogparseGenConstExprStr(pobj->data.expr0, module));
-		src1 = strdup(verilogparseGenConstExprStr(pobj->data.expr1, module));
+		src0 = strdup(verilogparseGenExprStr(pobj->data.expr0, module));
+		src1 = strdup(verilogparseGenExprStr(pobj->data.expr1, module));
 		sprintf(hdl4se_parse_logbuf(), operator_name_c_fmt[pobj->data.op], src0, src1);
 		free(src0);
 		free(src1);
@@ -1757,7 +1791,7 @@ const char * verilogparseGenConstExprStr(HOBJECT expr, HOBJECT module)
 	case EXPRTYPE_UNOP:
 	{
 		char * src0;
-		src0 = strdup(verilogparseGenConstExprStr(pobj->data.expr0, module));
+		src0 = strdup(verilogparseGenExprStr(pobj->data.expr, module));
 		sprintf(hdl4se_parse_logbuf(), operator_name_c_fmt[pobj->data.op], src0);
 		free(src0);
 		return hdl4se_parse_logbuf();
@@ -1767,9 +1801,9 @@ const char * verilogparseGenConstExprStr(HOBJECT expr, HOBJECT module)
 		char * src0;
 		char * src1;
 		char * src2;
-		src0 = strdup(verilogparseGenConstExprStr(pobj->data.expr0, module));
-		src1 = strdup(verilogparseGenConstExprStr(pobj->data.expr1, module));
-		src1 = strdup(verilogparseGenConstExprStr(pobj->data.expr2, module));
+		src0 = strdup(verilogparseGenExprStr(pobj->data.expr0, module));
+		src1 = strdup(verilogparseGenExprStr(pobj->data.expr1, module));
+		src2 = strdup(verilogparseGenExprStr(pobj->data.expr2, module));
 		sprintf(hdl4se_parse_logbuf(), "(%s)?(%s):(%s)", src0, src1, src2);
 		free(src0);
 		free(src1);
@@ -1790,7 +1824,10 @@ const char * verilogparseGenConstExprStr(HOBJECT expr, HOBJECT module)
 			sprintf(hdl4se_parse_logbuf(), "pobj->%s", select->name->string);
 			return hdl4se_parse_logbuf();
 		} else {
-			sprintf(hdl4se_parse_logbuf(), "VAR(%s)?Fixed me", select->name->string);
+			if (width <= 32)
+				sprintf(hdl4se_parse_logbuf(), "GEN_VREAD_S32(%s)", select->name->string);
+			else
+				sprintf(hdl4se_parse_logbuf(), "GEN_VREAD_U64(%s)", select->name->string);
 			return hdl4se_parse_logbuf();			
 		}
 		break;
@@ -1804,6 +1841,248 @@ const char * verilogparseGenConstExprStr(HOBJECT expr, HOBJECT module)
 	return "ERROR";
 }
 
+const char* verilogparseGenExprWidthStr(HOBJECT expr, HOBJECT module)
+{
+	int width;
+	width = verilogparseGenExprWidth(expr, module);
+	if (width > 0) {
+		sprintf(hdl4se_parse_logbuf(), "%d", width);
+		return hdl4se_parse_logbuf();
+	}
+	sExpr* pobj;
+	pobj = (sExpr*)objectThis(expr);
+	if (pobj == NULL)
+		return "NULL";
+	switch (pobj->data.exprtype) {
+	case EXPRTYPE_NUMBER:
+	{
+		int width;
+		IBigNumber** number;
+		number = bigintegerCreate(0);
+		objectCall3(number, AssignStr, pobj->data.value->string, NULL, 1);
+		width = objectCall0(number, GetWidth);
+		objectRelease(number);
+		sprintf(hdl4se_parse_logbuf(), "%d", width);
+		return hdl4se_parse_logbuf();
+		break;
+	}
+	case EXPRTYPE_BIGNUMBER:
+	{
+		sprintf(hdl4se_parse_logbuf(), "%d", objectCall0(pobj->data.bignumber, GetWidth));
+		return hdl4se_parse_logbuf();
+		break;
+	}
+	case EXPRTYPE_STRING:
+	{
+		return 0;
+		break;
+	}
+	case EXPRTYPE_PARAM:
+	{
+		return "64";
+		break;
+	}
+	case EXPRTYPE_LOCALPARAM:
+	{
+		return "64";
+		break;
+	}
+	case EXPRTYPE_BINOP:
+	{
+		if (isBinLogicOp(pobj->data.op)) {
+			return "1";
+		}
+		else {
+			char* src0;
+			char* src1;
+			src0 = strdup(verilogparseGenExprWidthStr(pobj->data.expr0, module));
+			src1 = strdup(verilogparseGenExprWidthStr(pobj->data.expr1, module));
+			sprintf(hdl4se_parse_logbuf(), "max(%s, %s)", src0, src1);
+			free(src0);
+			free(src1);
+			return hdl4se_parse_logbuf();
+		}
+		break;
+	}
+	case EXPRTYPE_UNOP:
+	{
+		if (isUnLogicOp(pobj->data.op))
+			return "1";
+		else
+			return verilogparseGenExprWidthStr(pobj->data.expr, module);
+	}
+	case EXPRTYPE_IFOP:
+	{
+		char* src1;
+		char* src2;
+		src1 = strdup(verilogparseGenExprWidthStr(pobj->data.expr1, module));
+		src2 = strdup(verilogparseGenExprWidthStr(pobj->data.expr2, module));
+		sprintf(hdl4se_parse_logbuf(), "max(%s, %s)", src1, src2);
+		free(src1);
+		free(src2);
+		return hdl4se_parse_logbuf();
+		break;
+	}
+	case EXPRTYPE_HIERARCHICAL_IDENT:
+	{
+		/* 目前只取第一个名称 */
+		verilogVarSel* select;
+		verilogVariableInfo* varinfo;
+		select = verilogVarSelGetData(pobj->data.hierarchical_identifier->__dlist_pNext);
+		if (verilogparseGetVarInfo(module, select->name->string, &varinfo)) {
+			if (varinfo->type == VAR_TYPE_PARAM && varinfo->range_type == RANGE_TYPE_NONE)
+				return "32";
+			return verilogparseGetRangeWidthStr(varinfo->range_type, varinfo->range_msb, varinfo->range_lsb, module);
+		}
+		break;
+	}
+	default:
+	{
+		return "ERROR";
+		break;
+	}
+	}
+	return "ERROR";
+}
+
+int verilogparseGetVarInfo(HOBJECT module, const char* name, verilogVariableInfo** varinfo)
+{
+	verilogParameter* param = verilogModuleGetParam(module, name);
+	if (param != NULL) {
+		*varinfo = (verilogVariableInfo*)param;
+		return 1;
+	}
+	verilogPort* port = verilogModuleGetPort(module, name);
+	if (port != NULL) {
+		*varinfo = (verilogVariableInfo*)port;
+		return 1;
+	}
+	verilogVarDecl* net = verilogModuleGetNet(module, name);
+	if (net != NULL) {
+		*varinfo = (verilogVariableInfo*)net;
+		return 1;
+	}
+	return 0;
+}
+
+int verilogparseIsLValueExpr(HOBJECT expr, HOBJECT module, verilogVariableInfo **varinfo)
+{
+	sExpr* pobj;
+	pobj = (sExpr*)objectThis(expr);
+	if (pobj == NULL)
+		return 0;
+	if (pobj->data.exprtype != EXPRTYPE_HIERARCHICAL_IDENT)
+		return 0;
+	/* 目前只取第一个名称 */
+	verilogVarSel* select;
+	verilogVariableInfo* var;
+	select = verilogVarSelGetData(pobj->data.hierarchical_identifier->__dlist_pNext);
+	if (0 == verilogparseGetVarInfo(module, select->name->string, &var))
+		return 0;
+	if (varinfo != NULL)
+		*varinfo = var;
+	if (var->type == VAR_TYPE_WIRE 
+	 || var->type == VAR_TYPE_PORT
+	 || var->type == VAR_TYPE_REG
+		)
+		return 1;
+	return 0;
+}
+
+int verilogparseGenExprWidth(HOBJECT expr, HOBJECT module)
+{
+	sExpr* pobj;
+	pobj = (sExpr*)objectThis(expr);
+	if (pobj == NULL)
+		return -1;
+	switch (pobj->data.exprtype) {
+	case EXPRTYPE_NUMBER:
+	{
+		int width;
+		IBigNumber** number;
+		number = bigintegerCreate(0);
+		objectCall3(number, AssignStr, pobj->data.value->string, NULL, 1);
+		width = objectCall0(number, GetWidth);
+		objectRelease(number);
+		return width;
+		break;
+	}
+	case EXPRTYPE_BIGNUMBER:
+	{
+		return objectCall0(pobj->data.bignumber, GetWidth);
+		break;
+	}
+	case EXPRTYPE_STRING:
+	{
+		return 0;
+		break;
+	}
+	case EXPRTYPE_PARAM:
+	{
+		return 64;
+		break;
+	}
+	case EXPRTYPE_LOCALPARAM:
+	{
+		return 64;
+		break;
+	}
+	case EXPRTYPE_BINOP:
+	{
+		if (isBinLogicOp(pobj->data.op)) {
+			return 1;
+		}
+		else {
+			int src0;
+			int src1;
+			src0 = verilogparseGenExprWidth(pobj->data.expr0, module);
+			src1 = verilogparseGenExprWidth(pobj->data.expr1, module);
+			if (src0 > 0 && src1 > 0)
+				return max(src0, src1);
+			else
+				return -1;
+		}
+		break;
+	}
+	case EXPRTYPE_UNOP:
+	{
+		if (isUnLogicOp(pobj->data.op))
+			return 1;
+		else
+			return verilogparseGenExprWidth(pobj->data.expr, module);
+	}
+	case EXPRTYPE_IFOP:
+	{
+		int src1;
+		int src2;
+		src1 = verilogparseGenExprWidth(pobj->data.expr1, module);
+		src2 = verilogparseGenExprWidth(pobj->data.expr2, module);
+		if (src1 > 0 && src2 > 0)
+			return max(src1, src2);
+		else
+			return -1;
+		break;
+	}
+	case EXPRTYPE_HIERARCHICAL_IDENT:
+	{
+		/* 目前只取第一个名称 */
+		verilogVarSel* select;
+		verilogVariableInfo* varinfo;
+		select = verilogVarSelGetData(pobj->data.hierarchical_identifier->__dlist_pNext);
+		if (verilogparseGetVarInfo(module, select->name->string, &varinfo)) {
+			if (varinfo->type == VAR_TYPE_PARAM && varinfo->range_type == RANGE_TYPE_NONE)
+				return 32;
+			return verilogparseGetRangeWidth(varinfo->range_type, varinfo->range_msb, varinfo->range_lsb, module);
+		}
+	}
+	default:
+	{
+		return -1;
+		break;
+	}
+	}
+	return -1;
+}
 
 int verilogparseIsConstExpr(HOBJECT expr, HOBJECT module)
 {

parser/verilog_moduleinst.c

@@ -347,7 +347,36 @@ static int moduleinst_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT
 	return 0;
 }
 
-
+static port_connections_check_named_connet(verilogModuleInstance* moduleinst)
+{
+	IDListVarPtr pitem, pitemtemp;
+	IDListVarPtr plist = moduleinst->port_connections;
+	verilogModule* moduleinfo = verilogModuleGetData(moduleinst->moduledecl);
+	pitem = plist->__dlist_pNext;
+	while (pitem != plist) {
+		pitemtemp = pitem->__dlist_pNext;
+		verilogParameterInstance* connect = verilogParameterInstanceGetData(pitem);
+		if (connect->index == -1) {
+			IDListVarPtr pport, pporttemp;
+			IDListVarPtr pportlist = moduleinfo->module_ports;
+			pport = pportlist->__dlist_pNext;
+			while (pport != pportlist) {
+				verilogPort* port = verilogPortGetData(pport);
+				pporttemp = pport->__dlist_pNext;
+				if (strcmp(connect->name->string, port->name->string) == 0) {
+					connect->index = port->index;
+					break;
+				}
+				pport = pporttemp;
+			}
+			if (connect->index == -1) {
+				sprintf(hdl4se_parse_logbuf(), "%s is not a port of module %s", connect->name->string, moduleinfo->name->string);
+				yyerror(hdl4se_parse_logbuf());
+			}
+		}
+		pitem = pitemtemp;
+	}
+}
 
 HOBJECT verilogparseCreateModuleInstance(
 	IConstStringVar * instname,
@@ -370,11 +399,10 @@ HOBJECT verilogparseCreateModuleInstance(
 	objectQueryInterface(range_lsb, IID_VERILOG_NODE, (void**)&pobj->data.range_lsb);
 	objectRelease(range_lsb);
 	pobj->data.port_connections = port_connections;
+	port_connections_check_named_connet(&pobj->data);
 	return moduleinst;
 }
 
-;
-
 int verilogparseSetModuleInstanceOption(
 	HOBJECT inst,
 	IDListVarPtr attributes,

parser/verilog_parameter.c

@@ -170,6 +170,7 @@ HOBJECT verilogparseCreateParameter(
 	if (parameter == NULL)
 		return NULL;
 	pobj = (sParameter *)objectThis(parameter);
+	pobj->data.type = VAR_TYPE_PARAM;
 	if (param_type == PARAM_TYPE_ASPRE) {
 		if (param_range_msb == NULL) {
 			printf("Expect parameter\n");

parser/verilog_parsetree.c

@@ -173,9 +173,9 @@ int verilog_dump_mapstr2ptr_list(IDListVarPtr list, FILE* pFile, const char* lin
     return 0;
 }
 
-const char * get_range_width_expr_str(int type, IVerilogNode **msbnode, IVerilogNode ** lsbnode, HOBJECT module)
+const char * verilogparseGetRangeWidthStr(int type, IVerilogNode **msbnode, IVerilogNode ** lsbnode, HOBJECT module)
 {
-	if (type == RANGE_TYPE_NONE) {
+	if (type == RANGE_TYPE_NONE || type == RANGE_TYPE_BITSELECT) {
 		return "1";
 	}
 	else if (type == RANGE_TYPE_PARTSELECT) {
@@ -193,9 +193,9 @@ const char * get_range_width_expr_str(int type, IVerilogNode **msbnode, IVerilog
 		}
 		else {
             const char * rst;
-            rst = verilogparseGenConstExprStr(msbnode, module);
+            rst = verilogparseGenExprStr(msbnode, module);
 			char * msb = strdup(rst);
-            rst = verilogparseGenConstExprStr(lsbnode, module);
+            rst = verilogparseGenExprStr(lsbnode, module);
 			char * lsb = strdup(rst);
 			sprintf(hdl4se_parse_logbuf(), "(%s) - (%s) + 1", msb, lsb);
 			free(msb);
@@ -209,6 +209,33 @@ const char * get_range_width_expr_str(int type, IVerilogNode **msbnode, IVerilog
 	return "ERROR";
 }
 
+int verilogparseGetRangeWidth(int type, IVerilogNode** msbnode, IVerilogNode** lsbnode, HOBJECT module)
+{
+    if (type == RANGE_TYPE_NONE || type == RANGE_TYPE_BITSELECT) {
+        return 1;
+    }
+    else if (type == RANGE_TYPE_PARTSELECT) {
+        verilogExpr* msb = verilogExprGetData(msbnode);
+        verilogExpr* lsb = verilogExprGetData(lsbnode);
+        if (lsb != NULL && lsb->exprtype == EXPRTYPE_BIGNUMBER && msb != NULL && msb->exprtype == EXPRTYPE_BIGNUMBER) {
+            int width;
+            IBigNumber** temp = bigintegerCreate(32);
+            objectCall2(temp, Sub, msb->bignumber, lsb->bignumber);
+            objectCall2(temp, AddInt32, temp, 1);
+            objectCall1(temp, GetInt32, &width);
+            objectRelease(temp);
+            return width;
+        }
+        else {
+            return -1;
+        }
+    }
+    else {
+        return -1;
+    }
+    return -1;
+}
+
 static char log_buf[64 * 1024];
 char* hdl4se_parse_logbuf()
 {

parser/verilog_parsetree.h

@@ -118,6 +118,8 @@ enum VAR_TYPE {
     VAR_TYPE_INTEGER,
     VAR_TYPE_TIME,
     VAR_TYPE_REG,
+    VAR_TYPE_PORT,
+    VAR_TYPE_PARAM,
 };
 
 enum EXPR_TYPE {
@@ -350,16 +352,27 @@ HOBJECT verilogparseCreateNullStatement();
 
 verilog_Statement* verilogStatementGetData(HOBJECT object);
 
+typedef struct _s_verilog_VariableInfo {
+    int type;
+    int index;
+    IConstStringVar* name;
+    int issigned;
+    int range_type;
+    IVerilogNode** range_msb;
+    IVerilogNode** range_lsb;
+}verilogVariableInfo;
+
 typedef struct _s_verilog_Port {
-    IDListVarPtr attributes;
+    int type;
     int index;
-    int port_direct;
-    int port_type;
+    IConstStringVar* name;
     int port_issigned;
     int range_type;
     IVerilogNode** port_range_msb; /* expression */
     IVerilogNode** port_range_lsb; /* expression */
-    IConstStringVar* name;
+    IDListVarPtr attributes;
+    int port_direct;
+    int port_type;
     IVerilogNode** expr;
 }verilogPort;
 
@@ -376,17 +389,19 @@ HOBJECT verilogparseCreatePort(
 );
 
 verilogPort* verilogPortGetData(HOBJECT port);
-const char * get_range_width_expr_str(int type, IVerilogNode **msb, IVerilogNode ** lsb, HOBJECT module);
+const char * verilogparseGetRangeWidthStr(int type, IVerilogNode **msb, IVerilogNode ** lsb, HOBJECT module);
+int verilogparseGetRangeWidth(int type, IVerilogNode** msb, IVerilogNode** lsb, HOBJECT module);
 
 typedef struct _s_verilog_Parameter {
+    int type;
     int index;
-    int param_type;
-    int param_data_type;
+    IConstStringVar* name;
     int param_issigned;
     int range_type;
     IVerilogNode** param_range_msb; /* expression */
     IVerilogNode** param_range_lsb; /* expression */
-    IConstStringVar* name;
+    int param_type;
+    int param_data_type;
     IVerilogNode** expr;
 }verilogParameter;
 
@@ -630,21 +645,25 @@ typedef struct s_expr_code_result {
 verilogExpr* verilogExprGetData(HOBJECT object);
 
 int verilogparseGenConstExpr(FILE* pFile, const char* pre, HOBJECT expr, HOBJECT module);
-const char * verilogparseGenConstExprStr(HOBJECT expr, HOBJECT module);
+const char * verilogparseGenExprStr(HOBJECT expr, HOBJECT module);
+const char* verilogparseGenExprWidthStr(HOBJECT expr, HOBJECT module);
+int verilogparseGenExprWidth(HOBJECT expr, HOBJECT module);
 int verilogparseIsConstExpr(HOBJECT expr, HOBJECT module);
+int verilogparseIsLValueExpr(HOBJECT expr, HOBJECT module, verilogVariableInfo** varinfo);
+int verilogparseGetVarInfo(HOBJECT module, const char * name, verilogVariableInfo** varinfo);
 
 typedef struct _s_verilog_VarDecl {
     int type;
     int index;
     IConstStringVar* name;
-    IVerilogNode** assignexpr;
-    IDListVar* attributes;
-    IDListVar* dimensions;
-    int vectored_or_scalared;
     int issigned;
     int range_type;
     IVerilogNode** range_msb;
     IVerilogNode** range_lsb;
+    IVerilogNode** assignexpr;
+    IDListVar* attributes;
+    IDListVar* dimensions;
+    int vectored_or_scalared;
 }verilogVarDecl;
 
 HOBJECT verilogparseCreateVarDecl(IConstStringVar* name);
@@ -703,6 +722,11 @@ int verilogparseSetParamInstanceIndex(
 
 verilogParameterInstance* verilogParameterInstanceGetData(HOBJECT object);
 
+verilogPort* verilogModuleGetPort(HOBJECT object, const char* name);
+verilogVarDecl* verilogModuleGetNet(HOBJECT object, const char* name);
+verilogParameter* verilogModuleGetParam(HOBJECT object, const char* name);
+
+
 #endif    
 
 #ifdef __cplusplus

parser/verilog_port.c

@@ -336,6 +336,7 @@ HOBJECT verilogparseCreatePort(
 	if (port == NULL)
 		return NULL;
 	pobj = (sPort *)objectThis(port);
+	pobj->data.type = VAR_TYPE_PORT;
 	if (port_direct == PORT_DIRECT_ASPRE) {
 		if (port_range_msb == NULL) {
 			printf("Warning: A port can not no DIRECT\n");

parser/verilog_vardecl.c

@@ -166,6 +166,8 @@ static const char* var_type_name[] = {
 	"integer",
 	"time",
 	"reg",
+	"port",
+	"parameter"
 };
 
 

testparser/main.c

@@ -18,9 +18,9 @@ extern char* yytext;
 
 static char logbuf[64 * 1024];
 
-#define GOOGLENET 1
+#define GOOGLENET 0
 #define TERRIS    0
-#define COUNTER   0
+#define COUNTER   1
 
 #ifdef WIN32
 #define WORKDIR "d:/gitwork"