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e1fcf06e
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体验新版 GitCode,发现更多精彩内容 >>
提交
e1fcf06e
编写于
8月 28, 2021
作者:
饶先宏
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电子邮件补丁
差异文件
202108281731
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10348246
变更
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29 changed file
with
7895 addition
and
5621 deletion
+7895
-5621
examples/hdl4se_riscv/de1/.qsys_edit/filters.xml
examples/hdl4se_riscv/de1/.qsys_edit/filters.xml
+2
-0
examples/hdl4se_riscv/de1/.qsys_edit/layout.xml
examples/hdl4se_riscv/de1/.qsys_edit/layout.xml
+1848
-0
examples/hdl4se_riscv/de1/.qsys_edit/preferences.xml
examples/hdl4se_riscv/de1/.qsys_edit/preferences.xml
+20
-0
examples/hdl4se_riscv/de1/de1_riscv.asm.rpt
examples/hdl4se_riscv/de1/de1_riscv.asm.rpt
+8
-8
examples/hdl4se_riscv/de1/de1_riscv.done
examples/hdl4se_riscv/de1/de1_riscv.done
+1
-1
examples/hdl4se_riscv/de1/de1_riscv.fit.rpt
examples/hdl4se_riscv/de1/de1_riscv.fit.rpt
+1070
-1052
examples/hdl4se_riscv/de1/de1_riscv.fit.summary
examples/hdl4se_riscv/de1/de1_riscv.fit.summary
+3
-3
examples/hdl4se_riscv/de1/de1_riscv.flow.rpt
examples/hdl4se_riscv/de1/de1_riscv.flow.rpt
+35
-26
examples/hdl4se_riscv/de1/de1_riscv.jdi
examples/hdl4se_riscv/de1/de1_riscv.jdi
+1
-1
examples/hdl4se_riscv/de1/de1_riscv.map.rpt
examples/hdl4se_riscv/de1/de1_riscv.map.rpt
+146
-231
examples/hdl4se_riscv/de1/de1_riscv.map.summary
examples/hdl4se_riscv/de1/de1_riscv.map.summary
+2
-2
examples/hdl4se_riscv/de1/de1_riscv.sof
examples/hdl4se_riscv/de1/de1_riscv.sof
+0
-0
examples/hdl4se_riscv/de1/de1_riscv.sta.rpt
examples/hdl4se_riscv/de1/de1_riscv.sta.rpt
+841
-815
examples/hdl4se_riscv/de1/de1_riscv.sta.summary
examples/hdl4se_riscv/de1/de1_riscv.sta.summary
+14
-14
examples/hdl4se_riscv/de1/de1_riscv_0.v
examples/hdl4se_riscv/de1/de1_riscv_0.v
+0
-0
examples/hdl4se_riscv/de1/de1_riscv_v2.v
examples/hdl4se_riscv/de1/de1_riscv_v2.v
+18
-6
examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml
examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml
+1
-1
examples/hdl4se_riscv/de1/test.mif
examples/hdl4se_riscv/de1/test.mif
+853
-853
examples/hdl4se_riscv/de1/uart/uart_ctrl.v
examples/hdl4se_riscv/de1/uart/uart_ctrl.v
+131
-0
examples/hdl4se_riscv/de1/uart/uart_fifo.qip
examples/hdl4se_riscv/de1/uart/uart_fifo.qip
+4
-0
examples/hdl4se_riscv/de1/uart/uart_fifo.v
examples/hdl4se_riscv/de1/uart/uart_fifo.v
+171
-0
examples/hdl4se_riscv/de1/uart/uart_fifo_bb.v
examples/hdl4se_riscv/de1/uart/uart_fifo_bb.v
+128
-0
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_ram8k.c
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_ram8k.c
+1
-1
examples/hdl4se_riscv/test_code/main_v2.c
examples/hdl4se_riscv/test_code/main_v2.c
+4
-3
examples/hdl4se_riscv/test_code/test.cod
examples/hdl4se_riscv/test_code/test.cod
+185
-187
examples/hdl4se_riscv/test_code/test.elf
examples/hdl4se_riscv/test_code/test.elf
+0
-0
examples/hdl4se_riscv/test_code/test.hex
examples/hdl4se_riscv/test_code/test.hex
+209
-211
examples/hdl4se_riscv/test_code/test.mif
examples/hdl4se_riscv/test_code/test.mif
+853
-853
examples/hdl4se_riscv/test_code/test.txt
examples/hdl4se_riscv/test_code/test.txt
+1346
-1353
未找到文件。
examples/hdl4se_riscv/de1/.qsys_edit/filters.xml
0 → 100644
浏览文件 @
e1fcf06e
<?xml version="1.0" encoding="UTF-8"?>
<filters
version=
"13.1"
/>
examples/hdl4se_riscv/de1/.qsys_edit/layout.xml
0 → 100644
浏览文件 @
e1fcf06e
此差异已折叠。
点击以展开。
examples/hdl4se_riscv/de1/.qsys_edit/preferences.xml
0 → 100644
浏览文件 @
e1fcf06e
<?xml version="1.0" encoding="UTF-8"?>
<preferences>
<debug
showDebugMenu=
"0"
/>
<systemtable>
<columns>
<connections
preferredWidth=
"47"
/>
<irq
preferredWidth=
"34"
/>
</columns>
</systemtable>
<clocktable>
<columns>
<clockname
preferredWidth=
"175"
/>
<clocksource
preferredWidth=
"174"
/>
<frequency
preferredWidth=
"155"
/>
</columns>
</clocktable>
<window
width=
"1100"
height=
"800"
x=
"0"
y=
"0"
/>
<library
expandedCategories=
"Library/Interface Protocols,Project,Library,Library/Interface Protocols/Serial"
/>
</preferences>
examples/hdl4se_riscv/de1/de1_riscv.asm.rpt
浏览文件 @
e1fcf06e
Assembler report for de1_riscv
Assembler report for de1_riscv
Sat Aug 28 1
0:56:11
2021
Sat Aug 28 1
6:28:45
2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
...
@@ -37,7 +37,7 @@ applicable agreement for further details.
...
@@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
+---------------------------------------------------------------+
; Assembler Summary ;
; Assembler Summary ;
+-----------------------+---------------------------------------+
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sat Aug 28 1
0:56:11
2021 ;
; Assembler Status ; Successful - Sat Aug 28 1
6:28:45
2021 ;
; Revision Name ; de1_riscv ;
; Revision Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ;
; Family ; Cyclone V ;
; Family ; Cyclone V ;
...
@@ -92,8 +92,8 @@ applicable agreement for further details.
...
@@ -92,8 +92,8 @@ applicable agreement for further details.
; Option ; Setting ;
; Option ; Setting ;
+----------------+--------------------------------------------------------------------+
+----------------+--------------------------------------------------------------------+
; Device ; 5CSEMA5F31C6 ;
; Device ; 5CSEMA5F31C6 ;
; JTAG usercode ; 0x012
2B7FD
;
; JTAG usercode ; 0x012
48964
;
; Checksum ; 0x012
2B7FD
;
; Checksum ; 0x012
48964
;
+----------------+--------------------------------------------------------------------+
+----------------+--------------------------------------------------------------------+
...
@@ -103,13 +103,13 @@ applicable agreement for further details.
...
@@ -103,13 +103,13 @@ applicable agreement for further details.
Info: *******************************************************************
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Info: Processing started: Sat Aug 28 1
0:55:56
2021
Info: Processing started: Sat Aug 28 1
6:28:30
2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv
Info (115030): Assembler is generating device programming files
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 66
1
megabytes
Info: Peak virtual memory: 66
0
megabytes
Info: Processing ended: Sat Aug 28 1
0:56:11
2021
Info: Processing ended: Sat Aug 28 1
6:28:45
2021
Info: Elapsed time: 00:00:15
Info: Elapsed time: 00:00:15
Info: Total CPU time (on all processors): 00:00:1
5
Info: Total CPU time (on all processors): 00:00:1
6
examples/hdl4se_riscv/de1/de1_riscv.done
浏览文件 @
e1fcf06e
Sat Aug 28 1
0:56:46
2021
Sat Aug 28 1
6:29:20
2021
examples/hdl4se_riscv/de1/de1_riscv.fit.rpt
浏览文件 @
e1fcf06e
此差异已折叠。
点击以展开。
examples/hdl4se_riscv/de1/de1_riscv.fit.summary
浏览文件 @
e1fcf06e
Fitter Status : Successful - Sat Aug 28 1
0:55:51
2021
Fitter Status : Successful - Sat Aug 28 1
6:28:25
2021
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : de1_riscv
Revision Name : de1_riscv
Top-level Entity Name : de1_riscv
Top-level Entity Name : de1_riscv
Family : Cyclone V
Family : Cyclone V
Device : 5CSEMA5F31C6
Device : 5CSEMA5F31C6
Timing Models : Preliminary
Timing Models : Preliminary
Logic utilization (in ALMs) : 2,
49
4 / 32,070 ( 8 % )
Logic utilization (in ALMs) : 2,
51
4 / 32,070 ( 8 % )
Total registers : 18
63
Total registers : 18
59
Total pins : 204 / 457 ( 45 % )
Total pins : 204 / 457 ( 45 % )
Total virtual pins : 0
Total virtual pins : 0
Total block memory bits : 66,560 / 4,065,280 ( 2 % )
Total block memory bits : 66,560 / 4,065,280 ( 2 % )
...
...
examples/hdl4se_riscv/de1/de1_riscv.flow.rpt
浏览文件 @
e1fcf06e
Flow report for de1_riscv
Flow report for de1_riscv
Sat Aug 28 1
1:02:31
2021
Sat Aug 28 1
6:29:19
2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
...
@@ -40,25 +40,25 @@ applicable agreement for further details.
...
@@ -40,25 +40,25 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
+-------------------------------------------------------------------------------+
; Flow Summary ;
; Flow Summary ;
+---------------------------------+---------------------------------------------+
+---------------------------------+---------------------------------------------+
; Flow Status ; Successful - Sat Aug 28 1
1:02:31
2021 ;
; Flow Status ; Successful - Sat Aug 28 1
6:28:45
2021 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name ; de1_riscv ;
; Revision Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ;
; Family ; Cyclone V ;
; Family ; Cyclone V ;
; Device ; 5CSEMA5F31C6 ;
; Device ; 5CSEMA5F31C6 ;
; Timing Models ; Preliminary ;
; Timing Models ; Preliminary ;
; Logic utilization (in ALMs) ;
N/A
;
; Logic utilization (in ALMs) ;
2,514 / 32,070 ( 8 % )
;
; Total registers ; 1
636
;
; Total registers ; 1
859
;
; Total pins ; 204
;
; Total pins ; 204
/ 457 ( 45 % )
;
; Total virtual pins ; 0 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 6
7,296
;
; Total block memory bits ; 6
6,560 / 4,065,280 ( 2 % )
;
; Total DSP Blocks ; 10
;
; Total DSP Blocks ; 10
/ 87 ( 11 % )
;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI TX Channels ; 0 ;
; Total HSSI TX Channels ; 0 ;
; Total PLLs ; 1
;
; Total PLLs ; 1
/ 6 ( 17 % )
;
; Total DLLs ; 0
;
; Total DLLs ; 0
/ 4 ( 0 % )
;
+---------------------------------+---------------------------------------------+
+---------------------------------+---------------------------------------------+
...
@@ -67,7 +67,7 @@ applicable agreement for further details.
...
@@ -67,7 +67,7 @@ applicable agreement for further details.
+-------------------+---------------------+
+-------------------+---------------------+
; Option ; Setting ;
; Option ; Setting ;
+-------------------+---------------------+
+-------------------+---------------------+
; Start date & time ; 08/28/2021 1
1:02:08
;
; Start date & time ; 08/28/2021 1
6:23:04
;
; Main task ; Compilation ;
; Main task ; Compilation ;
; Revision Name ; de1_riscv ;
; Revision Name ; de1_riscv ;
+-------------------+---------------------+
+-------------------+---------------------+
...
@@ -78,7 +78,7 @@ applicable agreement for further details.
...
@@ -78,7 +78,7 @@ applicable agreement for further details.
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
; COMPILER_SIGNATURE_ID ; 621136229624.16301
197282456
4 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 621136229624.16301
389842252
4 ; -- ; -- ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M_0002 ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M_0002 ; -- ;
...
@@ -129,29 +129,38 @@ applicable agreement for further details.
...
@@ -129,29 +129,38 @@ applicable agreement for further details.
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
+--------------------------------------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------
-----
+
; Flow Elapsed Time ;
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+----------------------
-----
+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:22 ; 1.0 ; 670 MB ; 00:00:21 ;
; Analysis & Synthesis ; 00:00:24 ; 1.0 ; 669 MB ; 00:00:23 ;
; Total ; 00:00:22 ; -- ; -- ; 00:00:21 ;
; Fitter ; 00:01:43 ; 1.3 ; 2331 MB ; 00:02:12 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Assembler ; 00:00:15 ; 1.0 ; 660 MB ; 00:00:16 ;
; TimeQuest Timing Analyzer ; 00:00:32 ; 1.4 ; 1126 MB ; 00:00:42 ;
; Total ; 00:02:54 ; -- ; -- ; 00:03:33 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+-----------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------
-----
+
; Flow OS Summary ;
; Flow OS Summary ;
+----------------------+------------------+-----------+------------+----------------+
+----------------------
-----
+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+-----------+------------+----------------+
+----------------------
-----
+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
; Analysis & Synthesis ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
+----------------------+------------------+-----------+------------+----------------+
; Fitter ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
; Assembler ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
; TimeQuest Timing Analyzer ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+
------------
------------
; Flow Log ;
; Flow Log ;
------------
------------
quartus_map --read_settings_files=on --write_settings_files=off de1_riscv -c de1_riscv
quartus_map --read_settings_files=on --write_settings_files=off de1_riscv -c de1_riscv
quartus_fit --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv
quartus_asm --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv
quartus_sta de1_riscv -c de1_riscv
examples/hdl4se_riscv/de1/de1_riscv.jdi
浏览文件 @
e1fcf06e
<sld_project_info>
<sld_project_info>
<project>
<project>
<hash md5_digest_80b="
1756052714224fa8aed
0"/>
<hash md5_digest_80b="
6598e35802d3352c8d4
0"/>
</project>
</project>
<file_info>
<file_info>
<file device="5CSEMA5F31C6" path="de1_riscv.sof" usercode="0xFFFFFFFF"/>
<file device="5CSEMA5F31C6" path="de1_riscv.sof" usercode="0xFFFFFFFF"/>
...
...
examples/hdl4se_riscv/de1/de1_riscv.map.rpt
浏览文件 @
e1fcf06e
此差异已折叠。
点击以展开。
examples/hdl4se_riscv/de1/de1_riscv.map.summary
浏览文件 @
e1fcf06e
Analysis & Synthesis Status : Successful - Sat Aug 28 1
1:02:31
2021
Analysis & Synthesis Status : Successful - Sat Aug 28 1
6:23:29
2021
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : de1_riscv
Revision Name : de1_riscv
Top-level Entity Name : de1_riscv
Top-level Entity Name : de1_riscv
Family : Cyclone V
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Logic utilization (in ALMs) : N/A
Total registers : 1
636
Total registers : 1
702
Total pins : 204
Total pins : 204
Total virtual pins : 0
Total virtual pins : 0
Total block memory bits : 67,296
Total block memory bits : 67,296
...
...
examples/hdl4se_riscv/de1/de1_riscv.sof
0 → 100644
浏览文件 @
e1fcf06e
文件已添加
examples/hdl4se_riscv/de1/de1_riscv.sta.rpt
浏览文件 @
e1fcf06e
因为 它太大了无法显示 source diff 。你可以改为
查看blob
。
examples/hdl4se_riscv/de1/de1_riscv.sta.summary
浏览文件 @
e1fcf06e
...
@@ -3,11 +3,11 @@ TimeQuest Timing Analyzer Summary
...
@@ -3,11 +3,11 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------
------------------------------------------------------------
Type : Slow 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Type : Slow 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack :
-1.197
Slack :
6.342
TNS :
-95.783
TNS :
0.000
Type : Slow 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Type : Slow 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.2
66
Slack : 0.2
71
TNS : 0.000
TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
...
@@ -15,7 +15,7 @@ Slack : 1.666
...
@@ -15,7 +15,7 @@ Slack : 1.666
TNS : 0.000
TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack :
3.775
Slack :
8.772
TNS : 0.000
TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
...
@@ -23,11 +23,11 @@ Slack : 9.670
...
@@ -23,11 +23,11 @@ Slack : 9.670
TNS : 0.000
TNS : 0.000
Type : Slow 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Type : Slow 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack :
-1.352
Slack :
6.283
TNS :
-121.67
0
TNS :
0.00
0
Type : Slow 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Type : Slow 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.2
47
Slack : 0.2
56
TNS : 0.000
TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
...
@@ -35,7 +35,7 @@ Slack : 1.666
...
@@ -35,7 +35,7 @@ Slack : 1.666
TNS : 0.000
TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack :
3.758
Slack :
8.754
TNS : 0.000
TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
...
@@ -43,11 +43,11 @@ Slack : 9.673
...
@@ -43,11 +43,11 @@ Slack : 9.673
TNS : 0.000
TNS : 0.000
Type : Fast 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Type : Fast 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack :
3.503
Slack :
11.576
TNS : 0.000
TNS : 0.000
Type : Fast 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Type : Fast 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.1
54
Slack : 0.1
62
TNS : 0.000
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
...
@@ -55,7 +55,7 @@ Slack : 1.666
...
@@ -55,7 +55,7 @@ Slack : 1.666
TNS : 0.000
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack :
3.888
Slack :
8.890
TNS : 0.000
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
...
@@ -63,11 +63,11 @@ Slack : 9.336
...
@@ -63,11 +63,11 @@ Slack : 9.336
TNS : 0.000
TNS : 0.000
Type : Fast 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Type : Fast 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack :
3.81
2
Slack :
12.16
2
TNS : 0.000
TNS : 0.000
Type : Fast 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Type : Fast 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack : 0.1
41
Slack : 0.1
52
TNS : 0.000
TNS : 0.000
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
...
@@ -75,7 +75,7 @@ Slack : 1.666
...
@@ -75,7 +75,7 @@ Slack : 1.666
TNS : 0.000
TNS : 0.000
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
Slack :
3.888
Slack :
8.891
TNS : 0.000
TNS : 0.000
Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
...
...
examples/hdl4se_riscv/de1/de1_riscv.v
→
examples/hdl4se_riscv/de1/de1_riscv
_0
.v
浏览文件 @
e1fcf06e
文件已移动
examples/hdl4se_riscv/de1/de1_riscv_v2.v
浏览文件 @
e1fcf06e
...
@@ -136,9 +136,9 @@ module de1_riscv(
...
@@ -136,9 +136,9 @@ module de1_riscv(
end
end
assign
bReadData
=
assign
bReadData
=
((
bReadAddr_out
&
32'hffffff00
)
==
32'h
f
0000000
)
?
bReadDataKey
:
(
((
bReadAddr_out
&
32'hffffff00
)
==
32'h
F
0000000
)
?
bReadDataKey
:
(
((
bReadAddr_out
&
32'hffffc000
)
==
32'h00000000
)
?
bReadDataRam
:
(
((
bReadAddr_out
&
32'hffffc000
)
==
32'h00000000
)
?
bReadDataRam
:
(
((
bReadAddr_out
&
32'hffffff00
)
==
32'h
0
0000100
)
?
bReadDataUart
:
(
0
)
((
bReadAddr_out
&
32'hffffff00
)
==
32'h
F
0000100
)
?
bReadDataUart
:
(
0
)
)
)
);
);
...
@@ -150,12 +150,13 @@ module de1_riscv(
...
@@ -150,12 +150,13 @@ module de1_riscv(
wire
[
31
:
0
]
regwrdata
;
wire
[
31
:
0
]
regwrdata
;
wire
regwren
;
wire
regwren
;
wire
[
31
:
0
]
regrddata
;
wire
[
31
:
0
]
regrddata
;
wire
[
2
:
0
]
uartaddr
;
/*
assign
uartaddr
=
wWrite
?
bWriteAddr
[
4
:
2
]
:
bReadAddr
[
4
:
2
];
wire [31:0] uartaddr;
assign uartaddr = wWrite?bWriteAddr:bReadAddr;
altera_uart uart(
altera_uart uart(
// inputs:
// inputs:
.
address
(
uartaddr
),
.address(uartaddr
[4:2]
),
.
begintransfer
(
SW
[
0
]
),
.begintransfer(
1'b1
),
.chipselect((uartaddr & 32'hffffff00)==32'hf0000100),
.chipselect((uartaddr & 32'hffffff00)==32'hf0000100),
.clk(wClk),
.clk(wClk),
.read_n(~wRead),
.read_n(~wRead),
...
@@ -171,6 +172,17 @@ module de1_riscv(
...
@@ -171,6 +172,17 @@ module de1_riscv(
.readyfordata(LEDR[2]),
.readyfordata(LEDR[2]),
.txd(uart_tx)
.txd(uart_tx)
);
);
*/
uart_ctrl
uart_ctrl
(
wClk
,
nwReset
,
((
bReadAddr
&
32'hffffff00
)
==
32'hf0000100
)
?
wRead
:
1'b0
,
bReadAddr
,
((
bWriteAddr
&
32'hffffff00
)
==
32'hf0000100
)
?
wWrite
:
1'b0
,
bWriteAddr
,
bWriteData
,
bReadDataUart
,
uart_tx
,
uart_rx
);
regfile
regs
(
regno
,
regena
,
wClk
,
regwrdata
,
regwren
,
regrddata
);
regfile
regs
(
regno
,
regena
,
wClk
,
regwrdata
,
regwren
,
regrddata
);
ram8kb
ram
(
ramaddr
,
~
bWriteMask
,
wClk
,
bWriteData
,
((
bWriteAddr
&
32'hffffc000
)
==
0
)
?
wWrite
:
1'b0
,
bReadDataRam
);
ram8kb
ram
(
ramaddr
,
~
bWriteMask
,
wClk
,
bWriteData
,
((
bWriteAddr
&
32'hffffc000
)
==
0
)
?
wWrite
:
1'b0
,
bReadDataRam
);
...
...
examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml
浏览文件 @
e1fcf06e
...
@@ -16,5 +16,5 @@
...
@@ -16,5 +16,5 @@
</clocktable>
</clocktable>
<window
width=
"1936"
height=
"1176"
x=
"-8"
y=
"-8"
/>
<window
width=
"1936"
height=
"1176"
x=
"-8"
y=
"-8"
/>
<library
<library
expandedCategories=
"
Library/Window Bridge,Library/Peripherals/Microcontroller Peripherals,Library/Peripherals,Library/Verification,Library,Project
"
/>
expandedCategories=
"
Project,Library/Interface Protocols,Library,Library/Interface Protocols/Serial
"
/>
</preferences>
</preferences>
examples/hdl4se_riscv/de1/test.mif
浏览文件 @
e1fcf06e
此差异已折叠。
点击以展开。
examples/hdl4se_riscv/de1/uart/uart_ctrl.v
0 → 100644
浏览文件 @
e1fcf06e
module
uart_ctrl
(
input
wClk
,
input
nwReset
,
input
wRead
,
input
[
31
:
0
]
bReadAddr
,
input
wWrite
,
input
[
31
:
0
]
bWriteAddr
,
input
[
31
:
0
]
bWriteData
,
output
[
31
:
0
]
bReadData
,
output
uart_tx
,
input
uart_rx
);
wire
[
31
:
0
]
ctl_state
;
wire
[
7
:
0
]
send_buf_data
,
send_buf_q
;
wire
send_buf_full
;
wire
send_buf_empty
;
wire
[
9
:
0
]
send_buf_used
;
reg
send_buf_read
;
reg
send_buf_write
;
assign
send_buf_data
=
bWriteData
[
7
:
0
];
assign
ctl_state
[
15
:
0
]
=
{
5'b0
,
send_buf_used
,
send_buf_full
}
;
uart_fifo
uart_send_buf
(
.
clock
(
wClk
),
.
data
(
send_buf_data
),
.
rdreq
(
send_buf_read
),
.
wrreq
(
send_buf_write
),
.
almost_full
(
send_buf_full
),
.
empty
(
send_buf_empty
),
.
full
(),
.
q
(
send_buf_q
),
.
usedw
(
send_buf_used
));
wire
[
7
:
0
]
recv_buf_data
,
recv_buf_q
;
wire
recv_buf_empty
;
wire
recv_buf_full
;
wire
[
9
:
0
]
recv_buf_used
;
reg
recv_buf_read
;
reg
recv_buf_write
;
assign
ctl_state
[
31
:
16
]
=
{
5'b0
,
recv_buf_used
,
recv_buf_empty
}
;
uart_fifo
uart_recv_buf
(
.
clock
(
wClk
),
.
data
(
recv_buf_data
),
.
rdreq
(
recv_buf_read
),
.
wrreq
(
recv_buf_write
),
.
almost_full
(
recv_buf_full
),
.
empty
(
recv_buf_empty
),
.
full
(),
.
q
(
recv_buf_q
),
.
usedw
(
recv_buf_used
));
reg
[
2
:
0
]
uartaddr
;
reg
uart_read
,
uart_write
;
reg
[
15
:
0
]
uart_write_data
;
wire
[
15
:
0
]
uart_read_data
;
wire
uart_has_data
;
wire
uart_can_send
;
altera_uart
uart
(
// inputs:
.
address
(
uartaddr
),
.
begintransfer
(
1'b1
),
.
chipselect
(
1'b1
),
.
clk
(
wClk
),
.
read_n
(
~
uart_read
),
.
reset_n
(
nwReset
),
.
rxd
(
uart_rx
),
.
write_n
(
uart_write
),
.
writedata
(
uart_write_data
),
// outputs:
.
dataavailable
(
uart_has_data
),
.
irq
(),
.
readdata
(
uart_read_data
),
.
readyfordata
(
uart_can_send
),
.
txd
(
uart_tx
)
);
always
@
(
posedge
wClk
)
if
(
~
nwReset
)
begin
uart_read
<=
1'b0
;
uart_write
<
=
1'b0
;
uart_addr
<=
3'b0
;
recv_buf_write
<=
1'b0
;
end
else
begin
uart_read
<=
1'b0
;
uart_write
<
=
1'b0
;
uart_addr
<=
3'b0
;
recv_buf_write
<=
1'b0
;
if
(
uart_has_data
&&
~
recv_buf_full
)
begin
recv_buf_write
<=
1'b1
;
recv_buf_data
<=
end
end
/* */
reg
[
31
:
0
]
bReadData
;
wire
[
1
:
0
]
readaddr
=
bReadAddr
[
3
:
2
];
always
@
(
posedge
wClk
)
if
(
~
nwReset
)
begin
bReadData
<=
32'h0
;
recv_buf_read
<=
1'b0
;
end
else
begin
recv_buf_read
<=
1'b0
;
if
(
wRead
)
begin
if
(
readaddr
==
0
)
begin
/* state */
bReadData
<=
ctl_state
;
end
else
if
(
readaddr
==
1
)
begin
bReadData
<=
{
24'b0
,
uartrecvdata
}
;
recv_buf_read
<=
~
ctl_state
[
16
];
/* empty */
end
end
end
/* д */
wire
[
1
:
0
]
writeaddr
=
bWriteAddr
[
3
:
2
];
always
@
(
posedge
wClk
)
if
(
~
nwReset
)
begin
send_buf_write
<=
1'b0
;
end
else
begin
send_buf_write
<=
1'b0
;
if
(
wWrite
&&
(
writeaddr
==
2
))
begin
send_buf_write
<=
1'b1
;
end
end
endmodule
\ No newline at end of file
examples/hdl4se_riscv/de1/uart/uart_fifo.qip
0 → 100644
浏览文件 @
e1fcf06e
set_global_assignment -name IP_TOOL_NAME "FIFO"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "uart_fifo.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "uart_fifo_bb.v"]
examples/hdl4se_riscv/de1/uart/uart_fifo.v
0 → 100644
浏览文件 @
e1fcf06e
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: uart_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale
1
ps
/
1
ps
// synopsys translate_on
module
uart_fifo
(
clock
,
data
,
rdreq
,
wrreq
,
almost_full
,
empty
,
full
,
q
,
usedw
);
input
clock
;
input
[
7
:
0
]
data
;
input
rdreq
;
input
wrreq
;
output
almost_full
;
output
empty
;
output
full
;
output
[
7
:
0
]
q
;
output
[
9
:
0
]
usedw
;
wire
[
9
:
0
]
sub_wire0
;
wire
sub_wire1
;
wire
sub_wire2
;
wire
[
7
:
0
]
sub_wire3
;
wire
sub_wire4
;
wire
[
9
:
0
]
usedw
=
sub_wire0
[
9
:
0
];
wire
empty
=
sub_wire1
;
wire
full
=
sub_wire2
;
wire
[
7
:
0
]
q
=
sub_wire3
[
7
:
0
];
wire
almost_full
=
sub_wire4
;
scfifo
scfifo_component
(
.
clock
(
clock
),
.
wrreq
(
wrreq
),
.
data
(
data
),
.
rdreq
(
rdreq
),
.
usedw
(
sub_wire0
),
.
empty
(
sub_wire1
),
.
full
(
sub_wire2
),
.
q
(
sub_wire3
),
.
almost_full
(
sub_wire4
),
.
aclr
(),
.
almost_empty
(),
.
sclr
());
defparam
scfifo_component
.
add_ram_output_register
=
"OFF"
,
scfifo_component
.
almost_full_value
=
240
,
scfifo_component
.
intended_device_family
=
"Cyclone V"
,
scfifo_component
.
lpm_numwords
=
1024
,
scfifo_component
.
lpm_showahead
=
"OFF"
,
scfifo_component
.
lpm_type
=
"scfifo"
,
scfifo_component
.
lpm_width
=
8
,
scfifo_component
.
lpm_widthu
=
10
,
scfifo_component
.
overflow_checking
=
"ON"
,
scfifo_component
.
underflow_checking
=
"ON"
,
scfifo_component
.
use_eab
=
"ON"
;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "240"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "240"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL "usedw[9..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
examples/hdl4se_riscv/de1/uart/uart_fifo_bb.v
0 → 100644
浏览文件 @
e1fcf06e
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: uart_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module
uart_fifo
(
clock
,
data
,
rdreq
,
wrreq
,
almost_full
,
empty
,
full
,
q
,
usedw
);
input
clock
;
input
[
7
:
0
]
data
;
input
rdreq
;
input
wrreq
;
output
almost_full
;
output
empty
;
output
full
;
output
[
7
:
0
]
q
;
output
[
9
:
0
]
usedw
;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "240"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "240"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL "usedw[9..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_ram8k.c
浏览文件 @
e1fcf06e
...
@@ -144,7 +144,7 @@ static int loadExecImage(unsigned char* data, int maxlen)
...
@@ -144,7 +144,7 @@ static int loadExecImage(unsigned char* data, int maxlen)
unsigned
int
addr
;
unsigned
int
addr
;
FILE
*
pFile
=
fopen
(
DATADIR
"test_code/test.cod"
,
"rt"
);
FILE
*
pFile
=
fopen
(
DATADIR
"test_code/test.cod"
,
"rt"
);
if
(
pFile
==
NULL
)
{
if
(
pFile
==
NULL
)
{
printf
(
"File %s can not open
\n
"
,
DATADIR
"test_code/test.
bin
"
);
printf
(
"File %s can not open
\n
"
,
DATADIR
"test_code/test.
cod
"
);
exit
(
-
1
);
exit
(
-
1
);
}
}
addr
=
0
;
addr
=
0
;
...
...
examples/hdl4se_riscv/test_code/main_v2.c
浏览文件 @
e1fcf06e
...
@@ -30,15 +30,16 @@ int main(int argc, char* argv[])
...
@@ -30,15 +30,16 @@ int main(int argc, char* argv[])
count
=
0
;
count
=
0
;
leddata
[
0
]
=
0x6f7f077d
;
leddata
[
0
]
=
0x6f7f077d
;
leddata
[
1
]
=
0x6d664f5b
;
leddata
[
1
]
=
0x6d664f5b
;
uart
[
4
]
=
100000000
/
115200
;
/* set baudrate to 115200 */
//
uart[4] = 100000000 / 115200;/* set baudrate to 115200 */
uart
[
1
]
=
'H'
;
//
uart[1] = 'H';
uart
[
1
]
=
'\n'
;
//
uart[1] = '\n';
do
{
do
{
unsigned
int
key
;
unsigned
int
key
;
unsigned
int
uartstate
;
unsigned
int
uartstate
;
uartstate
=
uart
[
2
];
uartstate
=
uart
[
2
];
if
(
uartstate
&
0x80
)
{
/*rrdy*/
if
(
uartstate
&
0x80
)
{
/*rrdy*/
uart
[
1
]
=
uart
[
0
];
/* writeback */
uart
[
1
]
=
uart
[
0
];
/* writeback */
uart
[
2
]
=
0
;
continue
;
continue
;
}
}
key
=
*
ledkey
;
key
=
*
ledkey
;
...
...
examples/hdl4se_riscv/test_code/test.cod
浏览文件 @
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此差异已折叠。
点击以展开。
examples/hdl4se_riscv/test_code/test.elf
浏览文件 @
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无法预览此类型文件
examples/hdl4se_riscv/test_code/test.hex
浏览文件 @
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此差异已折叠。
点击以展开。
examples/hdl4se_riscv/test_code/test.mif
浏览文件 @
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此差异已折叠。
点击以展开。
examples/hdl4se_riscv/test_code/test.txt
浏览文件 @
e1fcf06e
此差异已折叠。
点击以展开。
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