diff --git a/examples/hdl4se_riscv/de1/.qsys_edit/filters.xml b/examples/hdl4se_riscv/de1/.qsys_edit/filters.xml
new file mode 100644
index 0000000000000000000000000000000000000000..6462567e116dbc40b64912b310b2e274bfd96c38
--- /dev/null
+++ b/examples/hdl4se_riscv/de1/.qsys_edit/filters.xml
@@ -0,0 +1,2 @@
+
+
diff --git a/examples/hdl4se_riscv/de1/.qsys_edit/layout.xml b/examples/hdl4se_riscv/de1/.qsys_edit/layout.xml
new file mode 100644
index 0000000000000000000000000000000000000000..0e6f0390706ae45d1e84fa8cf2459d36c2ea7338
--- /dev/null
+++ b/examples/hdl4se_riscv/de1/.qsys_edit/layout.xml
@@ -0,0 +1,1848 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ ccontrol center
+ true
+
+ false
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ dock.CContentArea.center
+
+
+
+
+
+ 0
+
+ 0
+ dock.PlaceholderList
+
+
+ dock.single.Library
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 0
+ - 0
+ - dock.single.Library
+
+
+
+
+
+
+
+
+ Library
+
+
+
+
+
+
+
+
+
+ 0
+
+ 0
+ dock.PlaceholderList
+
+
+ dock.single.Hierarchy
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 0
+ - 0
+ - dock.single.Hierarchy
+
+
+
+
+
+
+
+
+ Hierarchy
+
+
+
+
+
+
+
+
+
+ 0
+
+ 0
+ dock.PlaceholderList
+
+
+ dock.single.System\ Contents
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 0
+ - 0
+ - dock.single.System\ Contents
+
+
+
+ dock.single.Address\ Map
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 1
+ - 1
+ - dock.single.Address\ Map
+
+
+
+ dock.single.Instrumentation
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 2
+ - 2
+ - dock.single.Instrumentation
+
+
+
+ dock.single.Clock\ Settings
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 3
+ - 3
+ - dock.single.Clock\ Settings
+
+
+
+ dock.single.Instance\ Parameters
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 4
+ - 4
+ - dock.single.Instance\ Parameters
+
+
+
+ dock.single.Project\ Settings
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 5
+ - 5
+ - dock.single.Project\ Settings
+
+
+
+ dock.single.HDL\ Example
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 6
+ - 6
+ - dock.single.HDL\ Example
+
+
+
+ dock.single.Generation
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 7
+ - 7
+ - dock.single.Generation
+
+
+
+ dock.single.Connections
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 8
+ - 8
+ - dock.single.Connections
+
+
+
+ dock.single.Data\ Path
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 9
+ - 9
+ - dock.single.Data\ Path
+
+
+
+ dock.single.Domains
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 10
+ - 10
+ - dock.single.Domains
+
+
+
+
+
+
+
+
+ System Contents
+
+
+
+
+
+
+
+
+
+ Address Map
+
+
+
+
+
+
+
+
+
+ Instrumentation
+
+
+
+
+
+
+
+
+
+ Clock Settings
+
+
+
+
+
+
+
+
+
+ Instance Parameters
+
+
+
+
+
+
+
+
+
+ Project Settings
+
+
+
+
+
+
+
+
+
+ HDL Example
+
+
+
+
+
+
+
+
+
+ Generation
+
+
+
+
+
+
+
+
+
+ Connections
+
+
+
+
+
+
+
+
+
+ Data Path
+
+
+
+
+
+
+
+
+
+ Domains
+
+
+
+
+
+
+
+
+
+ 0
+
+ 0
+ dock.PlaceholderList
+
+
+ dock.single.Parameter\ Editor
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 0
+ - 0
+ - dock.single.Parameter\ Editor
+
+
+
+
+
+
+
+
+ Parameter Editor
+
+
+
+
+
+
+
+
+
+ 0
+
+ 0
+ dock.PlaceholderList
+
+
+ dock.single.Block\ Symbol
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 0
+ - 0
+ - dock.single.Block\ Symbol
+
+
+
+ dock.single.Element\ Docs
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 1
+ - 1
+ - dock.single.Element\ Docs
+
+
+
+
+
+
+
+
+ Block Symbol
+
+
+
+
+
+
+
+
+
+ Element Docs
+
+
+
+
+
+
+
+
+
+ 0
+
+ 0
+ dock.PlaceholderList
+
+
+ dock.single.Presets
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 0
+ - 0
+ - dock.single.Presets
+
+
+
+
+
+
+
+
+ Presets
+
+
+
+
+
+
+
+
+
+ 0
+
+ 0
+ dock.PlaceholderList
+
+
+ dock.single.Messages
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 0
+ - 0
+ - dock.single.Messages
+
+
+
+
+
+
+
+
+ Messages
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ccontrol south
+ true
+
+
+
+ 0
+ dock.PlaceholderList
+
+
+
+
+
+
+ dock.CContentArea.minimize
+
+
+
+
+
+
+
+
+ ccontrol north
+ true
+
+
+
+ 0
+ dock.PlaceholderList
+
+
+
+
+
+
+ dock.CContentArea.minimize
+
+
+
+
+
+
+
+
+ external
+ true
+
+
+ 0
+ dock.PlaceholderList
+
+
+
+
+
+
+ dock.CExternalizeArea
+
+
+
+
+
+
+
+
+ ccontrol east
+ true
+
+
+
+ 0
+ dock.PlaceholderList
+
+
+
+
+
+
+ dock.CContentArea.minimize
+
+
+
+
+
+
+
+
+ ccontrol west
+ true
+
+
+
+ 0
+ dock.PlaceholderList
+
+
+
+
+
+
+ dock.CContentArea.minimize
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ccontrol center
+ true
+
+ false
+
+
+
+
+ dock.single.Library
+
+
+ 0
+ dock.PlaceholderList
+
+
+
+
+ dock.single.Hierarchy
+
+
+
+
+
+
+
+
+ dock.single.Clocks
+ dock.single.Project\ Settings
+ dock.single.Generation
+ dock.single.Instrumentation\ \-\ Beta
+ dock.single.Connections
+ dock.single.Parameters
+ dock.single.Connections\ \-\ Beta
+ dock.single.Clock\ Settings
+ dock.single.Address\ Map
+ dock.single.System\ Contents
+ dock.single.Interconnect\ Requirements
+ dock.single.Instance\ Parameters
+ dock.single.Clock\ Domains\ \-\ Beta
+ dock.single.Data\ Path
+ dock.single.Data\ Path\ \-\ Beta
+ dock.single.Instrumentation
+ dock.single.Domains
+ dock.single.HDL\ Example
+
+
+ 0
+ dock.PlaceholderList
+
+
+
+
+ dock.single.Parameter\ Editor
+
+
+
+
+
+
+ dock.single.Element\ Docs
+ dock.single.Block\ Symbol
+
+
+
+
+ dock.single.Presets
+
+
+
+
+
+
+ dock.single.Messages
+
+
+ 0
+ dock.PlaceholderList
+
+
+
+
+
+
+
+
+
+ dock.CContentArea.center
+
+
+
+
+
+
+
+ Hierarchy
+
+
+
+
+
+
+
+
+
+ Messages
+
+
+
+
+
+
+
+ 0
+
+ 0
+ dock.PlaceholderList
+
+
+ dock.single.System\ Contents
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 0
+ - 0
+ - dock.single.System\ Contents
+
+
+
+ dock.single.Address\ Map
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 1
+ - 1
+ - dock.single.Address\ Map
+
+
+
+ dock.single.Instrumentation\ \-\ Beta
+
+
+
+
+ dock.single.Instance\ Parameters
+
+
+
+
+ dock.single.Project\ Settings
+
+ - true
+ -
+
- id
+ - index
+ - placeholder
+
+ - 2
+ - 2
+ - dock.single.Project\ Settings
+
+
+
+ dock.single.Clocks
+
+
+
+
+ dock.single.Clock\ Domains\ \-\ Beta
+
+
+
+
+ dock.single.Connections\ \-\ Beta
+
+
+
+
+ dock.single.Interconnect\ Requirements
+
+
+
+
+ dock.single.Data\ Path\ \-\ Beta
+
+
+
+
+ dock.single.Parameters
+
+
+
+
+
+
+
+
+
+ System Contents
+
+
+
+
+
+
+
+
+
+ Address Map
+
+
+
+
+
+
+
+
+
+ Project Settings
+
+
+
+
+
+
+
+
+
+
+
+ Library
+
+
+
+
+
+
+
+
+
+
+
+ true
+
+
+ 0
+ dock.PlaceholderList
+
+
+
+
+
+
+ dock.CExternalizeArea
+
+
+
+
+
+
+
+
+ true
+
+
+
+ 0
+ dock.PlaceholderList
+
+
+ dock.single.Hierarchy
+
+
+
+
+
+
+
+
+ dock.CContentArea.minimize
+
+
+
+
+
+
+
+
+ true
+
+
+
+ 0
+ dock.PlaceholderList
+
+
+
+
+
+
+ dock.CContentArea.minimize
+
+
+
+
+
+
+
+
+ true
+
+
+
+ 0
+ dock.PlaceholderList
+
+
+
+
+
+
+ dock.CContentArea.minimize
+
+
+
+
+
+
+
+
+ true
+
+
+
+ 0
+ dock.PlaceholderList
+
+
+
+
+
+
+ dock.CContentArea.minimize
+
+
+
+
+
+
+
+
+
+ dock.single.Clock\ Domains\ \-\ Beta
+
+
+
+
+
+
+
+
+
+ 6
+ dock.single.Clock\ Domains\ \-\ Beta
+
+
+
+
+
+
+ Clock Domains - Beta
+
+
+
+
+
+
+
+
+
+ dock.single.Instance\ Parameters
+
+
+
+
+
+
+
+
+
+ 3
+ dock.single.Instance\ Parameters
+
+
+
+
+
+
+ Instance Parameters
+
+
+
+
+
+
+
+
+
+ dock.single.Clocks
+
+
+
+
+
+
+
+
+
+ 5
+ dock.single.Clocks
+
+
+
+
+
+
+ Clocks
+
+
+
+
+
+
+
+
+
+ dock.single.Connections\ \-\ Beta
+
+
+
+
+
+
+
+
+
+ 7
+ dock.single.Connections\ \-\ Beta
+
+
+
+
+
+
+ Connections - Beta
+
+
+
+
+
+
+
+
+
+ dock.single.Parameters
+
+
+
+
+
+
+
+
+
+ 10
+ dock.single.Parameters
+
+
+
+
+
+
+ Parameters
+
+
+
+
+
+
+
+
+
+ dock.single.Presets
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Presets
+
+
+
+
+
+
+
+
+
+ dock.single.Instrumentation\ \-\ Beta
+
+
+
+
+
+
+
+
+
+ 2
+ dock.single.Instrumentation\ \-\ Beta
+
+
+
+
+
+
+ Instrumentation - Beta
+
+
+
+
+
+
+
+
+
+ dock.single.Interconnect\ Requirements
+
+
+
+
+
+
+
+
+
+ 8
+ dock.single.Interconnect\ Requirements
+
+
+
+
+
+
+ Interconnect Requirements
+
+
+
+
+
+
+
+
+
+ dock.single.Block\ Symbol
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Block Symbol
+
+
+
+
+
+
+
+
+
+ dock.single.Data\ Path\ \-\ Beta
+
+
+
+
+
+
+
+
+
+ 9
+ dock.single.Data\ Path\ \-\ Beta
+
+
+
+
+
+
+ Data Path - Beta
+
+
+
+
+
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Project\ Settings
+
+
+
+
+
+
+
+
+
+
+ 5
+ dock.single.Project\ Settings
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Library
+
+
+
+
+
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.System\ Contents
+
+
+
+
+
+
+
+
+
+
+ 0
+ dock.single.System\ Contents
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Clock\ Domains\ \-\ Beta
+
+
+
+
+
+
+
+
+
+
+ 9
+ dock.single.Clock\ Domains\ \-\ Beta
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Instance\ Parameters
+
+
+
+
+
+
+
+
+
+
+ 4
+ dock.single.Instance\ Parameters
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Address\ Map
+
+
+
+
+
+
+
+
+
+
+ 1
+ dock.single.Address\ Map
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Clocks
+
+
+
+
+
+
+
+
+
+
+ 3
+ dock.single.Clocks
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Connections\ \-\ Beta
+
+
+
+
+
+
+
+
+
+
+ 7
+ dock.single.Connections\ \-\ Beta
+
+
+
+
+
+
+
+ dock.mode.minimized
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Parameters
+
+
+
+
+
+
+
+
+
+ 1
+ dock.single.Parameters
+
+
+
+
+ dock.mode.minimized
+ ccontrol west
+
+
+ 0
+ false
+ 400
+ dock.single.Parameters
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Presets
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Messages
+
+
+
+
+
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Instrumentation\ \-\ Beta
+
+
+
+
+
+
+
+
+
+
+ 2
+ dock.single.Instrumentation\ \-\ Beta
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Interconnect\ Requirements
+
+
+
+
+
+
+
+
+
+
+ 8
+ dock.single.Interconnect\ Requirements
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Block\ Symbol
+
+
+
+
+
+
+
+
+
+ 0
+ dock.single.Block\ Symbol
+
+
+
+
+
+
+
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Data\ Path\ \-\ Beta
+
+
+
+
+
+
+
+
+
+
+ 8
+ dock.single.Data\ Path\ \-\ Beta
+
+
+
+
+
+
+
+ dock.mode.minimized
+ dock.mode.normal
+
+
+
+ dock.mode.normal
+ ccontrol center
+
+
+ dock.single.Hierarchy
+
+
+
+
+
+
+
+
+
+ dock.mode.minimized
+ ccontrol north
+
+
+ 0
+ false
+ 400
+ dock.single.Hierarchy
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ eclipse
+
+
\ No newline at end of file
diff --git a/examples/hdl4se_riscv/de1/.qsys_edit/preferences.xml b/examples/hdl4se_riscv/de1/.qsys_edit/preferences.xml
new file mode 100644
index 0000000000000000000000000000000000000000..b0ee87312379e8b8efa076288681f3cae6c6206b
--- /dev/null
+++ b/examples/hdl4se_riscv/de1/.qsys_edit/preferences.xml
@@ -0,0 +1,20 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/examples/hdl4se_riscv/de1/de1_riscv.asm.rpt b/examples/hdl4se_riscv/de1/de1_riscv.asm.rpt
index 56051246aa91db567d45a394e468b233e2152ff2..34a2f22e12debc7534146d688082b8d1fb06298a 100644
--- a/examples/hdl4se_riscv/de1/de1_riscv.asm.rpt
+++ b/examples/hdl4se_riscv/de1/de1_riscv.asm.rpt
@@ -1,5 +1,5 @@
Assembler report for de1_riscv
-Sat Aug 28 10:56:11 2021
+Sat Aug 28 16:28:45 2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
@@ -37,7 +37,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Sat Aug 28 10:56:11 2021 ;
+; Assembler Status ; Successful - Sat Aug 28 16:28:45 2021 ;
; Revision Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ;
; Family ; Cyclone V ;
@@ -92,8 +92,8 @@ applicable agreement for further details.
; Option ; Setting ;
+----------------+--------------------------------------------------------------------+
; Device ; 5CSEMA5F31C6 ;
-; JTAG usercode ; 0x0122B7FD ;
-; Checksum ; 0x0122B7FD ;
+; JTAG usercode ; 0x01248964 ;
+; Checksum ; 0x01248964 ;
+----------------+--------------------------------------------------------------------+
@@ -103,13 +103,13 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
- Info: Processing started: Sat Aug 28 10:55:56 2021
+ Info: Processing started: Sat Aug 28 16:28:30 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 661 megabytes
- Info: Processing ended: Sat Aug 28 10:56:11 2021
+ Info: Peak virtual memory: 660 megabytes
+ Info: Processing ended: Sat Aug 28 16:28:45 2021
Info: Elapsed time: 00:00:15
- Info: Total CPU time (on all processors): 00:00:15
+ Info: Total CPU time (on all processors): 00:00:16
diff --git a/examples/hdl4se_riscv/de1/de1_riscv.done b/examples/hdl4se_riscv/de1/de1_riscv.done
index dde85829518822dc1232a811112624b2ad7c44e6..da4f4c18954f58b9607f6a186c8933b812486ef2 100644
--- a/examples/hdl4se_riscv/de1/de1_riscv.done
+++ b/examples/hdl4se_riscv/de1/de1_riscv.done
@@ -1 +1 @@
-Sat Aug 28 10:56:46 2021
+Sat Aug 28 16:29:20 2021
diff --git a/examples/hdl4se_riscv/de1/de1_riscv.fit.rpt b/examples/hdl4se_riscv/de1/de1_riscv.fit.rpt
index 563bfb1a6fc1c0d27a022e4c23cbeb265f2145b7..933885516d2aab460b610f60ceeb26345560887a 100644
--- a/examples/hdl4se_riscv/de1/de1_riscv.fit.rpt
+++ b/examples/hdl4se_riscv/de1/de1_riscv.fit.rpt
@@ -1,5 +1,5 @@
Fitter report for de1_riscv
-Sat Aug 28 10:55:52 2021
+Sat Aug 28 16:28:25 2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
@@ -67,15 +67,15 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------------+---------------------------------------------+
-; Fitter Status ; Successful - Sat Aug 28 10:55:51 2021 ;
+; Fitter Status ; Successful - Sat Aug 28 16:28:25 2021 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ;
; Family ; Cyclone V ;
; Device ; 5CSEMA5F31C6 ;
; Timing Models ; Preliminary ;
-; Logic utilization (in ALMs) ; 2,494 / 32,070 ( 8 % ) ;
-; Total registers ; 1863 ;
+; Logic utilization (in ALMs) ; 2,514 / 32,070 ( 8 % ) ;
+; Total registers ; 1859 ;
; Total pins ; 204 / 457 ( 45 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 66,560 / 4,065,280 ( 2 % ) ;
@@ -154,12 +154,12 @@ applicable agreement for further details.
; Number detected on machine ; 4 ;
; Maximum allowed ; 2 ;
; ; ;
-; Average used ; 1.41 ;
+; Average used ; 1.28 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
-; Processor 2 ; 41.2% ;
+; Processor 2 ; 28.2% ;
; Processors 3-4 ; 0.0% ;
+----------------------------+-------------+
@@ -1118,201 +1118,131 @@ applicable agreement for further details.
; riscv_core:core|rs2[31]~_Duplicate_4 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; riscv_core:core|rs2[31]~_Duplicate_5 ; Q ; ;
; riscv_core:core|rs2[31]~_Duplicate_5 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component|mult_61n:auto_generated|Mult0~781 ; AY ; ;
; riscv_core:core|rs2[31]~_Duplicate_5 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; riscv_core:core|rs2[31]~_Duplicate_6 ; Q ; ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[24] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[24]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[47] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[47]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[50] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[50]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[52] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[52]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[53] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[53]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[56] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[56]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[58] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[58]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[60] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[60]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[75] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[75]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[79] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[79]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[92] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[92]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[93] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[93]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[96] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[96]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[102] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[102]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[104] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[104]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[108] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[108]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[136] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[136]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[142] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[142]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[151] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[151]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[156] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[156]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[161] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[161]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[162] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[162]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[163] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[163]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[164] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[164]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[165] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[165]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[166] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[166]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[167] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[167]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[169] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[169]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[174] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[174]~DUPLICATE ; ; ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_char_ready ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_char_ready~DUPLICATE ; ; ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7]~DUPLICATE ; ; ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0]~DUPLICATE ; ; ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[4]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[17] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[17]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[30] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[30]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[40] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[40]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[45] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[45]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[78] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[78]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[83] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[83]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[84] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[84]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[85] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[85]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[112] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[112]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[120] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[120]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[126] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[126]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[157] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[157]~DUPLICATE ; ; ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[178] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[178]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[184] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[184]~DUPLICATE ; ; ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[188] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[188]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[190] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[190]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[189] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[189]~DUPLICATE ; ; ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[213] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[213]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[216] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[216]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[282] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[282]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[283] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[283]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[284] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[284]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[310] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[310]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[70] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[70]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[128] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[128]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[129] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[129]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[225] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[225]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[258] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[258]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[260] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[260]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[65] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[65]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[97] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[97]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[131] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[131]~DUPLICATE ; ; ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[132] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[132]~DUPLICATE ; ; ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[133] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[133]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[160] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[160]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[170] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[170]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[192] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[192]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[196] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[196]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[204] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[204]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[205] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[205]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[227] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[227]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[230] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[230]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[256] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[256]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[259] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[259]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[261] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[261]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[265] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[265]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[274] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[274]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[275] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[275]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[137] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[137]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[138] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[138]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[139] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[139]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[224] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[224]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[225] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[225]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[235] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[235]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[240] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[240]~DUPLICATE ; ; ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[277] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[277]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[289] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[289]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[295] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[295]~DUPLICATE ; ; ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[320] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[320]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[321] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[321]~DUPLICATE ; ; ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[322] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[322]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[323] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[323]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[324] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[324]~DUPLICATE ; ; ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[325] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[325]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[344] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[344]~DUPLICATE ; ; ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[347] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[347]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[67] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[67]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[70] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[70]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[73] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[73]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[107] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[107]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[118] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[118]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[119] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[119]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[120] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[120]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[146] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[146]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[147] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[147]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[180] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[180]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[184] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[184]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[189] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[189]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[213] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[213]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[215] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[215]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[216] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[216]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[217] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[217]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[257] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[257]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[283] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[283]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[287] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[287]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[289] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[289]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[290] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[290]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[304] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[304]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[306] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[306]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[316] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[316]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[318] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[318]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[350] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[350]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[354] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[354]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[356] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[356]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[362] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[362]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[367] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[367]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[368] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[368]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[369] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[369]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[370] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[370]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[383] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[383]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[57] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[57]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[329] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[329]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[335] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[335]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[353] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[353]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[361] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[361]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[364] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[364]~DUPLICATE ; ; ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[369] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFStage[369]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[2]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[4] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[4]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[41] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[41]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[46] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[46]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[80] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[80]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[83] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[83]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[95] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[95]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[143] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[143]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[144] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[144]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[145] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[145]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[151] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[151]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[178] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[178]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[182] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[182]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[214] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[214]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[247] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[247]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[248] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[248]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[249] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[249]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[251] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[251]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[253] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[253]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[255] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[255]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[258] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[258]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[260] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[260]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[320] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[320]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[354] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[354]~DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[64] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[64]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[66] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[66]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[97] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[97]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[98] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[98]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[101] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[101]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[103] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[103]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[104] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[104]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[128] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[128]~DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[129] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[129]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[138] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[138]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[163] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[163]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[169] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[169]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[170] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[170]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[174] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[174]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[224] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[224]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[130] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[130]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[134] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[134]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[136] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[136]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[166] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[166]~DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[225] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[225]~DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[226] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[226]~DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[227] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[227]~DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[228] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[228]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[230] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[230]~DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[231] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[231]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[232] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[232]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[236] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[236]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[233] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[233]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[234] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[234]~DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[237] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[237]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[238] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[238]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[240] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[240]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[241] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[241]~DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[242] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[242]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[257] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[257]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[263] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[263]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[264] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[264]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[265] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[265]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[268] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[268]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[269] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[269]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[270] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[270]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[271] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[271]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[273] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[273]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[274] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[274]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[258] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[258]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[259] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[259]~DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[275] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[275]~DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[276] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[276]~DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[278] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[278]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[289] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[289]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[290] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[290]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[291] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[291]~DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[320] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[320]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[326] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[326]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[327] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[327]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[329] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[329]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[330] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[330]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[331] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[331]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[332] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[332]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[321] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[321]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[323] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[323]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[324] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[324]~DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[335] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[335]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[336] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[336]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[338] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[338]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[339] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[339]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[340] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[340]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[341] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[341]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[343] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[343]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[346] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[346]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[352] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[352]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[354] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[354]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[362] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[362]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[342] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[342]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[370] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[370]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[381] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[381]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[382] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[382]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0]~DUPLICATE ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[1]~DUPLICATE ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2]~DUPLICATE ; ; ;
; riscv_core:core|imm[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[2]~DUPLICATE ; ; ;
-; riscv_core:core|imm[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[5]~DUPLICATE ; ; ;
-; riscv_core:core|imm[12] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[12]~DUPLICATE ; ; ;
-; riscv_core:core|imm[14] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[14]~DUPLICATE ; ; ;
-; riscv_core:core|imm[15] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[15]~DUPLICATE ; ; ;
-; riscv_core:core|imm[16] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[16]~DUPLICATE ; ; ;
-; riscv_core:core|imm[17] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[17]~DUPLICATE ; ; ;
-; riscv_core:core|imm[18] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[18]~DUPLICATE ; ; ;
; riscv_core:core|imm[22] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[22]~DUPLICATE ; ; ;
+; riscv_core:core|imm[23] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[23]~DUPLICATE ; ; ;
; riscv_core:core|imm[25] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[25]~DUPLICATE ; ; ;
-; riscv_core:core|imm[31] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[31]~DUPLICATE ; ; ;
-; riscv_core:core|ldaddr[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|ldaddr[0]~DUPLICATE ; ; ;
+; riscv_core:core|imm[27] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|imm[27]~DUPLICATE ; ; ;
; riscv_core:core|ldaddr[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|ldaddr[1]~DUPLICATE ; ; ;
-; riscv_core:core|rs1[9]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[9]~_Duplicate_6DUPLICATE ; ; ;
-; riscv_core:core|rs1[19]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[19]~_Duplicate_6DUPLICATE ; ; ;
-; riscv_core:core|rs1[28]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[28]~_Duplicate_6DUPLICATE ; ; ;
-; riscv_core:core|rs1[31]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs1[31]~_Duplicate_6DUPLICATE ; ; ;
-; riscv_core:core|rs2[0]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[0]~_Duplicate_6DUPLICATE ; ; ;
-; riscv_core:core|rs2[1]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[1]~_Duplicate_6DUPLICATE ; ; ;
-; riscv_core:core|rs2[3]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[3]~_Duplicate_6DUPLICATE ; ; ;
-; riscv_core:core|rs2[4]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[4]~_Duplicate_6DUPLICATE ; ; ;
-; riscv_core:core|rs2[7]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[7]~_Duplicate_6DUPLICATE ; ; ;
-; riscv_core:core|rs2[10]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[10]~_Duplicate_6DUPLICATE ; ; ;
-; riscv_core:core|rs2[13]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[13]~_Duplicate_6DUPLICATE ; ; ;
-; riscv_core:core|rs2[17]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[17]~_Duplicate_6DUPLICATE ; ; ;
-; riscv_core:core|rs2[18]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[18]~_Duplicate_6DUPLICATE ; ; ;
-; riscv_core:core|rs2[28]~_Duplicate_6 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; riscv_core:core|rs2[28]~_Duplicate_6DUPLICATE ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg0FITTER_CREATED_FF ; Created ; Placement ; Location assignment ; Q ; ; ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg1FITTER_CREATED_FF ; Created ; Placement ; Location assignment ; Q ; ; ; ; ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg2FITTER_CREATED_FF ; Created ; Placement ; Location assignment ; Q ; ; ; ; ;
@@ -1354,8 +1284,8 @@ applicable agreement for further details.
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
+---------------------+---------------------+----------------------------+--------------------------+
; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 6036 ) ; 0.00 % ( 0 / 6036 ) ; 0.00 % ( 0 / 6036 ) ;
-; -- Achieved ; 0.00 % ( 0 / 6036 ) ; 0.00 % ( 0 / 6036 ) ; 0.00 % ( 0 / 6036 ) ;
+; -- Requested ; 0.00 % ( 0 / 6167 ) ; 0.00 % ( 0 / 6167 ) ; 0.00 % ( 0 / 6167 ) ;
+; -- Achieved ; 0.00 % ( 0 / 6167 ) ; 0.00 % ( 0 / 6167 ) ; 0.00 % ( 0 / 6167 ) ;
; ; ; ; ;
; Routing (by net) ; ; ; ;
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
@@ -1378,7 +1308,7 @@ applicable agreement for further details.
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 6027 ) ; N/A ; Source File ; N/A ; ;
+; Top ; 0.00 % ( 0 / 6158 ) ; N/A ; Source File ; N/A ; ;
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 9 ) ; N/A ; Source File ; N/A ; ;
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
@@ -1394,44 +1324,44 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1
+-------------------------------------------------------------+--------------------+-------+
; Resource ; Usage ; % ;
+-------------------------------------------------------------+--------------------+-------+
-; Logic utilization (ALMs needed / total ALMs on device) ; 2,494 / 32,070 ; 8 % ;
-; ALMs needed [=A-B+C] ; 2,494 ; ;
-; [A] ALMs used in final placement [=a+b+c+d] ; 2,611 / 32,070 ; 8 % ;
-; [a] ALMs used for LUT logic and registers ; 427 ; ;
-; [b] ALMs used for LUT logic ; 1,679 ; ;
-; [c] ALMs used for registers ; 405 ; ;
+; Logic utilization (ALMs needed / total ALMs on device) ; 2,514 / 32,070 ; 8 % ;
+; ALMs needed [=A-B+C] ; 2,514 ; ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 2,563 / 32,070 ; 8 % ;
+; [a] ALMs used for LUT logic and registers ; 510 ; ;
+; [b] ALMs used for LUT logic ; 1,597 ; ;
+; [c] ALMs used for registers ; 356 ; ;
; [d] ALMs used for memory (up to half of total ALMs) ; 100 ; ;
-; [B] Estimate of ALMs recoverable by dense packing ; 175 / 32,070 ; < 1 % ;
-; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 58 / 32,070 ; < 1 % ;
-; [a] Due to location constrained logic ; 3 ; ;
+; [B] Estimate of ALMs recoverable by dense packing ; 109 / 32,070 ; < 1 % ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 60 / 32,070 ; < 1 % ;
+; [a] Due to location constrained logic ; 2 ; ;
; [b] Due to LAB-wide signal conflicts ; 0 ; ;
-; [c] Due to LAB input limits ; 55 ; ;
+; [c] Due to LAB input limits ; 58 ; ;
; [d] Due to virtual I/Os ; 0 ; ;
; ; ; ;
; Difficulty packing design ; Low ; ;
; ; ; ;
-; Total LABs: partially or completely used ; 331 / 3,207 ; 10 % ;
-; -- Logic LABs ; 321 ; ;
+; Total LABs: partially or completely used ; 296 / 3,207 ; 9 % ;
+; -- Logic LABs ; 286 ; ;
; -- Memory LABs (up to half of total LABs) ; 10 ; ;
; ; ; ;
-; Combinational ALUT usage for logic ; 3,763 ; ;
-; -- 7 input functions ; 47 ; ;
-; -- 6 input functions ; 327 ; ;
-; -- 5 input functions ; 472 ; ;
-; -- 4 input functions ; 831 ; ;
-; -- <=3 input functions ; 2,086 ; ;
-; Combinational ALUT usage for route-throughs ; 547 ; ;
+; Combinational ALUT usage for logic ; 3,827 ; ;
+; -- 7 input functions ; 53 ; ;
+; -- 6 input functions ; 334 ; ;
+; -- 5 input functions ; 487 ; ;
+; -- 4 input functions ; 853 ; ;
+; -- <=3 input functions ; 2,100 ; ;
+; Combinational ALUT usage for route-throughs ; 486 ; ;
; Memory ALUT usage ; 103 ; ;
; -- 64-address deep ; 0 ; ;
; -- 32-address deep ; 103 ; ;
; ; ; ;
-; Dedicated logic registers ; 1,863 ; ;
+; Dedicated logic registers ; 1,859 ; ;
; -- By type: ; ; ;
-; -- Primary logic registers ; 1,662 / 64,140 ; 3 % ;
-; -- Secondary logic registers ; 201 / 64,140 ; < 1 % ;
+; -- Primary logic registers ; 1,731 / 64,140 ; 3 % ;
+; -- Secondary logic registers ; 128 / 64,140 ; < 1 % ;
; -- By function: ; ; ;
-; -- Design implementation registers ; 1,668 ; ;
-; -- Routing optimization registers ; 195 ; ;
+; -- Design implementation registers ; 1,734 ; ;
+; -- Routing optimization registers ; 125 ; ;
; ; ; ;
; Virtual pins ; 0 ; ;
; I/O pins ; 204 / 457 ; 45 % ;
@@ -1484,11 +1414,11 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1
; Impedance control blocks ; 0 / 4 ; 0 % ;
; Hard Memory Controllers ; 0 / 2 ; 0 % ;
; Average interconnect usage (total/H/V) ; 2% / 2% / 2% ; ;
-; Peak interconnect usage (total/H/V) ; 30% / 31% / 27% ; ;
-; Maximum fan-out ; 2099 ; ;
-; Highest non-global fan-out ; 246 ; ;
-; Total fan-out ; 21324 ; ;
-; Average fan-out ; 3.15 ; ;
+; Peak interconnect usage (total/H/V) ; 27% / 26% / 29% ; ;
+; Maximum fan-out ; 2095 ; ;
+; Highest non-global fan-out ; 235 ; ;
+; Total fan-out ; 21578 ; ;
+; Average fan-out ; 3.19 ; ;
+-------------------------------------------------------------+--------------------+-------+
@@ -1497,44 +1427,44 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1
+-------------------------------------------------------------+-----------------------+--------------------------------+
; Statistic ; Top ; hard_block:auto_generated_inst ;
+-------------------------------------------------------------+-----------------------+--------------------------------+
-; Logic utilization (ALMs needed / total ALMs on device) ; 2494 / 32070 ( 8 % ) ; 0 / 32070 ( 0 % ) ;
-; ALMs needed [=A-B+C] ; 2494 ; 0 ;
-; [A] ALMs used in final placement [=a+b+c+d] ; 2611 / 32070 ( 8 % ) ; 0 / 32070 ( 0 % ) ;
-; [a] ALMs used for LUT logic and registers ; 427 ; 0 ;
-; [b] ALMs used for LUT logic ; 1679 ; 0 ;
-; [c] ALMs used for registers ; 405 ; 0 ;
+; Logic utilization (ALMs needed / total ALMs on device) ; 2514 / 32070 ( 8 % ) ; 0 / 32070 ( 0 % ) ;
+; ALMs needed [=A-B+C] ; 2514 ; 0 ;
+; [A] ALMs used in final placement [=a+b+c+d] ; 2563 / 32070 ( 8 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] ALMs used for LUT logic and registers ; 510 ; 0 ;
+; [b] ALMs used for LUT logic ; 1597 ; 0 ;
+; [c] ALMs used for registers ; 356 ; 0 ;
; [d] ALMs used for memory (up to half of total ALMs) ; 100 ; 0 ;
-; [B] Estimate of ALMs recoverable by dense packing ; 175 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
-; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 58 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
-; [a] Due to location constrained logic ; 3 ; 0 ;
+; [B] Estimate of ALMs recoverable by dense packing ; 109 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 60 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
+; [a] Due to location constrained logic ; 2 ; 0 ;
; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
-; [c] Due to LAB input limits ; 55 ; 0 ;
+; [c] Due to LAB input limits ; 58 ; 0 ;
; [d] Due to virtual I/Os ; 0 ; 0 ;
; ; ; ;
; Difficulty packing design ; Low ; Low ;
; ; ; ;
-; Total LABs: partially or completely used ; 331 / 3207 ( 10 % ) ; 0 / 3207 ( 0 % ) ;
-; -- Logic LABs ; 321 ; 0 ;
+; Total LABs: partially or completely used ; 296 / 3207 ( 9 % ) ; 0 / 3207 ( 0 % ) ;
+; -- Logic LABs ; 286 ; 0 ;
; -- Memory LABs (up to half of total LABs) ; 10 ; 0 ;
; ; ; ;
-; Combinational ALUT usage for logic ; 3866 ; 0 ;
-; -- 7 input functions ; 47 ; 0 ;
-; -- 6 input functions ; 327 ; 0 ;
-; -- 5 input functions ; 472 ; 0 ;
-; -- 4 input functions ; 831 ; 0 ;
-; -- <=3 input functions ; 2086 ; 0 ;
-; Combinational ALUT usage for route-throughs ; 547 ; 0 ;
+; Combinational ALUT usage for logic ; 3930 ; 0 ;
+; -- 7 input functions ; 53 ; 0 ;
+; -- 6 input functions ; 334 ; 0 ;
+; -- 5 input functions ; 487 ; 0 ;
+; -- 4 input functions ; 853 ; 0 ;
+; -- <=3 input functions ; 2100 ; 0 ;
+; Combinational ALUT usage for route-throughs ; 486 ; 0 ;
; Memory ALUT usage ; 103 ; 0 ;
; -- 64-address deep ; 0 ; 0 ;
; -- 32-address deep ; 103 ; 0 ;
; ; ; ;
; Dedicated logic registers ; 0 ; 0 ;
; -- By type: ; ; ;
-; -- Primary logic registers ; 1662 / 64140 ( 3 % ) ; 0 / 64140 ( 0 % ) ;
-; -- Secondary logic registers ; 201 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ;
+; -- Primary logic registers ; 1731 / 64140 ( 3 % ) ; 0 / 64140 ( 0 % ) ;
+; -- Secondary logic registers ; 128 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ;
; -- By function: ; ; ;
-; -- Design implementation registers ; 1668 ; 0 ;
-; -- Routing optimization registers ; 195 ; 0 ;
+; -- Design implementation registers ; 1734 ; 0 ;
+; -- Routing optimization registers ; 125 ; 0 ;
; ; ; ;
; ; ; ;
; Virtual pins ; 0 ; 0 ;
@@ -1551,18 +1481,18 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1
; PLL Reference Clock Select Block ; 0 / 6 ( 0 % ) ; 1 / 6 ( 16 % ) ;
; ; ; ;
; Connections ; ; ;
-; -- Input Connections ; 2246 ; 0 ;
-; -- Registered Input Connections ; 1925 ; 0 ;
-; -- Output Connections ; 60 ; 2186 ;
+; -- Input Connections ; 2334 ; 0 ;
+; -- Registered Input Connections ; 2014 ; 0 ;
+; -- Output Connections ; 60 ; 2274 ;
; -- Registered Output Connections ; 0 ; 0 ;
; ; ; ;
; Internal Connections ; ; ;
-; -- Total Connections ; 22412 ; 2220 ;
-; -- Registered Connections ; 9803 ; 0 ;
+; -- Total Connections ; 22666 ; 2308 ;
+; -- Registered Connections ; 10066 ; 0 ;
; ; ; ;
; External Connections ; ; ;
-; -- Top ; 120 ; 2186 ;
-; -- hard_block:auto_generated_inst ; 2186 ; 0 ;
+; -- Top ; 120 ; 2274 ;
+; -- hard_block:auto_generated_inst ; 2274 ; 0 ;
; ; ; ;
; Partition Interface ; ; ;
; -- Input Ports ; 32 ; 2 ;
@@ -1600,7 +1530,7 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1
; KEY[0] ; AA14 ; 3B ; 36 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
; KEY[1] ; AA15 ; 3B ; 36 ; 0 ; 17 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
; KEY[2] ; W15 ; 3B ; 40 ; 0 ; 0 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
-; KEY[3] ; Y16 ; 3B ; 40 ; 0 ; 17 ; 88 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
+; KEY[3] ; Y16 ; 3B ; 40 ; 0 ; 17 ; 180 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
; SW[0] ; AB12 ; 3A ; 12 ; 0 ; 17 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
; SW[1] ; AC12 ; 3A ; 16 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
; SW[2] ; AF9 ; 3A ; 8 ; 0 ; 34 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
@@ -1608,9 +1538,9 @@ The pin-out file can be found in D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1
; SW[4] ; AD11 ; 3A ; 2 ; 0 ; 40 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
; SW[5] ; AD12 ; 3A ; 16 ; 0 ; 17 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
; SW[6] ; AE11 ; 3A ; 4 ; 0 ; 34 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
-; SW[7] ; AC9 ; 3A ; 4 ; 0 ; 0 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
-; SW[8] ; AD10 ; 3A ; 4 ; 0 ; 17 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
-; SW[9] ; AE12 ; 3A ; 2 ; 0 ; 57 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
+; SW[7] ; AC9 ; 3A ; 4 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
+; SW[8] ; AD10 ; 3A ; 4 ; 0 ; 17 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
+; SW[9] ; AE12 ; 3A ; 2 ; 0 ; 57 ; 6 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
; TD_CLK27 ; H15 ; 8A ; 40 ; 81 ; 0 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
; TD_DATA[0] ; D2 ; 8A ; 12 ; 81 ; 34 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
; TD_DATA[1] ; B1 ; 8A ; 16 ; 81 ; 51 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ;
@@ -2776,12 +2706,12 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
; -- CLKIN(3) source ; N/A ;
; -- PLL Output Counter ; ;
; -- clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER ; ;
-; -- Output Clock Frequency ; 100.0 MHz ;
+; -- Output Clock Frequency ; 50.0 MHz ;
; -- Output Clock Location ; PLLOUTPUTCOUNTER_X0_Y20_N1 ;
-; -- C Counter Odd Divider Even Duty Enable ; On ;
+; -- C Counter Odd Divider Even Duty Enable ; Off ;
; -- Duty Cycle ; 50.0000 ;
; -- Phase Shift ; 0.000000 degrees ;
-; -- C Counter ; 3 ;
+; -- C Counter ; 6 ;
; -- C Counter PH Mux PRST ; 0 ;
; -- C Counter PRST ; 1 ;
; ; ;
@@ -2793,11 +2723,12 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
+----------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
-; |de1_riscv ; 2493.5 (64.7) ; 2609.5 (70.4) ; 173.0 (6.5) ; 57.0 (0.8) ; 100.0 (0.0) ; 3763 (95) ; 1863 (66) ; 0 (0) ; 66560 ; 9 ; 10 ; 204 ; 0 ; |de1_riscv ; work ;
-; |altera_uart:uart| ; 18.5 (0.0) ; 20.5 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 36 (0) ; 29 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart ; work ;
-; |altera_uart_regs:the_altera_uart_regs| ; 0.9 (0.9) ; 1.2 (1.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_regs:the_altera_uart_regs ; work ;
-; |altera_uart_rx:the_altera_uart_rx| ; 17.6 (16.9) ; 19.3 (18.7) ; 1.7 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 35 (35) ; 27 (25) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx ; work ;
-; |altera_std_synchronizer:the_altera_std_synchronizer| ; 0.7 (0.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer ; work ;
+; |de1_riscv ; 2514.0 (68.1) ; 2562.0 (67.5) ; 108.0 (2.1) ; 60.0 (2.7) ; 100.0 (0.0) ; 3827 (99) ; 1859 (66) ; 0 (0) ; 66560 ; 9 ; 10 ; 204 ; 0 ; |de1_riscv ; work ;
+; |altera_uart:uart| ; 56.4 (0.0) ; 62.2 (0.0) ; 6.1 (0.0) ; 0.3 (0.0) ; 0.0 (0.0) ; 89 (0) ; 98 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart ; work ;
+; |altera_uart_regs:the_altera_uart_regs| ; 18.3 (18.3) ; 20.5 (20.5) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (23) ; 31 (31) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_regs:the_altera_uart_regs ; work ;
+; |altera_uart_rx:the_altera_uart_rx| ; 23.2 (22.4) ; 26.3 (25.5) ; 3.4 (3.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 43 (43) ; 39 (37) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx ; work ;
+; |altera_std_synchronizer:the_altera_std_synchronizer| ; 0.7 (0.7) ; 0.8 (0.8) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer ; work ;
+; |altera_uart_tx:the_altera_uart_tx| ; 14.9 (14.9) ; 15.3 (15.3) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (23) ; 28 (28) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_tx:the_altera_uart_tx ; work ;
; |clk100M:clk100| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100 ; clk100M ;
; |clk100M_0002:clk100m_inst| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst ; clk100M ;
; |altera_pll:altera_pll_i| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i ; work ;
@@ -2807,69 +2738,69 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
; |regfile:regs| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs ; work ;
; |altsyncram:altsyncram_component| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component ; work ;
; |altsyncram_nco1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 1024 ; 1 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated ; work ;
-; |riscv_core:core| ; 2410.3 (842.3) ; 2518.6 (868.5) ; 164.5 (60.1) ; 56.2 (33.9) ; 100.0 (0.0) ; 3632 (1189) ; 1768 (314) ; 0 (0) ; 0 ; 0 ; 10 ; 0 ; 0 ; |de1_riscv|riscv_core:core ; work ;
-; |adder:add| ; 9.0 (0.0) ; 9.8 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add ; work ;
-; |lpm_add_sub:LPM_ADD_SUB_component| ; 9.0 (0.0) ; 9.8 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component ; work ;
-; |add_sub_tih:auto_generated| ; 9.0 (9.0) ; 9.8 (9.8) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (33) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component|add_sub_tih:auto_generated ; work ;
-; |div:div| ; 622.1 (0.0) ; 657.9 (0.0) ; 43.1 (0.0) ; 7.3 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 648 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div ; work ;
-; |lpm_divide:LPM_DIVIDE_component| ; 622.1 (0.0) ; 657.9 (0.0) ; 43.1 (0.0) ; 7.3 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 648 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component ; work ;
-; |lpm_divide_2jt:auto_generated| ; 622.1 (0.0) ; 657.9 (0.0) ; 43.1 (0.0) ; 7.3 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 648 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated ; work ;
-; |sign_div_unsign_8ai:divider| ; 622.1 (0.0) ; 657.9 (0.0) ; 43.1 (0.0) ; 7.3 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 648 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider ; work ;
-; |alt_u_div_nlf:divider| ; 622.1 (622.1) ; 657.9 (657.9) ; 43.1 (43.1) ; 7.3 (7.3) ; 0.0 (0.0) ; 1002 (1002) ; 648 (648) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider ; work ;
-; |div_s:divs| ; 869.4 (0.0) ; 917.4 (0.0) ; 60.4 (0.0) ; 12.5 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 806 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs ; work ;
-; |lpm_divide:LPM_DIVIDE_component| ; 869.4 (0.0) ; 917.4 (0.0) ; 60.4 (0.0) ; 12.5 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 806 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component ; work ;
-; |lpm_divide_s4t:auto_generated| ; 869.4 (0.0) ; 917.4 (0.0) ; 60.4 (0.0) ; 12.5 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 806 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated ; work ;
-; |sign_div_unsign_2sh:divider| ; 869.4 (80.0) ; 917.4 (76.2) ; 60.4 (1.6) ; 12.5 (5.4) ; 100.0 (0.0) ; 1278 (175) ; 806 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider ; work ;
-; |alt_u_div_5eg:divider| ; 772.8 (630.8) ; 822.7 (668.0) ; 57.0 (44.3) ; 7.1 (7.1) ; 90.0 (0.0) ; 1090 (987) ; 779 (682) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider ; work ;
-; |altshift_taps:DFFNumerator_rtl_0| ; 17.0 (0.0) ; 19.0 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 ; work ;
-; |shift_taps_hm21:auto_generated| ; 17.0 (2.9) ; 19.0 (4.0) ; 2.0 (1.1) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (8) ; 13 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated ; work ;
-; |altsyncram_9u91:altsyncram5| ; 11.1 (11.1) ; 11.5 (11.5) ; 0.4 (0.4) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 ; work ;
-; |cntr_9jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1 ; work ;
-; |altshift_taps:DFFNumerator_rtl_1| ; 16.5 (0.0) ; 18.5 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 ; work ;
-; |shift_taps_gm21:auto_generated| ; 16.5 (2.3) ; 18.5 (3.3) ; 2.0 (1.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (7) ; 14 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated ; work ;
+; |riscv_core:core| ; 2389.5 (830.1) ; 2432.3 (811.1) ; 99.9 (14.2) ; 57.1 (33.2) ; 100.0 (0.0) ; 3639 (1196) ; 1695 (293) ; 0 (0) ; 0 ; 0 ; 10 ; 0 ; 0 ; |de1_riscv|riscv_core:core ; work ;
+; |adder:add| ; 10.0 (0.0) ; 10.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add ; work ;
+; |lpm_add_sub:LPM_ADD_SUB_component| ; 10.0 (0.0) ; 10.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component ; work ;
+; |add_sub_tih:auto_generated| ; 10.0 (10.0) ; 10.0 (10.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (33) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component|add_sub_tih:auto_generated ; work ;
+; |div:div| ; 619.1 (0.0) ; 645.3 (0.0) ; 34.7 (0.0) ; 8.5 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 630 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div ; work ;
+; |lpm_divide:LPM_DIVIDE_component| ; 619.1 (0.0) ; 645.3 (0.0) ; 34.7 (0.0) ; 8.5 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 630 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component ; work ;
+; |lpm_divide_2jt:auto_generated| ; 619.1 (0.0) ; 645.3 (0.0) ; 34.7 (0.0) ; 8.5 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 630 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated ; work ;
+; |sign_div_unsign_8ai:divider| ; 619.1 (0.0) ; 645.3 (0.0) ; 34.7 (0.0) ; 8.5 (0.0) ; 0.0 (0.0) ; 1002 (0) ; 630 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider ; work ;
+; |alt_u_div_nlf:divider| ; 619.1 (619.1) ; 645.3 (645.3) ; 34.7 (34.7) ; 8.5 (8.5) ; 0.0 (0.0) ; 1002 (1002) ; 630 (630) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider ; work ;
+; |div_s:divs| ; 863.8 (0.0) ; 900.9 (0.0) ; 51.0 (0.0) ; 13.8 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 772 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs ; work ;
+; |lpm_divide:LPM_DIVIDE_component| ; 863.8 (0.0) ; 900.9 (0.0) ; 51.0 (0.0) ; 13.8 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 772 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component ; work ;
+; |lpm_divide_s4t:auto_generated| ; 863.8 (0.0) ; 900.9 (0.0) ; 51.0 (0.0) ; 13.8 (0.0) ; 100.0 (0.0) ; 1278 (0) ; 772 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated ; work ;
+; |sign_div_unsign_2sh:divider| ; 863.8 (79.8) ; 900.9 (76.0) ; 51.0 (1.8) ; 13.8 (5.6) ; 100.0 (0.0) ; 1278 (175) ; 772 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider ; work ;
+; |alt_u_div_5eg:divider| ; 767.4 (625.4) ; 807.2 (655.7) ; 47.9 (38.4) ; 8.2 (8.2) ; 90.0 (0.0) ; 1090 (987) ; 744 (654) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider ; work ;
+; |altshift_taps:DFFNumerator_rtl_0| ; 17.0 (0.0) ; 18.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0 ; work ;
+; |shift_taps_hm21:auto_generated| ; 17.0 (2.9) ; 18.5 (3.4) ; 1.5 (0.5) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (8) ; 14 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated ; work ;
+; |altsyncram_9u91:altsyncram5| ; 11.1 (11.1) ; 11.6 (11.6) ; 0.5 (0.5) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5 ; work ;
+; |cntr_9jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1 ; work ;
+; |altshift_taps:DFFNumerator_rtl_1| ; 16.5 (0.0) ; 18.0 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 14 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1 ; work ;
+; |shift_taps_gm21:auto_generated| ; 16.5 (2.3) ; 18.0 (2.8) ; 1.5 (0.5) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (7) ; 14 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated ; work ;
; |altsyncram_7u91:altsyncram5| ; 11.3 (11.3) ; 11.8 (11.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5 ; work ;
; |cntr_8jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1 ; work ;
-; |altshift_taps:DFFNumerator_rtl_2| ; 17.0 (0.0) ; 19.0 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 ; work ;
-; |shift_taps_bl21:auto_generated| ; 17.0 (2.9) ; 19.0 (4.0) ; 2.0 (1.1) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (8) ; 16 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated ; work ;
-; |altsyncram_rr91:altsyncram5| ; 11.1 (11.1) ; 11.5 (11.5) ; 0.4 (0.4) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 ; work ;
-; |cntr_0if:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1 ; work ;
-; |altshift_taps:DFFNumerator_rtl_3| ; 14.5 (0.0) ; 15.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 8 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 ; work ;
-; |shift_taps_9l21:auto_generated| ; 14.5 (2.3) ; 15.0 (2.6) ; 0.5 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 8 (5) ; 9 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated ; work ;
+; |altshift_taps:DFFNumerator_rtl_2| ; 17.0 (0.0) ; 18.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 12 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2 ; work ;
+; |shift_taps_bl21:auto_generated| ; 17.0 (2.9) ; 18.5 (3.4) ; 1.5 (0.5) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (8) ; 12 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated ; work ;
+; |altsyncram_rr91:altsyncram5| ; 11.1 (11.1) ; 11.6 (11.6) ; 0.5 (0.5) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5 ; work ;
+; |cntr_0if:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1 ; work ;
+; |altshift_taps:DFFNumerator_rtl_3| ; 14.5 (0.0) ; 15.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 8 (0) ; 10 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3 ; work ;
+; |shift_taps_9l21:auto_generated| ; 14.5 (2.3) ; 15.0 (2.4) ; 0.5 (0.2) ; 0.0 (0.0) ; 10.0 (0.0) ; 8 (5) ; 10 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated ; work ;
; |altsyncram_lr91:altsyncram4| ; 10.8 (10.8) ; 10.9 (10.9) ; 0.2 (0.2) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4 ; work ;
-; |cntr_uhf:cntr1| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1 ; work ;
-; |altshift_taps:DFFNumerator_rtl_4| ; 17.0 (0.0) ; 18.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 ; work ;
-; |shift_taps_cl21:auto_generated| ; 17.0 (3.1) ; 18.5 (3.4) ; 1.5 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (7) ; 9 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated ; work ;
-; |altsyncram_hr91:altsyncram5| ; 10.5 (10.5) ; 11.1 (11.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 ; work ;
-; |cntr_thf:cntr1| ; 3.4 (3.4) ; 4.0 (4.0) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1 ; work ;
-; |altshift_taps:DFFNumerator_rtl_5| ; 16.5 (0.0) ; 18.2 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 10 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 ; work ;
-; |shift_taps_dl21:auto_generated| ; 16.5 (2.3) ; 18.2 (3.0) ; 1.7 (0.8) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (6) ; 10 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated ; work ;
-; |altsyncram_mr91:altsyncram5| ; 10.6 (10.6) ; 11.2 (11.2) ; 0.6 (0.6) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 ; work ;
-; |cntr_shf:cntr1| ; 3.7 (3.7) ; 4.0 (4.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1 ; work ;
-; |altshift_taps:DFFNumerator_rtl_6| ; 17.0 (0.0) ; 18.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 12 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 ; work ;
-; |shift_taps_4l21:auto_generated| ; 17.0 (3.1) ; 18.5 (3.4) ; 1.5 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (7) ; 12 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated ; work ;
-; |altsyncram_dr91:altsyncram5| ; 10.5 (10.5) ; 11.1 (11.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 ; work ;
-; |cntr_rhf:cntr1| ; 3.4 (3.4) ; 4.0 (4.0) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1 ; work ;
-; |altshift_taps:DFFNumerator_rtl_7| ; 13.0 (0.0) ; 13.5 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 6 (0) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 ; work ;
-; |shift_taps_3l21:auto_generated| ; 13.0 (1.8) ; 13.5 (1.9) ; 0.5 (0.2) ; 0.0 (0.0) ; 10.0 (0.0) ; 6 (4) ; 7 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated ; work ;
+; |cntr_uhf:cntr1| ; 1.5 (1.5) ; 1.7 (1.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1 ; work ;
+; |altshift_taps:DFFNumerator_rtl_4| ; 17.0 (0.0) ; 18.0 (0.0) ; 1.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 10 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4 ; work ;
+; |shift_taps_cl21:auto_generated| ; 17.0 (3.1) ; 18.0 (3.4) ; 1.0 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (7) ; 10 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated ; work ;
+; |altsyncram_hr91:altsyncram5| ; 10.5 (10.5) ; 10.8 (10.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5 ; work ;
+; |cntr_thf:cntr1| ; 3.4 (3.4) ; 3.8 (3.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1 ; work ;
+; |altshift_taps:DFFNumerator_rtl_5| ; 16.5 (0.0) ; 17.5 (0.0) ; 1.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5 ; work ;
+; |shift_taps_dl21:auto_generated| ; 16.5 (2.3) ; 17.5 (2.6) ; 1.0 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (6) ; 9 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated ; work ;
+; |altsyncram_mr91:altsyncram5| ; 10.6 (10.6) ; 10.9 (10.9) ; 0.3 (0.3) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5 ; work ;
+; |cntr_shf:cntr1| ; 3.7 (3.7) ; 4.0 (4.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1 ; work ;
+; |altshift_taps:DFFNumerator_rtl_6| ; 17.0 (0.0) ; 18.0 (0.0) ; 1.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6 ; work ;
+; |shift_taps_4l21:auto_generated| ; 17.0 (3.1) ; 18.0 (3.4) ; 1.0 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 14 (7) ; 9 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated ; work ;
+; |altsyncram_dr91:altsyncram5| ; 10.5 (10.5) ; 10.8 (10.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5 ; work ;
+; |cntr_rhf:cntr1| ; 3.4 (3.4) ; 3.8 (3.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1 ; work ;
+; |altshift_taps:DFFNumerator_rtl_7| ; 13.0 (0.0) ; 13.5 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 6 (0) ; 6 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7 ; work ;
+; |shift_taps_3l21:auto_generated| ; 13.0 (1.8) ; 13.5 (1.9) ; 0.5 (0.2) ; 0.0 (0.0) ; 10.0 (0.0) ; 6 (4) ; 6 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated ; work ;
; |altsyncram_9r91:altsyncram4| ; 10.4 (10.4) ; 10.6 (10.6) ; 0.2 (0.2) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4 ; work ;
-; |cntr_phf:cntr1| ; 0.8 (0.8) ; 1.0 (1.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1 ; work ;
-; |altshift_taps:DFFNumerator_rtl_8| ; 13.5 (0.0) ; 14.5 (0.0) ; 1.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 7 (0) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 ; work ;
-; |shift_taps_5l21:auto_generated| ; 13.5 (0.9) ; 14.5 (1.3) ; 1.0 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 7 (2) ; 7 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated ; work ;
-; |altsyncram_br91:altsyncram4| ; 10.4 (10.4) ; 10.8 (10.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 ; work ;
-; |cntr_ohf:cntr1| ; 2.2 (2.2) ; 2.5 (2.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1 ; work ;
-; |altshift_taps:DFF_Num_Sign_rtl_0| ; 16.6 (0.0) ; 18.5 (0.0) ; 1.9 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 13 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 ; work ;
-; |shift_taps_7l21:auto_generated| ; 16.6 (2.5) ; 18.5 (3.5) ; 1.9 (1.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (7) ; 13 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated ; work ;
-; |altsyncram_kr91:altsyncram5| ; 11.0 (11.0) ; 11.5 (11.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 ; work ;
-; |cntr_8jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1 ; work ;
+; |cntr_phf:cntr1| ; 0.8 (0.8) ; 1.0 (1.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1 ; work ;
+; |altshift_taps:DFFNumerator_rtl_8| ; 13.5 (0.0) ; 14.5 (0.0) ; 1.0 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 7 (0) ; 6 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8 ; work ;
+; |shift_taps_5l21:auto_generated| ; 13.5 (1.1) ; 14.5 (1.4) ; 1.0 (0.3) ; 0.0 (0.0) ; 10.0 (0.0) ; 7 (2) ; 6 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated ; work ;
+; |altsyncram_br91:altsyncram4| ; 10.3 (10.3) ; 10.6 (10.6) ; 0.3 (0.3) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4 ; work ;
+; |cntr_ohf:cntr1| ; 2.2 (2.2) ; 2.5 (2.5) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1 ; work ;
+; |altshift_taps:DFF_Num_Sign_rtl_0| ; 16.6 (0.0) ; 17.8 (0.0) ; 1.2 (0.0) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (0) ; 12 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0 ; work ;
+; |shift_taps_7l21:auto_generated| ; 16.6 (2.5) ; 17.8 (2.9) ; 1.2 (0.4) ; 0.0 (0.0) ; 10.0 (0.0) ; 13 (7) ; 12 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated ; work ;
+; |altsyncram_kr91:altsyncram5| ; 11.0 (11.0) ; 11.4 (11.4) ; 0.4 (0.4) ; 0.0 (0.0) ; 10.0 (10.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5 ; work ;
+; |cntr_8jf:cntr1| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1 ; work ;
; |mulsu:mul_su| ; 19.5 (0.0) ; 19.0 (0.0) ; 0.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 38 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su ; work ;
; |lpm_mult:lpm_mult_component| ; 19.5 (0.0) ; 19.0 (0.0) ; 0.0 (0.0) ; 0.5 (0.0) ; 0.0 (0.0) ; 38 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component ; work ;
; |mult_61n:auto_generated| ; 19.5 (19.5) ; 19.0 (19.0) ; 0.0 (0.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 38 (38) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 4 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component|mult_61n:auto_generated ; work ;
-; |mult:mul| ; 24.2 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 1.2 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul ; work ;
-; |lpm_mult:lpm_mult_component| ; 24.2 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 1.2 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component ; work ;
-; |mult_b8n:auto_generated| ; 24.2 (24.2) ; 23.0 (23.0) ; 0.0 (0.0) ; 1.2 (1.2) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component|mult_b8n:auto_generated ; work ;
-; |mult_s:mul_s| ; 23.7 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.7 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s ; work ;
-; |lpm_mult:lpm_mult_component| ; 23.7 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.7 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component ; work ;
-; |mult_81n:auto_generated| ; 23.7 (23.7) ; 23.0 (23.0) ; 0.0 (0.0) ; 0.7 (0.7) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component|mult_81n:auto_generated ; work ;
+; |mult:mul| ; 23.7 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.7 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul ; work ;
+; |lpm_mult:lpm_mult_component| ; 23.7 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.7 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component ; work ;
+; |mult_b8n:auto_generated| ; 23.7 (23.7) ; 23.0 (23.0) ; 0.0 (0.0) ; 0.7 (0.7) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult:mul|lpm_mult:lpm_mult_component|mult_b8n:auto_generated ; work ;
+; |mult_s:mul_s| ; 23.3 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.3 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s ; work ;
+; |lpm_mult:lpm_mult_component| ; 23.3 (0.0) ; 23.0 (0.0) ; 0.0 (0.0) ; 0.3 (0.0) ; 0.0 (0.0) ; 46 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component ; work ;
+; |mult_81n:auto_generated| ; 23.3 (23.3) ; 23.0 (23.0) ; 0.0 (0.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 3 ; 0 ; 0 ; |de1_riscv|riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component|mult_81n:auto_generated ; work ;
+----------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -3072,243 +3003,325 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; SW[8] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; SW[9] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; CLOCK_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; KEY[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; SW[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; SW[3] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; SW[6] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; KEY[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[6] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; SW[4] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; SW[5] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+; SW[5] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; SW[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
; SW[7] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; KEY[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; KEY[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
+; KEY[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
; SW[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
+---------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+-----------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+-----------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
-; ADC_DOUT ; ; ;
-; AUD_ADCDAT ; ; ;
-; CLOCK2_50 ; ; ;
-; CLOCK3_50 ; ; ;
-; CLOCK4_50 ; ; ;
-; IRDA_RXD ; ; ;
-; TD_CLK27 ; ; ;
-; TD_DATA[0] ; ; ;
-; TD_DATA[1] ; ; ;
-; TD_DATA[2] ; ; ;
-; TD_DATA[3] ; ; ;
-; TD_DATA[4] ; ; ;
-; TD_DATA[5] ; ; ;
-; TD_DATA[6] ; ; ;
-; TD_DATA[7] ; ; ;
-; TD_HS ; ; ;
-; TD_VS ; ; ;
-; AUD_ADCLRCK ; ; ;
-; AUD_BCLK ; ; ;
-; AUD_DACLRCK ; ; ;
-; DRAM_DQ[0] ; ; ;
-; DRAM_DQ[1] ; ; ;
-; DRAM_DQ[2] ; ; ;
-; DRAM_DQ[3] ; ; ;
-; DRAM_DQ[4] ; ; ;
-; DRAM_DQ[5] ; ; ;
-; DRAM_DQ[6] ; ; ;
-; DRAM_DQ[7] ; ; ;
-; DRAM_DQ[8] ; ; ;
-; DRAM_DQ[9] ; ; ;
-; DRAM_DQ[10] ; ; ;
-; DRAM_DQ[11] ; ; ;
-; DRAM_DQ[12] ; ; ;
-; DRAM_DQ[13] ; ; ;
-; DRAM_DQ[14] ; ; ;
-; DRAM_DQ[15] ; ; ;
-; FPGA_I2C_SDAT ; ; ;
-; PS2_CLK ; ; ;
-; PS2_CLK2 ; ; ;
-; PS2_DAT ; ; ;
-; PS2_DAT2 ; ; ;
-; GPIO[0] ; ; ;
-; GPIO[1] ; ; ;
-; GPIO[2] ; ; ;
-; GPIO[3] ; ; ;
-; GPIO[4] ; ; ;
-; GPIO[6] ; ; ;
-; GPIO[8] ; ; ;
-; GPIO[9] ; ; ;
-; GPIO[10] ; ; ;
-; GPIO[11] ; ; ;
-; GPIO[12] ; ; ;
-; GPIO[13] ; ; ;
-; GPIO[14] ; ; ;
-; GPIO[15] ; ; ;
-; GPIO[16] ; ; ;
-; GPIO[17] ; ; ;
-; GPIO[18] ; ; ;
-; GPIO[19] ; ; ;
-; GPIO[20] ; ; ;
-; GPIO[21] ; ; ;
-; GPIO[22] ; ; ;
-; GPIO[23] ; ; ;
-; GPIO[24] ; ; ;
-; GPIO[25] ; ; ;
-; GPIO[26] ; ; ;
-; GPIO[27] ; ; ;
-; GPIO[28] ; ; ;
-; GPIO[29] ; ; ;
-; GPIO[30] ; ; ;
-; GPIO[31] ; ; ;
-; GPIO[32] ; ; ;
-; GPIO[33] ; ; ;
-; GPIO[34] ; ; ;
-; GPIO[35] ; ; ;
-; GPIO[5] ; ; ;
-; GPIO[7] ; ; ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~feeder ; 0 ; 0 ;
-; KEY[3] ; ; ;
-; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|d1_rx_char_ready ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|d1_tx_ready ; 0 ; 0 ;
-; - riscv_core:core|pc[18] ; 0 ; 0 ;
-; - riscv_core:core|pc[3] ; 0 ; 0 ;
-; - riscv_core:core|pc[14] ; 0 ; 0 ;
-; - riscv_core:core|pc[8] ; 0 ; 0 ;
-; - riscv_core:core|pc[9] ; 0 ; 0 ;
-; - riscv_core:core|pc[10] ; 0 ; 0 ;
-; - riscv_core:core|pc[11] ; 0 ; 0 ;
-; - riscv_core:core|pc[12] ; 0 ; 0 ;
-; - riscv_core:core|pc[13] ; 0 ; 0 ;
-; - riscv_core:core|pc[30] ; 0 ; 0 ;
-; - riscv_core:core|pc[15] ; 0 ; 0 ;
-; - riscv_core:core|pc[16] ; 0 ; 0 ;
-; - riscv_core:core|pc[17] ; 0 ; 0 ;
-; - riscv_core:core|pc[19] ; 0 ; 0 ;
-; - riscv_core:core|pc[20] ; 0 ; 0 ;
-; - riscv_core:core|pc[21] ; 0 ; 0 ;
-; - riscv_core:core|pc[22] ; 0 ; 0 ;
-; - riscv_core:core|pc[23] ; 0 ; 0 ;
-; - riscv_core:core|pc[24] ; 0 ; 0 ;
-; - riscv_core:core|pc[7] ; 0 ; 0 ;
-; - riscv_core:core|pc[26] ; 0 ; 0 ;
-; - riscv_core:core|pc[27] ; 0 ; 0 ;
-; - riscv_core:core|pc[28] ; 0 ; 0 ;
-; - riscv_core:core|pc[29] ; 0 ; 0 ;
-; - riscv_core:core|pc[25] ; 0 ; 0 ;
-; - riscv_core:core|write ; 0 ; 0 ;
-; - riscv_core:core|pc[0] ; 0 ; 0 ;
-; - riscv_core:core|pc[1] ; 0 ; 0 ;
-; - riscv_core:core|state.0110 ; 0 ; 0 ;
-; - riscv_core:core|state.1010 ; 0 ; 0 ;
-; - riscv_core:core|state.0010 ; 0 ; 0 ;
-; - riscv_core:core|pc[31] ; 0 ; 0 ;
-; - led0~0 ; 0 ; 0 ;
-; - led2~0 ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_char_ready ; 0 ; 0 ;
-; - riscv_core:core|writedata[0]~2 ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxrx_in_processxx3 ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] ; 0 ; 0 ;
-; - bReadData[13]~1 ; 0 ; 0 ;
-; - riscv_core:core|state~25 ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_clk_en ; 0 ; 0 ;
-; - riscv_core:core|state.0000 ; 0 ; 0 ;
-; - riscv_core:core|state~26 ; 0 ; 0 ;
-; - readaddr~1 ; 0 ; 0 ;
-; - riscv_core:core|state~27 ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx1 ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[3] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[2] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[8] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[7] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[6] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[5] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[4] ; 0 ; 0 ;
-; - riscv_core:core|state~28 ; 0 ; 0 ;
-; - riscv_core:core|state~29 ; 0 ; 0 ;
-; - riscv_core:core|pc[31]~3 ; 0 ; 0 ;
-; - riscv_core:core|pc~26 ; 0 ; 0 ;
-; - riscv_core:core|pc~28 ; 0 ; 0 ;
-; - riscv_core:core|pc~29 ; 0 ; 0 ;
-; - riscv_core:core|pc~30 ; 0 ; 0 ;
-; - riscv_core:core|Mux5~0 ; 0 ; 0 ;
-; - riscv_core:core|Selector247~4 ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] ; 0 ; 0 ;
-; - riscv_core:core|state~30 ; 0 ; 0 ;
-; - riscv_core:core|divclk[4]~0 ; 0 ; 0 ;
-; - riscv_core:core|divclk[3]~1 ; 0 ; 0 ;
-; - riscv_core:core|divclk[2]~2 ; 0 ; 0 ;
-; - riscv_core:core|divclk[0]~3 ; 0 ; 0 ;
-; - riscv_core:core|divclk[1]~4 ; 0 ; 0 ;
-; - riscv_core:core|pc[0]~33 ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; 0 ; 0 ;
-; - KEY[3]~_wirecell ; 0 ; 0 ;
-; - clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL ; 0 ; 0 ;
-; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0]~DUPLICATE ; 0 ; 0 ;
-; SW[8] ; ; ;
-; - led0~0 ; 1 ; 0 ;
-; - led2~0 ; 1 ; 0 ;
-; - riscv_core:core|Mux57~2 ; 1 ; 0 ;
-; - bReadData[8]~21 ; 1 ; 0 ;
-; - riscv_core:core|Selector244~2 ; 1 ; 0 ;
-; SW[9] ; ; ;
-; - led2[3]~1 ; 1 ; 0 ;
-; - led2[3]~4 ; 1 ; 0 ;
-; - led2~5 ; 1 ; 0 ;
-; - led3~0 ; 1 ; 0 ;
-; - led4[4]~0 ; 1 ; 0 ;
-; - led4~1 ; 1 ; 0 ;
-; - led5~0 ; 1 ; 0 ;
-; - bReadData[9]~19 ; 1 ; 0 ;
-; - riscv_core:core|Mux9~0 ; 1 ; 0 ;
-; - riscv_core:core|Mux56~1 ; 1 ; 0 ;
-; CLOCK_50 ; ; ;
-; KEY[2] ; ; ;
-; - bReadData[12]~0 ; 1 ; 0 ;
-; - riscv_core:core|Mux6~0 ; 1 ; 0 ;
-; - riscv_core:core|Selector248~4 ; 1 ; 0 ;
-; SW[2] ; ; ;
-; - bReadData[2]~3 ; 0 ; 0 ;
-; SW[3] ; ; ;
-; - bReadData[3]~4 ; 0 ; 0 ;
-; SW[6] ; ; ;
-; - bReadData[6]~5 ; 1 ; 0 ;
-; SW[4] ; ; ;
-; - bReadData[4]~6 ; 0 ; 0 ;
-; SW[5] ; ; ;
-; - bReadData[5]~7 ; 0 ; 0 ;
-; SW[0] ; ; ;
-; - riscv_core:core|Mux57~4 ; 1 ; 0 ;
-; SW[7] ; ; ;
-; - riscv_core:core|Mux18~0 ; 0 ; 0 ;
-; - bReadData[7]~20 ; 0 ; 0 ;
-; - riscv_core:core|Mux1~3 ; 0 ; 0 ;
-; - riscv_core:core|Mux1~4 ; 0 ; 0 ;
-; - riscv_core:core|Mux26~4 ; 0 ; 0 ;
-; KEY[0] ; ; ;
-; - bReadData[10]~28 ; 0 ; 0 ;
-; - riscv_core:core|Mux8~0 ; 0 ; 0 ;
-; - riscv_core:core|Selector250~4 ; 0 ; 0 ;
-; KEY[1] ; ; ;
-; - bReadData[11]~30 ; 1 ; 0 ;
-; - riscv_core:core|Mux7~0 ; 1 ; 0 ;
-; - riscv_core:core|Selector249~4 ; 1 ; 0 ;
-; SW[1] ; ; ;
-; - riscv_core:core|Mux56~2 ; 0 ; 0 ;
-+-----------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+; ADC_DOUT ; ; ;
+; AUD_ADCDAT ; ; ;
+; CLOCK2_50 ; ; ;
+; CLOCK3_50 ; ; ;
+; CLOCK4_50 ; ; ;
+; IRDA_RXD ; ; ;
+; TD_CLK27 ; ; ;
+; TD_DATA[0] ; ; ;
+; TD_DATA[1] ; ; ;
+; TD_DATA[2] ; ; ;
+; TD_DATA[3] ; ; ;
+; TD_DATA[4] ; ; ;
+; TD_DATA[5] ; ; ;
+; TD_DATA[6] ; ; ;
+; TD_DATA[7] ; ; ;
+; TD_HS ; ; ;
+; TD_VS ; ; ;
+; AUD_ADCLRCK ; ; ;
+; AUD_BCLK ; ; ;
+; AUD_DACLRCK ; ; ;
+; DRAM_DQ[0] ; ; ;
+; DRAM_DQ[1] ; ; ;
+; DRAM_DQ[2] ; ; ;
+; DRAM_DQ[3] ; ; ;
+; DRAM_DQ[4] ; ; ;
+; DRAM_DQ[5] ; ; ;
+; DRAM_DQ[6] ; ; ;
+; DRAM_DQ[7] ; ; ;
+; DRAM_DQ[8] ; ; ;
+; DRAM_DQ[9] ; ; ;
+; DRAM_DQ[10] ; ; ;
+; DRAM_DQ[11] ; ; ;
+; DRAM_DQ[12] ; ; ;
+; DRAM_DQ[13] ; ; ;
+; DRAM_DQ[14] ; ; ;
+; DRAM_DQ[15] ; ; ;
+; FPGA_I2C_SDAT ; ; ;
+; PS2_CLK ; ; ;
+; PS2_CLK2 ; ; ;
+; PS2_DAT ; ; ;
+; PS2_DAT2 ; ; ;
+; GPIO[0] ; ; ;
+; GPIO[1] ; ; ;
+; GPIO[2] ; ; ;
+; GPIO[3] ; ; ;
+; GPIO[4] ; ; ;
+; GPIO[6] ; ; ;
+; GPIO[8] ; ; ;
+; GPIO[9] ; ; ;
+; GPIO[10] ; ; ;
+; GPIO[11] ; ; ;
+; GPIO[12] ; ; ;
+; GPIO[13] ; ; ;
+; GPIO[14] ; ; ;
+; GPIO[15] ; ; ;
+; GPIO[16] ; ; ;
+; GPIO[17] ; ; ;
+; GPIO[18] ; ; ;
+; GPIO[19] ; ; ;
+; GPIO[20] ; ; ;
+; GPIO[21] ; ; ;
+; GPIO[22] ; ; ;
+; GPIO[23] ; ; ;
+; GPIO[24] ; ; ;
+; GPIO[25] ; ; ;
+; GPIO[26] ; ; ;
+; GPIO[27] ; ; ;
+; GPIO[28] ; ; ;
+; GPIO[29] ; ; ;
+; GPIO[30] ; ; ;
+; GPIO[31] ; ; ;
+; GPIO[32] ; ; ;
+; GPIO[33] ; ; ;
+; GPIO[34] ; ; ;
+; GPIO[35] ; ; ;
+; GPIO[5] ; ; ;
+; GPIO[7] ; ; ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1~feeder ; 0 ; 0 ;
+; KEY[3] ; ; ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|d1_rx_char_ready ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|irq ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|d1_tx_ready ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] ; 0 ; 0 ;
+; - readaddr[14] ; 0 ; 0 ;
+; - readaddr[31] ; 0 ; 0 ;
+; - readaddr[30] ; 0 ; 0 ;
+; - readaddr[9] ; 0 ; 0 ;
+; - readaddr[10] ; 0 ; 0 ;
+; - readaddr[11] ; 0 ; 0 ;
+; - readaddr[12] ; 0 ; 0 ;
+; - readaddr[13] ; 0 ; 0 ;
+; - readaddr[26] ; 0 ; 0 ;
+; - readaddr[15] ; 0 ; 0 ;
+; - readaddr[16] ; 0 ; 0 ;
+; - readaddr[17] ; 0 ; 0 ;
+; - readaddr[18] ; 0 ; 0 ;
+; - readaddr[19] ; 0 ; 0 ;
+; - readaddr[20] ; 0 ; 0 ;
+; - readaddr[21] ; 0 ; 0 ;
+; - readaddr[22] ; 0 ; 0 ;
+; - readaddr[23] ; 0 ; 0 ;
+; - readaddr[24] ; 0 ; 0 ;
+; - readaddr[25] ; 0 ; 0 ;
+; - readaddr[27] ; 0 ; 0 ;
+; - readaddr[28] ; 0 ; 0 ;
+; - readaddr[29] ; 0 ; 0 ;
+; - readaddr[8] ; 0 ; 0 ;
+; - riscv_core:core|pc[29] ; 0 ; 0 ;
+; - riscv_core:core|pc[28] ; 0 ; 0 ;
+; - riscv_core:core|pc[27] ; 0 ; 0 ;
+; - riscv_core:core|pc[15] ; 0 ; 0 ;
+; - riscv_core:core|pc[26] ; 0 ; 0 ;
+; - riscv_core:core|pc[22] ; 0 ; 0 ;
+; - riscv_core:core|pc[25] ; 0 ; 0 ;
+; - riscv_core:core|pc[24] ; 0 ; 0 ;
+; - riscv_core:core|pc[23] ; 0 ; 0 ;
+; - riscv_core:core|pc[30] ; 0 ; 0 ;
+; - riscv_core:core|pc[20] ; 0 ; 0 ;
+; - riscv_core:core|pc[18] ; 0 ; 0 ;
+; - riscv_core:core|pc[17] ; 0 ; 0 ;
+; - riscv_core:core|pc[16] ; 0 ; 0 ;
+; - riscv_core:core|pc[14] ; 0 ; 0 ;
+; - riscv_core:core|pc[19] ; 0 ; 0 ;
+; - riscv_core:core|pc[13] ; 0 ; 0 ;
+; - riscv_core:core|pc[12] ; 0 ; 0 ;
+; - riscv_core:core|pc[11] ; 0 ; 0 ;
+; - riscv_core:core|pc[21] ; 0 ; 0 ;
+; - riscv_core:core|pc[7] ; 0 ; 0 ;
+; - riscv_core:core|pc[3] ; 0 ; 0 ;
+; - riscv_core:core|pc[8] ; 0 ; 0 ;
+; - riscv_core:core|pc[9] ; 0 ; 0 ;
+; - riscv_core:core|pc[10] ; 0 ; 0 ;
+; - riscv_core:core|write ; 0 ; 0 ;
+; - riscv_core:core|pc[0] ; 0 ; 0 ;
+; - riscv_core:core|pc[1] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[8] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[7] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[6] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[5] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[4] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[3] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[2] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[1] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[0] ; 0 ; 0 ;
+; - riscv_core:core|state.0010 ; 0 ; 0 ;
+; - riscv_core:core|pc[31] ; 0 ; 0 ;
+; - riscv_core:core|state.0110 ; 0 ; 0 ;
+; - riscv_core:core|state.1010 ; 0 ; 0 ;
+; - led0~0 ; 0 ; 0 ;
+; - led2~0 ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_char_ready ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_ready ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[6] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|framing_error ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[1] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[7] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|break_detect ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[2] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[8] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_overrun ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_overrun ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[4] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_shift_empty ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[5] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[3] ; 0 ; 0 ;
+; - riscv_core:core|writedata[0]~2 ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxrx_in_processxx3 ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|do_load_shifter ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|txd ; 0 ; 0 ;
+; - bReadData[13]~1 ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[2] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[3] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[6] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[4] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[5] ; 0 ; 0 ;
+; - riscv_core:core|state~25 ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_clk_en ; 0 ; 0 ;
+; - riscv_core:core|pc[31]~1 ; 0 ; 0 ;
+; - riscv_core:core|pc~27 ; 0 ; 0 ;
+; - riscv_core:core|pc~28 ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[2] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_clk_en ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[1] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[4] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[3] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[0] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[7] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[5] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[6] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|pre_txd ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[9] ; 0 ; 0 ;
+; - riscv_core:core|state.0000 ; 0 ; 0 ;
+; - riscv_core:core|state~26 ; 0 ; 0 ;
+; - riscv_core:core|state~27 ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[2] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[3] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[6] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[4] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[5] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx1 ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[3] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[2] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[8] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[7] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[6] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[5] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[4] ; 0 ; 0 ;
+; - riscv_core:core|state~28 ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[0] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[8] ; 0 ; 0 ;
+; - riscv_core:core|state~29 ; 0 ; 0 ;
+; - riscv_core:core|pc~29 ; 0 ; 0 ;
+; - riscv_core:core|pc~30 ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[9] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[7] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[1] ; 0 ; 0 ;
+; - riscv_core:core|Mux5~0 ; 0 ; 0 ;
+; - riscv_core:core|Selector247~4 ; 0 ; 0 ;
+; - riscv_core:core|state~30 ; 0 ; 0 ;
+; - riscv_core:core|divclk[4]~1 ; 0 ; 0 ;
+; - riscv_core:core|divclk[3]~2 ; 0 ; 0 ;
+; - riscv_core:core|divclk[2]~3 ; 0 ; 0 ;
+; - riscv_core:core|divclk[0]~4 ; 0 ; 0 ;
+; - riscv_core:core|divclk[1]~5 ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[0] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[0] ; 0 ; 0 ;
+; - riscv_core:core|pc[0]~33 ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[7] ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[1] ; 0 ; 0 ;
+; - KEY[3]~_wirecell ; 0 ; 0 ;
+; - clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1]~DUPLICATE ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_char_ready~DUPLICATE ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7]~DUPLICATE ; 0 ; 0 ;
+; - altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0]~DUPLICATE ; 0 ; 0 ;
+; SW[8] ; ; ;
+; - led0~0 ; 1 ; 0 ;
+; - led2~0 ; 1 ; 0 ;
+; - bReadData[8]~16 ; 1 ; 0 ;
+; SW[9] ; ; ;
+; - led1[5]~0 ; 1 ; 0 ;
+; - led2~1 ; 1 ; 0 ;
+; - led3~0 ; 1 ; 0 ;
+; - led4~1 ; 1 ; 0 ;
+; - led5~0 ; 1 ; 0 ;
+; - bReadData[9]~21 ; 1 ; 0 ;
+; CLOCK_50 ; ; ;
+; KEY[2] ; ; ;
+; - bReadData[12]~0 ; 0 ; 0 ;
+; - riscv_core:core|Mux6~0 ; 0 ; 0 ;
+; - riscv_core:core|Selector248~4 ; 0 ; 0 ;
+; SW[2] ; ; ;
+; - bReadData[2]~4 ; 1 ; 0 ;
+; SW[3] ; ; ;
+; - bReadData[3]~5 ; 1 ; 0 ;
+; SW[6] ; ; ;
+; - bReadData[6]~6 ; 0 ; 0 ;
+; SW[4] ; ; ;
+; - bReadData[4]~7 ; 0 ; 0 ;
+; SW[5] ; ; ;
+; - bReadData[5]~8 ; 1 ; 0 ;
+; SW[0] ; ; ;
+; - bReadData[0]~14 ; 1 ; 0 ;
+; SW[7] ; ; ;
+; - bReadData[7]~22 ; 0 ; 0 ;
+; KEY[0] ; ; ;
+; - bReadData[10]~29 ; 0 ; 0 ;
+; - riscv_core:core|Mux8~0 ; 0 ; 0 ;
+; - riscv_core:core|Selector250~4 ; 0 ; 0 ;
+; KEY[1] ; ; ;
+; - bReadData[11]~31 ; 0 ; 0 ;
+; - riscv_core:core|Mux7~0 ; 0 ; 0 ;
+; - riscv_core:core|Selector249~4 ; 0 ; 0 ;
+; SW[1] ; ; ;
+; - bReadData[1]~32 ; 0 ; 0 ;
++------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
@@ -3316,61 +3329,65 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
-; KEY[3] ; PIN_Y16 ; 88 ; Async. clear, Sync. clear ; no ; -- ; -- ; -- ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]~0 ; LABCELL_X55_Y1_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
-; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ; PLLOUTPUTCOUNTER_X0_Y20_N1 ; 1986 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ;
-; comb~1 ; LABCELL_X45_Y16_N27 ; 8 ; Write enable ; no ; -- ; -- ; -- ;
-; led2[3]~1 ; LABCELL_X53_Y16_N33 ; 38 ; Sync. load ; no ; -- ; -- ; -- ;
-; led2[3]~4 ; LABCELL_X53_Y16_N3 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
-; led4[4]~0 ; LABCELL_X53_Y16_N0 ; 14 ; Clock enable ; no ; -- ; -- ; -- ;
-; readaddr[17]~0 ; LABCELL_X36_Y18_N21 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
-; readaddr~1 ; LABCELL_X40_Y14_N21 ; 24 ; Sync. clear ; no ; -- ; -- ; -- ;
-; riscv_core:core|Selector167~1 ; LABCELL_X48_Y14_N0 ; 2 ; Write enable ; no ; -- ; -- ; -- ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[198] ; LABCELL_X56_Y21_N12 ; 9 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[297] ; MLABCELL_X47_Y22_N39 ; 11 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[363] ; MLABCELL_X39_Y22_N24 ; 17 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[462] ; LABCELL_X40_Y22_N57 ; 18 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[561] ; LABCELL_X40_Y24_N24 ; 23 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[627] ; LABCELL_X37_Y24_N57 ; 23 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[726] ; LABCELL_X33_Y24_N12 ; 31 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[825] ; LABCELL_X29_Y25_N12 ; 27 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[891] ; LABCELL_X27_Y22_N9 ; 36 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[990] ; LABCELL_X31_Y19_N54 ; 32 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[99] ; LABCELL_X53_Y21_N15 ; 5 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|cout_actual ; MLABCELL_X34_Y23_N48 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|cout_actual ; LABCELL_X40_Y21_N48 ; 6 ; Sync. clear ; no ; -- ; -- ; -- ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|cout_actual ; LABCELL_X33_Y28_N18 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[198] ; LABCELL_X42_Y27_N24 ; 10 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[297] ; LABCELL_X40_Y28_N9 ; 11 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[363] ; LABCELL_X40_Y31_N57 ; 15 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[462] ; LABCELL_X36_Y29_N51 ; 20 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[561] ; LABCELL_X37_Y32_N54 ; 19 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[627] ; LABCELL_X45_Y30_N45 ; 34 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[726] ; LABCELL_X48_Y27_N12 ; 37 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[825] ; LABCELL_X45_Y25_N24 ; 28 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[891] ; LABCELL_X48_Y22_N21 ; 44 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[990] ; MLABCELL_X52_Y24_N33 ; 35 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[99] ; LABCELL_X45_Y23_N39 ; 5 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|cout_actual ; LABCELL_X35_Y20_N24 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ;
-; riscv_core:core|dstvalue[25]~59 ; MLABCELL_X34_Y13_N45 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ;
-; riscv_core:core|dstvalue[3]~0 ; LABCELL_X35_Y18_N9 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
-; riscv_core:core|dstvalue[3]~47 ; LABCELL_X40_Y17_N12 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
-; riscv_core:core|imm[12]~5 ; LABCELL_X40_Y18_N33 ; 14 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|imm[19]~4 ; LABCELL_X42_Y18_N24 ; 34 ; Clock enable ; no ; -- ; -- ; -- ;
-; riscv_core:core|imm[27]~6 ; LABCELL_X42_Y18_N30 ; 13 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|imm[4]~0 ; LABCELL_X42_Y18_N45 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
-; riscv_core:core|imm[4]~1 ; LABCELL_X42_Y18_N42 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
-; riscv_core:core|pc[0]~33 ; LABCELL_X40_Y14_N24 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
-; riscv_core:core|pc[31]~3 ; LABCELL_X36_Y13_N21 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
-; riscv_core:core|rs2[31]~_Duplicate_6 ; FF_X50_Y17_N35 ; 41 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|state.0010 ; FF_X40_Y17_N50 ; 34 ; Sync. load ; no ; -- ; -- ; -- ;
-; riscv_core:core|state.0011 ; FF_X36_Y13_N59 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
-; riscv_core:core|state.0100 ; FF_X36_Y13_N56 ; 55 ; Clock enable ; no ; -- ; -- ; -- ;
-; riscv_core:core|state.0101 ; FF_X36_Y13_N53 ; 53 ; Clock enable ; no ; -- ; -- ; -- ;
-; riscv_core:core|writedata[0]~2 ; LABCELL_X42_Y18_N48 ; 69 ; Clock enable ; no ; -- ; -- ; -- ;
-; riscv_core:core|writedata[19]~5 ; LABCELL_X51_Y18_N15 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ;
-; riscv_core:core|writedata[1]~0 ; LABCELL_X51_Y18_N39 ; 16 ; Sync. clear ; no ; -- ; -- ; -- ;
-; uartaddr[0]~0 ; LABCELL_X42_Y18_N36 ; 13 ; Clock enable ; no ; -- ; -- ; -- ;
+; KEY[3] ; PIN_Y16 ; 180 ; Async. clear, Sync. clear ; no ; -- ; -- ; -- ;
+; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_wr_strobe~1 ; MLABCELL_X59_Y23_N51 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
+; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_wr_strobe~0 ; MLABCELL_X59_Y23_N15 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|got_new_char ; MLABCELL_X59_Y23_N42 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5]~0 ; LABCELL_X62_Y19_N42 ; 11 ; Clock enable ; no ; -- ; -- ; -- ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|always4~0 ; LABCELL_X45_Y22_N9 ; 9 ; Sync. load ; no ; -- ; -- ; -- ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|do_load_shifter ; FF_X45_Y22_N5 ; 14 ; Sync. load ; no ; -- ; -- ; -- ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[0]~0 ; LABCELL_X51_Y23_N54 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;
+; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ; PLLOUTPUTCOUNTER_X0_Y20_N1 ; 1982 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ;
+; comb~1 ; LABCELL_X57_Y22_N9 ; 8 ; Write enable ; no ; -- ; -- ; -- ;
+; led1[5]~0 ; LABCELL_X60_Y22_N42 ; 40 ; Sync. load ; no ; -- ; -- ; -- ;
+; led1[5]~3 ; LABCELL_X60_Y22_N57 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
+; led4[0]~0 ; LABCELL_X60_Y22_N0 ; 14 ; Clock enable ; no ; -- ; -- ; -- ;
+; riscv_core:core|Selector167~1 ; LABCELL_X46_Y20_N18 ; 2 ; Write enable ; no ; -- ; -- ; -- ;
+; riscv_core:core|bReadAddr[21]~0 ; MLABCELL_X47_Y21_N18 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
+; riscv_core:core|bReadAddr[21]~25 ; LABCELL_X60_Y21_N15 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[198] ; LABCELL_X56_Y28_N12 ; 9 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[297] ; LABCELL_X55_Y31_N12 ; 12 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[363] ; LABCELL_X53_Y30_N18 ; 19 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[462] ; MLABCELL_X47_Y30_N27 ; 16 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[561] ; MLABCELL_X39_Y30_N51 ; 19 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[627] ; LABCELL_X37_Y30_N42 ; 25 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[726] ; LABCELL_X33_Y30_N57 ; 25 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[825] ; LABCELL_X29_Y29_N39 ; 29 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[891] ; LABCELL_X31_Y32_N39 ; 35 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[990] ; LABCELL_X27_Y36_N9 ; 36 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[99] ; LABCELL_X53_Y28_N9 ; 5 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|cout_actual ; LABCELL_X33_Y33_N24 ; 6 ; Sync. clear ; no ; -- ; -- ; -- ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|cout_actual ; LABCELL_X48_Y26_N54 ; 6 ; Sync. clear ; no ; -- ; -- ; -- ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|cout_actual ; MLABCELL_X52_Y27_N54 ; 4 ; Sync. clear ; no ; -- ; -- ; -- ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[198] ; LABCELL_X46_Y27_N12 ; 9 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[297] ; MLABCELL_X47_Y28_N42 ; 16 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[363] ; LABCELL_X46_Y28_N36 ; 18 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[462] ; LABCELL_X46_Y29_N51 ; 17 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[561] ; LABCELL_X42_Y29_N24 ; 19 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[627] ; LABCELL_X36_Y22_N15 ; 31 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[726] ; MLABCELL_X39_Y26_N6 ; 29 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[825] ; MLABCELL_X39_Y21_N57 ; 29 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[891] ; LABCELL_X36_Y24_N54 ; 35 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[990] ; LABCELL_X29_Y24_N51 ; 35 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[99] ; LABCELL_X50_Y27_N15 ; 5 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|cout_actual ; LABCELL_X35_Y21_N54 ; 4 ; Sync. clear ; no ; -- ; -- ; -- ;
+; riscv_core:core|dstvalue[25]~50 ; MLABCELL_X52_Y16_N3 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ;
+; riscv_core:core|dstvalue[2]~1 ; LABCELL_X53_Y26_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
+; riscv_core:core|dstvalue[2]~32 ; LABCELL_X48_Y20_N48 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
+; riscv_core:core|imm[14]~8 ; LABCELL_X56_Y21_N3 ; 8 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|imm[19]~7 ; MLABCELL_X47_Y21_N42 ; 29 ; Clock enable ; no ; -- ; -- ; -- ;
+; riscv_core:core|imm[29]~9 ; LABCELL_X46_Y19_N15 ; 15 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|imm[4]~1 ; MLABCELL_X47_Y21_N24 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
+; riscv_core:core|imm[4]~2 ; MLABCELL_X47_Y21_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
+; riscv_core:core|pc[0]~33 ; LABCELL_X55_Y17_N15 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
+; riscv_core:core|pc[31]~1 ; LABCELL_X55_Y17_N9 ; 30 ; Clock enable ; no ; -- ; -- ; -- ;
+; riscv_core:core|rs2[31]~_Duplicate_6 ; FF_X51_Y24_N59 ; 41 ; Sync. load ; no ; -- ; -- ; -- ;
+; riscv_core:core|state.0011 ; FF_X53_Y22_N17 ; 35 ; Clock enable ; no ; -- ; -- ; -- ;
+; riscv_core:core|state.0100 ; FF_X53_Y22_N14 ; 51 ; Clock enable ; no ; -- ; -- ; -- ;
+; riscv_core:core|state.0101 ; FF_X53_Y22_N41 ; 43 ; Clock enable ; no ; -- ; -- ; -- ;
+; riscv_core:core|writedata[0]~2 ; MLABCELL_X47_Y21_N30 ; 69 ; Clock enable ; no ; -- ; -- ; -- ;
+; riscv_core:core|writedata[22]~5 ; LABCELL_X56_Y25_N12 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ;
+; riscv_core:core|writedata[2]~0 ; LABCELL_X56_Y25_N9 ; 16 ; Sync. clear ; no ; -- ; -- ; -- ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+
@@ -3379,7 +3396,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+---------------------------------------------------------------------------------+----------------------------+---------+----------------------+------------------+---------------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
+---------------------------------------------------------------------------------+----------------------------+---------+----------------------+------------------+---------------------------+
-; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ; PLLOUTPUTCOUNTER_X0_Y20_N1 ; 1986 ; Global Clock ; GCLK0 ; -- ;
+; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ; PLLOUTPUTCOUNTER_X0_Y20_N1 ; 1982 ; Global Clock ; GCLK0 ; -- ;
+---------------------------------------------------------------------------------+----------------------------+---------+----------------------+------------------+---------------------------+
@@ -3388,103 +3405,102 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
-; riscv_core:core|instr[12] ; 246 ;
-; riscv_core:core|instr[13] ; 170 ;
-; riscv_core:core|Equal0~8 ; 97 ;
-; KEY[3]~input ; 88 ;
-; riscv_core:core|rs2[1]~_Duplicate_6DUPLICATE ; 80 ;
+; riscv_core:core|instr[12] ; 235 ;
+; KEY[3]~input ; 180 ;
+; riscv_core:core|instr[13] ; 169 ;
+; riscv_core:core|Equal0~8 ; 95 ;
+; riscv_core:core|rs2[1]~_Duplicate_6 ; 93 ;
+; riscv_core:core|rs2[0]~_Duplicate_6 ; 82 ;
; riscv_core:core|imm[1] ; 79 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_Num_Sign[0] ; 71 ;
+; riscv_core:core|rs2[3]~_Duplicate_6 ; 76 ;
; riscv_core:core|imm[3] ; 71 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_Num_Sign[0] ; 70 ;
; riscv_core:core|writedata[0]~2 ; 69 ;
; riscv_core:core|imm[0] ; 67 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|add_sub_31_result_int[32]~1 ; 66 ;
-; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[31] ; 65 ;
+; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[31] ; 64 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[957] ; 61 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[957] ; 61 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[924] ; 59 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[924] ; 59 ;
+; riscv_core:core|rs1[31]~_Duplicate_6 ; 59 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[858] ; 55 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[858] ; 55 ;
-; riscv_core:core|state.0100 ; 55 ;
-; riscv_core:core|state.0101 ; 53 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[792] ; 51 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[792] ; 51 ;
-; riscv_core:core|rs1[31]~_Duplicate_6DUPLICATE ; 49 ;
+; riscv_core:core|state.0100 ; 51 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[759] ; 49 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[759] ; 49 ;
-; riscv_core:core|rs2[0]~_Duplicate_6DUPLICATE ; 48 ;
-; Equal1~1 ; 48 ;
; riscv_core:core|instr[2] ; 47 ;
-; riscv_core:core|rs2[3]~_Duplicate_6 ; 46 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[693] ; 45 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[693] ; 45 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[891] ; 44 ;
; riscv_core:core|state.0111 ; 44 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[660] ; 43 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[660] ; 43 ;
+; riscv_core:core|state.0101 ; 43 ;
; riscv_core:core|rs2[2]~_Duplicate_6 ; 43 ;
-; riscv_core:core|instr[14] ; 43 ;
; riscv_core:core|rs2[31]~_Duplicate_6 ; 41 ;
; riscv_core:core|instr[6] ; 40 ;
+; led1[5]~0 ; 40 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[594] ; 39 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[594] ; 39 ;
+; Equal1~0 ; 39 ;
+; riscv_core:core|instr[14] ; 39 ;
; riscv_core:core|state.0110 ; 39 ;
-; led2[3]~1 ; 38 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[726] ; 37 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[891] ; 36 ;
-; riscv_core:core|state.1010 ; 36 ;
+; riscv_core:core|imm[2]~DUPLICATE ; 37 ;
+; riscv_core:core|state.1010 ; 37 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[990] ; 36 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[891] ; 35 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[891] ; 35 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[528] ; 35 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[528] ; 35 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[990] ; 35 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[0] ; 35 ;
; riscv_core:core|instr[30] ; 35 ;
; riscv_core:core|state.0011 ; 35 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[627] ; 34 ;
-; riscv_core:core|imm[19]~4 ; 34 ;
-; riscv_core:core|state.0010 ; 34 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[495] ; 33 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[495] ; 33 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[990] ; 32 ;
-; riscv_core:core|rs2[0]~_Duplicate_6 ; 32 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[726] ; 31 ;
-; riscv_core:core|dstvalue[30]~28 ; 31 ;
-; Equal0~6 ; 31 ;
-; riscv_core:core|rs2[3]~_Duplicate_6DUPLICATE ; 30 ;
-; riscv_core:core|pc[31]~3 ; 30 ;
-; riscv_core:core|pc[18]~1 ; 30 ;
-; riscv_core:core|instr[31] ; 30 ;
+; riscv_core:core|bReadAddr[21]~0 ; 32 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[627] ; 31 ;
+; riscv_core:core|dstvalue[29]~0 ; 31 ;
+; riscv_core:core|rs2[4]~_Duplicate_6 ; 31 ;
+; riscv_core:core|pc[29]~2 ; 30 ;
+; riscv_core:core|pc[31]~1 ; 30 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[429] ; 29 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[429] ; 29 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[825] ; 28 ;
-; riscv_core:core|dstvalue[3]~47 ; 28 ;
-; led2[3]~4 ; 28 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[726] ; 29 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[825] ; 29 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[825] ; 29 ;
+; riscv_core:core|imm[19]~7 ; 29 ;
+; riscv_core:core|state.0010 ; 29 ;
+; riscv_core:core|dstvalue[2]~32 ; 28 ;
+; riscv_core:core|rs1[11]~_Duplicate_6 ; 28 ;
+; led1[5]~3 ; 28 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[396] ; 27 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[396] ; 27 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[825] ; 27 ;
-; riscv_core:core|dstvalue[3]~31 ; 27 ;
-; riscv_core:core|dstvalue[3]~30 ; 27 ;
-; riscv_core:core|rs1[11]~_Duplicate_6 ; 27 ;
+; riscv_core:core|dstvalue[2]~16 ; 27 ;
+; riscv_core:core|dstvalue[2]~15 ; 27 ;
+; riscv_core:core|instr[31] ; 26 ;
+; riscv_core:core|rs1[9]~_Duplicate_6 ; 26 ;
; riscv_core:core|instr[5] ; 26 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[627] ; 25 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[726] ; 25 ;
; riscv_core:core|rs1[29]~_Duplicate_6 ; 25 ;
; riscv_core:core|rs1[20]~_Duplicate_6 ; 25 ;
-; riscv_core:core|rs1[9]~_Duplicate_6DUPLICATE ; 24 ;
-; riscv_core:core|rs2[4]~_Duplicate_6DUPLICATE ; 24 ;
-; readaddr~1 ; 24 ;
+; riscv_core:core|rs1[19]~_Duplicate_6 ; 25 ;
; riscv_core:core|rs1[30]~_Duplicate_6 ; 24 ;
; riscv_core:core|imm[4] ; 24 ;
+; riscv_core:core|rs1[10]~_Duplicate_6 ; 24 ;
; riscv_core:core|rs1[7]~_Duplicate_6 ; 24 ;
; riscv_core:core|rs1[21]~_Duplicate_6 ; 24 ;
+; riscv_core:core|rs1[0]~_Duplicate_6 ; 24 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[330] ; 23 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[330] ; 23 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[561] ; 23 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[627] ; 23 ;
; riscv_core:core|Selector214~5 ; 23 ;
; riscv_core:core|Selector214~4 ; 23 ;
; riscv_core:core|rs1[4]~_Duplicate_6 ; 23 ;
; riscv_core:core|rs1[13]~_Duplicate_6 ; 23 ;
; riscv_core:core|rs1[12]~_Duplicate_6 ; 23 ;
-; riscv_core:core|rs1[10]~_Duplicate_6 ; 23 ;
; riscv_core:core|rs1[5]~_Duplicate_6 ; 23 ;
; riscv_core:core|rs1[3]~_Duplicate_6 ; 23 ;
; riscv_core:core|rs1[23]~_Duplicate_6 ; 23 ;
@@ -3492,73 +3508,68 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|rs1[18]~_Duplicate_6 ; 23 ;
; riscv_core:core|rs1[27]~_Duplicate_6 ; 23 ;
; riscv_core:core|rs1[25]~_Duplicate_6 ; 23 ;
-; riscv_core:core|rs1[0]~_Duplicate_6 ; 23 ;
-; riscv_core:core|imm[2] ; 23 ;
; riscv_core:core|rs1[2]~_Duplicate_6 ; 23 ;
-; riscv_core:core|ldaddr[1]~DUPLICATE ; 22 ;
-; riscv_core:core|rs1[19]~_Duplicate_6DUPLICATE ; 22 ;
-; riscv_core:core|dstvalue[6]~50 ; 22 ;
-; riscv_core:core|dstvalue[6]~49 ; 22 ;
-; riscv_core:core|rs1[6]~_Duplicate_6 ; 21 ;
+; riscv_core:core|write ; 23 ;
+; riscv_core:core|dstvalue[5]~35 ; 22 ;
+; riscv_core:core|dstvalue[5]~34 ; 22 ;
+; riscv_core:core|rs1[28]~_Duplicate_6 ; 22 ;
+; riscv_core:core|rs1[6]~_Duplicate_6 ; 22 ;
+; riscv_core:core|rs1[8]~_Duplicate_6 ; 22 ;
; riscv_core:core|rs1[24]~_Duplicate_6 ; 21 ;
; riscv_core:core|rs1[17]~_Duplicate_6 ; 21 ;
; riscv_core:core|rs1[14]~_Duplicate_6 ; 21 ;
; riscv_core:core|rs1[26]~_Duplicate_6 ; 21 ;
-; riscv_core:core|rs1[8]~_Duplicate_6 ; 21 ;
+; uartaddr[4]~7 ; 21 ;
+; uartaddr[2]~6 ; 21 ;
+; uartaddr[3]~5 ; 21 ;
; riscv_core:core|instr[3] ; 21 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[462] ; 20 ;
-; riscv_core:core|rs1[15]~_Duplicate_6 ; 20 ;
; riscv_core:core|rs1[1]~_Duplicate_6 ; 20 ;
-; riscv_core:core|ldaddr[0]~DUPLICATE ; 19 ;
-; riscv_core:core|rs1[28]~_Duplicate_6DUPLICATE ; 19 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[264] ; 19 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[264] ; 19 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[363] ; 19 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[561] ; 19 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2] ; 19 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[561] ; 19 ;
+; riscv_core:core|ldaddr[0] ; 19 ;
; riscv_core:core|instr[25] ; 19 ;
; riscv_core:core|rs1[16]~_Duplicate_6 ; 19 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[462] ; 18 ;
+; riscv_core:core|rs1[15]~_Duplicate_6 ; 19 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[363] ; 18 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1] ; 18 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0] ; 18 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[231] ; 17 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[231] ; 17 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[363] ; 17 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2] ; 17 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[1] ; 17 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0] ; 17 ;
-; riscv_core:core|writedata[19]~3 ; 17 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[462] ; 17 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2] ; 17 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1] ; 17 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0] ; 17 ;
+; riscv_core:core|writedata[22]~3 ; 17 ;
; riscv_core:core|instr[4] ; 17 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3] ; 17 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2] ; 17 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1] ; 17 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0] ; 17 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[297] ; 16 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[462] ; 16 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[1] ; 16 ;
-; riscv_core:core|dstvalue[3]~34 ; 16 ;
-; riscv_core:core|writedata[1]~0 ; 16 ;
-; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[28] ; 16 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0]~DUPLICATE ; 15 ;
-; riscv_core:core|imm[2]~DUPLICATE ; 15 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[363] ; 15 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0] ; 15 ;
-; riscv_core:core|dstvalue[3]~42 ; 15 ;
-; riscv_core:core|dstvalue[3]~41 ; 15 ;
-; riscv_core:core|dstvalue[3]~36 ; 15 ;
-; riscv_core:core|dstvalue[3]~35 ; 15 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0] ; 16 ;
+; riscv_core:core|dstvalue[2]~19 ; 16 ;
+; riscv_core:core|writedata[2]~0 ; 16 ;
+; riscv_core:core|ldaddr[1]~DUPLICATE ; 15 ;
+; riscv_core:core|dstvalue[2]~27 ; 15 ;
+; riscv_core:core|dstvalue[2]~26 ; 15 ;
+; riscv_core:core|dstvalue[2]~21 ; 15 ;
+; riscv_core:core|dstvalue[2]~20 ; 15 ;
+; riscv_core:core|imm[29]~9 ; 15 ;
; riscv_core:core|state.0001 ; 15 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3] ; 15 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[2] ; 15 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1] ; 15 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; 15 ;
-; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[7] ; 15 ;
-; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[1] ; 15 ;
-; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[3] ; 15 ;
-; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[4] ; 15 ;
-; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[9] ; 15 ;
-; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[10] ; 15 ;
-; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[13] ; 15 ;
-; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[17] ; 15 ;
-; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[18] ; 15 ;
-; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[19] ; 15 ;
-; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[0] ; 15 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0] ; 14 ;
-; riscv_core:core|imm[12]~5 ; 14 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0] ; 15 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|do_load_shifter ; 14 ;
; riscv_core:core|Equal7~0 ; 14 ;
-; led4[4]~0 ; 14 ;
+; led4[0]~0 ; 14 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; 14 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; 14 ;
; riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component|mult_81n:auto_generated|Mult0~523 ; 14 ;
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[15] ; 14 ;
@@ -3568,28 +3579,37 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[25] ; 14 ;
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[26] ; 14 ;
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[27] ; 14 ;
+; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[28] ; 14 ;
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[29] ; 14 ;
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[30] ; 14 ;
+; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[7] ; 14 ;
+; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[1] ; 14 ;
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[2] ; 14 ;
+; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[3] ; 14 ;
+; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[4] ; 14 ;
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[5] ; 14 ;
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[6] ; 14 ;
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[8] ; 14 ;
+; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[9] ; 14 ;
+; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[10] ; 14 ;
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[11] ; 14 ;
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[12] ; 14 ;
+; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[13] ; 14 ;
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[14] ; 14 ;
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[16] ; 14 ;
+; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[17] ; 14 ;
+; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[18] ; 14 ;
+; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[19] ; 14 ;
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[20] ; 14 ;
; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[21] ; 14 ;
+; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|q_a[0] ; 14 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2]~DUPLICATE ; 13 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[165] ; 13 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[165] ; 13 ;
-; riscv_core:core|dstvalue[3]~1 ; 13 ;
+; riscv_core:core|dstvalue[2]~18 ; 13 ;
+; riscv_core:core|dstvalue[2]~2 ; 13 ;
; riscv_core:core|state.1000 ; 13 ;
-; riscv_core:core|imm[27]~6 ; 13 ;
-; uartaddr[0]~0 ; 13 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3] ; 13 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2] ; 13 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1] ; 13 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0] ; 13 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1]~DUPLICATE ; 12 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a0~portb_address_reg3FITTER_CREATED_FF ; 12 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a0~portb_address_reg2FITTER_CREATED_FF ; 12 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a0~portb_address_reg1FITTER_CREATED_FF ; 12 ;
@@ -3599,47 +3619,51 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a0~portb_address_reg0FITTER_CREATED_FF ; 12 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a0~portb_address_reg1FITTER_CREATED_FF ; 12 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a0~portb_address_reg0FITTER_CREATED_FF ; 12 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[297] ; 12 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[2] ; 12 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[1] ; 12 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[0] ; 12 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1] ; 12 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1|counter_reg_bit[1] ; 12 ;
-; riscv_core:core|dstvalue[25]~59 ; 12 ;
-; riscv_core:core|dstvalue[25]~55 ; 12 ;
-; riscv_core:core|dstvalue[25]~54 ; 12 ;
-; riscv_core:core|dstvalue[25]~53 ; 12 ;
-; riscv_core:core|dstvalue[25]~52 ; 12 ;
-; riscv_core:core|dstvalue[3]~45 ; 12 ;
-; riscv_core:core|dstvalue[3]~43 ; 12 ;
-; riscv_core:core|dstvalue[3]~39 ; 12 ;
-; riscv_core:core|dstvalue[3]~37 ; 12 ;
-; riscv_core:core|dstvalue[3]~16 ; 12 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1|counter_reg_bit[0] ; 12 ;
+; riscv_core:core|dstvalue[25]~50 ; 12 ;
+; riscv_core:core|dstvalue[25]~46 ; 12 ;
+; riscv_core:core|dstvalue[25]~45 ; 12 ;
+; riscv_core:core|dstvalue[25]~44 ; 12 ;
+; riscv_core:core|dstvalue[25]~43 ; 12 ;
+; riscv_core:core|dstvalue[2]~30 ; 12 ;
+; riscv_core:core|dstvalue[2]~28 ; 12 ;
+; riscv_core:core|dstvalue[2]~24 ; 12 ;
+; riscv_core:core|dstvalue[2]~22 ; 12 ;
+; riscv_core:core|dstvalue[2]~13 ; 12 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in[0]~0 ; 12 ;
+; riscv_core:core|rs2[7]~_Duplicate_6 ; 12 ;
+; Equal0~5 ; 12 ;
+; Equal0~4 ; 12 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|got_new_char ; 12 ;
; riscv_core:core|rs2[6]~_Duplicate_6 ; 12 ;
; riscv_core:core|rs2[5]~_Duplicate_6 ; 12 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; 12 ;
-; riscv_core:core|rs2[7]~_Duplicate_6DUPLICATE ; 11 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1]~DUPLICATE ; 11 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[0] ; 11 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[132] ; 11 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[132] ; 11 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[297] ; 11 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[297] ; 11 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2] ; 11 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|cntr_phf:cntr1|counter_reg_bit[0] ; 11 ;
-; riscv_core:core|rs2[15]~_Duplicate_6 ; 11 ;
; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; 11 ;
+; riscv_core:core|rs2[15]~_Duplicate_6 ; 11 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5]~0 ; 11 ;
; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; 11 ;
; riscv_core:core|rs2[14]~_Duplicate_6 ; 11 ;
+; riscv_core:core|rs2[13]~_Duplicate_6 ; 11 ;
; riscv_core:core|rs2[12]~_Duplicate_6 ; 11 ;
; riscv_core:core|rs2[11]~_Duplicate_6 ; 11 ;
+; riscv_core:core|rs2[10]~_Duplicate_6 ; 11 ;
; riscv_core:core|rs2[9]~_Duplicate_6 ; 11 ;
; riscv_core:core|rs2[8]~_Duplicate_6 ; 11 ;
-; riscv_core:core|rs2[1]~_Duplicate_6 ; 11 ;
; led0~0 ; 11 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; 11 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; 11 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; 11 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0] ; 11 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; 11 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2]~DUPLICATE ; 10 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|cntr_uhf:cntr1|counter_reg_bit[1]~DUPLICATE ; 10 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[2]~DUPLICATE ; 10 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3]~DUPLICATE ; 10 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg3FITTER_CREATED_FF ; 10 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg2FITTER_CREATED_FF ; 10 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0~portb_address_reg1FITTER_CREATED_FF ; 10 ;
@@ -3659,160 +3683,137 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a0~portb_address_reg0FITTER_CREATED_FF ; 10 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a0~portb_address_reg1FITTER_CREATED_FF ; 10 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a0~portb_address_reg0FITTER_CREATED_FF ; 10 ;
-; SW[9]~input ; 10 ;
; KEY[3]~_wirecell ; 10 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[198] ; 10 ;
-; riscv_core:core|Mux26~2 ; 10 ;
+; riscv_core:core|Mux26~1 ; 10 ;
+; riscv_core:core|Mux26~0 ; 10 ;
+; riscv_core:core|dstvalue[2]~1 ; 10 ;
; riscv_core:core|rs2[23]~_Duplicate_6 ; 10 ;
-; riscv_core:core|dstvalue[3]~0 ; 10 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9]~0 ; 10 ;
+; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_wr_strobe~1 ; 10 ;
+; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_wr_strobe~0 ; 10 ;
; riscv_core:core|rs2[30]~_Duplicate_6 ; 10 ;
; riscv_core:core|rs2[29]~_Duplicate_6 ; 10 ;
; riscv_core:core|rs2[22]~_Duplicate_6 ; 10 ;
; riscv_core:core|rs2[21]~_Duplicate_6 ; 10 ;
; riscv_core:core|rs2[20]~_Duplicate_6 ; 10 ;
; riscv_core:core|rs2[19]~_Duplicate_6 ; 10 ;
+; riscv_core:core|rs2[18]~_Duplicate_6 ; 10 ;
+; riscv_core:core|rs2[17]~_Duplicate_6 ; 10 ;
; riscv_core:core|rs2[16]~_Duplicate_6 ; 10 ;
-; riscv_core:core|writedata[19]~4 ; 10 ;
-; riscv_core:core|rs2[13]~_Duplicate_6 ; 10 ;
+; riscv_core:core|writedata[22]~4 ; 10 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[198] ; 9 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[198] ; 9 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|always4~0 ; 9 ;
+; riscv_core:core|ldaddr[1] ; 9 ;
; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx1 ; 9 ;
; riscv_core:core|state.0000 ; 9 ;
-; riscv_core:core|rs1[31]~_Duplicate_6 ; 9 ;
+; uartaddr[8]~4 ; 9 ;
+; uartaddr[9]~3 ; 9 ;
+; uartaddr[10]~2 ; 9 ;
+; uartaddr[11]~1 ; 9 ;
+; uartaddr[12]~0 ; 9 ;
+; riscv_core:core|rs2[28]~_Duplicate_6 ; 9 ;
; riscv_core:core|rs2[27]~_Duplicate_6 ; 9 ;
; riscv_core:core|rs2[26]~_Duplicate_6 ; 9 ;
; riscv_core:core|rs2[25]~_Duplicate_6 ; 9 ;
; riscv_core:core|rs2[24]~_Duplicate_6 ; 9 ;
-; riscv_core:core|writedata[19]~5 ; 9 ;
+; riscv_core:core|writedata[22]~5 ; 9 ;
; riscv_core:core|writeaddr[1] ; 9 ;
; riscv_core:core|writeaddr[0] ; 9 ;
-; riscv_core:core|write ; 9 ;
-; riscv_core:core|rs2[18]~_Duplicate_6DUPLICATE ; 8 ;
-; riscv_core:core|rs2[10]~_Duplicate_6DUPLICATE ; 8 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[64] ; 8 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|cout_actual ; 8 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[256] ; 8 ;
; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|Equal0~1 ; 8 ;
-; ramaddr[10]~7 ; 8 ;
-; ramaddr[9]~6 ; 8 ;
-; ramaddr[8]~5 ; 8 ;
-; ramaddr[7]~4 ; 8 ;
-; ramaddr[6]~3 ; 8 ;
-; ramaddr[5]~2 ; 8 ;
-; ramaddr[4]~1 ; 8 ;
-; ramaddr[3]~0 ; 8 ;
-; uartaddr[2]~5 ; 8 ;
-; uartaddr[1]~4 ; 8 ;
-; uartaddr[0]~3 ; 8 ;
+; riscv_core:core|imm[14]~8 ; 8 ;
+; ramaddr[5]~4 ; 8 ;
+; ramaddr[4]~3 ; 8 ;
+; ramaddr[3]~2 ; 8 ;
; comb~1 ; 8 ;
-; riscv_core:core|writedata[27]~7 ; 8 ;
-; riscv_core:core|writedata[27]~6 ; 8 ;
+; riscv_core:core|imm[11] ; 8 ;
+; riscv_core:core|writedata[28]~7 ; 8 ;
+; riscv_core:core|writedata[28]~6 ; 8 ;
; riscv_core:core|Equal3~3 ; 8 ;
-; led2~0 ; 8 ;
-; riscv_core:core|rs2[28]~_Duplicate_6DUPLICATE ; 7 ;
-; riscv_core:core|rs2[17]~_Duplicate_6DUPLICATE ; 7 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2]~DUPLICATE ; 7 ;
+; riscv_core:core|writedata[6] ; 8 ;
+; riscv_core:core|writedata[5] ; 8 ;
+; riscv_core:core|writedata[4] ; 8 ;
+; riscv_core:core|writedata[3] ; 8 ;
+; riscv_core:core|writedata[2] ; 8 ;
+; riscv_core:core|writedata[1] ; 8 ;
+; riscv_core:core|writedata[0] ; 8 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a0~portb_address_reg3FITTER_CREATED_FF ; 7 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a0~portb_address_reg2FITTER_CREATED_FF ; 7 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a0~portb_address_reg1FITTER_CREATED_FF ; 7 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a0~portb_address_reg0FITTER_CREATED_FF ; 7 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[64] ; 7 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[128] ; 7 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[32] ; 7 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[160] ; 7 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[224] ; 7 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[256] ; 7 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[320] ; 7 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[66] ; 7 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[66] ; 7 ;
-; riscv_core:core|Selector241~0 ; 7 ;
-; riscv_core:core|Selector244~0 ; 7 ;
-; riscv_core:core|imm[11] ; 7 ;
-; riscv_core:core|rs2[4]~_Duplicate_6 ; 7 ;
+; riscv_core:core|dstvalue[8]~37 ; 7 ;
+; riscv_core:core|imm[10] ; 7 ;
+; riscv_core:core|imm[6] ; 7 ;
+; riscv_core:core|imm[9] ; 7 ;
+; riscv_core:core|imm[8] ; 7 ;
+; riscv_core:core|imm[31] ; 7 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_ready ; 7 ;
+; riscv_core:core|writedata[9] ; 7 ;
+; riscv_core:core|writedata[8] ; 7 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|add_sub_31_result_int[32]~1 ; 7 ;
; riscv_core:core|imm[30] ; 7 ;
; riscv_core:core|imm[29] ; 7 ;
; riscv_core:core|imm[28] ; 7 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2]~DUPLICATE ; 6 ;
+; readaddr[8] ; 7 ;
+; SW[9]~input ; 6 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|cout_actual ; 6 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|cout_actual ; 6 ;
-; riscv_core:core|Selector125~0 ; 6 ;
-; riscv_core:core|Mux26~1 ; 6 ;
+; riscv_core:core|divclk[4]~0 ; 6 ;
; riscv_core:core|Selector249~14 ; 6 ;
-; riscv_core:core|dstvalue[3]~33 ; 6 ;
+; bReadData[23]~20 ; 6 ;
; riscv_core:core|Selector121~0 ; 6 ;
; riscv_core:core|always7~0 ; 6 ;
-; uartaddr[0]~2 ; 6 ;
-; uartaddr[0]~1 ; 6 ;
-; riscv_core:core|imm[10] ; 6 ;
; riscv_core:core|imm[7] ; 6 ;
-; riscv_core:core|imm[6] ; 6 ;
-; riscv_core:core|imm[9] ; 6 ;
-; riscv_core:core|imm[8] ; 6 ;
+; riscv_core:core|imm[5] ; 6 ;
+; ramaddr[5]~1 ; 6 ;
+; ramaddr[5]~0 ; 6 ;
; riscv_core:core|writedata[14] ; 6 ;
; riscv_core:core|writedata[13] ; 6 ;
; riscv_core:core|writedata[12] ; 6 ;
; riscv_core:core|writedata[11] ; 6 ;
; riscv_core:core|writedata[10] ; 6 ;
-; riscv_core:core|writedata[9] ; 6 ;
-; riscv_core:core|writedata[8] ; 6 ;
+; led2~0 ; 6 ;
; riscv_core:core|imm[13] ; 6 ;
+; riscv_core:core|imm[12] ; 6 ;
; riscv_core:core|imm[24] ; 6 ;
-; riscv_core:core|imm[23] ; 6 ;
; riscv_core:core|imm[20] ; 6 ;
-; riscv_core:core|imm[27] ; 6 ;
+; riscv_core:core|imm[18] ; 6 ;
+; riscv_core:core|imm[17] ; 6 ;
+; riscv_core:core|imm[16] ; 6 ;
+; riscv_core:core|imm[15] ; 6 ;
+; riscv_core:core|imm[14] ; 6 ;
; riscv_core:core|imm[26] ; 6 ;
; riscv_core:core|imm[19] ; 6 ;
-; riscv_core:core|writedata[6] ; 6 ;
-; riscv_core:core|writedata[5] ; 6 ;
-; riscv_core:core|writedata[4] ; 6 ;
-; riscv_core:core|writedata[3] ; 6 ;
-; riscv_core:core|writedata[2] ; 6 ;
-; riscv_core:core|writedata[1] ; 6 ;
-; riscv_core:core|writedata[0] ; 6 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1]~DUPLICATE ; 5 ;
-; riscv_core:core|imm[5]~DUPLICATE ; 5 ;
-; riscv_core:core|imm[12]~DUPLICATE ; 5 ;
-; riscv_core:core|imm[15]~DUPLICATE ; 5 ;
-; SW[7]~input ; 5 ;
-; SW[8]~input ; 5 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[135] ; 5 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[134] ; 5 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[133] ; 5 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[132] ; 5 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[131] ; 5 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[130] ; 5 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[129] ; 5 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[137] ; 5 ;
+; riscv_core:core|writedata[7] ; 6 ;
+; ~GND ; 5 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[96] ; 5 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[192] ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[225] ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[35] ; 5 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[70] ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[274] ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[272] ; 5 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[278] ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[258] ; 5 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288] ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|cout_actual ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|cout_actual ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[338] ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[337] ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[336] ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[335] ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[330] ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[324] ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[322] ; 5 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[228] ; 5 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[228] ; 5 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[226] ; 5 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[226] ; 5 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[320] ; 5 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[99] ; 5 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[99] ; 5 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[72] ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[351] ; 5 ;
-; riscv_core:core|dstvalue[3]~46 ; 5 ;
-; riscv_core:core|dstvalue[3]~40 ; 5 ;
-; riscv_core:core|dstvalue[3]~32 ; 5 ;
-; bReadData[23]~18 ; 5 ;
+; riscv_core:core|Mux26~3 ; 5 ;
+; riscv_core:core|dstvalue[2]~31 ; 5 ;
+; riscv_core:core|dstvalue[2]~25 ; 5 ;
+; riscv_core:core|dstvalue[2]~17 ; 5 ;
+; bReadData[7]~22 ; 5 ;
; riscv_core:core|Equal0~7 ; 5 ;
-; riscv_core:core|dstreg[0]~1 ; 5 ;
-; riscv_core:core|imm[4]~1 ; 5 ;
-; readaddr[17]~0 ; 5 ;
-; bReadData[17]~10 ; 5 ;
-; bReadData[16]~9 ; 5 ;
+; riscv_core:core|dstreg[4]~1 ; 5 ;
+; riscv_core:core|imm[4]~2 ; 5 ;
+; bReadData[17]~11 ; 5 ;
+; bReadData[16]~10 ; 5 ;
+; bReadData[7]~3 ; 5 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] ; 5 ;
; riscv_core:core|writedata[30] ; 5 ;
; riscv_core:core|writedata[29] ; 5 ;
; riscv_core:core|writedata[28] ; 5 ;
@@ -3820,13 +3821,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|writedata[26] ; 5 ;
; riscv_core:core|writedata[25] ; 5 ;
; riscv_core:core|writedata[24] ; 5 ;
-; riscv_core:core|Mux26~5 ; 5 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[2] ; 5 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; 5 ;
; riscv_core:core|imm[21] ; 5 ;
-; riscv_core:core|Add0~101 ; 5 ;
-; riscv_core:core|Add0~97 ; 5 ;
-; riscv_core:core|Add0~93 ; 5 ;
-; riscv_core:core|Add0~17 ; 5 ;
-; riscv_core:core|Add0~13 ; 5 ;
; riscv_core:core|writedata[22] ; 5 ;
; riscv_core:core|writedata[21] ; 5 ;
; riscv_core:core|writedata[20] ; 5 ;
@@ -3834,52 +3831,63 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|writedata[18] ; 5 ;
; riscv_core:core|writedata[17] ; 5 ;
; riscv_core:core|writedata[16] ; 5 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[257]~DUPLICATE ; 4 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[142]~DUPLICATE ; 4 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0]~DUPLICATE ; 4 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3]~DUPLICATE ; 4 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2]~DUPLICATE ; 4 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1]~DUPLICATE ; 4 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0]~DUPLICATE ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288]~DUPLICATE ; 4 ;
+; riscv_core:core|imm[23]~DUPLICATE ; 4 ;
; riscv_core:core|imm[22]~DUPLICATE ; 4 ;
-; riscv_core:core|imm[18]~DUPLICATE ; 4 ;
-; riscv_core:core|imm[17]~DUPLICATE ; 4 ;
-; riscv_core:core|imm[14]~DUPLICATE ; 4 ;
; riscv_core:core|imm[25]~DUPLICATE ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[65] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[65] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[66] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[66] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[135] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[135] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[134] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[134] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[133] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[133] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[132] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[132] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[131] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[131] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[130] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[130] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[129] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[129] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[67] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[67] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[136] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[136] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[171] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[171] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[170] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[170] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[169] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[169] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[167] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[168] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[168] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[167] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[166] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[166] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[165] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[165] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[164] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[164] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[163] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[163] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[162] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[162] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[161] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[161] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[33] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[33] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[68] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[68] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[137] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[137] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[172] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[172] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[193] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[34] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[34] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[69] ; 4 ;
@@ -3916,14 +3924,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[230] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[229] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[229] ; 4 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[228] ; 4 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[228] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[227] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[227] ; 4 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[226] ; 4 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[226] ; 4 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[225] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[225] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[35] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[35] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[70] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[70] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[277] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[277] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[276] ; 4 ;
@@ -3933,11 +3940,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[139] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[139] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[274] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[274] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[273] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[273] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[271] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[272] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[272] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[271] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[174] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[174] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[270] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[270] ; 4 ;
@@ -3957,17 +3967,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[264] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[264] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[263] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[278] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[278] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[262] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[262] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[261] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[261] ; 4 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[260] ; 4 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[260] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[259] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[259] ; 4 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[258] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[257] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[257] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[36] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[36] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[71] ; 4 ;
@@ -3980,6 +3989,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[244] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[279] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[279] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|cout_actual ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[348] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[348] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[347] ; 4 ;
@@ -3994,6 +4004,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[343] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[342] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[342] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|cout_actual ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[341] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[341] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[340] ; 4 ;
@@ -4001,9 +4012,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[339] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[339] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[338] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[338] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[337] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[337] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[335] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[336] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[336] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[335] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[334] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[334] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[333] ; 4 ;
@@ -4013,6 +4028,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[331] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[331] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[330] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[330] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[329] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[329] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[327] ; 4 ;
@@ -4024,9 +4040,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[325] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[325] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[324] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[324] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[323] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[323] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[322] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[322] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[321] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[321] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[29] ; 4 ;
@@ -4038,12 +4056,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[0] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[37] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[37] ; 4 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[38] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[73] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[72] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[73] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[72] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[141] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[141] ; 4 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[142] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[142] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[177] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[176] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[177] ; 4 ;
@@ -4057,6 +4078,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[349] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[349] ; 4 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[350] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[350] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[351] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[1] ; 4 ;
; riscv_core:core|writedata[31] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~31 ; 4 ;
@@ -4065,63 +4088,66 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~28 ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~27 ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~25 ; 4 ;
-; riscv_core:core|Mux1~0 ; 4 ;
; riscv_core:core|ShiftLeft0~5 ; 4 ;
; riscv_core:core|ShiftLeft1~5 ; 4 ;
; riscv_core:core|ShiftLeft0~3 ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~23 ; 4 ;
; riscv_core:core|ShiftRight0~26 ; 4 ;
-; riscv_core:core|dstvalue[3]~44 ; 4 ;
+; riscv_core:core|dstvalue[2]~29 ; 4 ;
; riscv_core:core|ShiftLeft1~3 ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~20 ; 4 ;
; riscv_core:core|ShiftRight1~28 ; 4 ;
-; riscv_core:core|dstvalue[3]~38 ; 4 ;
+; riscv_core:core|dstvalue[2]~23 ; 4 ;
; riscv_core:core|ShiftLeft1~1 ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~16 ; 4 ;
; riscv_core:core|ShiftRight1~17 ; 4 ;
; riscv_core:core|ShiftLeft0~1 ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~13 ; 4 ;
; riscv_core:core|ShiftRight0~15 ; 4 ;
-; riscv_core:core|dstvalue[7] ; 4 ;
-; bReadData[22]~17 ; 4 ;
+; bReadData[25]~26 ; 4 ;
+; bReadData[9]~21 ; 4 ;
+; bReadData[22]~19 ; 4 ;
; riscv_core:core|writedata[15] ; 4 ;
-; riscv_core:core|Selector252~1 ; 4 ;
-; bReadData[24]~14 ; 4 ;
+; riscv_core:core|Selector252~0 ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~10 ; 4 ;
; riscv_core:core|ShiftRight1~6 ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~4 ; 4 ;
; riscv_core:core|ShiftRight0~5 ; 4 ;
+; bReadData[8]~16 ; 4 ;
+; bReadData[24]~15 ; 4 ;
; riscv_core:core|divclk[0] ; 4 ;
-; riscv_core:core|imm[3]~7 ; 4 ;
; riscv_core:core|instr[7] ; 4 ;
; riscv_core:core|WideOr20 ; 4 ;
-; bReadData[19]~12 ; 4 ;
-; bReadData[18]~11 ; 4 ;
+; bReadData[19]~13 ; 4 ;
+; riscv_core:core|instr[23] ; 4 ;
+; bReadData[18]~12 ; 4 ;
; riscv_core:core|instr[22] ; 4 ;
-; bReadData[15]~8 ; 4 ;
+; bReadData[15]~9 ; 4 ;
; riscv_core:core|instr[20] ; 4 ;
-; riscv_core:core|imm[31] ; 4 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[0] ; 4 ;
+; riscv_core:core|imm[4]~0 ; 4 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|WideOr0 ; 4 ;
+; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|status_wr_strobe~0 ; 4 ;
+; riscv_core:core|bReadAddr[21]~25 ; 4 ;
; riscv_core:core|Equal2~0 ; 4 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_overrun ; 4 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_overrun ; 4 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|break_detect ; 4 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|framing_error ; 4 ;
+; riscv_core:core|writeaddr[31] ; 4 ;
; riscv_core:core|writeaddr[2] ; 4 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[1] ; 4 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[2] ; 4 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; 4 ;
-; riscv_core:core|writedata[7] ; 4 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1] ; 4 ;
; riscv_core:core|writedata[23] ; 4 ;
-; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|q_a[23] ; 4 ;
-; riscv_core:core|pc[11] ; 4 ;
-; riscv_core:core|pc[10] ; 4 ;
-; riscv_core:core|pc[9] ; 4 ;
-; riscv_core:core|pc[8] ; 4 ;
-; riscv_core:core|pc[12] ; 4 ;
; riscv_core:core|Add0~125 ; 4 ;
; riscv_core:core|Add0~121 ; 4 ;
; riscv_core:core|Add0~117 ; 4 ;
; riscv_core:core|Add0~113 ; 4 ;
; riscv_core:core|Add0~109 ; 4 ;
; riscv_core:core|Add0~105 ; 4 ;
+; riscv_core:core|Add0~101 ; 4 ;
+; riscv_core:core|Add0~97 ; 4 ;
+; riscv_core:core|Add0~93 ; 4 ;
; riscv_core:core|Add0~89 ; 4 ;
; riscv_core:core|Add0~85 ; 4 ;
; riscv_core:core|Add0~81 ; 4 ;
@@ -4140,26 +4166,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|Add0~29 ; 4 ;
; riscv_core:core|Add0~25 ; 4 ;
; riscv_core:core|Add0~21 ; 4 ;
+; riscv_core:core|Add0~17 ; 4 ;
+; riscv_core:core|Add0~13 ; 4 ;
; riscv_core:core|Add0~9 ; 4 ;
; riscv_core:core|Add0~5 ; 4 ;
; riscv_core:core|Add0~1 ; 4 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[67]~DUPLICATE ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[169]~DUPLICATE ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[167]~DUPLICATE ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[166]~DUPLICATE ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[164]~DUPLICATE ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[163]~DUPLICATE ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[162]~DUPLICATE ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[174]~DUPLICATE ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[73]~DUPLICATE ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0]~DUPLICATE ; 3 ;
-; riscv_core:core|imm[31]~DUPLICATE ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1]~DUPLICATE ; 3 ;
-; riscv_core:core|imm[16]~DUPLICATE ; 3 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_char_ready~DUPLICATE ; 3 ;
+; riscv_core:core|imm[27]~DUPLICATE ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a5 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a6 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a1 ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a2 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a0 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5|ram_block6a5 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5|ram_block6a6 ; 3 ;
@@ -4168,18 +4184,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a5 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a6 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a1 ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a7 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a0 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a5 ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a1 ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a6 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a0 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a5 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a6 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a1 ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a7 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a0 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a5 ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a6 ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a1 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a0 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a7 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a1 ; 3 ;
@@ -4188,7 +4202,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a7 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a1 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a6 ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a8 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a0 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a7 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a1 ; 3 ;
@@ -4198,7 +4211,9 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; KEY[1]~input ; 3 ;
; KEY[0]~input ; 3 ;
; KEY[2]~input ; 3 ;
+; SW[8]~input ; 3 ;
; led2~0_wirecell ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[57] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[100] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[100] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[99] ; 3 ;
@@ -4207,16 +4222,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[98] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[97] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[97] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[96] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[58] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[58] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[101] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[101] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFNumerator[59] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFNumerator[59] ; 3 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[102] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[102] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[165] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[161] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[103] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[103] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[206] ; 3 ;
@@ -4247,16 +4260,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[195] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[194] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[194] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[193] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[193] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[104] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[104] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[208] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[208] ; 3 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[225] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[105] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[105] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[209] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[209] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[258] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cmpr4_aeb_int~0 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|op_2~0 ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[314] ; 3 ;
@@ -4267,6 +4281,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[312] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[312] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[311] ; 3 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[310] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[310] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[309] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[309] ; 3 ;
@@ -4277,12 +4292,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[307] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[307] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[306] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[306] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[305] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[305] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cmpr4_aeb_int~0 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|op_2~0 ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[303] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[304] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[304] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[303] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[302] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[302] ; 3 ;
@@ -4311,83 +4328,83 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[291] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[291] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[290] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[290] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[289] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[289] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[33]~47 ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[315] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[315] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[316] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[316] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[317] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[317] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[318] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[318] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[319] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[2] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[3] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[21] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[20] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[28] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[26] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[18] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[15] ; 3 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[13] ; 3 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[8] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[38] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[61] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[43] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[41] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[38] ; 3 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[53] ; 3 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[52] ; 3 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[51] ; 3 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[46] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[63] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[51] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[48] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[297]~24 ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[76] ; 3 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[88] ; 3 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[94] ; 3 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[80] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[297]~24 ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[88] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[87] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[86] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[75] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[107] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[119] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[124] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[110] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[114] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[115] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[107] ; 3 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[125] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[119] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[113] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[112] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[111] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[462]~13 ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[158] ; 3 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[152] ; 3 ;
+; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[156] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[146] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[462]~13 ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[152] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[148] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[157] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[150] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[146] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[561]~9 ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[184] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[181] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[561]~9 ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[185] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[183] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[181] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[211] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[211] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[5] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[216] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[217] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[215] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[223] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[221] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[219] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|selnose[726]~3 ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[252] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[251] ; 3 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[250] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|selnose[726]~3 ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[255] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[251] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[281] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[281] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[286] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[284] ; 3 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[350] ; 3 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[3] ; 3 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[352] ; 3 ;
; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|always2~0 ; 3 ;
-; riscv_core:core|dstvalue[30]~65 ; 3 ;
-; riscv_core:core|dstvalue[30]~64 ; 3 ;
-; riscv_core:core|dstvalue[30]~63 ; 3 ;
-; riscv_core:core|dstvalue[30]~62 ; 3 ;
-; riscv_core:core|dstvalue[30]~61 ; 3 ;
-; riscv_core:core|dstvalue[30]~60 ; 3 ;
+; riscv_core:core|dstvalue[29]~56 ; 3 ;
+; riscv_core:core|dstvalue[29]~55 ; 3 ;
+; riscv_core:core|dstvalue[29]~54 ; 3 ;
+; riscv_core:core|dstvalue[29]~53 ; 3 ;
+; riscv_core:core|dstvalue[29]~52 ; 3 ;
+; riscv_core:core|dstvalue[29]~51 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~33 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~32 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~26 ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|norm_num[30]~24 ; 3 ;
; riscv_core:core|Mux2~0 ; 3 ;
+; riscv_core:core|ShiftLeft0~22 ; 3 ;
+; riscv_core:core|ShiftLeft0~21 ; 3 ;
+; riscv_core:core|ShiftLeft1~22 ; 3 ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
@@ -4396,18 +4413,18 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+----------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+-------------------------------------------------------------------+
; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLAB cells ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; Fits in MLABs ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+----------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+-------------------------------------------------------------------+
-; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 2048 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 65536 ; 2048 ; 32 ; -- ; -- ; 65536 ; 8 ; 0 ; test.mif ; M10K_X38_Y16_N0, M10K_X38_Y18_N0, M10K_X41_Y15_N0, M10K_X41_Y17_N0, M10K_X41_Y16_N0, M10K_X38_Y15_N0, M10K_X38_Y17_N0, M10K_X41_Y18_N0 ; Don't care ; New data ; New data ; No - Address Too Wide ;
-; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 32 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 1024 ; 32 ; 32 ; -- ; -- ; 1024 ; 1 ; 0 ; None ; M10K_X49_Y14_N0 ; Don't care ; New data ; New data ; No - Single Port Feed Through New Data with Unregistered Data Out ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 11 ; 10 ; 11 ; 10 ; yes ; no ; no ; yes ; 110 ; 11 ; 10 ; 11 ; 10 ; 110 ; 0 ; 10 ; None ; LAB_X34_Y21_N0 ; ; ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 10 ; 10 ; 10 ; 10 ; yes ; no ; no ; yes ; 100 ; 10 ; 10 ; 10 ; 10 ; 100 ; 0 ; 10 ; None ; LAB_X39_Y21_N0 ; ; ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 9 ; 12 ; 9 ; 12 ; yes ; no ; no ; yes ; 108 ; 9 ; 12 ; 9 ; 12 ; 108 ; 0 ; 12 ; None ; LAB_X34_Y28_N0 ; ; ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 8 ; 10 ; 8 ; 10 ; yes ; no ; no ; yes ; 80 ; 8 ; 10 ; 8 ; 10 ; 80 ; 0 ; 10 ; None ; LAB_X39_Y27_N0 ; ; ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 7 ; 10 ; 7 ; 10 ; yes ; no ; no ; yes ; 70 ; 7 ; 10 ; 7 ; 10 ; 70 ; 0 ; 10 ; None ; LAB_X34_Y22_N0 ; ; ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 6 ; 12 ; 6 ; 12 ; yes ; no ; no ; yes ; 72 ; 6 ; 12 ; 6 ; 12 ; 72 ; 0 ; 12 ; None ; LAB_X39_Y29_N0 ; ; ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 5 ; 10 ; 5 ; 10 ; yes ; no ; no ; yes ; 50 ; 5 ; 10 ; 5 ; 10 ; 50 ; 0 ; 10 ; None ; LAB_X34_Y26_N0 ; ; ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 4 ; 10 ; 4 ; 10 ; yes ; no ; no ; yes ; 40 ; 4 ; 10 ; 4 ; 10 ; 40 ; 0 ; 10 ; None ; LAB_X47_Y24_N0 ; ; ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 3 ; 12 ; 3 ; 12 ; yes ; no ; no ; yes ; 36 ; 3 ; 12 ; 3 ; 12 ; 36 ; 0 ; 12 ; None ; LAB_X47_Y25_N0 ; ; ; ; ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 10 ; 7 ; 10 ; 7 ; yes ; no ; no ; yes ; 70 ; 10 ; 7 ; 10 ; 7 ; 70 ; 0 ; 7 ; None ; LAB_X34_Y20_N0 ; ; ; ; ;
+; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 2048 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 65536 ; 2048 ; 32 ; -- ; -- ; 65536 ; 8 ; 0 ; test.mif ; M10K_X58_Y23_N0, M10K_X58_Y22_N0, M10K_X49_Y21_N0, M10K_X49_Y22_N0, M10K_X49_Y23_N0, M10K_X49_Y24_N0, M10K_X58_Y21_N0, M10K_X49_Y19_N0 ; Don't care ; New data ; New data ; No - Address Too Wide ;
+; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 32 ; 32 ; -- ; -- ; yes ; no ; -- ; -- ; 1024 ; 32 ; 32 ; -- ; -- ; 1024 ; 1 ; 0 ; None ; M10K_X49_Y20_N0 ; Don't care ; New data ; New data ; No - Single Port Feed Through New Data with Unregistered Data Out ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 11 ; 10 ; 11 ; 10 ; yes ; no ; no ; yes ; 110 ; 11 ; 10 ; 11 ; 10 ; 110 ; 0 ; 10 ; None ; LAB_X34_Y33_N0 ; ; ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 10 ; 10 ; 10 ; 10 ; yes ; no ; no ; yes ; 100 ; 10 ; 10 ; 10 ; 10 ; 100 ; 0 ; 10 ; None ; LAB_X47_Y26_N0 ; ; ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 9 ; 12 ; 9 ; 12 ; yes ; no ; no ; yes ; 108 ; 9 ; 12 ; 9 ; 12 ; 108 ; 0 ; 12 ; None ; LAB_X47_Y27_N0 ; ; ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 8 ; 10 ; 8 ; 10 ; yes ; no ; no ; yes ; 80 ; 8 ; 10 ; 8 ; 10 ; 80 ; 0 ; 10 ; None ; LAB_X39_Y32_N0 ; ; ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 7 ; 10 ; 7 ; 10 ; yes ; no ; no ; yes ; 70 ; 7 ; 10 ; 7 ; 10 ; 70 ; 0 ; 10 ; None ; LAB_X47_Y32_N0 ; ; ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 6 ; 12 ; 6 ; 12 ; yes ; no ; no ; yes ; 72 ; 6 ; 12 ; 6 ; 12 ; 72 ; 0 ; 12 ; None ; LAB_X34_Y29_N0 ; ; ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 5 ; 10 ; 5 ; 10 ; yes ; no ; no ; yes ; 50 ; 5 ; 10 ; 5 ; 10 ; 50 ; 0 ; 10 ; None ; LAB_X52_Y29_N0 ; ; ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 4 ; 10 ; 4 ; 10 ; yes ; no ; no ; yes ; 40 ; 4 ; 10 ; 4 ; 10 ; 40 ; 0 ; 10 ; None ; LAB_X34_Y26_N0 ; ; ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 3 ; 12 ; 3 ; 12 ; yes ; no ; no ; yes ; 36 ; 3 ; 12 ; 3 ; 12 ; 36 ; 0 ; 12 ; None ; LAB_X34_Y28_N0 ; ; ; ; ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ALTSYNCRAM ; MLAB ; Simple Dual Port ; Dual Clocks ; 10 ; 7 ; 10 ; 7 ; yes ; no ; no ; yes ; 70 ; 10 ; 7 ; 10 ; 7 ; 70 ; 0 ; 7 ; None ; LAB_X34_Y21_N0 ; ; ; ; ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+----------+----------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+-------------------------------------------------------------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
@@ -4435,14 +4452,14 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing.
+---------------------------------------------+-------------------------+
; Routing Resource Type ; Usage ;
+---------------------------------------------+-------------------------+
-; Block interconnects ; 8,941 / 289,320 ( 3 % ) ;
-; C12 interconnects ; 94 / 13,420 ( < 1 % ) ;
-; C2 interconnects ; 3,192 / 119,108 ( 3 % ) ;
-; C4 interconnects ; 1,703 / 56,300 ( 3 % ) ;
+; Block interconnects ; 8,826 / 289,320 ( 3 % ) ;
+; C12 interconnects ; 218 / 13,420 ( 2 % ) ;
+; C2 interconnects ; 3,554 / 119,108 ( 3 % ) ;
+; C4 interconnects ; 1,886 / 56,300 ( 3 % ) ;
; DQS bus muxes ; 0 / 25 ( 0 % ) ;
; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ;
; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ;
-; Direct links ; 917 / 289,320 ( < 1 % ) ;
+; Direct links ; 771 / 289,320 ( < 1 % ) ;
; Global clocks ; 1 / 16 ( 6 % ) ;
; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
@@ -4498,12 +4515,12 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing.
; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ;
-; Local interconnects ; 1,536 / 84,580 ( 2 % ) ;
+; Local interconnects ; 1,641 / 84,580 ( 2 % ) ;
; Quadrant clocks ; 0 / 66 ( 0 % ) ;
-; R14 interconnects ; 313 / 12,676 ( 2 % ) ;
-; R14/C12 interconnect drivers ; 374 / 20,720 ( 2 % ) ;
-; R3 interconnects ; 3,906 / 130,992 ( 3 % ) ;
-; R6 interconnects ; 6,099 / 266,960 ( 2 % ) ;
+; R14 interconnects ; 363 / 12,676 ( 3 % ) ;
+; R14/C12 interconnect drivers ; 532 / 20,720 ( 3 % ) ;
+; R3 interconnects ; 4,177 / 130,992 ( 3 % ) ;
+; R6 interconnects ; 6,312 / 266,960 ( 2 % ) ;
; Spine clocks ; 5 / 360 ( 1 % ) ;
; Wire stub REs ; 0 / 15,858 ( 0 % ) ;
+---------------------------------------------+-------------------------+
@@ -4818,7 +4835,7 @@ Note: Fitter may spread logical memories into multiple blocks to improve timing.
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-------------------+
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-------------------+
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 60.1 ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 60.6 ;
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-------------------+
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
@@ -4829,106 +4846,106 @@ This will disable optimization of problematic paths and expose them for further
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
; Source Register ; Destination Register ; Delay Added in ns ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.864 ;
-; riscv_core:core|divclk[3] ; riscv_core:core|dstvalue[31] ; 0.811 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.808 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.784 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.784 ;
-; riscv_core:core|divclk[2] ; riscv_core:core|dstvalue[31] ; 0.763 ;
-; riscv_core:core|divclk[1] ; riscv_core:core|dstvalue[31] ; 0.735 ;
-; riscv_core:core|divclk[0] ; riscv_core:core|dstvalue[31] ; 0.719 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.708 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.674 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.629 ;
-; riscv_core:core|divclk[4] ; riscv_core:core|dstvalue[31] ; 0.597 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.586 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.571 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.537 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.504 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; 0.504 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; 0.444 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.444 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.444 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.431 ;
-; riscv_core:core|dstvalue[31] ; riscv_core:core|dstvalue[31] ; 0.416 ;
-; riscv_core:core|instr[13] ; riscv_core:core|dstvalue[31] ; 0.416 ;
-; riscv_core:core|state.1000 ; riscv_core:core|dstvalue[31] ; 0.416 ;
-; riscv_core:core|state.1010 ; riscv_core:core|dstvalue[31] ; 0.416 ;
-; riscv_core:core|instr[12] ; riscv_core:core|dstvalue[31] ; 0.416 ;
-; riscv_core:core|instr[14] ; riscv_core:core|dstvalue[31] ; 0.416 ;
-; riscv_core:core|state.0111 ; riscv_core:core|dstvalue[31] ; 0.416 ;
-; riscv_core:core|state.0001 ; regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated|ram_block1a7~porta_address_reg0 ; 0.409 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.402 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.402 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.402 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.402 ;
-; riscv_core:core|rs1[13]~_Duplicate_6 ; riscv_core:core|dstvalue[14] ; 0.397 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.390 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; riscv_core:core|dstvalue[12] ; 0.369 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.366 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.364 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxsync_rxdxx1 ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0.363 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; riscv_core:core|dstvalue[12] ; 0.363 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[3] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0.352 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.351 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.349 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; 0.349 ;
-; riscv_core:core|dstvalue[15] ; riscv_core:core|dstvalue[15] ; 0.347 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; 0.340 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; 0.340 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.338 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.337 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[3] ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; 0.621 ;
+; riscv_core:core|divclk[3] ; riscv_core:core|dstvalue[31] ; 0.602 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[1] ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; 0.601 ;
+; readaddr[8] ; riscv_core:core|dstvalue[15] ; 0.586 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.581 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[0] ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; 0.579 ;
+; riscv_core:core|divclk[4] ; riscv_core:core|dstvalue[31] ; 0.566 ;
+; riscv_core:core|pc[8] ; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[4] ; 0.565 ;
+; riscv_core:core|dstvalue[31] ; riscv_core:core|dstvalue[31] ; 0.553 ;
+; riscv_core:core|instr[13] ; riscv_core:core|dstvalue[31] ; 0.553 ;
+; riscv_core:core|state.1000 ; riscv_core:core|dstvalue[31] ; 0.553 ;
+; riscv_core:core|divclk[2] ; riscv_core:core|dstvalue[31] ; 0.553 ;
+; riscv_core:core|divclk[0] ; riscv_core:core|dstvalue[31] ; 0.553 ;
+; riscv_core:core|divclk[1] ; riscv_core:core|dstvalue[31] ; 0.553 ;
+; riscv_core:core|state.1010 ; riscv_core:core|dstvalue[31] ; 0.553 ;
+; riscv_core:core|instr[12] ; riscv_core:core|dstvalue[31] ; 0.553 ;
+; riscv_core:core|instr[14] ; riscv_core:core|dstvalue[31] ; 0.553 ;
+; riscv_core:core|state.0111 ; riscv_core:core|dstvalue[31] ; 0.553 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.520 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.479 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; 0.471 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.456 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[8] ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; 0.440 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[7] ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; 0.440 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[6] ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; 0.440 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[5] ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; 0.440 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[4] ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; 0.440 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; 0.434 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.419 ;
+; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[7] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[18] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[24] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[25] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[27] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[14] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[26] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[15] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[16] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[17] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[19] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[20] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[21] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[22] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[12] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[13] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[28] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[29] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[31] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[30] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[9] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[10] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[11] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; riscv_core:core|ldaddr[1] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a15~porta_datain_reg0 ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a15~porta_we_reg ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a31~porta_datain_reg0 ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a31~porta_we_reg ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; readaddr[23] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; riscv_core:core|dstvalue[15] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; riscv_core:core|ldaddr[0] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a7~porta_datain_reg0 ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a7~porta_we_reg ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; SW[7] ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a23~porta_datain_reg0 ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a23~porta_we_reg ; riscv_core:core|dstvalue[15] ; 0.395 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[324] ; 0.386 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[324] ; 0.386 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[324] ; 0.386 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|cntr_8jf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[324] ; 0.386 ;
+; riscv_core:core|dstvalue[1] ; riscv_core:core|dstvalue[1] ; 0.384 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[177] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.378 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.378 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[2] ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0] ; 0.372 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.372 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.372 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|cntr_0if:cntr1|counter_reg_bit[3] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.372 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|dffe3a[1] ; riscv_core:core|dstvalue[12] ; 0.365 ;
+; riscv_core:core|rs2[27]~_Duplicate_6 ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[27] ; 0.364 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4|ram_block5a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.364 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.362 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; riscv_core:core|dstvalue[12] ; 0.362 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.361 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4|ram_block5a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.361 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|cntr_rhf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.357 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.356 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|cntr_9jf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|dffe3a[1] ; 0.356 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|cntr_thf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.353 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[6] ; 0.351 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5|ram_block6a5~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.344 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.341 ;
+; riscv_core:core|rs2[28]~_Duplicate_6 ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[28] ; 0.339 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4|ram_block5a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.338 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[2] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|cntr_shf:cntr1|counter_reg_bit[1] ; 0.338 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5|ram_block6a4~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.337 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; 0.335 ;
-; riscv_core:core|rs2[11]~_Duplicate_6 ; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[11] ; 0.335 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[324] ; 0.334 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0.334 ;
-; riscv_core:core|rs2[0]~_Duplicate_6 ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[30] ; 0.331 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; 0.331 ;
-; riscv_core:core|rs1[14]~_Duplicate_6 ; riscv_core:core|dstvalue[14] ; 0.329 ;
-; riscv_core:core|dstvalue[7] ; riscv_core:core|dstvalue[7] ; 0.327 ;
-; riscv_core:core|instr[7] ; riscv_core:core|dstreg[0] ; 0.324 ;
-; riscv_core:core|pc[2] ; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a0~porta_address_reg0 ; 0.320 ;
-; riscv_core:core|pc[0] ; riscv_core:core|ldaddr[0] ; 0.318 ;
-; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[1] ; 0.315 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[2] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0.314 ;
-; riscv_core:core|state.0011 ; riscv_core:core|dstvalue[31] ; 0.313 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] ; 0.312 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] ; 0.312 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] ; 0.312 ;
-; riscv_core:core|pc[1] ; riscv_core:core|ldaddr[1] ; 0.311 ;
-; riscv_core:core|state.0100 ; riscv_core:core|dstvalue[31] ; 0.299 ;
-; riscv_core:core|state.0101 ; riscv_core:core|dstvalue[31] ; 0.299 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[7] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[6] ; 0.298 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[4] ; 0.298 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[3] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[2] ; 0.298 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[1] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|do_start_rx ; 0.298 ;
-; riscv_core:core|readreg[1] ; riscv_core:core|dstreg[1] ; 0.298 ;
-; riscv_core:core|readreg[3] ; riscv_core:core|dstreg[3] ; 0.298 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|delayed_unxrx_in_processxx3 ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_char_ready ; 0.295 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[8] ; 0.295 ;
-; riscv_core:core|readreg[2] ; riscv_core:core|dstreg[2] ; 0.283 ;
-; riscv_core:core|readreg[0] ; riscv_core:core|dstreg[0] ; 0.283 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5|ram_block6a9~FITTER_CREATED_MLAB_CELL0porta_datain_reg0 ; 0.282 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[0] ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|baud_rate_counter[1] ; 0.274 ;
-; riscv_core:core|rs1[15]~_Duplicate_6 ; HEX0[0] ; 0.256 ;
-; SW[1] ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a1~porta_datain_reg0 ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated|ram_block1a1~porta_we_reg ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; readaddr[24] ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; readaddr[14] ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; readaddr[18] ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; readaddr[20] ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; readaddr[17] ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; readaddr[21] ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; readaddr[22] ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; readaddr[16] ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; readaddr[23] ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; readaddr[25] ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; readaddr[26] ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; readaddr[27] ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; readaddr[15] ; riscv_core:core|dstvalue[1] ; 0.249 ;
-; readaddr[19] ; riscv_core:core|dstvalue[1] ; 0.249 ;
+; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[8] ; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[8] ; 0.336 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|pre_txd ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|txd ; 0.334 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_char_ready ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_overrun ; 0.334 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[0] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|cntr_ohf:cntr1|counter_reg_bit[1] ; 0.333 ;
+; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|dffe3a[1] ; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFQuotient[324] ; 0.332 ;
+; SW[9] ; riscv_core:core|dstvalue[1] ; 0.331 ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+
Note: This table only shows the top 100 path(s) that have the largest delay added for hold.
@@ -4948,7 +4965,7 @@ Warning (205009): Dummy RLC values generated in IBIS model files for device 5CSE
Info (184020): Starting Fitter periphery placement operations
Warning (205009): Dummy RLC values generated in IBIS model files for device 5CSEMA5 with package FBGA and pin count 896
Info (11191): Automatically promoted 1 clock (1 global)
- Info (11162): clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0 with 1906 fanout uses global clock CLKCTRL_G0
+ Info (11162): clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0 with 1972 fanout uses global clock CLKCTRL_G0
Warning (205009): Dummy RLC values generated in IBIS model files for device 5CSEMA5 with package FBGA and pin count 896
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
Info (332164): Evaluating HDL-embedded SDC commands
@@ -4976,7 +4993,7 @@ Warning (332049): Ignored set_output_delay at de1_riscv.sdc(34): Argument is an empty collection
@@ -4994,7 +5011,7 @@ Info (332111): Found 11 clocks
Info (332111): Period Clock Name
Info (332111): ======== ============
Info (332111): 3.333 clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]
- Info (332111): 10.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
+ Info (332111): 20.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
Info (332111): 54.253 clk_audxck
Info (332111): 2.500 clk_core
Info (332111): 10.000 clk_dram
@@ -5008,7 +5025,7 @@ Info (176233): Starting register packing
Info (176235): Finished register packing
Extra Info (176218): Packed 384 registers into blocks of type DSP block
Extra Info (176220): Created 384 register duplicates
-Info (11798): Fitter preparation operations ending: elapsed time is 00:00:14
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:15
Info (170189): Fitter placement preparation operations beginning
Warning (170052): Fitter has implemented the following 103 RAMs using MLAB locations, which can behave differently during power up than dedicated RAM locations
Info (170241): For more information about RAMs, refer to the Fitter RAM Summary report.
@@ -5017,14 +5034,15 @@ Info (170056): Fitter has implemented the following 103 RAMs using MLAB location
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:06
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:14
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:06
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 2% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 28% of the available device resources in the region that extends from location X33_Y11 to location X44_Y22
-Info (170194): Fitter routing operations ending: elapsed time is 00:00:16
+ Info (170196): Router estimated peak interconnect usage is 25% of the available device resources in the region that extends from location X45_Y11 to location X55_Y22
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:09
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info (170201): Optimizations that may affect the design's routability were skipped
-Info (11888): Total time spent on timing analysis during the Fitter is 10.22 seconds.
+ Info (170200): Optimizations that may affect the design's timing were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 9.00 seconds.
Info (334003): Started post-fitting delay annotation
Warning (334000): Timing characteristics of device 5CSEMA5F31C6 are preliminary
Info (334004): Delay annotation completed successfully
@@ -5095,10 +5113,10 @@ Warning (169064): Following 60 pins have no output enable or a GND or VCC output
Info (169065): Pin GPIO[7] has a permanently disabled output enable
Info (144001): Generated suppressed messages file D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv.fit.smsg
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 29 warnings
- Info: Peak virtual memory: 2323 megabytes
- Info: Processing ended: Sat Aug 28 10:55:54 2021
- Info: Elapsed time: 00:01:57
- Info: Total CPU time (on all processors): 00:02:34
+ Info: Peak virtual memory: 2331 megabytes
+ Info: Processing ended: Sat Aug 28 16:28:28 2021
+ Info: Elapsed time: 00:01:46
+ Info: Total CPU time (on all processors): 00:02:14
+----------------------------+
diff --git a/examples/hdl4se_riscv/de1/de1_riscv.fit.summary b/examples/hdl4se_riscv/de1/de1_riscv.fit.summary
index 45b60eee8d0d0e5c34d9da1dcb1ef0be17fd6038..8ed2b9c79c8f11b191ebbe3b84739487680876dd 100644
--- a/examples/hdl4se_riscv/de1/de1_riscv.fit.summary
+++ b/examples/hdl4se_riscv/de1/de1_riscv.fit.summary
@@ -1,12 +1,12 @@
-Fitter Status : Successful - Sat Aug 28 10:55:51 2021
+Fitter Status : Successful - Sat Aug 28 16:28:25 2021
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : de1_riscv
Top-level Entity Name : de1_riscv
Family : Cyclone V
Device : 5CSEMA5F31C6
Timing Models : Preliminary
-Logic utilization (in ALMs) : 2,494 / 32,070 ( 8 % )
-Total registers : 1863
+Logic utilization (in ALMs) : 2,514 / 32,070 ( 8 % )
+Total registers : 1859
Total pins : 204 / 457 ( 45 % )
Total virtual pins : 0
Total block memory bits : 66,560 / 4,065,280 ( 2 % )
diff --git a/examples/hdl4se_riscv/de1/de1_riscv.flow.rpt b/examples/hdl4se_riscv/de1/de1_riscv.flow.rpt
index 7ab1e81ebf4840ee9e697f997766a7582145f170..0c68395ebd13dc9e6bd8f1437ad8a6d557adc0f1 100644
--- a/examples/hdl4se_riscv/de1/de1_riscv.flow.rpt
+++ b/examples/hdl4se_riscv/de1/de1_riscv.flow.rpt
@@ -1,5 +1,5 @@
Flow report for de1_riscv
-Sat Aug 28 11:02:31 2021
+Sat Aug 28 16:29:19 2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
@@ -40,25 +40,25 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+---------------------------------------------+
-; Flow Status ; Successful - Sat Aug 28 11:02:31 2021 ;
+; Flow Status ; Successful - Sat Aug 28 16:28:45 2021 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ;
; Family ; Cyclone V ;
; Device ; 5CSEMA5F31C6 ;
; Timing Models ; Preliminary ;
-; Logic utilization (in ALMs) ; N/A ;
-; Total registers ; 1636 ;
-; Total pins ; 204 ;
+; Logic utilization (in ALMs) ; 2,514 / 32,070 ( 8 % ) ;
+; Total registers ; 1859 ;
+; Total pins ; 204 / 457 ( 45 % ) ;
; Total virtual pins ; 0 ;
-; Total block memory bits ; 67,296 ;
-; Total DSP Blocks ; 10 ;
+; Total block memory bits ; 66,560 / 4,065,280 ( 2 % ) ;
+; Total DSP Blocks ; 10 / 87 ( 11 % ) ;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI TX Channels ; 0 ;
-; Total PLLs ; 1 ;
-; Total DLLs ; 0 ;
+; Total PLLs ; 1 / 6 ( 17 % ) ;
+; Total DLLs ; 0 / 4 ( 0 % ) ;
+---------------------------------+---------------------------------------------+
@@ -67,7 +67,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
-; Start date & time ; 08/28/2021 11:02:08 ;
+; Start date & time ; 08/28/2021 16:23:04 ;
; Main task ; Compilation ;
; Revision Name ; de1_riscv ;
+-------------------+---------------------+
@@ -78,7 +78,7 @@ applicable agreement for further details.
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
-; COMPILER_SIGNATURE_ID ; 621136229624.163011972824564 ; -- ; -- ; -- ;
+; COMPILER_SIGNATURE_ID ; 621136229624.163013898422524 ; -- ; -- ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M ; -- ;
; IP_TOOL_ENV ; mwpim ; -- ; clk100M_0002 ; -- ;
@@ -129,29 +129,38 @@ applicable agreement for further details.
+-------------------------------------+---------------------------------------+---------------+--------------+------------+
-+--------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:22 ; 1.0 ; 670 MB ; 00:00:21 ;
-; Total ; 00:00:22 ; -- ; -- ; 00:00:21 ;
-+----------------------+--------------+-------------------------+---------------------+------------------------------------+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Flow Elapsed Time ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+; Analysis & Synthesis ; 00:00:24 ; 1.0 ; 669 MB ; 00:00:23 ;
+; Fitter ; 00:01:43 ; 1.3 ; 2331 MB ; 00:02:12 ;
+; Assembler ; 00:00:15 ; 1.0 ; 660 MB ; 00:00:16 ;
+; TimeQuest Timing Analyzer ; 00:00:32 ; 1.4 ; 1126 MB ; 00:00:42 ;
+; Total ; 00:02:54 ; -- ; -- ; 00:03:33 ;
++---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-+-----------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+----------------------+------------------+-----------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+----------------------+------------------+-----------+------------+----------------+
-; Analysis & Synthesis ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
-+----------------------+------------------+-----------+------------+----------------+
++----------------------------------------------------------------------------------------+
+; Flow OS Summary ;
++---------------------------+------------------+-----------+------------+----------------+
+; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
++---------------------------+------------------+-----------+------------+----------------+
+; Analysis & Synthesis ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
+; Fitter ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
+; Assembler ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
+; TimeQuest Timing Analyzer ; RG6MXLMTA6KAGXI ; Windows 7 ; 6.1 ; x86_64 ;
++---------------------------+------------------+-----------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off de1_riscv -c de1_riscv
+quartus_fit --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv
+quartus_asm --read_settings_files=off --write_settings_files=off de1_riscv -c de1_riscv
+quartus_sta de1_riscv -c de1_riscv
diff --git a/examples/hdl4se_riscv/de1/de1_riscv.jdi b/examples/hdl4se_riscv/de1/de1_riscv.jdi
index b91d50455a910c65261f24d08c0cc7e2568f5c6a..3c135e05d4048623556c0009bbc663a72028bc42 100644
--- a/examples/hdl4se_riscv/de1/de1_riscv.jdi
+++ b/examples/hdl4se_riscv/de1/de1_riscv.jdi
@@ -1,6 +1,6 @@
-
+
diff --git a/examples/hdl4se_riscv/de1/de1_riscv.map.rpt b/examples/hdl4se_riscv/de1/de1_riscv.map.rpt
index c58c87201377f315e453f61d73b150f4785731f8..97521f37d6c8fa658594008d37f4d39b6985d8e8 100644
--- a/examples/hdl4se_riscv/de1/de1_riscv.map.rpt
+++ b/examples/hdl4se_riscv/de1/de1_riscv.map.rpt
@@ -1,5 +1,5 @@
Analysis & Synthesis report for de1_riscv
-Sat Aug 28 11:02:31 2021
+Sat Aug 28 16:23:30 2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
@@ -19,58 +19,57 @@ Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
11. State Machine - |de1_riscv|riscv_core:core|state
12. Registers Protected by Synthesis
13. Registers Removed During Synthesis
- 14. Removed Registers Triggering Further Register Optimizations
- 15. General Register Statistics
- 16. Inverted Register Statistics
- 17. Registers Packed Into Inferred Megafunctions
- 18. Multiplexer Restructuring Statistics (Restructuring Performed)
- 19. Source assignments for altera_uart:uart
- 20. Source assignments for altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer
- 21. Source assignments for regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated
- 22. Source assignments for ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated
- 23. Source assignments for riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider
- 24. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider
- 25. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5
- 26. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5
- 27. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5
- 28. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5
- 29. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4
- 30. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5
- 31. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5
- 32. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5
- 33. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4
- 34. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4
- 35. Parameter Settings for User Entity Instance: clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i
- 36. Parameter Settings for User Entity Instance: altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer
- 37. Parameter Settings for User Entity Instance: regfile:regs|altsyncram:altsyncram_component
- 38. Parameter Settings for User Entity Instance: ram8kb:ram|altsyncram:altsyncram_component
- 39. Parameter Settings for User Entity Instance: riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component
- 40. Parameter Settings for User Entity Instance: riscv_core:core|suber:sub|lpm_add_sub:LPM_ADD_SUB_component
- 41. Parameter Settings for User Entity Instance: riscv_core:core|mult:mul|lpm_mult:lpm_mult_component
- 42. Parameter Settings for User Entity Instance: riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component
- 43. Parameter Settings for User Entity Instance: riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component
- 44. Parameter Settings for User Entity Instance: riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component
- 45. Parameter Settings for User Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component
- 46. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0
- 47. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0
- 48. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1
- 49. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2
- 50. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3
- 51. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4
- 52. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5
- 53. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6
- 54. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7
- 55. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8
- 56. altsyncram Parameter Settings by Entity Instance
- 57. lpm_mult Parameter Settings by Entity Instance
- 58. altshift_taps Parameter Settings by Entity Instance
- 59. Port Connectivity Checks: "riscv_core:core|mulsu:mul_su"
- 60. Port Connectivity Checks: "riscv_core:core|mult:mul"
- 61. Port Connectivity Checks: "riscv_core:core"
- 62. Port Connectivity Checks: "altera_uart:uart"
- 63. Port Connectivity Checks: "clk100M:clk100"
- 64. Elapsed Time Per Partition
- 65. Analysis & Synthesis Messages
+ 14. General Register Statistics
+ 15. Inverted Register Statistics
+ 16. Registers Packed Into Inferred Megafunctions
+ 17. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 18. Source assignments for altera_uart:uart
+ 19. Source assignments for altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer
+ 20. Source assignments for regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated
+ 21. Source assignments for ram8kb:ram|altsyncram:altsyncram_component|altsyncram_bdq1:auto_generated
+ 22. Source assignments for riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider
+ 23. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider
+ 24. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5
+ 25. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0|shift_taps_hm21:auto_generated|altsyncram_9u91:altsyncram5
+ 26. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1|shift_taps_gm21:auto_generated|altsyncram_7u91:altsyncram5
+ 27. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2|shift_taps_bl21:auto_generated|altsyncram_rr91:altsyncram5
+ 28. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3|shift_taps_9l21:auto_generated|altsyncram_lr91:altsyncram4
+ 29. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4|shift_taps_cl21:auto_generated|altsyncram_hr91:altsyncram5
+ 30. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5|shift_taps_dl21:auto_generated|altsyncram_mr91:altsyncram5
+ 31. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6|shift_taps_4l21:auto_generated|altsyncram_dr91:altsyncram5
+ 32. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7|shift_taps_3l21:auto_generated|altsyncram_9r91:altsyncram4
+ 33. Source assignments for riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8|shift_taps_5l21:auto_generated|altsyncram_br91:altsyncram4
+ 34. Parameter Settings for User Entity Instance: clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i
+ 35. Parameter Settings for User Entity Instance: altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer
+ 36. Parameter Settings for User Entity Instance: regfile:regs|altsyncram:altsyncram_component
+ 37. Parameter Settings for User Entity Instance: ram8kb:ram|altsyncram:altsyncram_component
+ 38. Parameter Settings for User Entity Instance: riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component
+ 39. Parameter Settings for User Entity Instance: riscv_core:core|suber:sub|lpm_add_sub:LPM_ADD_SUB_component
+ 40. Parameter Settings for User Entity Instance: riscv_core:core|mult:mul|lpm_mult:lpm_mult_component
+ 41. Parameter Settings for User Entity Instance: riscv_core:core|mult_s:mul_s|lpm_mult:lpm_mult_component
+ 42. Parameter Settings for User Entity Instance: riscv_core:core|mulsu:mul_su|lpm_mult:lpm_mult_component
+ 43. Parameter Settings for User Entity Instance: riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component
+ 44. Parameter Settings for User Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component
+ 45. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0
+ 46. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_0
+ 47. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_1
+ 48. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_2
+ 49. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_3
+ 50. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_4
+ 51. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_5
+ 52. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_6
+ 53. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_7
+ 54. Parameter Settings for Inferred Entity Instance: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|altshift_taps:DFFNumerator_rtl_8
+ 55. altsyncram Parameter Settings by Entity Instance
+ 56. lpm_mult Parameter Settings by Entity Instance
+ 57. altshift_taps Parameter Settings by Entity Instance
+ 58. Port Connectivity Checks: "riscv_core:core|mulsu:mul_su"
+ 59. Port Connectivity Checks: "riscv_core:core|mult:mul"
+ 60. Port Connectivity Checks: "riscv_core:core"
+ 61. Port Connectivity Checks: "altera_uart:uart"
+ 62. Port Connectivity Checks: "clk100M:clk100"
+ 63. Elapsed Time Per Partition
+ 64. Analysis & Synthesis Messages
@@ -96,13 +95,13 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+---------------------------------+---------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Sat Aug 28 11:02:31 2021 ;
+; Analysis & Synthesis Status ; Successful - Sat Aug 28 16:23:29 2021 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Full Version ;
; Revision Name ; de1_riscv ;
; Top-level Entity Name ; de1_riscv ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A ;
-; Total registers ; 1636 ;
+; Total registers ; 1702 ;
; Total pins ; 204 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 67,296 ;
@@ -321,16 +320,16 @@ applicable agreement for further details.
+---------------------------------------------+---------------------------------------------------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+---------------------------------------------------------------------------------+
-; Estimate of Logic utilization (ALMs needed) ; 2177 ;
+; Estimate of Logic utilization (ALMs needed) ; 2214 ;
; ; ;
-; Combinational ALUT usage for logic ; 3750 ;
-; -- 7 input functions ; 47 ;
-; -- 6 input functions ; 327 ;
-; -- 5 input functions ; 472 ;
-; -- 4 input functions ; 831 ;
-; -- <=3 input functions ; 2073 ;
+; Combinational ALUT usage for logic ; 3815 ;
+; -- 7 input functions ; 53 ;
+; -- 6 input functions ; 334 ;
+; -- 5 input functions ; 487 ;
+; -- 4 input functions ; 853 ;
+; -- <=3 input functions ; 2088 ;
; ; ;
-; Dedicated logic registers ; 1636 ;
+; Dedicated logic registers ; 1702 ;
; ; ;
; I/O pins ; 204 ;
; Total MLAB memory bits ; 0 ;
@@ -340,9 +339,9 @@ applicable agreement for further details.
; -- PLLs ; 1 ;
; ; ;
; Maximum fan-out node ; clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|outclk_wire[0] ;
-; Maximum fan-out ; 1804 ;
-; Total fan-out ; 21004 ;
-; Average fan-out ; 3.48 ;
+; Maximum fan-out ; 1870 ;
+; Total fan-out ; 21518 ;
+; Average fan-out ; 3.49 ;
+---------------------------------------------+---------------------------------------------------------------------------------+
@@ -351,11 +350,12 @@ applicable agreement for further details.
+----------------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
-; |de1_riscv ; 3750 (83) ; 1636 (66) ; 67296 ; 10 ; 204 ; 0 ; |de1_riscv ; work ;
-; |altera_uart:uart| ; 35 (0) ; 28 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart ; work ;
-; |altera_uart_regs:the_altera_uart_regs| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_regs:the_altera_uart_regs ; work ;
-; |altera_uart_rx:the_altera_uart_rx| ; 35 (35) ; 26 (24) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx ; work ;
+; |de1_riscv ; 3815 (87) ; 1702 (66) ; 67296 ; 10 ; 204 ; 0 ; |de1_riscv ; work ;
+; |altera_uart:uart| ; 89 (0) ; 94 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart ; work ;
+; |altera_uart_regs:the_altera_uart_regs| ; 23 (23) ; 31 (31) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_regs:the_altera_uart_regs ; work ;
+; |altera_uart_rx:the_altera_uart_rx| ; 43 (43) ; 37 (35) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx ; work ;
; |altera_std_synchronizer:the_altera_std_synchronizer| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer ; work ;
+; |altera_uart_tx:the_altera_uart_tx| ; 23 (23) ; 26 (26) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|altera_uart:uart|altera_uart_tx:the_altera_uart_tx ; work ;
; |clk100M:clk100| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100 ; clk100M ;
; |clk100M_0002:clk100m_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst ; clk100M ;
; |altera_pll:altera_pll_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i ; work ;
@@ -365,7 +365,7 @@ applicable agreement for further details.
; |regfile:regs| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component ; work ;
; |altsyncram_nco1:auto_generated| ; 0 (0) ; 0 (0) ; 1024 ; 0 ; 0 ; 0 ; |de1_riscv|regfile:regs|altsyncram:altsyncram_component|altsyncram_nco1:auto_generated ; work ;
-; |riscv_core:core| ; 3632 (1189) ; 1542 (287) ; 736 ; 10 ; 0 ; 0 ; |de1_riscv|riscv_core:core ; work ;
+; |riscv_core:core| ; 3639 (1196) ; 1542 (287) ; 736 ; 10 ; 0 ; 0 ; |de1_riscv|riscv_core:core ; work ;
; |adder:add| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add ; work ;
; |lpm_add_sub:LPM_ADD_SUB_component| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component ; work ;
; |add_sub_tih:auto_generated| ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_riscv|riscv_core:core|adder:add|lpm_add_sub:LPM_ADD_SUB_component|add_sub_tih:auto_generated ; work ;
@@ -524,12 +524,6 @@ Encoding Type: One-Hot
; Register name ; Reason for Removal ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[10..15] ; Stuck at GND due to stuck port data_in ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[0..9] ; Stuck at GND due to stuck port clock_enable ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[9] ; Stuck at GND due to stuck port data_in ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|irq ; Stuck at GND due to stuck port data_in ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[0..7] ; Stuck at GND due to stuck port clock_enable ;
-; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_ready ; Stuck at VCC due to stuck port data_in ;
-; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|do_load_shifter ; Stuck at GND due to stuck port data_in ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[31] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[11] ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[63] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[10] ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[95] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[9] ;
@@ -555,104 +549,26 @@ Encoding Type: One-Hot
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[288] ; Merged with riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[288] ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[320] ; Merged with riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[320] ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFDenominator[352] ; Merged with riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[352] ;
-; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_overrun ; Stuck at GND due to stuck port data_in ;
-; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0..9] ; Stuck at GND due to stuck port data_in ;
-; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|pre_txd ; Stuck at VCC due to stuck port clock_enable ;
-; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|txd ; Stuck at VCC due to stuck port data_in ;
-; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_clk_en ; Lost fanout ;
-; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_shift_empty ; Stuck at VCC due to stuck port data_in ;
-; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[0..8] ; Lost fanout ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[2..6] ; Lost fanout ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[2] ; Lost fanout ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|break_detect ; Lost fanout ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[3] ; Lost fanout ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_overrun ; Lost fanout ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[4..6] ; Lost fanout ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[0,1,7,8] ; Lost fanout ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[1,7] ; Lost fanout ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|framing_error ; Lost fanout ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[0] ; Lost fanout ;
; riscv_core:core|state~10 ; Lost fanout ;
; riscv_core:core|state~11 ; Lost fanout ;
; riscv_core:core|state~12 ; Lost fanout ;
; riscv_core:core|state~13 ; Lost fanout ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|alt_u_div_5eg:divider|DFFStage[1] ; Stuck at GND due to stuck port data_in ;
-; Total Number of Removed Registers = 102 ; ;
+; Total Number of Removed Registers = 36 ; ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Removed Registers Triggering Further Register Optimizations ;
-+-----------------------------------------------------------------------+--------------------------------+--------------------------------------------------------------------------------------------------------------------+
-; Register name ; Reason for Removal ; Registers Removed due to This Register ;
-+-----------------------------------------------------------------------+--------------------------------+--------------------------------------------------------------------------------------------------------------------+
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[7] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[8], ;
-; ; due to stuck port clock_enable ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[0], ;
-; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|pre_txd, ;
-; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_clk_en, ;
-; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[8], ;
-; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[7], ;
-; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[6], ;
-; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[5], ;
-; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[4], ;
-; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[3], ;
-; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[2], ;
-; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[1], ;
-; ; ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|baud_rate_counter[0] ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[8] ; Stuck at GND ; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|irq, ;
-; ; due to stuck port clock_enable ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|break_detect, ;
-; ; ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_overrun, ;
-; ; ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|framing_error ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[9] ; Stuck at GND ; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|readdata[9], ;
-; ; due to stuck port clock_enable ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|txd ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[7] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[7] ;
-; ; due to stuck port clock_enable ; ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[6] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[6] ;
-; ; due to stuck port clock_enable ; ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[5] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[5] ;
-; ; due to stuck port clock_enable ; ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[4] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[4] ;
-; ; due to stuck port clock_enable ; ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[3] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[3] ;
-; ; due to stuck port clock_enable ; ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[2] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[2] ;
-; ; due to stuck port clock_enable ; ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[1] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[1] ;
-; ; due to stuck port clock_enable ; ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|control_reg[0] ; Stuck at GND ; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|rx_data[0] ;
-; ; due to stuck port clock_enable ; ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[6] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[7] ;
-; ; due to stuck port clock_enable ; ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[5] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[6] ;
-; ; due to stuck port clock_enable ; ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[4] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] ;
-; ; due to stuck port clock_enable ; ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[3] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[4] ;
-; ; due to stuck port clock_enable ; ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[2] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[3] ;
-; ; due to stuck port clock_enable ; ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[1] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[2] ;
-; ; due to stuck port clock_enable ; ;
-; altera_uart:uart|altera_uart_regs:the_altera_uart_regs|tx_data[0] ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[1] ;
-; ; due to stuck port clock_enable ; ;
-; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_ready ; Stuck at VCC ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_shift_empty ;
-; ; due to stuck port data_in ; ;
-; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|do_load_shifter ; Stuck at GND ; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[9] ;
-; ; due to stuck port data_in ; ;
-+-----------------------------------------------------------------------+--------------------------------+--------------------------------------------------------------------------------------------------------------------+
-
-
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
-; Total registers ; 1636 ;
-; Number of registers using Synchronous Clear ; 95 ;
-; Number of registers using Synchronous Load ; 493 ;
-; Number of registers using Asynchronous Clear ; 28 ;
+; Total registers ; 1702 ;
+; Number of registers using Synchronous Clear ; 100 ;
+; Number of registers using Synchronous Load ; 491 ;
+; Number of registers using Asynchronous Clear ; 94 ;
; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 316 ;
+; Number of registers using Clock Enable ; 352 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
@@ -662,6 +578,10 @@ Encoding Type: One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register ; Fan out ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_ready ; 7 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|tx_shift_empty ; 2 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|txd ; 1 ;
+; altera_uart:uart|altera_uart_tx:the_altera_uart_tx|pre_txd ; 2 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[0] ; 35 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[352] ; 3 ;
; riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|DFF_q_is_neg[1] ; 4 ;
@@ -758,11 +678,7 @@ Encoding Type: One-Hot
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[111] ; 2 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[112] ; 2 ;
; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[114] ; 2 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[113] ; 2 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[121] ; 2 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[122] ; 2 ;
-; riscv_core:core|div:div|lpm_divide:LPM_DIVIDE_component|lpm_divide_2jt:auto_generated|sign_div_unsign_8ai:divider|alt_u_div_nlf:divider|DFFDenominator[123] ; 2 ;
-; Total number of inverted registers = 384* ; ;
+; Total number of inverted registers = 388* ; ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
* Table truncated at 100 items. To change the number of inverted registers reported, set the "Number of Inverted Registers Reported" option under Assignments->Settings->Analysis and Synthesis Settings->More Settings
@@ -816,49 +732,49 @@ Encoding Type: One-Hot
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed) ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------+
-; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[9] ;
-; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de1_riscv|riscv_core:core|ldaddr[1] ;
-; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[14] ;
-; 5:1 ; 19 bits ; 57 LEs ; 0 LEs ; 57 LEs ; Yes ; |de1_riscv|readaddr[17] ;
-; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |de1_riscv|led1[6] ;
-; 6:1 ; 24 bits ; 96 LEs ; 48 LEs ; 48 LEs ; Yes ; |de1_riscv|led2[3] ;
-; 5:1 ; 8 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[1] ;
-; 14:1 ; 6 bits ; 54 LEs ; 6 LEs ; 48 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[5] ;
-; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |de1_riscv|led4[6] ;
-; 7:1 ; 12 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |de1_riscv|led4[4] ;
-; 7:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |de1_riscv|riscv_core:core|divclk[1] ;
-; 15:1 ; 8 bits ; 80 LEs ; 0 LEs ; 80 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[12] ;
-; 16:1 ; 4 bits ; 40 LEs ; 8 LEs ; 32 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[3] ;
-; 10:1 ; 11 bits ; 66 LEs ; 0 LEs ; 66 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[27] ;
-; 14:1 ; 2 bits ; 18 LEs ; 4 LEs ; 14 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[0] ;
-; 14:1 ; 25 bits ; 225 LEs ; 50 LEs ; 175 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[18] ;
-; 14:1 ; 4 bits ; 36 LEs ; 8 LEs ; 28 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[2] ;
-; 8:1 ; 8 bits ; 40 LEs ; 16 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[19] ;
-; 8:1 ; 8 bits ; 40 LEs ; 16 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[27] ;
-; 22:1 ; 5 bits ; 70 LEs ; 25 LEs ; 45 LEs ; Yes ; |de1_riscv|riscv_core:core|dstreg[0] ;
-; 60:1 ; 12 bits ; 480 LEs ; 276 LEs ; 204 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[25] ;
-; 63:1 ; 7 bits ; 294 LEs ; 238 LEs ; 56 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[8] ;
-; 64:1 ; 3 bits ; 126 LEs ; 102 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[30] ;
-; 65:1 ; 3 bits ; 129 LEs ; 102 LEs ; 27 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[6] ;
-; 69:1 ; 2 bits ; 92 LEs ; 72 LEs ; 20 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[3] ;
-; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[9] ;
-; 3:1 ; 18 bits ; 36 LEs ; 36 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[23] ;
-; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight1 ;
-; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft1 ;
-; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight1 ;
-; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft0 ;
-; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight0 ;
-; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft0 ;
-; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|bReadAddr[8] ;
-; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[2] ;
-; 5:1 ; 6 bits ; 18 LEs ; 18 LEs ; 0 LEs ; No ; |de1_riscv|uartaddr[0] ;
-; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|Selector162 ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed) ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+
+; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |de1_riscv|altera_uart:uart|altera_uart_rx:the_altera_uart_rx|unxshiftxrxd_shift_regxshift_reg_start_bit_nxx6_out[5] ;
+; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |de1_riscv|altera_uart:uart|altera_uart_tx:the_altera_uart_tx|unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out[5] ;
+; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |de1_riscv|riscv_core:core|ldaddr[0] ;
+; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[12] ;
+; 6:1 ; 4 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |de1_riscv|led0[6] ;
+; 6:1 ; 24 bits ; 96 LEs ; 48 LEs ; 48 LEs ; Yes ; |de1_riscv|led1[5] ;
+; 5:1 ; 8 bits ; 24 LEs ; 0 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[2] ;
+; 14:1 ; 6 bits ; 54 LEs ; 6 LEs ; 48 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[10] ;
+; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |de1_riscv|led5[6] ;
+; 7:1 ; 12 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |de1_riscv|led4[0] ;
+; 7:1 ; 5 bits ; 20 LEs ; 5 LEs ; 15 LEs ; Yes ; |de1_riscv|riscv_core:core|divclk[4] ;
+; 15:1 ; 8 bits ; 80 LEs ; 0 LEs ; 80 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[14] ;
+; 16:1 ; 4 bits ; 40 LEs ; 8 LEs ; 32 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[4] ;
+; 10:1 ; 11 bits ; 66 LEs ; 0 LEs ; 66 LEs ; Yes ; |de1_riscv|riscv_core:core|imm[29] ;
+; 14:1 ; 2 bits ; 18 LEs ; 4 LEs ; 14 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[0] ;
+; 14:1 ; 25 bits ; 225 LEs ; 50 LEs ; 175 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[29] ;
+; 14:1 ; 4 bits ; 36 LEs ; 8 LEs ; 28 LEs ; Yes ; |de1_riscv|riscv_core:core|pc[4] ;
+; 8:1 ; 8 bits ; 40 LEs ; 16 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[22] ;
+; 8:1 ; 8 bits ; 40 LEs ; 16 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|writedata[28] ;
+; 22:1 ; 5 bits ; 70 LEs ; 25 LEs ; 45 LEs ; Yes ; |de1_riscv|riscv_core:core|dstreg[4] ;
+; 60:1 ; 12 bits ; 480 LEs ; 276 LEs ; 204 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[25] ;
+; 63:1 ; 7 bits ; 294 LEs ; 238 LEs ; 56 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[8] ;
+; 64:1 ; 3 bits ; 126 LEs ; 102 LEs ; 24 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[29] ;
+; 65:1 ; 3 bits ; 129 LEs ; 102 LEs ; 27 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[5] ;
+; 69:1 ; 2 bits ; 92 LEs ; 72 LEs ; 20 LEs ; Yes ; |de1_riscv|riscv_core:core|dstvalue[2] ;
+; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[11] ;
+; 3:1 ; 18 bits ; 36 LEs ; 36 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[27] ;
+; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft1 ;
+; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight1 ;
+; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftLeft1 ;
+; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight0 ;
+; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight0 ;
+; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|ShiftRight0 ;
+; 4:1 ; 24 bits ; 48 LEs ; 48 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|bReadAddr[21] ;
+; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_riscv|bReadData[7] ;
+; 5:1 ; 6 bits ; 18 LEs ; 18 LEs ; 0 LEs ; No ; |de1_riscv|ramaddr[5] ;
+; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |de1_riscv|riscv_core:core|Selector162 ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------------------------------------+
+-------------------------------------------------+
@@ -3026,15 +2942,15 @@ Note: In order to hide this table in the UI and the text report file, please set
+-----------------+--------+----------+-------------------------------------------------------------------------------------+
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "altera_uart:uart" ;
-+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; chipselect ; Input ; Info ; Stuck at GND ;
-; writedata ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (16 bits) it drives. The 16 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
-; readdata ; Output ; Warning ; Output or bidir port (16 bits) is smaller than the port expression (32 bits) it drives. The 16 most-significant bit(s) in the port expression will be connected to GND. ;
-+------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port Connectivity Checks: "altera_uart:uart" ;
++---------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Port ; Type ; Severity ; Details ;
++---------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; begintransfer ; Input ; Info ; Stuck at VCC ;
+; writedata ; Input ; Warning ; Input port expression (32 bits) is wider than the input port (16 bits) it drives. The 16 most-significant bit(s) in the expression will be dangling if they have no other fanouts. ;
+; readdata ; Output ; Warning ; Output or bidir port (16 bits) is smaller than the port expression (32 bits) it drives. The 16 most-significant bit(s) in the port expression will be connected to GND. ;
++---------------+--------+----------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------+
@@ -3052,7 +2968,7 @@ Note: In order to hide this table in the UI and the text report file, please set
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
-; Top ; 00:00:18 ;
+; Top ; 00:00:20 ;
+----------------+--------------+
@@ -3062,7 +2978,7 @@ Note: In order to hide this table in the UI and the text report file, please set
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
- Info: Processing started: Sat Aug 28 11:02:08 2021
+ Info: Processing started: Sat Aug 28 16:23:04 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off de1_riscv -c de1_riscv
Warning (125092): Tcl Script File alu/add_sub.qip not found
Info (125063): set_global_assignment -name QIP_FILE alu/add_sub.qip
@@ -3571,6 +3487,8 @@ Info (12021): Found 1 design units, including 1 entities, in source file db/cntr
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_a9c.tdf
Info (12023): Found entity 1: cmpr_a9c
Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13034): The following nodes have both tri-state and non-tri-state drivers
+ Warning (13035): Inserted always-enabled tri-state buffer between "GPIO[5]" and its non-tri-state driver.
Warning (13039): The following bidir pins have no drivers
Warning (13040): Bidir "AUD_ADCLRCK" has no driver
Warning (13040): Bidir "AUD_BCLK" has no driver
@@ -3630,8 +3548,6 @@ Warning (13039): The following bidir pins have no drivers
Warning (13040): Bidir "GPIO[33]" has no driver
Warning (13040): Bidir "GPIO[34]" has no driver
Warning (13040): Bidir "GPIO[35]" has no driver
-Warning (13032): The following tri-state nodes are fed by constants
- Warning (13033): The pin "GPIO[5]" is fed by VCC
Warning (13009): TRI or OPNDRN buffers permanently enabled
Warning (13010): Node "GPIO[5]~synth"
Warning (13024): Output pins are stuck at VCC or GND
@@ -3665,7 +3581,6 @@ Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "DRAM_WE_N" is stuck at GND
Warning (13410): Pin "FPGA_I2C_SCLK" is stuck at GND
Warning (13410): Pin "IRDA_TXD" is stuck at GND
- Warning (13410): Pin "LEDR[1]" is stuck at GND
Warning (13410): Pin "LEDR[3]" is stuck at GND
Warning (13410): Pin "LEDR[4]" is stuck at GND
Warning (13410): Pin "LEDR[5]" is stuck at GND
@@ -3703,7 +3618,7 @@ Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "VGA_R[7]" is stuck at GND
Warning (13410): Pin "VGA_SYNC_N" is stuck at GND
Warning (13410): Pin "VGA_VS" is stuck at GND
-Info (17049): 34 registers lost all their fanouts during netlist optimizations.
+Info (17049): 4 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Info (16011): Adding 5 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 17 input pin(s) that do not drive logic
@@ -3724,18 +3639,18 @@ Warning (21074): Design contains 17 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "TD_DATA[7]"
Warning (15610): No output dependent on input pin "TD_HS"
Warning (15610): No output dependent on input pin "TD_VS"
-Info (21057): Implemented 5105 device resources after synthesis - the final resource count might be different
+Info (21057): Implemented 5209 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 32 input pins
Info (21059): Implemented 112 output pins
Info (21060): Implemented 60 bidirectional pins
- Info (21061): Implemented 4723 logic cells
+ Info (21061): Implemented 4827 logic cells
Info (21064): Implemented 167 RAM segments
Info (21065): Implemented 1 PLLs
Info (21062): Implemented 10 DSP elements
-Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 215 warnings
- Info: Peak virtual memory: 670 megabytes
- Info: Processing ended: Sat Aug 28 11:02:31 2021
- Info: Elapsed time: 00:00:23
- Info: Total CPU time (on all processors): 00:00:23
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 214 warnings
+ Info: Peak virtual memory: 669 megabytes
+ Info: Processing ended: Sat Aug 28 16:23:30 2021
+ Info: Elapsed time: 00:00:26
+ Info: Total CPU time (on all processors): 00:00:25
diff --git a/examples/hdl4se_riscv/de1/de1_riscv.map.summary b/examples/hdl4se_riscv/de1/de1_riscv.map.summary
index f9856d7e486e800f94632d95669f5419d1a5f5a4..78d057fbe45b5a3ec5ef9ed61d05fc97c59feb57 100644
--- a/examples/hdl4se_riscv/de1/de1_riscv.map.summary
+++ b/examples/hdl4se_riscv/de1/de1_riscv.map.summary
@@ -1,10 +1,10 @@
-Analysis & Synthesis Status : Successful - Sat Aug 28 11:02:31 2021
+Analysis & Synthesis Status : Successful - Sat Aug 28 16:23:29 2021
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Full Version
Revision Name : de1_riscv
Top-level Entity Name : de1_riscv
Family : Cyclone V
Logic utilization (in ALMs) : N/A
-Total registers : 1636
+Total registers : 1702
Total pins : 204
Total virtual pins : 0
Total block memory bits : 67,296
diff --git a/examples/hdl4se_riscv/de1/de1_riscv.sof b/examples/hdl4se_riscv/de1/de1_riscv.sof
new file mode 100644
index 0000000000000000000000000000000000000000..4d97addd3319fdc41601450a49690b95f7bf5dad
Binary files /dev/null and b/examples/hdl4se_riscv/de1/de1_riscv.sof differ
diff --git a/examples/hdl4se_riscv/de1/de1_riscv.sta.rpt b/examples/hdl4se_riscv/de1/de1_riscv.sta.rpt
index 30b67aae3f6eea3304216029a1d6ba521f02a562..b56716969e6a362dd76685a987a30d1fa81153d5 100644
--- a/examples/hdl4se_riscv/de1/de1_riscv.sta.rpt
+++ b/examples/hdl4se_riscv/de1/de1_riscv.sta.rpt
@@ -1,5 +1,5 @@
TimeQuest Timing Analyzer report for de1_riscv
-Sat Aug 28 10:56:45 2021
+Sat Aug 28 16:29:19 2021
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
@@ -122,12 +122,12 @@ applicable agreement for further details.
; Number detected on machine ; 4 ;
; Maximum allowed ; 2 ;
; ; ;
-; Average used ; 1.37 ;
+; Average used ; 1.35 ;
; Maximum used ; 2 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
-; Processor 2 ; 36.7% ;
+; Processor 2 ; 35.5% ;
; Processors 3-4 ; 0.0% ;
+----------------------------+-------------+
@@ -137,7 +137,7 @@ applicable agreement for further details.
+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ;
+---------------+--------+--------------------------+
-; de1_riscv.SDC ; OK ; Sat Aug 28 10:56:17 2021 ;
+; de1_riscv.SDC ; OK ; Sat Aug 28 16:28:52 2021 ;
+---------------+--------+--------------------------+
@@ -147,7 +147,7 @@ applicable agreement for further details.
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+----------------------------------------------------------------------------+-----------+--------+------------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------------------------------------------------------------------------+-------------------------------------------------------------------------------+--------------------------------------------------------------------------------+
; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; Generated ; 3.333 ; 300.03 MHz ; 0.000 ; 1.666 ; 50.00 ; 1 ; 6 ; ; ; ; ; false ; CLOCK_50 ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin ; { clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] } ;
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; Generated ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000 ; 50.00 ; 3 ; 1 ; ; ; ; ; false ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; { clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; Generated ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; 50.00 ; 6 ; 1 ; ; ; ; ; false ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0] ; { clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } ;
; clk_audxck ; Base ; 54.253 ; 18.43 MHz ; 0.000 ; 27.126 ; ; ; ; ; ; ; ; ; ; ; { AUD_XCK } ;
; clk_core ; Virtual ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; ; ; ; ; ; ; ; ; ; ; { } ;
; clk_dram ; Base ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000 ; ; ; ; ; ; ; ; ; ; ; { DRAM_CLK } ;
@@ -165,7 +165,7 @@ applicable agreement for further details.
+-----------+-----------------+----------------------------------------------------------------------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+----------------------------------------------------------------------------+------+
-; 89.31 MHz ; 89.31 MHz ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ;
+; 73.22 MHz ; 73.22 MHz ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ;
+-----------+-----------------+----------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
@@ -176,13 +176,13 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
HTML report is unavailable in plain text report export.
-+-----------------------------------------------------------------------------------------------------+
-; Slow 1100mV 85C Model Setup Summary ;
-+----------------------------------------------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+----------------------------------------------------------------------------+--------+---------------+
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -1.197 ; -95.783 ;
-+----------------------------------------------------------------------------+--------+---------------+
++----------------------------------------------------------------------------------------------------+
+; Slow 1100mV 85C Model Setup Summary ;
++----------------------------------------------------------------------------+-------+---------------+
+; Clock ; Slack ; End Point TNS ;
++----------------------------------------------------------------------------+-------+---------------+
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 6.342 ; 0.000 ;
++----------------------------------------------------------------------------+-------+---------------+
+----------------------------------------------------------------------------------------------------+
@@ -190,7 +190,7 @@ HTML report is unavailable in plain text report export.
+----------------------------------------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------------------------+-------+---------------+
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.266 ; 0.000 ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.271 ; 0.000 ;
+----------------------------------------------------------------------------+-------+---------------+
@@ -212,7 +212,7 @@ No paths to report.
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------------------------+-------+---------------+
; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; 1.666 ; 0.000 ;
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.775 ; 0.000 ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 8.772 ; 0.000 ;
; CLOCK_50 ; 9.670 ; 0.000 ;
+----------------------------------------------------------------------------+-------+---------------+
@@ -222,22 +222,22 @@ No paths to report.
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
-; KEY[*] ; CLOCK_50 ; 1.172 ; 2.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[0] ; CLOCK_50 ; 0.834 ; 1.942 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[1] ; CLOCK_50 ; 1.172 ; 2.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[2] ; CLOCK_50 ; -0.187 ; 0.869 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[3] ; CLOCK_50 ; -0.416 ; 0.790 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[*] ; CLOCK_50 ; 2.873 ; 4.412 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[0] ; CLOCK_50 ; 0.534 ; 0.859 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[1] ; CLOCK_50 ; -0.605 ; 0.090 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[2] ; CLOCK_50 ; -0.912 ; 0.016 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[3] ; CLOCK_50 ; -0.577 ; 0.402 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[4] ; CLOCK_50 ; 0.128 ; 1.022 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[5] ; CLOCK_50 ; -1.518 ; -1.025 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[6] ; CLOCK_50 ; 0.963 ; 1.365 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[7] ; CLOCK_50 ; 2.873 ; 4.412 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[8] ; CLOCK_50 ; 1.752 ; 2.499 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[9] ; CLOCK_50 ; 1.529 ; 2.464 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[*] ; CLOCK_50 ; 3.956 ; 4.889 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[0] ; CLOCK_50 ; 0.749 ; 1.459 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[1] ; CLOCK_50 ; -0.664 ; 0.328 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[2] ; CLOCK_50 ; 0.409 ; 1.627 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[3] ; CLOCK_50 ; 3.956 ; 4.889 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[*] ; CLOCK_50 ; 6.646 ; 8.100 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[0] ; CLOCK_50 ; -0.254 ; 0.714 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[1] ; CLOCK_50 ; -0.051 ; 0.640 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[2] ; CLOCK_50 ; 0.178 ; 1.273 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[3] ; CLOCK_50 ; -0.724 ; -0.023 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[4] ; CLOCK_50 ; 0.742 ; 1.828 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[5] ; CLOCK_50 ; 0.085 ; 1.313 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[6] ; CLOCK_50 ; 3.266 ; 4.577 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[7] ; CLOCK_50 ; 6.646 ; 8.100 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[8] ; CLOCK_50 ; 3.455 ; 4.402 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[9] ; CLOCK_50 ; 1.437 ; 2.413 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
@@ -246,22 +246,22 @@ No paths to report.
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
-; KEY[*] ; CLOCK_50 ; 4.302 ; 3.725 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[0] ; CLOCK_50 ; 3.367 ; 2.664 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[1] ; CLOCK_50 ; 3.157 ; 2.342 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[2] ; CLOCK_50 ; 3.591 ; 2.859 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[3] ; CLOCK_50 ; 4.302 ; 3.725 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[*] ; CLOCK_50 ; 3.581 ; 3.092 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[0] ; CLOCK_50 ; 1.571 ; 1.170 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[1] ; CLOCK_50 ; 2.354 ; 1.795 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[2] ; CLOCK_50 ; 3.058 ; 2.482 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[3] ; CLOCK_50 ; 3.291 ; 2.737 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[4] ; CLOCK_50 ; 2.945 ; 2.456 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[5] ; CLOCK_50 ; 3.581 ; 3.092 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[6] ; CLOCK_50 ; 2.675 ; 2.107 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[7] ; CLOCK_50 ; 3.114 ; 2.543 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[8] ; CLOCK_50 ; 3.218 ; 2.673 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[9] ; CLOCK_50 ; 3.468 ; 2.939 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[*] ; CLOCK_50 ; 3.897 ; 3.204 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[0] ; CLOCK_50 ; 3.579 ; 2.894 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[1] ; CLOCK_50 ; 3.897 ; 3.204 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[2] ; CLOCK_50 ; 3.482 ; 2.554 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[3] ; CLOCK_50 ; 3.879 ; 3.191 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[*] ; CLOCK_50 ; 3.306 ; 2.804 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[0] ; CLOCK_50 ; 2.439 ; 1.742 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[1] ; CLOCK_50 ; 2.226 ; 1.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[2] ; CLOCK_50 ; 2.957 ; 2.333 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[3] ; CLOCK_50 ; 3.282 ; 2.804 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[4] ; CLOCK_50 ; 2.583 ; 1.830 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[5] ; CLOCK_50 ; 2.700 ; 1.851 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[6] ; CLOCK_50 ; 2.695 ; 1.949 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[7] ; CLOCK_50 ; 2.665 ; 1.911 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[8] ; CLOCK_50 ; 3.084 ; 2.573 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[9] ; CLOCK_50 ; 3.306 ; 2.744 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
@@ -270,57 +270,60 @@ No paths to report.
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
-; HEX0[*] ; CLOCK_50 ; 14.191 ; 13.318 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[0] ; CLOCK_50 ; 14.002 ; 13.202 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[1] ; CLOCK_50 ; 13.120 ; 12.618 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[2] ; CLOCK_50 ; 13.313 ; 12.753 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[3] ; CLOCK_50 ; 13.693 ; 13.119 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[4] ; CLOCK_50 ; 13.759 ; 12.974 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[5] ; CLOCK_50 ; 12.800 ; 12.470 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[6] ; CLOCK_50 ; 14.191 ; 13.318 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[*] ; CLOCK_50 ; 14.089 ; 13.259 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[0] ; CLOCK_50 ; 14.089 ; 13.259 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[1] ; CLOCK_50 ; 12.430 ; 12.213 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[2] ; CLOCK_50 ; 11.957 ; 11.913 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[3] ; CLOCK_50 ; 12.990 ; 12.479 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[4] ; CLOCK_50 ; 13.273 ; 12.643 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[5] ; CLOCK_50 ; 13.295 ; 12.675 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[6] ; CLOCK_50 ; 12.618 ; 12.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[*] ; CLOCK_50 ; 14.089 ; 13.234 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[0] ; CLOCK_50 ; 13.457 ; 12.840 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[1] ; CLOCK_50 ; 13.921 ; 13.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[2] ; CLOCK_50 ; 12.588 ; 12.366 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[3] ; CLOCK_50 ; 12.623 ; 12.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[4] ; CLOCK_50 ; 13.284 ; 12.846 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[5] ; CLOCK_50 ; 13.455 ; 12.789 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[6] ; CLOCK_50 ; 14.089 ; 13.234 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[*] ; CLOCK_50 ; 13.619 ; 12.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[0] ; CLOCK_50 ; 12.868 ; 12.384 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[1] ; CLOCK_50 ; 13.020 ; 12.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[2] ; CLOCK_50 ; 13.619 ; 12.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[3] ; CLOCK_50 ; 13.452 ; 12.942 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[4] ; CLOCK_50 ; 13.575 ; 12.892 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[5] ; CLOCK_50 ; 13.547 ; 12.847 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[6] ; CLOCK_50 ; 12.700 ; 12.379 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[*] ; CLOCK_50 ; 13.903 ; 13.093 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[0] ; CLOCK_50 ; 13.197 ; 12.664 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[1] ; CLOCK_50 ; 13.581 ; 12.835 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[2] ; CLOCK_50 ; 13.297 ; 12.673 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[3] ; CLOCK_50 ; 13.903 ; 13.093 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[4] ; CLOCK_50 ; 12.741 ; 12.370 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[5] ; CLOCK_50 ; 12.477 ; 12.232 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[6] ; CLOCK_50 ; 12.414 ; 12.191 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[*] ; CLOCK_50 ; 13.948 ; 13.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[0] ; CLOCK_50 ; 13.425 ; 12.769 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[1] ; CLOCK_50 ; 13.810 ; 13.023 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[2] ; CLOCK_50 ; 13.826 ; 13.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[3] ; CLOCK_50 ; 12.646 ; 12.467 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[4] ; CLOCK_50 ; 13.948 ; 13.129 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[5] ; CLOCK_50 ; 13.937 ; 13.102 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[6] ; CLOCK_50 ; 12.793 ; 12.471 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[*] ; CLOCK_50 ; 12.801 ; 12.941 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[0] ; CLOCK_50 ; 12.801 ; 12.941 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[2] ; CLOCK_50 ; 12.782 ; 12.899 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[*] ; CLOCK_50 ; 15.059 ; 14.406 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[5] ; CLOCK_50 ; 15.059 ; 14.406 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[*] ; CLOCK_50 ; 14.377 ; 13.668 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[0] ; CLOCK_50 ; 13.924 ; 13.135 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[1] ; CLOCK_50 ; 13.877 ; 13.309 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[2] ; CLOCK_50 ; 14.377 ; 13.668 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[3] ; CLOCK_50 ; 13.254 ; 12.755 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[4] ; CLOCK_50 ; 13.655 ; 12.939 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[5] ; CLOCK_50 ; 13.136 ; 12.696 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[6] ; CLOCK_50 ; 13.930 ; 13.174 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[*] ; CLOCK_50 ; 14.179 ; 13.351 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[0] ; CLOCK_50 ; 14.179 ; 13.351 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[1] ; CLOCK_50 ; 13.068 ; 12.675 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[2] ; CLOCK_50 ; 12.656 ; 12.367 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[3] ; CLOCK_50 ; 13.466 ; 12.812 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[4] ; CLOCK_50 ; 13.639 ; 12.968 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[5] ; CLOCK_50 ; 13.314 ; 12.690 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[6] ; CLOCK_50 ; 12.764 ; 12.473 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[*] ; CLOCK_50 ; 13.962 ; 13.190 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[0] ; CLOCK_50 ; 13.962 ; 13.190 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[1] ; CLOCK_50 ; 13.269 ; 12.839 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[2] ; CLOCK_50 ; 12.436 ; 12.119 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[3] ; CLOCK_50 ; 12.962 ; 12.415 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[4] ; CLOCK_50 ; 13.020 ; 12.469 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[5] ; CLOCK_50 ; 12.796 ; 12.311 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[6] ; CLOCK_50 ; 13.077 ; 12.512 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[*] ; CLOCK_50 ; 14.812 ; 13.774 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[0] ; CLOCK_50 ; 14.812 ; 13.774 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[1] ; CLOCK_50 ; 12.857 ; 12.448 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[2] ; CLOCK_50 ; 13.202 ; 12.788 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[3] ; CLOCK_50 ; 13.760 ; 13.041 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[4] ; CLOCK_50 ; 12.467 ; 12.153 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[5] ; CLOCK_50 ; 12.285 ; 12.154 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[6] ; CLOCK_50 ; 12.442 ; 12.275 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[*] ; CLOCK_50 ; 15.196 ; 14.040 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[0] ; CLOCK_50 ; 13.287 ; 12.753 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[1] ; CLOCK_50 ; 14.189 ; 13.490 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[2] ; CLOCK_50 ; 15.196 ; 14.040 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[3] ; CLOCK_50 ; 13.362 ; 12.746 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[4] ; CLOCK_50 ; 13.473 ; 12.864 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[5] ; CLOCK_50 ; 12.757 ; 12.406 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[6] ; CLOCK_50 ; 12.865 ; 12.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[*] ; CLOCK_50 ; 14.045 ; 13.226 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[0] ; CLOCK_50 ; 13.664 ; 13.138 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[1] ; CLOCK_50 ; 12.918 ; 12.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[2] ; CLOCK_50 ; 12.906 ; 12.632 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[3] ; CLOCK_50 ; 12.924 ; 12.427 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[4] ; CLOCK_50 ; 13.299 ; 12.697 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[5] ; CLOCK_50 ; 12.797 ; 12.286 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[6] ; CLOCK_50 ; 14.045 ; 13.226 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[*] ; CLOCK_50 ; 14.456 ; 15.165 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[0] ; CLOCK_50 ; 14.357 ; 15.010 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[1] ; CLOCK_50 ; 14.456 ; 15.165 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[2] ; CLOCK_50 ; 14.011 ; 14.549 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
@@ -329,57 +332,60 @@ No paths to report.
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
-; HEX0[*] ; CLOCK_50 ; 11.448 ; 11.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[0] ; CLOCK_50 ; 12.320 ; 11.814 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[1] ; CLOCK_50 ; 11.662 ; 11.334 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[2] ; CLOCK_50 ; 11.854 ; 11.468 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[3] ; CLOCK_50 ; 12.274 ; 11.829 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[4] ; CLOCK_50 ; 12.093 ; 11.596 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[5] ; CLOCK_50 ; 11.448 ; 11.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[6] ; CLOCK_50 ; 12.491 ; 11.917 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[*] ; CLOCK_50 ; 10.744 ; 10.741 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[0] ; CLOCK_50 ; 12.415 ; 11.868 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[1] ; CLOCK_50 ; 11.163 ; 11.018 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[2] ; CLOCK_50 ; 10.744 ; 10.741 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[3] ; CLOCK_50 ; 11.442 ; 11.163 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[4] ; CLOCK_50 ; 11.689 ; 11.310 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[5] ; CLOCK_50 ; 11.714 ; 11.343 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[6] ; CLOCK_50 ; 11.320 ; 11.228 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[*] ; CLOCK_50 ; 11.310 ; 11.149 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[0] ; CLOCK_50 ; 11.931 ; 11.522 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[1] ; CLOCK_50 ; 12.275 ; 11.755 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[2] ; CLOCK_50 ; 11.312 ; 11.150 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[3] ; CLOCK_50 ; 11.310 ; 11.149 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[4] ; CLOCK_50 ; 11.867 ; 11.558 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[5] ; CLOCK_50 ; 11.854 ; 11.450 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[6] ; CLOCK_50 ; 12.395 ; 11.835 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[*] ; CLOCK_50 ; 11.333 ; 11.073 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[0] ; CLOCK_50 ; 11.333 ; 11.073 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[1] ; CLOCK_50 ; 11.451 ; 11.144 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[2] ; CLOCK_50 ; 12.096 ; 11.657 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[3] ; CLOCK_50 ; 12.042 ; 11.656 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[4] ; CLOCK_50 ; 11.982 ; 11.544 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[5] ; CLOCK_50 ; 11.955 ; 11.506 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[6] ; CLOCK_50 ; 11.390 ; 11.162 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[*] ; CLOCK_50 ; 11.118 ; 10.978 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[0] ; CLOCK_50 ; 11.716 ; 11.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[1] ; CLOCK_50 ; 11.932 ; 11.473 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[2] ; CLOCK_50 ; 11.706 ; 11.327 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[3] ; CLOCK_50 ; 12.243 ; 11.717 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[4] ; CLOCK_50 ; 11.302 ; 11.098 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[5] ; CLOCK_50 ; 11.152 ; 10.999 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[6] ; CLOCK_50 ; 11.118 ; 10.978 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[*] ; CLOCK_50 ; 11.339 ; 11.229 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[0] ; CLOCK_50 ; 11.817 ; 11.427 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[1] ; CLOCK_50 ; 12.120 ; 11.626 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[2] ; CLOCK_50 ; 12.178 ; 11.750 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[3] ; CLOCK_50 ; 11.339 ; 11.229 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[4] ; CLOCK_50 ; 12.302 ; 11.761 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[5] ; CLOCK_50 ; 12.258 ; 11.718 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[6] ; CLOCK_50 ; 11.474 ; 11.243 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[*] ; CLOCK_50 ; 10.599 ; 10.683 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[0] ; CLOCK_50 ; 10.623 ; 10.733 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[2] ; CLOCK_50 ; 10.599 ; 10.683 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[*] ; CLOCK_50 ; 12.631 ; 12.079 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[5] ; CLOCK_50 ; 12.631 ; 12.079 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[*] ; CLOCK_50 ; 11.701 ; 11.406 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[0] ; CLOCK_50 ; 12.343 ; 11.788 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[1] ; CLOCK_50 ; 12.291 ; 11.951 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[2] ; CLOCK_50 ; 12.762 ; 12.270 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[3] ; CLOCK_50 ; 11.803 ; 11.467 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[4] ; CLOCK_50 ; 12.092 ; 11.606 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[5] ; CLOCK_50 ; 11.701 ; 11.406 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[6] ; CLOCK_50 ; 12.356 ; 11.826 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[*] ; CLOCK_50 ; 11.316 ; 11.133 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[0] ; CLOCK_50 ; 12.544 ; 11.974 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[1] ; CLOCK_50 ; 11.662 ; 11.404 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[2] ; CLOCK_50 ; 11.316 ; 11.133 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[3] ; CLOCK_50 ; 11.882 ; 11.478 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[4] ; CLOCK_50 ; 12.066 ; 11.625 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[5] ; CLOCK_50 ; 11.775 ; 11.376 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[6] ; CLOCK_50 ; 11.394 ; 11.212 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[*] ; CLOCK_50 ; 11.096 ; 10.898 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[0] ; CLOCK_50 ; 12.337 ; 11.824 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[1] ; CLOCK_50 ; 11.766 ; 11.531 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[2] ; CLOCK_50 ; 11.096 ; 10.898 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[3] ; CLOCK_50 ; 11.470 ; 11.133 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[4] ; CLOCK_50 ; 11.515 ; 11.179 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[5] ; CLOCK_50 ; 11.319 ; 11.031 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[6] ; CLOCK_50 ; 11.567 ; 11.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[*] ; CLOCK_50 ; 11.064 ; 10.930 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[0] ; CLOCK_50 ; 12.904 ; 12.274 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[1] ; CLOCK_50 ; 11.449 ; 11.188 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[2] ; CLOCK_50 ; 11.887 ; 11.541 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[3] ; CLOCK_50 ; 12.182 ; 11.696 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[4] ; CLOCK_50 ; 11.125 ; 10.930 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[5] ; CLOCK_50 ; 11.064 ; 10.962 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[6] ; CLOCK_50 ; 11.173 ; 11.065 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[*] ; CLOCK_50 ; 11.364 ; 11.048 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[0] ; CLOCK_50 ; 11.880 ; 11.479 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[1] ; CLOCK_50 ; 12.544 ; 12.091 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[2] ; CLOCK_50 ; 13.235 ; 12.517 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[3] ; CLOCK_50 ; 11.797 ; 11.417 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[4] ; CLOCK_50 ; 11.872 ; 11.511 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[5] ; CLOCK_50 ; 11.377 ; 11.152 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[6] ; CLOCK_50 ; 11.364 ; 11.048 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[*] ; CLOCK_50 ; 11.301 ; 10.997 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[0] ; CLOCK_50 ; 12.089 ; 11.779 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[1] ; CLOCK_50 ; 11.427 ; 11.090 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[2] ; CLOCK_50 ; 11.451 ; 11.331 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[3] ; CLOCK_50 ; 11.386 ; 11.117 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[4] ; CLOCK_50 ; 11.751 ; 11.375 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[5] ; CLOCK_50 ; 11.301 ; 10.997 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[6] ; CLOCK_50 ; 12.445 ; 11.863 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[*] ; CLOCK_50 ; 11.726 ; 12.183 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[0] ; CLOCK_50 ; 12.028 ; 12.567 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[1] ; CLOCK_50 ; 12.146 ; 12.780 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[2] ; CLOCK_50 ; 11.726 ; 12.183 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
@@ -392,7 +398,7 @@ Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
Number of Synchronizer Chains Found: 1
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
-Worst Case Available Settling Time: 17.536 ns
+Worst Case Available Settling Time: 37.358 ns
Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
- Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 79.4
@@ -433,38 +439,38 @@ Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ;
; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ;
; Number of Synchronization Registers in Chain ; 2 ; ; ; ;
-; Available Settling Time (ns) ; 17.536 ; ; ; ;
-; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ;
+; Available Settling Time (ns) ; 37.358 ; ; ; ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 6.25 ; ; ; ;
; Source Clock ; ; ; ; ;
; Unknown ; ; ; ; ;
; Synchronization Clock ; ; ; ; ;
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 10.000 ; 100.0 MHz ; ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 20.000 ; 50.0 MHz ; ;
; Asynchronous Source ; ; ; ; ;
; GPIO[7] ; ; ; ; ;
; Synchronization Registers ; ; ; ; ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.080 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 8.456 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 18.997 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 18.361 ;
+-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
-+-----------------------------------------------------------------------------------------------------------------+
-; Slow 1100mV 0C Model Fmax Summary ;
-+-----------+-----------------+----------------------------------------------------------------------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+-----------+-----------------+----------------------------------------------------------------------------+------+
-; 88.09 MHz ; 88.09 MHz ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ;
-+-----------+-----------------+----------------------------------------------------------------------------+------+
++----------------------------------------------------------------------------------------------------------------+
+; Slow 1100mV 0C Model Fmax Summary ;
++----------+-----------------+----------------------------------------------------------------------------+------+
+; Fmax ; Restricted Fmax ; Clock Name ; Note ;
++----------+-----------------+----------------------------------------------------------------------------+------+
+; 72.9 MHz ; 72.9 MHz ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ;
++----------+-----------------+----------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-+-----------------------------------------------------------------------------------------------------+
-; Slow 1100mV 0C Model Setup Summary ;
-+----------------------------------------------------------------------------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+----------------------------------------------------------------------------+--------+---------------+
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -1.352 ; -121.670 ;
-+----------------------------------------------------------------------------+--------+---------------+
++----------------------------------------------------------------------------------------------------+
+; Slow 1100mV 0C Model Setup Summary ;
++----------------------------------------------------------------------------+-------+---------------+
+; Clock ; Slack ; End Point TNS ;
++----------------------------------------------------------------------------+-------+---------------+
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 6.283 ; 0.000 ;
++----------------------------------------------------------------------------+-------+---------------+
+----------------------------------------------------------------------------------------------------+
@@ -472,7 +478,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+----------------------------------------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------------------------+-------+---------------+
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.247 ; 0.000 ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.256 ; 0.000 ;
+----------------------------------------------------------------------------+-------+---------------+
@@ -494,7 +500,7 @@ No paths to report.
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------------------------+-------+---------------+
; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; 1.666 ; 0.000 ;
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.758 ; 0.000 ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 8.754 ; 0.000 ;
; CLOCK_50 ; 9.673 ; 0.000 ;
+----------------------------------------------------------------------------+-------+---------------+
@@ -504,22 +510,22 @@ No paths to report.
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
-; KEY[*] ; CLOCK_50 ; 0.981 ; 2.410 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[0] ; CLOCK_50 ; 0.699 ; 1.824 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[1] ; CLOCK_50 ; 0.981 ; 2.410 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[2] ; CLOCK_50 ; -0.379 ; 0.805 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[3] ; CLOCK_50 ; -0.703 ; 0.621 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[*] ; CLOCK_50 ; 2.585 ; 4.241 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[0] ; CLOCK_50 ; 0.417 ; 0.774 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[1] ; CLOCK_50 ; -0.805 ; -0.023 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[2] ; CLOCK_50 ; -1.104 ; -0.076 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[3] ; CLOCK_50 ; -0.767 ; 0.312 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[4] ; CLOCK_50 ; -0.065 ; 0.911 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[5] ; CLOCK_50 ; -1.669 ; -1.138 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[6] ; CLOCK_50 ; 0.758 ; 1.223 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[7] ; CLOCK_50 ; 2.585 ; 4.241 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[8] ; CLOCK_50 ; 1.516 ; 2.359 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[9] ; CLOCK_50 ; 1.239 ; 2.310 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[*] ; CLOCK_50 ; 3.769 ; 4.790 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[0] ; CLOCK_50 ; 0.625 ; 1.366 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[1] ; CLOCK_50 ; -0.829 ; 0.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[2] ; CLOCK_50 ; 0.309 ; 1.589 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[3] ; CLOCK_50 ; 3.769 ; 4.790 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[*] ; CLOCK_50 ; 6.506 ; 7.974 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[0] ; CLOCK_50 ; -0.449 ; 0.587 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[1] ; CLOCK_50 ; -0.221 ; 0.552 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[2] ; CLOCK_50 ; -0.038 ; 1.180 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[3] ; CLOCK_50 ; -0.965 ; -0.132 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[4] ; CLOCK_50 ; 0.604 ; 1.767 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[5] ; CLOCK_50 ; -0.039 ; 1.264 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[6] ; CLOCK_50 ; 3.177 ; 4.532 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[7] ; CLOCK_50 ; 6.506 ; 7.974 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[8] ; CLOCK_50 ; 3.238 ; 4.247 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[9] ; CLOCK_50 ; 1.192 ; 2.215 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
@@ -528,22 +534,22 @@ No paths to report.
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
-; KEY[*] ; CLOCK_50 ; 4.379 ; 3.793 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[0] ; CLOCK_50 ; 3.381 ; 2.697 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[1] ; CLOCK_50 ; 3.217 ; 2.374 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[2] ; CLOCK_50 ; 3.644 ; 2.916 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[3] ; CLOCK_50 ; 4.379 ; 3.793 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[*] ; CLOCK_50 ; 3.685 ; 3.161 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[0] ; CLOCK_50 ; 1.617 ; 1.188 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[1] ; CLOCK_50 ; 2.455 ; 1.832 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[2] ; CLOCK_50 ; 3.152 ; 2.520 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[3] ; CLOCK_50 ; 3.415 ; 2.830 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[4] ; CLOCK_50 ; 3.069 ; 2.508 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[5] ; CLOCK_50 ; 3.685 ; 3.161 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[6] ; CLOCK_50 ; 2.788 ; 2.146 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[7] ; CLOCK_50 ; 3.171 ; 2.538 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[8] ; CLOCK_50 ; 3.327 ; 2.721 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[9] ; CLOCK_50 ; 3.589 ; 2.995 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[*] ; CLOCK_50 ; 4.017 ; 3.307 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[0] ; CLOCK_50 ; 3.636 ; 2.928 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[1] ; CLOCK_50 ; 3.984 ; 3.254 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[2] ; CLOCK_50 ; 3.517 ; 2.561 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[3] ; CLOCK_50 ; 4.017 ; 3.307 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[*] ; CLOCK_50 ; 3.445 ; 2.873 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[0] ; CLOCK_50 ; 2.585 ; 1.816 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[1] ; CLOCK_50 ; 2.337 ; 1.735 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[2] ; CLOCK_50 ; 3.054 ; 2.366 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[3] ; CLOCK_50 ; 3.428 ; 2.873 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[4] ; CLOCK_50 ; 2.629 ; 1.805 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[5] ; CLOCK_50 ; 2.740 ; 1.828 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[6] ; CLOCK_50 ; 2.765 ; 1.938 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[7] ; CLOCK_50 ; 2.739 ; 1.923 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[8] ; CLOCK_50 ; 3.208 ; 2.624 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[9] ; CLOCK_50 ; 3.445 ; 2.817 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
@@ -552,57 +558,60 @@ No paths to report.
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
-; HEX0[*] ; CLOCK_50 ; 13.992 ; 13.085 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[0] ; CLOCK_50 ; 13.779 ; 12.963 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[1] ; CLOCK_50 ; 12.857 ; 12.333 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[2] ; CLOCK_50 ; 13.056 ; 12.486 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[3] ; CLOCK_50 ; 13.462 ; 12.860 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[4] ; CLOCK_50 ; 13.546 ; 12.751 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[5] ; CLOCK_50 ; 12.535 ; 12.172 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[6] ; CLOCK_50 ; 13.992 ; 13.085 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[*] ; CLOCK_50 ; 13.862 ; 13.007 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[0] ; CLOCK_50 ; 13.862 ; 13.007 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[1] ; CLOCK_50 ; 12.110 ; 11.866 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[2] ; CLOCK_50 ; 11.676 ; 11.611 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[3] ; CLOCK_50 ; 12.760 ; 12.241 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[4] ; CLOCK_50 ; 13.042 ; 12.404 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[5] ; CLOCK_50 ; 13.041 ; 12.409 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[6] ; CLOCK_50 ; 12.305 ; 12.109 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[*] ; CLOCK_50 ; 13.878 ; 12.987 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[0] ; CLOCK_50 ; 13.237 ; 12.601 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[1] ; CLOCK_50 ; 13.715 ; 12.900 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[2] ; CLOCK_50 ; 12.278 ; 12.022 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[3] ; CLOCK_50 ; 12.364 ; 12.091 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[4] ; CLOCK_50 ; 13.022 ; 12.549 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[5] ; CLOCK_50 ; 13.230 ; 12.555 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[6] ; CLOCK_50 ; 13.878 ; 12.987 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[*] ; CLOCK_50 ; 13.372 ; 12.708 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[0] ; CLOCK_50 ; 12.627 ; 12.136 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[1] ; CLOCK_50 ; 12.790 ; 12.216 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[2] ; CLOCK_50 ; 13.372 ; 12.708 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[3] ; CLOCK_50 ; 13.222 ; 12.682 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[4] ; CLOCK_50 ; 13.327 ; 12.629 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[5] ; CLOCK_50 ; 13.321 ; 12.598 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[6] ; CLOCK_50 ; 12.410 ; 12.059 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[*] ; CLOCK_50 ; 13.696 ; 12.872 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[0] ; CLOCK_50 ; 12.951 ; 12.392 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[1] ; CLOCK_50 ; 13.367 ; 12.622 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[2] ; CLOCK_50 ; 13.056 ; 12.408 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[3] ; CLOCK_50 ; 13.696 ; 12.872 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[4] ; CLOCK_50 ; 12.463 ; 12.069 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[5] ; CLOCK_50 ; 12.210 ; 11.946 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[6] ; CLOCK_50 ; 12.148 ; 11.895 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[*] ; CLOCK_50 ; 13.741 ; 12.916 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[0] ; CLOCK_50 ; 13.199 ; 12.528 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[1] ; CLOCK_50 ; 13.591 ; 12.769 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[2] ; CLOCK_50 ; 13.591 ; 12.868 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[3] ; CLOCK_50 ; 12.339 ; 12.122 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[4] ; CLOCK_50 ; 13.741 ; 12.916 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[5] ; CLOCK_50 ; 13.734 ; 12.882 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[6] ; CLOCK_50 ; 12.540 ; 12.184 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[*] ; CLOCK_50 ; 12.502 ; 12.619 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[0] ; CLOCK_50 ; 12.502 ; 12.619 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[2] ; CLOCK_50 ; 12.467 ; 12.583 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[*] ; CLOCK_50 ; 14.761 ; 14.090 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[5] ; CLOCK_50 ; 14.761 ; 14.090 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[*] ; CLOCK_50 ; 14.138 ; 13.378 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[0] ; CLOCK_50 ; 13.699 ; 12.881 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[1] ; CLOCK_50 ; 13.596 ; 12.980 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[2] ; CLOCK_50 ; 14.138 ; 13.378 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[3] ; CLOCK_50 ; 12.948 ; 12.411 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[4] ; CLOCK_50 ; 13.397 ; 12.669 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[5] ; CLOCK_50 ; 12.817 ; 12.344 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[6] ; CLOCK_50 ; 13.642 ; 12.870 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[*] ; CLOCK_50 ; 13.932 ; 13.068 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[0] ; CLOCK_50 ; 13.932 ; 13.068 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[1] ; CLOCK_50 ; 12.750 ; 12.328 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[2] ; CLOCK_50 ; 12.338 ; 12.026 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[3] ; CLOCK_50 ; 13.221 ; 12.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[4] ; CLOCK_50 ; 13.413 ; 12.719 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[5] ; CLOCK_50 ; 13.073 ; 12.427 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[6] ; CLOCK_50 ; 12.440 ; 12.122 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[*] ; CLOCK_50 ; 13.715 ; 12.893 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[0] ; CLOCK_50 ; 13.715 ; 12.893 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[1] ; CLOCK_50 ; 13.023 ; 12.553 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[2] ; CLOCK_50 ; 12.144 ; 11.813 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[3] ; CLOCK_50 ; 12.710 ; 12.161 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[4] ; CLOCK_50 ; 12.775 ; 12.215 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[5] ; CLOCK_50 ; 12.534 ; 12.038 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[6] ; CLOCK_50 ; 12.830 ; 12.260 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[*] ; CLOCK_50 ; 14.622 ; 13.551 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[0] ; CLOCK_50 ; 14.622 ; 13.551 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[1] ; CLOCK_50 ; 12.562 ; 12.118 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[2] ; CLOCK_50 ; 12.916 ; 12.462 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[3] ; CLOCK_50 ; 13.474 ; 12.728 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[4] ; CLOCK_50 ; 12.179 ; 11.844 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[5] ; CLOCK_50 ; 11.959 ; 11.793 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[6] ; CLOCK_50 ; 12.096 ; 11.888 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[*] ; CLOCK_50 ; 15.011 ; 13.809 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[0] ; CLOCK_50 ; 13.021 ; 12.462 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[1] ; CLOCK_50 ; 13.952 ; 13.207 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[2] ; CLOCK_50 ; 15.011 ; 13.809 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[3] ; CLOCK_50 ; 13.066 ; 12.421 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[4] ; CLOCK_50 ; 13.228 ; 12.571 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[5] ; CLOCK_50 ; 12.482 ; 12.102 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[6] ; CLOCK_50 ; 12.608 ; 12.079 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[*] ; CLOCK_50 ; 13.804 ; 12.964 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[0] ; CLOCK_50 ; 13.432 ; 12.854 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[1] ; CLOCK_50 ; 12.673 ; 12.120 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[2] ; CLOCK_50 ; 12.625 ; 12.301 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[3] ; CLOCK_50 ; 12.659 ; 12.139 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[4] ; CLOCK_50 ; 13.012 ; 12.395 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[5] ; CLOCK_50 ; 12.538 ; 12.015 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[6] ; CLOCK_50 ; 13.804 ; 12.964 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[*] ; CLOCK_50 ; 14.182 ; 14.899 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[0] ; CLOCK_50 ; 14.013 ; 14.703 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[1] ; CLOCK_50 ; 14.182 ; 14.899 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[2] ; CLOCK_50 ; 13.675 ; 14.240 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
@@ -611,57 +620,60 @@ No paths to report.
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
-; HEX0[*] ; CLOCK_50 ; 11.294 ; 11.028 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[0] ; CLOCK_50 ; 12.204 ; 11.668 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[1] ; CLOCK_50 ; 11.509 ; 11.150 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[2] ; CLOCK_50 ; 11.711 ; 11.299 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[3] ; CLOCK_50 ; 12.135 ; 11.666 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[4] ; CLOCK_50 ; 11.979 ; 11.466 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[5] ; CLOCK_50 ; 11.294 ; 11.028 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[6] ; CLOCK_50 ; 12.384 ; 11.777 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[*] ; CLOCK_50 ; 10.569 ; 10.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[0] ; CLOCK_50 ; 12.299 ; 11.713 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[1] ; CLOCK_50 ; 10.953 ; 10.778 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[2] ; CLOCK_50 ; 10.569 ; 10.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[3] ; CLOCK_50 ; 11.316 ; 11.019 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[4] ; CLOCK_50 ; 11.563 ; 11.168 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[5] ; CLOCK_50 ; 11.584 ; 11.176 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[6] ; CLOCK_50 ; 11.106 ; 10.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[*] ; CLOCK_50 ; 11.106 ; 10.914 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[0] ; CLOCK_50 ; 11.803 ; 11.374 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[1] ; CLOCK_50 ; 12.160 ; 11.622 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[2] ; CLOCK_50 ; 11.106 ; 10.914 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[3] ; CLOCK_50 ; 11.149 ; 10.969 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[4] ; CLOCK_50 ; 11.705 ; 11.364 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[5] ; CLOCK_50 ; 11.725 ; 11.308 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[6] ; CLOCK_50 ; 12.281 ; 11.684 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[*] ; CLOCK_50 ; 11.198 ; 10.920 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[0] ; CLOCK_50 ; 11.198 ; 10.920 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[1] ; CLOCK_50 ; 11.328 ; 10.990 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[2] ; CLOCK_50 ; 11.962 ; 11.483 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[3] ; CLOCK_50 ; 11.900 ; 11.492 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[4] ; CLOCK_50 ; 11.854 ; 11.381 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[5] ; CLOCK_50 ; 11.833 ; 11.351 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[6] ; CLOCK_50 ; 11.224 ; 10.947 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[*] ; CLOCK_50 ; 10.953 ; 10.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[0] ; CLOCK_50 ; 11.582 ; 11.195 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[1] ; CLOCK_50 ; 11.814 ; 11.348 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[2] ; CLOCK_50 ; 11.568 ; 11.160 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[3] ; CLOCK_50 ; 12.126 ; 11.585 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[4] ; CLOCK_50 ; 11.139 ; 10.898 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[5] ; CLOCK_50 ; 10.989 ; 10.814 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[6] ; CLOCK_50 ; 10.953 ; 10.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[*] ; CLOCK_50 ; 11.126 ; 10.988 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[0] ; CLOCK_50 ; 11.686 ; 11.277 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[1] ; CLOCK_50 ; 12.006 ; 11.473 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[2] ; CLOCK_50 ; 12.050 ; 11.575 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[3] ; CLOCK_50 ; 11.126 ; 10.988 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[4] ; CLOCK_50 ; 12.183 ; 11.635 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[5] ; CLOCK_50 ; 12.145 ; 11.586 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[6] ; CLOCK_50 ; 11.318 ; 11.058 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[*] ; CLOCK_50 ; 10.411 ; 10.495 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[0] ; CLOCK_50 ; 10.448 ; 10.545 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[2] ; CLOCK_50 ; 10.411 ; 10.495 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[*] ; CLOCK_50 ; 12.455 ; 11.887 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[5] ; CLOCK_50 ; 12.455 ; 11.887 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[*] ; CLOCK_50 ; 11.483 ; 11.165 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[0] ; CLOCK_50 ; 12.208 ; 11.630 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[1] ; CLOCK_50 ; 12.138 ; 11.723 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[2] ; CLOCK_50 ; 12.640 ; 12.080 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[3] ; CLOCK_50 ; 11.592 ; 11.230 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[4] ; CLOCK_50 ; 11.941 ; 11.436 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[5] ; CLOCK_50 ; 11.483 ; 11.165 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[6] ; CLOCK_50 ; 12.175 ; 11.623 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[*] ; CLOCK_50 ; 11.103 ; 10.900 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[0] ; CLOCK_50 ; 12.401 ; 11.790 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[1] ; CLOCK_50 ; 11.455 ; 11.164 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[2] ; CLOCK_50 ; 11.103 ; 10.900 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[3] ; CLOCK_50 ; 11.736 ; 11.304 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[4] ; CLOCK_50 ; 11.945 ; 11.473 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[5] ; CLOCK_50 ; 11.632 ; 11.210 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[6] ; CLOCK_50 ; 11.175 ; 10.972 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[*] ; CLOCK_50 ; 10.919 ; 10.698 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[0] ; CLOCK_50 ; 12.194 ; 11.626 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[1] ; CLOCK_50 ; 11.643 ; 11.344 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[2] ; CLOCK_50 ; 10.919 ; 10.698 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[3] ; CLOCK_50 ; 11.321 ; 10.976 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[4] ; CLOCK_50 ; 11.373 ; 11.021 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[5] ; CLOCK_50 ; 11.166 ; 10.859 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[6] ; CLOCK_50 ; 11.419 ; 11.064 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[*] ; CLOCK_50 ; 10.837 ; 10.710 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[0] ; CLOCK_50 ; 12.827 ; 12.139 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[1] ; CLOCK_50 ; 11.278 ; 10.964 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[2] ; CLOCK_50 ; 11.704 ; 11.319 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[3] ; CLOCK_50 ; 12.002 ; 11.483 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[4] ; CLOCK_50 ; 10.951 ; 10.728 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[5] ; CLOCK_50 ; 10.837 ; 10.710 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[6] ; CLOCK_50 ; 10.938 ; 10.789 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[*] ; CLOCK_50 ; 11.202 ; 10.884 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[0] ; CLOCK_50 ; 11.721 ; 11.289 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[1] ; CLOCK_50 ; 12.421 ; 11.906 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[2] ; CLOCK_50 ; 13.155 ; 12.372 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[3] ; CLOCK_50 ; 11.614 ; 11.195 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[4] ; CLOCK_50 ; 11.726 ; 11.316 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[5] ; CLOCK_50 ; 11.202 ; 10.948 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[6] ; CLOCK_50 ; 11.212 ; 10.884 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[*] ; CLOCK_50 ; 11.149 ; 10.825 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[0] ; CLOCK_50 ; 11.968 ; 11.592 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[1] ; CLOCK_50 ; 11.282 ; 10.936 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[2] ; CLOCK_50 ; 11.277 ; 11.104 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[3] ; CLOCK_50 ; 11.228 ; 10.929 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[4] ; CLOCK_50 ; 11.564 ; 11.174 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[5] ; CLOCK_50 ; 11.149 ; 10.825 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[6] ; CLOCK_50 ; 12.313 ; 11.699 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[*] ; CLOCK_50 ; 11.516 ; 11.995 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[0] ; CLOCK_50 ; 11.812 ; 12.389 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[1] ; CLOCK_50 ; 11.990 ; 12.616 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[2] ; CLOCK_50 ; 11.516 ; 11.995 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
@@ -674,7 +686,7 @@ Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
Number of Synchronizer Chains Found: 1
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
-Worst Case Available Settling Time: 17.571 ns
+Worst Case Available Settling Time: 37.423 ns
Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
- Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 5.2
@@ -715,28 +727,28 @@ Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ;
; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ;
; Number of Synchronization Registers in Chain ; 2 ; ; ; ;
-; Available Settling Time (ns) ; 17.571 ; ; ; ;
-; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ;
+; Available Settling Time (ns) ; 37.423 ; ; ; ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 6.25 ; ; ; ;
; Source Clock ; ; ; ; ;
; Unknown ; ; ; ; ;
; Synchronization Clock ; ; ; ; ;
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 10.000 ; 100.0 MHz ; ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 20.000 ; 50.0 MHz ; ;
; Asynchronous Source ; ; ; ; ;
; GPIO[7] ; ; ; ; ;
; Synchronization Registers ; ; ; ; ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.075 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 8.496 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 19.013 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 18.410 ;
+-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
-+----------------------------------------------------------------------------------------------------+
-; Fast 1100mV 85C Model Setup Summary ;
-+----------------------------------------------------------------------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+----------------------------------------------------------------------------+-------+---------------+
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.503 ; 0.000 ;
-+----------------------------------------------------------------------------+-------+---------------+
++-----------------------------------------------------------------------------------------------------+
+; Fast 1100mV 85C Model Setup Summary ;
++----------------------------------------------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++----------------------------------------------------------------------------+--------+---------------+
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 11.576 ; 0.000 ;
++----------------------------------------------------------------------------+--------+---------------+
+----------------------------------------------------------------------------------------------------+
@@ -744,7 +756,7 @@ Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+----------------------------------------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------------------------+-------+---------------+
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.154 ; 0.000 ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.162 ; 0.000 ;
+----------------------------------------------------------------------------+-------+---------------+
@@ -766,33 +778,33 @@ No paths to report.
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------------------------+-------+---------------+
; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; 1.666 ; 0.000 ;
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.888 ; 0.000 ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 8.890 ; 0.000 ;
; CLOCK_50 ; 9.336 ; 0.000 ;
+----------------------------------------------------------------------------+-------+---------------+
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Setup Times ;
-+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
-; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
-; KEY[*] ; CLOCK_50 ; 0.692 ; 2.270 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[0] ; CLOCK_50 ; 0.464 ; 1.837 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[1] ; CLOCK_50 ; 0.692 ; 2.270 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[2] ; CLOCK_50 ; -0.037 ; 1.200 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[3] ; CLOCK_50 ; -0.145 ; 1.240 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[*] ; CLOCK_50 ; 1.719 ; 3.429 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[0] ; CLOCK_50 ; 0.339 ; 1.060 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[1] ; CLOCK_50 ; -0.452 ; 0.600 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[2] ; CLOCK_50 ; -0.605 ; 0.598 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[3] ; CLOCK_50 ; -0.373 ; 0.897 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[4] ; CLOCK_50 ; -0.021 ; 1.245 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[5] ; CLOCK_50 ; -1.060 ; -0.170 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[6] ; CLOCK_50 ; 0.487 ; 1.358 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[7] ; CLOCK_50 ; 1.719 ; 3.429 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[8] ; CLOCK_50 ; 0.986 ; 2.118 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[9] ; CLOCK_50 ; 0.864 ; 2.176 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Setup Times ;
++-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+
+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+
+; KEY[*] ; CLOCK_50 ; 2.564 ; 3.848 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[0] ; CLOCK_50 ; 0.383 ; 1.424 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[1] ; CLOCK_50 ; -0.289 ; 0.848 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[2] ; CLOCK_50 ; 0.361 ; 1.780 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[3] ; CLOCK_50 ; 2.564 ; 3.848 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[*] ; CLOCK_50 ; 4.285 ; 6.023 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[0] ; CLOCK_50 ; -0.177 ; 1.068 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[1] ; CLOCK_50 ; -0.222 ; 0.854 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[2] ; CLOCK_50 ; 0.118 ; 1.528 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[3] ; CLOCK_50 ; -0.514 ; 0.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[4] ; CLOCK_50 ; 0.528 ; 1.992 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[5] ; CLOCK_50 ; 0.148 ; 1.665 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[6] ; CLOCK_50 ; 2.213 ; 3.796 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[7] ; CLOCK_50 ; 4.285 ; 6.023 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[8] ; CLOCK_50 ; 2.084 ; 3.413 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[9] ; CLOCK_50 ; 0.787 ; 2.225 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
++-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------+
@@ -800,22 +812,22 @@ No paths to report.
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
-; KEY[*] ; CLOCK_50 ; 2.443 ; 1.566 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[0] ; CLOCK_50 ; 1.878 ; 0.901 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[1] ; CLOCK_50 ; 1.722 ; 0.631 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[2] ; CLOCK_50 ; 2.001 ; 1.020 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[3] ; CLOCK_50 ; 2.443 ; 1.566 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[*] ; CLOCK_50 ; 2.083 ; 1.225 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[0] ; CLOCK_50 ; 0.781 ; 0.016 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[1] ; CLOCK_50 ; 1.352 ; 0.408 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[2] ; CLOCK_50 ; 1.693 ; 0.753 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[3] ; CLOCK_50 ; 1.821 ; 0.909 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[4] ; CLOCK_50 ; 1.684 ; 0.801 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[5] ; CLOCK_50 ; 2.083 ; 1.225 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[6] ; CLOCK_50 ; 1.499 ; 0.536 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[7] ; CLOCK_50 ; 1.689 ; 0.744 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[8] ; CLOCK_50 ; 1.846 ; 0.908 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[9] ; CLOCK_50 ; 1.921 ; 0.974 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[*] ; CLOCK_50 ; 2.210 ; 1.239 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[0] ; CLOCK_50 ; 2.006 ; 1.021 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[1] ; CLOCK_50 ; 2.210 ; 1.231 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[2] ; CLOCK_50 ; 1.825 ; 0.675 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[3] ; CLOCK_50 ; 2.185 ; 1.239 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[*] ; CLOCK_50 ; 1.876 ; 0.988 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[0] ; CLOCK_50 ; 1.289 ; 0.223 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[1] ; CLOCK_50 ; 1.302 ; 0.338 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[2] ; CLOCK_50 ; 1.606 ; 0.592 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[3] ; CLOCK_50 ; 1.876 ; 0.988 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[4] ; CLOCK_50 ; 1.285 ; 0.164 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[5] ; CLOCK_50 ; 1.371 ; 0.193 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[6] ; CLOCK_50 ; 1.371 ; 0.265 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[7] ; CLOCK_50 ; 1.336 ; 0.247 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[8] ; CLOCK_50 ; 1.740 ; 0.802 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[9] ; CLOCK_50 ; 1.824 ; 0.882 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
@@ -824,57 +836,60 @@ No paths to report.
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
-; HEX0[*] ; CLOCK_50 ; 8.963 ; 8.164 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[0] ; CLOCK_50 ; 8.774 ; 8.038 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[1] ; CLOCK_50 ; 8.038 ; 7.547 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[2] ; CLOCK_50 ; 8.213 ; 7.680 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[3] ; CLOCK_50 ; 8.510 ; 7.943 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[4] ; CLOCK_50 ; 8.604 ; 7.891 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[5] ; CLOCK_50 ; 7.795 ; 7.441 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[6] ; CLOCK_50 ; 8.963 ; 8.164 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[*] ; CLOCK_50 ; 8.830 ; 8.062 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[0] ; CLOCK_50 ; 8.830 ; 8.062 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[1] ; CLOCK_50 ; 7.520 ; 7.281 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[2] ; CLOCK_50 ; 7.183 ; 7.067 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[3] ; CLOCK_50 ; 8.034 ; 7.547 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[4] ; CLOCK_50 ; 8.211 ; 7.628 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[5] ; CLOCK_50 ; 8.222 ; 7.645 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[6] ; CLOCK_50 ; 7.666 ; 7.468 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[*] ; CLOCK_50 ; 8.818 ; 8.043 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[0] ; CLOCK_50 ; 8.414 ; 7.834 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[1] ; CLOCK_50 ; 8.726 ; 7.989 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[2] ; CLOCK_50 ; 7.631 ; 7.371 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[3] ; CLOCK_50 ; 7.716 ; 7.434 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[4] ; CLOCK_50 ; 8.192 ; 7.738 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[5] ; CLOCK_50 ; 8.385 ; 7.763 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[6] ; CLOCK_50 ; 8.818 ; 8.043 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[*] ; CLOCK_50 ; 8.516 ; 7.906 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[0] ; CLOCK_50 ; 7.959 ; 7.496 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[1] ; CLOCK_50 ; 8.090 ; 7.575 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[2] ; CLOCK_50 ; 8.516 ; 7.906 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[3] ; CLOCK_50 ; 8.404 ; 7.901 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[4] ; CLOCK_50 ; 8.423 ; 7.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[5] ; CLOCK_50 ; 8.452 ; 7.804 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[6] ; CLOCK_50 ; 7.795 ; 7.442 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[*] ; CLOCK_50 ; 8.761 ; 8.020 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[0] ; CLOCK_50 ; 8.176 ; 7.663 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[1] ; CLOCK_50 ; 8.521 ; 7.847 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[2] ; CLOCK_50 ; 8.253 ; 7.670 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[3] ; CLOCK_50 ; 8.761 ; 8.020 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[4] ; CLOCK_50 ; 7.808 ; 7.429 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[5] ; CLOCK_50 ; 7.635 ; 7.364 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[6] ; CLOCK_50 ; 7.586 ; 7.331 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[*] ; CLOCK_50 ; 8.793 ; 8.026 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[0] ; CLOCK_50 ; 8.388 ; 7.773 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[1] ; CLOCK_50 ; 8.657 ; 7.930 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[2] ; CLOCK_50 ; 8.658 ; 8.001 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[3] ; CLOCK_50 ; 7.697 ; 7.485 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[4] ; CLOCK_50 ; 8.776 ; 8.019 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[5] ; CLOCK_50 ; 8.793 ; 8.026 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[6] ; CLOCK_50 ; 7.831 ; 7.486 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[*] ; CLOCK_50 ; 7.522 ; 7.658 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[0] ; CLOCK_50 ; 7.522 ; 7.658 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[2] ; CLOCK_50 ; 7.508 ; 7.634 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[*] ; CLOCK_50 ; 9.230 ; 8.626 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[5] ; CLOCK_50 ; 9.230 ; 8.626 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[*] ; CLOCK_50 ; 9.046 ; 8.336 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[0] ; CLOCK_50 ; 8.701 ; 7.978 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[1] ; CLOCK_50 ; 8.601 ; 8.027 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[2] ; CLOCK_50 ; 9.046 ; 8.336 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[3] ; CLOCK_50 ; 8.112 ; 7.633 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[4] ; CLOCK_50 ; 8.479 ; 7.829 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[5] ; CLOCK_50 ; 8.022 ; 7.593 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[6] ; CLOCK_50 ; 8.671 ; 7.985 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[*] ; CLOCK_50 ; 8.850 ; 8.090 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[0] ; CLOCK_50 ; 8.850 ; 8.090 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[1] ; CLOCK_50 ; 7.967 ; 7.568 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[2] ; CLOCK_50 ; 7.642 ; 7.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[3] ; CLOCK_50 ; 8.364 ; 7.757 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[4] ; CLOCK_50 ; 8.488 ; 7.858 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[5] ; CLOCK_50 ; 8.273 ; 7.689 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[6] ; CLOCK_50 ; 7.762 ; 7.453 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[*] ; CLOCK_50 ; 8.746 ; 8.023 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[0] ; CLOCK_50 ; 8.746 ; 8.023 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[1] ; CLOCK_50 ; 8.196 ; 7.740 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[2] ; CLOCK_50 ; 7.546 ; 7.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[3] ; CLOCK_50 ; 7.977 ; 7.476 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[4] ; CLOCK_50 ; 8.028 ; 7.517 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[5] ; CLOCK_50 ; 7.865 ; 7.413 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[6] ; CLOCK_50 ; 8.087 ; 7.563 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[*] ; CLOCK_50 ; 9.464 ; 8.509 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[0] ; CLOCK_50 ; 9.464 ; 8.509 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[1] ; CLOCK_50 ; 7.880 ; 7.463 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[2] ; CLOCK_50 ; 8.132 ; 7.686 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[3] ; CLOCK_50 ; 8.565 ; 7.917 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[4] ; CLOCK_50 ; 7.550 ; 7.221 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[5] ; CLOCK_50 ; 7.420 ; 7.240 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[6] ; CLOCK_50 ; 7.505 ; 7.280 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[*] ; CLOCK_50 ; 9.742 ; 8.688 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[0] ; CLOCK_50 ; 8.245 ; 7.716 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[1] ; CLOCK_50 ; 8.949 ; 8.268 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[2] ; CLOCK_50 ; 9.742 ; 8.688 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[3] ; CLOCK_50 ; 8.258 ; 7.701 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[4] ; CLOCK_50 ; 8.364 ; 7.790 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[5] ; CLOCK_50 ; 7.825 ; 7.460 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[6] ; CLOCK_50 ; 7.947 ; 7.459 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[*] ; CLOCK_50 ; 8.789 ; 8.030 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[0] ; CLOCK_50 ; 8.550 ; 8.014 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[1] ; CLOCK_50 ; 7.940 ; 7.438 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[2] ; CLOCK_50 ; 7.903 ; 7.583 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[3] ; CLOCK_50 ; 7.976 ; 7.506 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[4] ; CLOCK_50 ; 8.202 ; 7.664 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[5] ; CLOCK_50 ; 7.901 ; 7.423 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[6] ; CLOCK_50 ; 8.789 ; 8.030 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[*] ; CLOCK_50 ; 8.717 ; 9.361 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[0] ; CLOCK_50 ; 8.564 ; 9.173 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[1] ; CLOCK_50 ; 8.717 ; 9.361 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[2] ; CLOCK_50 ; 8.349 ; 8.853 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
@@ -883,57 +898,60 @@ No paths to report.
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
-; HEX0[*] ; CLOCK_50 ; 7.076 ; 6.808 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[0] ; CLOCK_50 ; 7.807 ; 7.305 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[1] ; CLOCK_50 ; 7.246 ; 6.893 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[2] ; CLOCK_50 ; 7.419 ; 7.024 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[3] ; CLOCK_50 ; 7.744 ; 7.282 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[4] ; CLOCK_50 ; 7.644 ; 7.162 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[5] ; CLOCK_50 ; 7.076 ; 6.808 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[6] ; CLOCK_50 ; 7.979 ; 7.421 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[*] ; CLOCK_50 ; 6.562 ; 6.484 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[0] ; CLOCK_50 ; 7.870 ; 7.329 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[1] ; CLOCK_50 ; 6.868 ; 6.686 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[2] ; CLOCK_50 ; 6.562 ; 6.484 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[3] ; CLOCK_50 ; 7.159 ; 6.860 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[4] ; CLOCK_50 ; 7.314 ; 6.932 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[5] ; CLOCK_50 ; 7.332 ; 6.952 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[6] ; CLOCK_50 ; 6.982 ; 6.841 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[*] ; CLOCK_50 ; 6.969 ; 6.761 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[0] ; CLOCK_50 ; 7.558 ; 7.146 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[1] ; CLOCK_50 ; 7.784 ; 7.269 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[2] ; CLOCK_50 ; 6.969 ; 6.761 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[3] ; CLOCK_50 ; 7.018 ; 6.813 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[4] ; CLOCK_50 ; 7.422 ; 7.075 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[5] ; CLOCK_50 ; 7.475 ; 7.063 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[6] ; CLOCK_50 ; 7.849 ; 7.308 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[*] ; CLOCK_50 ; 7.095 ; 6.812 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[0] ; CLOCK_50 ; 7.095 ; 6.812 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[1] ; CLOCK_50 ; 7.198 ; 6.883 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[2] ; CLOCK_50 ; 7.669 ; 7.220 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[3] ; CLOCK_50 ; 7.634 ; 7.235 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[4] ; CLOCK_50 ; 7.524 ; 7.079 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[5] ; CLOCK_50 ; 7.550 ; 7.102 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[6] ; CLOCK_50 ; 7.108 ; 6.833 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[*] ; CLOCK_50 ; 6.901 ; 6.717 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[0] ; CLOCK_50 ; 7.360 ; 6.996 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[1] ; CLOCK_50 ; 7.572 ; 7.128 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[2] ; CLOCK_50 ; 7.355 ; 6.969 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[3] ; CLOCK_50 ; 7.809 ; 7.295 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[4] ; CLOCK_50 ; 7.024 ; 6.779 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[5] ; CLOCK_50 ; 6.925 ; 6.734 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[6] ; CLOCK_50 ; 6.901 ; 6.717 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[*] ; CLOCK_50 ; 7.009 ; 6.856 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[0] ; CLOCK_50 ; 7.473 ; 7.071 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[1] ; CLOCK_50 ; 7.678 ; 7.189 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[2] ; CLOCK_50 ; 7.718 ; 7.270 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[3] ; CLOCK_50 ; 7.009 ; 6.856 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[4] ; CLOCK_50 ; 7.835 ; 7.301 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[5] ; CLOCK_50 ; 7.822 ; 7.292 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[6] ; CLOCK_50 ; 7.132 ; 6.865 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[*] ; CLOCK_50 ; 6.378 ; 6.474 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[0] ; CLOCK_50 ; 6.396 ; 6.507 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[2] ; CLOCK_50 ; 6.378 ; 6.474 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[*] ; CLOCK_50 ; 7.931 ; 7.409 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[5] ; CLOCK_50 ; 7.931 ; 7.409 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[*] ; CLOCK_50 ; 7.245 ; 6.934 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[0] ; CLOCK_50 ; 7.811 ; 7.276 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[1] ; CLOCK_50 ; 7.709 ; 7.322 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[2] ; CLOCK_50 ; 8.131 ; 7.602 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[3] ; CLOCK_50 ; 7.328 ; 6.977 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[4] ; CLOCK_50 ; 7.608 ; 7.139 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[5] ; CLOCK_50 ; 7.245 ; 6.934 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[6] ; CLOCK_50 ; 7.791 ; 7.283 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[*] ; CLOCK_50 ; 6.938 ; 6.722 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[0] ; CLOCK_50 ; 7.930 ; 7.373 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[1] ; CLOCK_50 ; 7.219 ; 6.928 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[2] ; CLOCK_50 ; 6.938 ; 6.722 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[3] ; CLOCK_50 ; 7.472 ; 7.064 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[4] ; CLOCK_50 ; 7.602 ; 7.157 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[5] ; CLOCK_50 ; 7.407 ; 7.005 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[6] ; CLOCK_50 ; 7.033 ; 6.815 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[*] ; CLOCK_50 ; 6.836 ; 6.606 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[0] ; CLOCK_50 ; 7.832 ; 7.315 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[1] ; CLOCK_50 ; 7.358 ; 7.064 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[2] ; CLOCK_50 ; 6.836 ; 6.606 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[3] ; CLOCK_50 ; 7.147 ; 6.813 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[4] ; CLOCK_50 ; 7.187 ; 6.849 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[5] ; CLOCK_50 ; 7.047 ; 6.752 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[6] ; CLOCK_50 ; 7.245 ; 6.895 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[*] ; CLOCK_50 ; 6.798 ; 6.606 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[0] ; CLOCK_50 ; 8.325 ; 7.699 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[1] ; CLOCK_50 ; 7.124 ; 6.825 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[2] ; CLOCK_50 ; 7.449 ; 7.060 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[3] ; CLOCK_50 ; 7.681 ; 7.217 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[4] ; CLOCK_50 ; 6.840 ; 6.606 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[5] ; CLOCK_50 ; 6.798 ; 6.646 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[6] ; CLOCK_50 ; 6.857 ; 6.681 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[*] ; CLOCK_50 ; 7.088 ; 6.788 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[0] ; CLOCK_50 ; 7.484 ; 7.065 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[1] ; CLOCK_50 ; 8.005 ; 7.527 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[2] ; CLOCK_50 ; 8.566 ; 7.864 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[3] ; CLOCK_50 ; 7.385 ; 7.012 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[4] ; CLOCK_50 ; 7.466 ; 7.088 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[5] ; CLOCK_50 ; 7.088 ; 6.824 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[6] ; CLOCK_50 ; 7.109 ; 6.788 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[*] ; CLOCK_50 ; 7.067 ; 6.755 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[0] ; CLOCK_50 ; 7.655 ; 7.298 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[1] ; CLOCK_50 ; 7.113 ; 6.780 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[2] ; CLOCK_50 ; 7.113 ; 6.918 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[3] ; CLOCK_50 ; 7.116 ; 6.829 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[4] ; CLOCK_50 ; 7.337 ; 6.977 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[5] ; CLOCK_50 ; 7.067 ; 6.755 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[6] ; CLOCK_50 ; 7.885 ; 7.317 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[*] ; CLOCK_50 ; 7.159 ; 7.597 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[0] ; CLOCK_50 ; 7.347 ; 7.863 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[1] ; CLOCK_50 ; 7.506 ; 8.089 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[2] ; CLOCK_50 ; 7.159 ; 7.597 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
@@ -946,7 +964,7 @@ Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
Number of Synchronizer Chains Found: 1
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
-Worst Case Available Settling Time: 18.511 ns
+Worst Case Available Settling Time: 38.447 ns
Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
- Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 79.4
@@ -987,28 +1005,28 @@ Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ;
; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ;
; Number of Synchronization Registers in Chain ; 2 ; ; ; ;
-; Available Settling Time (ns) ; 18.511 ; ; ; ;
-; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ;
+; Available Settling Time (ns) ; 38.447 ; ; ; ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 6.25 ; ; ; ;
; Source Clock ; ; ; ; ;
; Unknown ; ; ; ; ;
; Synchronization Clock ; ; ; ; ;
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 10.000 ; 100.0 MHz ; ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 20.000 ; 50.0 MHz ; ;
; Asynchronous Source ; ; ; ; ;
; GPIO[7] ; ; ; ; ;
; Synchronization Registers ; ; ; ; ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.479 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 9.032 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 19.426 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 19.021 ;
+-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
-+----------------------------------------------------------------------------------------------------+
-; Fast 1100mV 0C Model Setup Summary ;
-+----------------------------------------------------------------------------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+----------------------------------------------------------------------------+-------+---------------+
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.812 ; 0.000 ;
-+----------------------------------------------------------------------------+-------+---------------+
++-----------------------------------------------------------------------------------------------------+
+; Fast 1100mV 0C Model Setup Summary ;
++----------------------------------------------------------------------------+--------+---------------+
+; Clock ; Slack ; End Point TNS ;
++----------------------------------------------------------------------------+--------+---------------+
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 12.162 ; 0.000 ;
++----------------------------------------------------------------------------+--------+---------------+
+----------------------------------------------------------------------------------------------------+
@@ -1016,7 +1034,7 @@ Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+----------------------------------------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------------------------+-------+---------------+
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.141 ; 0.000 ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.152 ; 0.000 ;
+----------------------------------------------------------------------------+-------+---------------+
@@ -1038,33 +1056,33 @@ No paths to report.
; Clock ; Slack ; End Point TNS ;
+----------------------------------------------------------------------------+-------+---------------+
; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; 1.666 ; 0.000 ;
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 3.888 ; 0.000 ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 8.891 ; 0.000 ;
; CLOCK_50 ; 9.286 ; 0.000 ;
+----------------------------------------------------------------------------+-------+---------------+
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Setup Times ;
-+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
-; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
-; KEY[*] ; CLOCK_50 ; 0.539 ; 2.077 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[0] ; CLOCK_50 ; 0.338 ; 1.679 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[1] ; CLOCK_50 ; 0.539 ; 2.077 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[2] ; CLOCK_50 ; -0.167 ; 1.103 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[3] ; CLOCK_50 ; -0.291 ; 1.104 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[*] ; CLOCK_50 ; 1.447 ; 3.120 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[0] ; CLOCK_50 ; 0.193 ; 0.984 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[1] ; CLOCK_50 ; -0.563 ; 0.520 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[2] ; CLOCK_50 ; -0.671 ; 0.548 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[3] ; CLOCK_50 ; -0.456 ; 0.823 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[4] ; CLOCK_50 ; -0.154 ; 1.118 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[5] ; CLOCK_50 ; -1.126 ; -0.193 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[6] ; CLOCK_50 ; 0.332 ; 1.250 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[7] ; CLOCK_50 ; 1.447 ; 3.120 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[8] ; CLOCK_50 ; 0.755 ; 1.924 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[9] ; CLOCK_50 ; 0.643 ; 1.975 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Setup Times ;
++-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+
+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+
+; KEY[*] ; CLOCK_50 ; 2.254 ; 3.558 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[0] ; CLOCK_50 ; 0.243 ; 1.302 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[1] ; CLOCK_50 ; -0.441 ; 0.754 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[2] ; CLOCK_50 ; 0.249 ; 1.653 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[3] ; CLOCK_50 ; 2.254 ; 3.558 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[*] ; CLOCK_50 ; 3.933 ; 5.636 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[0] ; CLOCK_50 ; -0.303 ; 0.954 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[1] ; CLOCK_50 ; -0.357 ; 0.764 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[2] ; CLOCK_50 ; -0.002 ; 1.411 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[3] ; CLOCK_50 ; -0.627 ; 0.491 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[4] ; CLOCK_50 ; 0.416 ; 1.855 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[5] ; CLOCK_50 ; 0.062 ; 1.536 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[6] ; CLOCK_50 ; 2.040 ; 3.558 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[7] ; CLOCK_50 ; 3.933 ; 5.636 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[8] ; CLOCK_50 ; 1.806 ; 3.126 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[9] ; CLOCK_50 ; 0.589 ; 2.008 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
++-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------+
@@ -1072,22 +1090,22 @@ No paths to report.
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
-; KEY[*] ; CLOCK_50 ; 2.428 ; 1.516 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[0] ; CLOCK_50 ; 1.868 ; 0.876 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[1] ; CLOCK_50 ; 1.733 ; 0.631 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[2] ; CLOCK_50 ; 1.997 ; 0.997 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[3] ; CLOCK_50 ; 2.428 ; 1.516 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[*] ; CLOCK_50 ; 2.105 ; 1.207 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[0] ; CLOCK_50 ; 0.858 ; 0.041 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[1] ; CLOCK_50 ; 1.411 ; 0.433 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[2] ; CLOCK_50 ; 1.696 ; 0.721 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[3] ; CLOCK_50 ; 1.844 ; 0.898 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[4] ; CLOCK_50 ; 1.735 ; 0.799 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[5] ; CLOCK_50 ; 2.105 ; 1.207 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[6] ; CLOCK_50 ; 1.529 ; 0.529 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[7] ; CLOCK_50 ; 1.691 ; 0.712 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[8] ; CLOCK_50 ; 1.898 ; 0.913 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[9] ; CLOCK_50 ; 1.951 ; 0.959 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[*] ; CLOCK_50 ; 2.232 ; 1.245 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[0] ; CLOCK_50 ; 2.011 ; 1.001 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[1] ; CLOCK_50 ; 2.223 ; 1.209 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[2] ; CLOCK_50 ; 1.814 ; 0.655 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[3] ; CLOCK_50 ; 2.232 ; 1.245 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[*] ; CLOCK_50 ; 1.914 ; 0.968 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[0] ; CLOCK_50 ; 1.368 ; 0.273 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[1] ; CLOCK_50 ; 1.391 ; 0.389 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[2] ; CLOCK_50 ; 1.628 ; 0.574 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[3] ; CLOCK_50 ; 1.914 ; 0.968 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[4] ; CLOCK_50 ; 1.305 ; 0.162 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[5] ; CLOCK_50 ; 1.381 ; 0.199 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[6] ; CLOCK_50 ; 1.378 ; 0.246 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[7] ; CLOCK_50 ; 1.368 ; 0.254 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[8] ; CLOCK_50 ; 1.799 ; 0.814 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[9] ; CLOCK_50 ; 1.883 ; 0.894 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
@@ -1096,57 +1114,60 @@ No paths to report.
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
-; HEX0[*] ; CLOCK_50 ; 8.459 ; 7.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[0] ; CLOCK_50 ; 8.289 ; 7.667 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[1] ; CLOCK_50 ; 7.574 ; 7.154 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[2] ; CLOCK_50 ; 7.728 ; 7.276 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[3] ; CLOCK_50 ; 8.034 ; 7.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[4] ; CLOCK_50 ; 8.116 ; 7.518 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[5] ; CLOCK_50 ; 7.353 ; 7.044 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[6] ; CLOCK_50 ; 8.459 ; 7.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[*] ; CLOCK_50 ; 8.329 ; 7.683 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[0] ; CLOCK_50 ; 8.329 ; 7.683 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[1] ; CLOCK_50 ; 7.063 ; 6.844 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[2] ; CLOCK_50 ; 6.786 ; 6.678 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[3] ; CLOCK_50 ; 7.590 ; 7.183 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[4] ; CLOCK_50 ; 7.757 ; 7.268 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[5] ; CLOCK_50 ; 7.747 ; 7.262 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[6] ; CLOCK_50 ; 7.206 ; 7.013 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[*] ; CLOCK_50 ; 8.305 ; 7.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[0] ; CLOCK_50 ; 7.930 ; 7.432 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[1] ; CLOCK_50 ; 8.242 ; 7.622 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[2] ; CLOCK_50 ; 7.166 ; 6.926 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[3] ; CLOCK_50 ; 7.294 ; 7.042 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[4] ; CLOCK_50 ; 7.730 ; 7.328 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[5] ; CLOCK_50 ; 7.911 ; 7.394 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[6] ; CLOCK_50 ; 8.305 ; 7.649 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[*] ; CLOCK_50 ; 8.007 ; 7.492 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[0] ; CLOCK_50 ; 7.502 ; 7.117 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[1] ; CLOCK_50 ; 7.631 ; 7.194 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[2] ; CLOCK_50 ; 8.007 ; 7.492 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[3] ; CLOCK_50 ; 7.921 ; 7.484 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[4] ; CLOCK_50 ; 7.944 ; 7.405 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[5] ; CLOCK_50 ; 7.954 ; 7.411 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[6] ; CLOCK_50 ; 7.324 ; 7.014 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[*] ; CLOCK_50 ; 8.258 ; 7.636 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[0] ; CLOCK_50 ; 7.697 ; 7.257 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[1] ; CLOCK_50 ; 8.037 ; 7.469 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[2] ; CLOCK_50 ; 7.772 ; 7.278 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[3] ; CLOCK_50 ; 8.258 ; 7.636 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[4] ; CLOCK_50 ; 7.344 ; 7.017 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[5] ; CLOCK_50 ; 7.193 ; 6.953 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[6] ; CLOCK_50 ; 7.145 ; 6.916 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[*] ; CLOCK_50 ; 8.289 ; 7.647 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[0] ; CLOCK_50 ; 7.905 ; 7.387 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[1] ; CLOCK_50 ; 8.167 ; 7.552 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[2] ; CLOCK_50 ; 8.153 ; 7.592 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[3] ; CLOCK_50 ; 7.224 ; 7.022 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[4] ; CLOCK_50 ; 8.278 ; 7.643 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[5] ; CLOCK_50 ; 8.289 ; 7.647 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[6] ; CLOCK_50 ; 7.393 ; 7.091 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[*] ; CLOCK_50 ; 7.159 ; 7.266 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[0] ; CLOCK_50 ; 7.159 ; 7.266 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[2] ; CLOCK_50 ; 7.141 ; 7.244 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[*] ; CLOCK_50 ; 8.729 ; 8.226 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[5] ; CLOCK_50 ; 8.729 ; 8.226 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[*] ; CLOCK_50 ; 8.523 ; 7.906 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[0] ; CLOCK_50 ; 8.211 ; 7.601 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[1] ; CLOCK_50 ; 8.096 ; 7.588 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[2] ; CLOCK_50 ; 8.523 ; 7.906 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[3] ; CLOCK_50 ; 7.628 ; 7.204 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[4] ; CLOCK_50 ; 7.982 ; 7.435 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[5] ; CLOCK_50 ; 7.539 ; 7.161 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[6] ; CLOCK_50 ; 8.147 ; 7.556 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[*] ; CLOCK_50 ; 8.339 ; 7.698 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[0] ; CLOCK_50 ; 8.339 ; 7.698 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[1] ; CLOCK_50 ; 7.476 ; 7.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[2] ; CLOCK_50 ; 7.184 ; 6.919 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[3] ; CLOCK_50 ; 7.881 ; 7.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[4] ; CLOCK_50 ; 8.019 ; 7.486 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[5] ; CLOCK_50 ; 7.802 ; 7.313 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[6] ; CLOCK_50 ; 7.289 ; 7.012 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[*] ; CLOCK_50 ; 8.219 ; 7.606 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[0] ; CLOCK_50 ; 8.219 ; 7.606 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[1] ; CLOCK_50 ; 7.746 ; 7.339 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[2] ; CLOCK_50 ; 7.105 ; 6.824 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[3] ; CLOCK_50 ; 7.536 ; 7.117 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[4] ; CLOCK_50 ; 7.587 ; 7.159 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[5] ; CLOCK_50 ; 7.416 ; 7.039 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[6] ; CLOCK_50 ; 7.628 ; 7.188 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[*] ; CLOCK_50 ; 8.927 ; 8.117 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[0] ; CLOCK_50 ; 8.927 ; 8.117 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[1] ; CLOCK_50 ; 7.402 ; 7.038 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[2] ; CLOCK_50 ; 7.637 ; 7.244 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[3] ; CLOCK_50 ; 8.036 ; 7.479 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[4] ; CLOCK_50 ; 7.119 ; 6.834 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[5] ; CLOCK_50 ; 6.957 ; 6.786 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[6] ; CLOCK_50 ; 7.027 ; 6.808 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[*] ; CLOCK_50 ; 9.184 ; 8.287 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[0] ; CLOCK_50 ; 7.751 ; 7.302 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[1] ; CLOCK_50 ; 8.428 ; 7.832 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[2] ; CLOCK_50 ; 9.184 ; 8.287 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[3] ; CLOCK_50 ; 7.749 ; 7.267 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[4] ; CLOCK_50 ; 7.873 ; 7.382 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[5] ; CLOCK_50 ; 7.362 ; 7.049 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[6] ; CLOCK_50 ; 7.486 ; 7.078 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[*] ; CLOCK_50 ; 8.287 ; 7.655 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[0] ; CLOCK_50 ; 8.062 ; 7.591 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[1] ; CLOCK_50 ; 7.482 ; 7.065 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[2] ; CLOCK_50 ; 7.446 ; 7.151 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[3] ; CLOCK_50 ; 7.512 ; 7.108 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[4] ; CLOCK_50 ; 7.708 ; 7.250 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[5] ; CLOCK_50 ; 7.443 ; 7.044 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[6] ; CLOCK_50 ; 8.287 ; 7.655 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[*] ; CLOCK_50 ; 8.329 ; 8.870 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[0] ; CLOCK_50 ; 8.153 ; 8.665 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[1] ; CLOCK_50 ; 8.329 ; 8.870 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[2] ; CLOCK_50 ; 7.949 ; 8.372 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
@@ -1155,57 +1176,60 @@ No paths to report.
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
-; HEX0[*] ; CLOCK_50 ; 6.692 ; 6.455 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[0] ; CLOCK_50 ; 7.398 ; 6.973 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[1] ; CLOCK_50 ; 6.848 ; 6.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[2] ; CLOCK_50 ; 7.003 ; 6.660 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[3] ; CLOCK_50 ; 7.320 ; 6.923 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[4] ; CLOCK_50 ; 7.230 ; 6.829 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[5] ; CLOCK_50 ; 6.692 ; 6.455 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[6] ; CLOCK_50 ; 7.543 ; 7.077 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[*] ; CLOCK_50 ; 6.210 ; 6.134 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[0] ; CLOCK_50 ; 7.449 ; 6.992 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[1] ; CLOCK_50 ; 6.460 ; 6.290 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[2] ; CLOCK_50 ; 6.210 ; 6.134 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[3] ; CLOCK_50 ; 6.782 ; 6.534 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[4] ; CLOCK_50 ; 6.930 ; 6.612 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[5] ; CLOCK_50 ; 6.938 ; 6.611 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[6] ; CLOCK_50 ; 6.566 ; 6.430 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[*] ; CLOCK_50 ; 6.550 ; 6.360 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[0] ; CLOCK_50 ; 7.134 ; 6.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[1] ; CLOCK_50 ; 7.369 ; 6.940 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[2] ; CLOCK_50 ; 6.550 ; 6.360 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[3] ; CLOCK_50 ; 6.644 ; 6.461 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[4] ; CLOCK_50 ; 7.014 ; 6.709 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[5] ; CLOCK_50 ; 7.070 ; 6.731 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[6] ; CLOCK_50 ; 7.408 ; 6.955 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[*] ; CLOCK_50 ; 6.699 ; 6.443 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[0] ; CLOCK_50 ; 6.706 ; 6.472 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[1] ; CLOCK_50 ; 6.807 ; 6.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[2] ; CLOCK_50 ; 7.230 ; 6.845 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[3] ; CLOCK_50 ; 7.198 ; 6.857 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[4] ; CLOCK_50 ; 7.123 ; 6.744 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[5] ; CLOCK_50 ; 7.125 ; 6.749 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[6] ; CLOCK_50 ; 6.699 ; 6.443 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[*] ; CLOCK_50 ; 6.508 ; 6.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[0] ; CLOCK_50 ; 6.949 ; 6.629 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[1] ; CLOCK_50 ; 7.158 ; 6.787 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[2] ; CLOCK_50 ; 6.943 ; 6.617 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[3] ; CLOCK_50 ; 7.374 ; 6.948 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[4] ; CLOCK_50 ; 6.627 ; 6.409 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[5] ; CLOCK_50 ; 6.533 ; 6.364 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[6] ; CLOCK_50 ; 6.508 ; 6.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[*] ; CLOCK_50 ; 6.580 ; 6.437 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[0] ; CLOCK_50 ; 7.059 ; 6.723 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[1] ; CLOCK_50 ; 7.263 ; 6.853 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[2] ; CLOCK_50 ; 7.287 ; 6.903 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[3] ; CLOCK_50 ; 6.580 ; 6.437 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[4] ; CLOCK_50 ; 7.404 ; 6.962 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[5] ; CLOCK_50 ; 7.388 ; 6.951 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[6] ; CLOCK_50 ; 6.741 ; 6.509 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[*] ; CLOCK_50 ; 6.046 ; 6.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[0] ; CLOCK_50 ; 6.068 ; 6.158 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[2] ; CLOCK_50 ; 6.046 ; 6.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[*] ; CLOCK_50 ; 7.479 ; 7.046 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[5] ; CLOCK_50 ; 7.479 ; 7.046 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[*] ; CLOCK_50 ; 6.818 ; 6.548 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[0] ; CLOCK_50 ; 7.382 ; 6.938 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[1] ; CLOCK_50 ; 7.292 ; 6.927 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[2] ; CLOCK_50 ; 7.685 ; 7.214 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[3] ; CLOCK_50 ; 6.899 ; 6.593 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[4] ; CLOCK_50 ; 7.179 ; 6.786 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[5] ; CLOCK_50 ; 6.818 ; 6.548 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[6] ; CLOCK_50 ; 7.334 ; 6.899 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[*] ; CLOCK_50 ; 6.532 ; 6.344 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[0] ; CLOCK_50 ; 7.490 ; 7.022 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[1] ; CLOCK_50 ; 6.789 ; 6.528 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[2] ; CLOCK_50 ; 6.532 ; 6.344 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[3] ; CLOCK_50 ; 7.056 ; 6.715 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[4] ; CLOCK_50 ; 7.201 ; 6.825 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[5] ; CLOCK_50 ; 6.999 ; 6.667 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[6] ; CLOCK_50 ; 6.614 ; 6.419 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[*] ; CLOCK_50 ; 6.454 ; 6.251 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[0] ; CLOCK_50 ; 7.379 ; 6.938 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[1] ; CLOCK_50 ; 6.987 ; 6.705 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[2] ; CLOCK_50 ; 6.454 ; 6.251 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[3] ; CLOCK_50 ; 6.769 ; 6.493 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[4] ; CLOCK_50 ; 6.810 ; 6.528 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[5] ; CLOCK_50 ; 6.661 ; 6.417 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[6] ; CLOCK_50 ; 6.849 ; 6.558 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[*] ; CLOCK_50 ; 6.375 ; 6.237 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[0] ; CLOCK_50 ; 7.885 ; 7.345 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[1] ; CLOCK_50 ; 6.715 ; 6.443 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[2] ; CLOCK_50 ; 7.002 ; 6.661 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[3] ; CLOCK_50 ; 7.220 ; 6.822 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[4] ; CLOCK_50 ; 6.468 ; 6.261 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[5] ; CLOCK_50 ; 6.375 ; 6.237 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[6] ; CLOCK_50 ; 6.430 ; 6.255 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[*] ; CLOCK_50 ; 6.676 ; 6.446 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[0] ; CLOCK_50 ; 7.049 ; 6.692 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[1] ; CLOCK_50 ; 7.564 ; 7.135 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[2] ; CLOCK_50 ; 8.108 ; 7.502 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[3] ; CLOCK_50 ; 6.949 ; 6.622 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[4] ; CLOCK_50 ; 7.042 ; 6.721 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[5] ; CLOCK_50 ; 6.676 ; 6.452 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[6] ; CLOCK_50 ; 6.712 ; 6.446 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[*] ; CLOCK_50 ; 6.672 ; 6.414 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[0] ; CLOCK_50 ; 7.242 ; 6.917 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[1] ; CLOCK_50 ; 6.720 ; 6.445 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[2] ; CLOCK_50 ; 6.715 ; 6.529 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[3] ; CLOCK_50 ; 6.720 ; 6.471 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[4] ; CLOCK_50 ; 6.907 ; 6.605 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[5] ; CLOCK_50 ; 6.672 ; 6.414 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[6] ; CLOCK_50 ; 7.455 ; 6.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[*] ; CLOCK_50 ; 6.797 ; 7.163 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[0] ; CLOCK_50 ; 6.975 ; 7.411 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[1] ; CLOCK_50 ; 7.154 ; 7.632 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[2] ; CLOCK_50 ; 6.797 ; 7.163 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
@@ -1218,7 +1242,7 @@ Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.
Number of Synchronizer Chains Found: 1
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
-Worst Case Available Settling Time: 18.610 ns
+Worst Case Available Settling Time: 38.555 ns
Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
- Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 5.2
@@ -1259,59 +1283,59 @@ Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
; Worst-Case MTBF (years) ; Greater than 1 Billion ; ; ; ;
; Typical MTBF (years) ; Greater than 1 Billion ; ; ; ;
; Number of Synchronization Registers in Chain ; 2 ; ; ; ;
-; Available Settling Time (ns) ; 18.610 ; ; ; ;
-; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 12.5 ; ; ; ;
+; Available Settling Time (ns) ; 38.555 ; ; ; ;
+; Data Toggle Rate Used in MTBF Calculation (millions of transitions / sec) ; 6.25 ; ; ; ;
; Source Clock ; ; ; ; ;
; Unknown ; ; ; ; ;
; Synchronization Clock ; ; ; ; ;
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 10.000 ; 100.0 MHz ; ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; 20.000 ; 50.0 MHz ; ;
; Asynchronous Source ; ; ; ; ;
; GPIO[7] ; ; ; ; ;
; Synchronization Registers ; ; ; ; ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 9.504 ;
-; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 9.106 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|din_s1 ; ; ; ; 19.456 ;
+; altera_uart:uart|altera_uart_rx:the_altera_uart_rx|altera_std_synchronizer:the_altera_std_synchronizer|dreg[0] ; ; ; ; 19.099 ;
+-----------------------------------------------------------------------------------------------------------------+------------------------+--------------+------------------+--------------+
-+-------------------------------------------------------------------------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+-----------------------------------------------------------------------------+----------+-------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+-----------------------------------------------------------------------------+----------+-------+----------+---------+---------------------+
-; Worst-case Slack ; -1.352 ; 0.141 ; N/A ; N/A ; 1.666 ;
-; CLOCK_50 ; N/A ; N/A ; N/A ; N/A ; 9.286 ;
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 1.666 ;
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -1.352 ; 0.141 ; N/A ; N/A ; 3.758 ;
-; Design-wide TNS ; -121.67 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
-; CLOCK_50 ; N/A ; N/A ; N/A ; N/A ; 0.000 ;
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 0.000 ;
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; -121.670 ; 0.000 ; N/A ; N/A ; 0.000 ;
-+-----------------------------------------------------------------------------+----------+-------+----------+---------+---------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Setup Times ;
-+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
-; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
-; KEY[*] ; CLOCK_50 ; 1.172 ; 2.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[0] ; CLOCK_50 ; 0.834 ; 1.942 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[1] ; CLOCK_50 ; 1.172 ; 2.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[2] ; CLOCK_50 ; -0.037 ; 1.200 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[3] ; CLOCK_50 ; -0.145 ; 1.240 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[*] ; CLOCK_50 ; 2.873 ; 4.412 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[0] ; CLOCK_50 ; 0.534 ; 1.060 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[1] ; CLOCK_50 ; -0.452 ; 0.600 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[2] ; CLOCK_50 ; -0.605 ; 0.598 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[3] ; CLOCK_50 ; -0.373 ; 0.897 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[4] ; CLOCK_50 ; 0.128 ; 1.245 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[5] ; CLOCK_50 ; -1.060 ; -0.170 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[6] ; CLOCK_50 ; 0.963 ; 1.365 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[7] ; CLOCK_50 ; 2.873 ; 4.412 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[8] ; CLOCK_50 ; 1.752 ; 2.499 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[9] ; CLOCK_50 ; 1.529 ; 2.464 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
++----------------------------------------------------------------------------------------------------------------------------------------+
+; Multicorner Timing Analysis Summary ;
++-----------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+
+; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
++-----------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+
+; Worst-case Slack ; 6.283 ; 0.152 ; N/A ; N/A ; 1.666 ;
+; CLOCK_50 ; N/A ; N/A ; N/A ; N/A ; 9.286 ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 1.666 ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 6.283 ; 0.152 ; N/A ; N/A ; 8.754 ;
+; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
+; CLOCK_50 ; N/A ; N/A ; N/A ; N/A ; 0.000 ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 0.000 ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ;
++-----------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------+
+; Setup Times ;
++-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+
+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+
+; KEY[*] ; CLOCK_50 ; 3.956 ; 4.889 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[0] ; CLOCK_50 ; 0.749 ; 1.459 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[1] ; CLOCK_50 ; -0.289 ; 0.848 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[2] ; CLOCK_50 ; 0.409 ; 1.780 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[3] ; CLOCK_50 ; 3.956 ; 4.889 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[*] ; CLOCK_50 ; 6.646 ; 8.100 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[0] ; CLOCK_50 ; -0.177 ; 1.068 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[1] ; CLOCK_50 ; -0.051 ; 0.854 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[2] ; CLOCK_50 ; 0.178 ; 1.528 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[3] ; CLOCK_50 ; -0.514 ; 0.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[4] ; CLOCK_50 ; 0.742 ; 1.992 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[5] ; CLOCK_50 ; 0.148 ; 1.665 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[6] ; CLOCK_50 ; 3.266 ; 4.577 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[7] ; CLOCK_50 ; 6.646 ; 8.100 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[8] ; CLOCK_50 ; 3.455 ; 4.402 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[9] ; CLOCK_50 ; 1.437 ; 2.413 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
++-----------+------------+--------+-------+------------+----------------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------+
@@ -1319,22 +1343,22 @@ Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
-; KEY[*] ; CLOCK_50 ; 4.379 ; 3.793 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[0] ; CLOCK_50 ; 3.381 ; 2.697 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[1] ; CLOCK_50 ; 3.217 ; 2.374 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[2] ; CLOCK_50 ; 3.644 ; 2.916 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; KEY[3] ; CLOCK_50 ; 4.379 ; 3.793 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[*] ; CLOCK_50 ; 3.685 ; 3.161 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[0] ; CLOCK_50 ; 1.617 ; 1.188 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[1] ; CLOCK_50 ; 2.455 ; 1.832 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[2] ; CLOCK_50 ; 3.152 ; 2.520 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[3] ; CLOCK_50 ; 3.415 ; 2.830 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[4] ; CLOCK_50 ; 3.069 ; 2.508 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[5] ; CLOCK_50 ; 3.685 ; 3.161 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[6] ; CLOCK_50 ; 2.788 ; 2.146 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[7] ; CLOCK_50 ; 3.171 ; 2.543 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[8] ; CLOCK_50 ; 3.327 ; 2.721 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; SW[9] ; CLOCK_50 ; 3.589 ; 2.995 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[*] ; CLOCK_50 ; 4.017 ; 3.307 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[0] ; CLOCK_50 ; 3.636 ; 2.928 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[1] ; CLOCK_50 ; 3.984 ; 3.254 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[2] ; CLOCK_50 ; 3.517 ; 2.561 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; KEY[3] ; CLOCK_50 ; 4.017 ; 3.307 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[*] ; CLOCK_50 ; 3.445 ; 2.873 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[0] ; CLOCK_50 ; 2.585 ; 1.816 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[1] ; CLOCK_50 ; 2.337 ; 1.735 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[2] ; CLOCK_50 ; 3.054 ; 2.366 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[3] ; CLOCK_50 ; 3.428 ; 2.873 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[4] ; CLOCK_50 ; 2.629 ; 1.830 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[5] ; CLOCK_50 ; 2.740 ; 1.851 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[6] ; CLOCK_50 ; 2.765 ; 1.949 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[7] ; CLOCK_50 ; 2.739 ; 1.923 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[8] ; CLOCK_50 ; 3.208 ; 2.624 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; SW[9] ; CLOCK_50 ; 3.445 ; 2.817 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
@@ -1343,57 +1367,60 @@ Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
-; HEX0[*] ; CLOCK_50 ; 14.191 ; 13.318 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[0] ; CLOCK_50 ; 14.002 ; 13.202 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[1] ; CLOCK_50 ; 13.120 ; 12.618 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[2] ; CLOCK_50 ; 13.313 ; 12.753 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[3] ; CLOCK_50 ; 13.693 ; 13.119 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[4] ; CLOCK_50 ; 13.759 ; 12.974 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[5] ; CLOCK_50 ; 12.800 ; 12.470 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[6] ; CLOCK_50 ; 14.191 ; 13.318 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[*] ; CLOCK_50 ; 14.089 ; 13.259 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[0] ; CLOCK_50 ; 14.089 ; 13.259 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[1] ; CLOCK_50 ; 12.430 ; 12.213 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[2] ; CLOCK_50 ; 11.957 ; 11.913 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[3] ; CLOCK_50 ; 12.990 ; 12.479 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[4] ; CLOCK_50 ; 13.273 ; 12.643 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[5] ; CLOCK_50 ; 13.295 ; 12.675 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[6] ; CLOCK_50 ; 12.618 ; 12.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[*] ; CLOCK_50 ; 14.089 ; 13.234 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[0] ; CLOCK_50 ; 13.457 ; 12.840 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[1] ; CLOCK_50 ; 13.921 ; 13.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[2] ; CLOCK_50 ; 12.588 ; 12.366 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[3] ; CLOCK_50 ; 12.623 ; 12.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[4] ; CLOCK_50 ; 13.284 ; 12.846 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[5] ; CLOCK_50 ; 13.455 ; 12.789 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[6] ; CLOCK_50 ; 14.089 ; 13.234 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[*] ; CLOCK_50 ; 13.619 ; 12.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[0] ; CLOCK_50 ; 12.868 ; 12.384 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[1] ; CLOCK_50 ; 13.020 ; 12.465 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[2] ; CLOCK_50 ; 13.619 ; 12.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[3] ; CLOCK_50 ; 13.452 ; 12.942 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[4] ; CLOCK_50 ; 13.575 ; 12.892 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[5] ; CLOCK_50 ; 13.547 ; 12.847 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[6] ; CLOCK_50 ; 12.700 ; 12.379 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[*] ; CLOCK_50 ; 13.903 ; 13.093 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[0] ; CLOCK_50 ; 13.197 ; 12.664 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[1] ; CLOCK_50 ; 13.581 ; 12.835 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[2] ; CLOCK_50 ; 13.297 ; 12.673 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[3] ; CLOCK_50 ; 13.903 ; 13.093 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[4] ; CLOCK_50 ; 12.741 ; 12.370 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[5] ; CLOCK_50 ; 12.477 ; 12.232 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[6] ; CLOCK_50 ; 12.414 ; 12.191 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[*] ; CLOCK_50 ; 13.948 ; 13.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[0] ; CLOCK_50 ; 13.425 ; 12.769 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[1] ; CLOCK_50 ; 13.810 ; 13.023 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[2] ; CLOCK_50 ; 13.826 ; 13.140 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[3] ; CLOCK_50 ; 12.646 ; 12.467 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[4] ; CLOCK_50 ; 13.948 ; 13.129 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[5] ; CLOCK_50 ; 13.937 ; 13.102 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[6] ; CLOCK_50 ; 12.793 ; 12.471 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[*] ; CLOCK_50 ; 12.801 ; 12.941 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[0] ; CLOCK_50 ; 12.801 ; 12.941 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[2] ; CLOCK_50 ; 12.782 ; 12.899 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[*] ; CLOCK_50 ; 15.059 ; 14.406 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[5] ; CLOCK_50 ; 15.059 ; 14.406 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[*] ; CLOCK_50 ; 14.377 ; 13.668 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[0] ; CLOCK_50 ; 13.924 ; 13.135 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[1] ; CLOCK_50 ; 13.877 ; 13.309 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[2] ; CLOCK_50 ; 14.377 ; 13.668 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[3] ; CLOCK_50 ; 13.254 ; 12.755 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[4] ; CLOCK_50 ; 13.655 ; 12.939 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[5] ; CLOCK_50 ; 13.136 ; 12.696 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[6] ; CLOCK_50 ; 13.930 ; 13.174 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[*] ; CLOCK_50 ; 14.179 ; 13.351 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[0] ; CLOCK_50 ; 14.179 ; 13.351 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[1] ; CLOCK_50 ; 13.068 ; 12.675 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[2] ; CLOCK_50 ; 12.656 ; 12.367 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[3] ; CLOCK_50 ; 13.466 ; 12.812 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[4] ; CLOCK_50 ; 13.639 ; 12.968 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[5] ; CLOCK_50 ; 13.314 ; 12.690 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[6] ; CLOCK_50 ; 12.764 ; 12.473 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[*] ; CLOCK_50 ; 13.962 ; 13.190 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[0] ; CLOCK_50 ; 13.962 ; 13.190 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[1] ; CLOCK_50 ; 13.269 ; 12.839 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[2] ; CLOCK_50 ; 12.436 ; 12.119 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[3] ; CLOCK_50 ; 12.962 ; 12.415 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[4] ; CLOCK_50 ; 13.020 ; 12.469 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[5] ; CLOCK_50 ; 12.796 ; 12.311 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[6] ; CLOCK_50 ; 13.077 ; 12.512 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[*] ; CLOCK_50 ; 14.812 ; 13.774 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[0] ; CLOCK_50 ; 14.812 ; 13.774 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[1] ; CLOCK_50 ; 12.857 ; 12.448 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[2] ; CLOCK_50 ; 13.202 ; 12.788 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[3] ; CLOCK_50 ; 13.760 ; 13.041 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[4] ; CLOCK_50 ; 12.467 ; 12.153 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[5] ; CLOCK_50 ; 12.285 ; 12.154 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[6] ; CLOCK_50 ; 12.442 ; 12.275 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[*] ; CLOCK_50 ; 15.196 ; 14.040 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[0] ; CLOCK_50 ; 13.287 ; 12.753 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[1] ; CLOCK_50 ; 14.189 ; 13.490 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[2] ; CLOCK_50 ; 15.196 ; 14.040 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[3] ; CLOCK_50 ; 13.362 ; 12.746 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[4] ; CLOCK_50 ; 13.473 ; 12.864 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[5] ; CLOCK_50 ; 12.757 ; 12.406 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[6] ; CLOCK_50 ; 12.865 ; 12.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[*] ; CLOCK_50 ; 14.045 ; 13.226 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[0] ; CLOCK_50 ; 13.664 ; 13.138 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[1] ; CLOCK_50 ; 12.918 ; 12.369 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[2] ; CLOCK_50 ; 12.906 ; 12.632 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[3] ; CLOCK_50 ; 12.924 ; 12.427 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[4] ; CLOCK_50 ; 13.299 ; 12.697 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[5] ; CLOCK_50 ; 12.797 ; 12.286 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[6] ; CLOCK_50 ; 14.045 ; 13.226 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[*] ; CLOCK_50 ; 14.456 ; 15.165 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[0] ; CLOCK_50 ; 14.357 ; 15.010 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[1] ; CLOCK_50 ; 14.456 ; 15.165 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[2] ; CLOCK_50 ; 14.011 ; 14.549 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+--------+--------+------------+----------------------------------------------------------------------------+
@@ -1402,57 +1429,60 @@ Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
-; HEX0[*] ; CLOCK_50 ; 6.692 ; 6.455 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[0] ; CLOCK_50 ; 7.398 ; 6.973 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[1] ; CLOCK_50 ; 6.848 ; 6.542 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[2] ; CLOCK_50 ; 7.003 ; 6.660 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[3] ; CLOCK_50 ; 7.320 ; 6.923 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[4] ; CLOCK_50 ; 7.230 ; 6.829 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[5] ; CLOCK_50 ; 6.692 ; 6.455 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX0[6] ; CLOCK_50 ; 7.543 ; 7.077 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[*] ; CLOCK_50 ; 6.210 ; 6.134 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[0] ; CLOCK_50 ; 7.449 ; 6.992 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[1] ; CLOCK_50 ; 6.460 ; 6.290 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[2] ; CLOCK_50 ; 6.210 ; 6.134 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[3] ; CLOCK_50 ; 6.782 ; 6.534 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[4] ; CLOCK_50 ; 6.930 ; 6.612 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[5] ; CLOCK_50 ; 6.938 ; 6.611 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX1[6] ; CLOCK_50 ; 6.566 ; 6.430 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[*] ; CLOCK_50 ; 6.550 ; 6.360 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[0] ; CLOCK_50 ; 7.134 ; 6.783 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[1] ; CLOCK_50 ; 7.369 ; 6.940 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[2] ; CLOCK_50 ; 6.550 ; 6.360 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[3] ; CLOCK_50 ; 6.644 ; 6.461 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[4] ; CLOCK_50 ; 7.014 ; 6.709 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[5] ; CLOCK_50 ; 7.070 ; 6.731 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX2[6] ; CLOCK_50 ; 7.408 ; 6.955 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[*] ; CLOCK_50 ; 6.699 ; 6.443 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[0] ; CLOCK_50 ; 6.706 ; 6.472 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[1] ; CLOCK_50 ; 6.807 ; 6.539 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[2] ; CLOCK_50 ; 7.230 ; 6.845 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[3] ; CLOCK_50 ; 7.198 ; 6.857 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[4] ; CLOCK_50 ; 7.123 ; 6.744 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[5] ; CLOCK_50 ; 7.125 ; 6.749 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX3[6] ; CLOCK_50 ; 6.699 ; 6.443 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[*] ; CLOCK_50 ; 6.508 ; 6.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[0] ; CLOCK_50 ; 6.949 ; 6.629 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[1] ; CLOCK_50 ; 7.158 ; 6.787 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[2] ; CLOCK_50 ; 6.943 ; 6.617 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[3] ; CLOCK_50 ; 7.374 ; 6.948 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[4] ; CLOCK_50 ; 6.627 ; 6.409 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[5] ; CLOCK_50 ; 6.533 ; 6.364 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX4[6] ; CLOCK_50 ; 6.508 ; 6.341 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[*] ; CLOCK_50 ; 6.580 ; 6.437 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[0] ; CLOCK_50 ; 7.059 ; 6.723 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[1] ; CLOCK_50 ; 7.263 ; 6.853 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[2] ; CLOCK_50 ; 7.287 ; 6.903 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[3] ; CLOCK_50 ; 6.580 ; 6.437 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[4] ; CLOCK_50 ; 7.404 ; 6.962 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[5] ; CLOCK_50 ; 7.388 ; 6.951 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; HEX5[6] ; CLOCK_50 ; 6.741 ; 6.509 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[*] ; CLOCK_50 ; 6.046 ; 6.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[0] ; CLOCK_50 ; 6.068 ; 6.158 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
-; LEDR[2] ; CLOCK_50 ; 6.046 ; 6.124 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[*] ; CLOCK_50 ; 7.479 ; 7.046 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; GPIO[5] ; CLOCK_50 ; 7.479 ; 7.046 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[*] ; CLOCK_50 ; 6.818 ; 6.548 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[0] ; CLOCK_50 ; 7.382 ; 6.938 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[1] ; CLOCK_50 ; 7.292 ; 6.927 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[2] ; CLOCK_50 ; 7.685 ; 7.214 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[3] ; CLOCK_50 ; 6.899 ; 6.593 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[4] ; CLOCK_50 ; 7.179 ; 6.786 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[5] ; CLOCK_50 ; 6.818 ; 6.548 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX0[6] ; CLOCK_50 ; 7.334 ; 6.899 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[*] ; CLOCK_50 ; 6.532 ; 6.344 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[0] ; CLOCK_50 ; 7.490 ; 7.022 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[1] ; CLOCK_50 ; 6.789 ; 6.528 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[2] ; CLOCK_50 ; 6.532 ; 6.344 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[3] ; CLOCK_50 ; 7.056 ; 6.715 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[4] ; CLOCK_50 ; 7.201 ; 6.825 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[5] ; CLOCK_50 ; 6.999 ; 6.667 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX1[6] ; CLOCK_50 ; 6.614 ; 6.419 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[*] ; CLOCK_50 ; 6.454 ; 6.251 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[0] ; CLOCK_50 ; 7.379 ; 6.938 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[1] ; CLOCK_50 ; 6.987 ; 6.705 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[2] ; CLOCK_50 ; 6.454 ; 6.251 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[3] ; CLOCK_50 ; 6.769 ; 6.493 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[4] ; CLOCK_50 ; 6.810 ; 6.528 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[5] ; CLOCK_50 ; 6.661 ; 6.417 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX2[6] ; CLOCK_50 ; 6.849 ; 6.558 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[*] ; CLOCK_50 ; 6.375 ; 6.237 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[0] ; CLOCK_50 ; 7.885 ; 7.345 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[1] ; CLOCK_50 ; 6.715 ; 6.443 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[2] ; CLOCK_50 ; 7.002 ; 6.661 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[3] ; CLOCK_50 ; 7.220 ; 6.822 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[4] ; CLOCK_50 ; 6.468 ; 6.261 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[5] ; CLOCK_50 ; 6.375 ; 6.237 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX3[6] ; CLOCK_50 ; 6.430 ; 6.255 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[*] ; CLOCK_50 ; 6.676 ; 6.446 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[0] ; CLOCK_50 ; 7.049 ; 6.692 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[1] ; CLOCK_50 ; 7.564 ; 7.135 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[2] ; CLOCK_50 ; 8.108 ; 7.502 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[3] ; CLOCK_50 ; 6.949 ; 6.622 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[4] ; CLOCK_50 ; 7.042 ; 6.721 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[5] ; CLOCK_50 ; 6.676 ; 6.452 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX4[6] ; CLOCK_50 ; 6.712 ; 6.446 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[*] ; CLOCK_50 ; 6.672 ; 6.414 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[0] ; CLOCK_50 ; 7.242 ; 6.917 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[1] ; CLOCK_50 ; 6.720 ; 6.445 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[2] ; CLOCK_50 ; 6.715 ; 6.529 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[3] ; CLOCK_50 ; 6.720 ; 6.471 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[4] ; CLOCK_50 ; 6.907 ; 6.605 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[5] ; CLOCK_50 ; 6.672 ; 6.414 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; HEX5[6] ; CLOCK_50 ; 7.455 ; 6.982 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[*] ; CLOCK_50 ; 6.797 ; 7.163 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[0] ; CLOCK_50 ; 6.975 ; 7.411 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[1] ; CLOCK_50 ; 7.154 ; 7.632 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+; LEDR[2] ; CLOCK_50 ; 6.797 ; 7.163 ; Rise ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ;
+-----------+------------+-------+-------+------------+----------------------------------------------------------------------------+
@@ -2461,7 +2491,7 @@ Synchronizer Chain #1: Worst-Case MTBF is Greater than 1 Billion Years
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 47863402 ; 0 ; 0 ; 0 ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 47578879 ; 0 ; 0 ; 0 ;
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@@ -2471,7 +2501,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+
-; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 47863402 ; 0 ; 0 ; 0 ;
+; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; 47578879 ; 0 ; 0 ; 0 ;
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@@ -2496,9 +2526,9 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 14 ; 14 ;
-; Unconstrained Input Port Paths ; 351 ; 351 ;
-; Unconstrained Output Ports ; 44 ; 44 ;
-; Unconstrained Output Port Paths ; 44 ; 44 ;
+; Unconstrained Input Port Paths ; 420 ; 420 ;
+; Unconstrained Output Ports ; 46 ; 46 ;
+; Unconstrained Output Port Paths ; 46 ; 46 ;
+---------------------------------+-------+------+
@@ -2512,7 +2542,7 @@ Warning (125092): Tcl Script File alu/add_sub_s.qip not found
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Full Version
- Info: Processing started: Sat Aug 28 10:56:13 2021
+ Info: Processing started: Sat Aug 28 16:28:47 2021
Info: Command: quartus_sta de1_riscv -c de1_riscv
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
@@ -2543,7 +2573,7 @@ Warning (332049): Ignored set_output_delay at de1_riscv.sdc(34): Argument is an empty collection
@@ -2661,23 +2691,21 @@ Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQue
Warning (332061): Virtual clock clk_core is never referenced in any input or output delay assignment.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1100mV 85C Model
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.197
+Info (332146): Worst-case setup slack is 6.342
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
- Info (332119): -1.197 -95.783 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
-Info (332146): Worst-case hold slack is 0.266
+ Info (332119): 6.342 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
+Info (332146): Worst-case hold slack is 0.271
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
- Info (332119): 0.266 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
+ Info (332119): 0.271 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 1.666
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 1.666 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]
- Info (332119): 3.775 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
+ Info (332119): 8.772 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
Info (332119): 9.670 0.000 CLOCK_50
Info (332114): Report Metastability: Found 1 synchronizer chains.
Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
@@ -2686,7 +2714,7 @@ Info (332114): Report Metastability: Found 1 synchronizer chains.
Info (332114): Number of Synchronizer Chains Found: 1
Info (332114): Shortest Synchronizer Chain: 2 Registers
Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
- Info (332114): Worst Case Available Settling Time: 17.536 ns
+ Info (332114): Worst Case Available Settling Time: 37.358 ns
Info (332114):
Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 79.4
@@ -2805,23 +2833,21 @@ Info (332097): The following timing edges are non-unate. TimeQuest will assume
Info (332098): From: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a6~FITTER_CREATED_MLAB_CELL0CLKMUX_0 to: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a6~FITTER_CREATED_MLAB_CELL0MEMORYREGOUT
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Warning (332061): Virtual clock clk_core is never referenced in any input or output delay assignment.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -1.352
+Info (332146): Worst-case setup slack is 6.283
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
- Info (332119): -1.352 -121.670 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
-Info (332146): Worst-case hold slack is 0.247
+ Info (332119): 6.283 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
+Info (332146): Worst-case hold slack is 0.256
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
- Info (332119): 0.247 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
+ Info (332119): 0.256 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 1.666
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 1.666 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]
- Info (332119): 3.758 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
+ Info (332119): 8.754 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
Info (332119): 9.673 0.000 CLOCK_50
Info (332114): Report Metastability: Found 1 synchronizer chains.
Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
@@ -2830,7 +2856,7 @@ Info (332114): Report Metastability: Found 1 synchronizer chains.
Info (332114): Number of Synchronizer Chains Found: 1
Info (332114): Shortest Synchronizer Chain: 2 Registers
Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
- Info (332114): Worst Case Available Settling Time: 17.571 ns
+ Info (332114): Worst Case Available Settling Time: 37.423 ns
Info (332114):
Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 5.2
@@ -2949,21 +2975,21 @@ Info (332097): The following timing edges are non-unate. TimeQuest will assume
Info (332098): From: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a6~FITTER_CREATED_MLAB_CELL0CLKMUX_0 to: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a6~FITTER_CREATED_MLAB_CELL0MEMORYREGOUT
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Warning (332061): Virtual clock clk_core is never referenced in any input or output delay assignment.
-Info (332146): Worst-case setup slack is 3.503
+Info (332146): Worst-case setup slack is 11.576
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
- Info (332119): 3.503 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
-Info (332146): Worst-case hold slack is 0.154
+ Info (332119): 11.576 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
+Info (332146): Worst-case hold slack is 0.162
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
- Info (332119): 0.154 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
+ Info (332119): 0.162 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 1.666
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 1.666 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]
- Info (332119): 3.888 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
+ Info (332119): 8.890 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
Info (332119): 9.336 0.000 CLOCK_50
Info (332114): Report Metastability: Found 1 synchronizer chains.
Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
@@ -2972,7 +2998,7 @@ Info (332114): Report Metastability: Found 1 synchronizer chains.
Info (332114): Number of Synchronizer Chains Found: 1
Info (332114): Shortest Synchronizer Chain: 2 Registers
Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
- Info (332114): Worst Case Available Settling Time: 18.511 ns
+ Info (332114): Worst Case Available Settling Time: 38.447 ns
Info (332114):
Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 79.4
@@ -3088,21 +3114,21 @@ Info (332097): The following timing edges are non-unate. TimeQuest will assume
Info (332098): From: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a6~FITTER_CREATED_MLAB_CELL0CLKMUX_0 to: riscv_core:core|div_s:divs|lpm_divide:LPM_DIVIDE_component|lpm_divide_s4t:auto_generated|sign_div_unsign_2sh:divider|altshift_taps:DFF_Num_Sign_rtl_0|shift_taps_7l21:auto_generated|altsyncram_kr91:altsyncram5|ram_block6a6~FITTER_CREATED_MLAB_CELL0MEMORYREGOUT
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Warning (332061): Virtual clock clk_core is never referenced in any input or output delay assignment.
-Info (332146): Worst-case setup slack is 3.812
+Info (332146): Worst-case setup slack is 12.162
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
- Info (332119): 3.812 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
-Info (332146): Worst-case hold slack is 0.141
+ Info (332119): 12.162 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
+Info (332146): Worst-case hold slack is 0.152
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
- Info (332119): 0.141 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
+ Info (332119): 0.152 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 1.666
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 1.666 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]
- Info (332119): 3.888 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
+ Info (332119): 8.891 0.000 clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
Info (332119): 9.286 0.000 CLOCK_50
Info (332114): Report Metastability: Found 1 synchronizer chains.
Info (332114): Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds.
@@ -3111,7 +3137,7 @@ Info (332114): Report Metastability: Found 1 synchronizer chains.
Info (332114): Number of Synchronizer Chains Found: 1
Info (332114): Shortest Synchronizer Chain: 2 Registers
Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 0.000
- Info (332114): Worst Case Available Settling Time: 18.610 ns
+ Info (332114): Worst Case Available Settling Time: 38.555 ns
Info (332114):
Info (332114): Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions.
Info (332114): - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 5.2
@@ -3119,9 +3145,9 @@ Info (332114): Report Metastability: Found 1 synchronizer chains.
Info (332114): - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 17.8
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 27 warnings
- Info: Peak virtual memory: 1136 megabytes
- Info: Processing ended: Sat Aug 28 10:56:45 2021
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 25 warnings
+ Info: Peak virtual memory: 1126 megabytes
+ Info: Processing ended: Sat Aug 28 16:29:19 2021
Info: Elapsed time: 00:00:32
Info: Total CPU time (on all processors): 00:00:42
diff --git a/examples/hdl4se_riscv/de1/de1_riscv.sta.summary b/examples/hdl4se_riscv/de1/de1_riscv.sta.summary
index f5e166bb9a68cf5b31d0993865190969c79f07fb..e764b8f9047325aa3b9734baeeac1847d86d8ca7 100644
--- a/examples/hdl4se_riscv/de1/de1_riscv.sta.summary
+++ b/examples/hdl4se_riscv/de1/de1_riscv.sta.summary
@@ -3,11 +3,11 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
-Slack : -1.197
-TNS : -95.783
+Slack : 6.342
+TNS : 0.000
Type : Slow 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
-Slack : 0.266
+Slack : 0.271
TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
@@ -15,7 +15,7 @@ Slack : 1.666
TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
-Slack : 3.775
+Slack : 8.772
TNS : 0.000
Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
@@ -23,11 +23,11 @@ Slack : 9.670
TNS : 0.000
Type : Slow 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
-Slack : -1.352
-TNS : -121.670
+Slack : 6.283
+TNS : 0.000
Type : Slow 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
-Slack : 0.247
+Slack : 0.256
TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
@@ -35,7 +35,7 @@ Slack : 1.666
TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
-Slack : 3.758
+Slack : 8.754
TNS : 0.000
Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
@@ -43,11 +43,11 @@ Slack : 9.673
TNS : 0.000
Type : Fast 1100mV 85C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
-Slack : 3.503
+Slack : 11.576
TNS : 0.000
Type : Fast 1100mV 85C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
-Slack : 0.154
+Slack : 0.162
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
@@ -55,7 +55,7 @@ Slack : 1.666
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
-Slack : 3.888
+Slack : 8.890
TNS : 0.000
Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
@@ -63,11 +63,11 @@ Slack : 9.336
TNS : 0.000
Type : Fast 1100mV 0C Model Setup 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
-Slack : 3.812
+Slack : 12.162
TNS : 0.000
Type : Fast 1100mV 0C Model Hold 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
-Slack : 0.141
+Slack : 0.152
TNS : 0.000
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]'
@@ -75,7 +75,7 @@ Slack : 1.666
TNS : 0.000
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clk100|clk100m_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk'
-Slack : 3.888
+Slack : 8.891
TNS : 0.000
Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
diff --git a/examples/hdl4se_riscv/de1/de1_riscv.v b/examples/hdl4se_riscv/de1/de1_riscv_0.v
similarity index 100%
rename from examples/hdl4se_riscv/de1/de1_riscv.v
rename to examples/hdl4se_riscv/de1/de1_riscv_0.v
diff --git a/examples/hdl4se_riscv/de1/de1_riscv_v2.v b/examples/hdl4se_riscv/de1/de1_riscv_v2.v
index 901b54b3f0da88eb758c73b43bd1a264ae7bfe18..f3c6c1191b95c0d1888b44a8811241fc05048062 100644
--- a/examples/hdl4se_riscv/de1/de1_riscv_v2.v
+++ b/examples/hdl4se_riscv/de1/de1_riscv_v2.v
@@ -136,9 +136,9 @@ module de1_riscv(
end
assign bReadData =
- ((bReadAddr_out & 32'hffffff00) == 32'hf0000000) ? bReadDataKey : (
+ ((bReadAddr_out & 32'hffffff00) == 32'hF0000000) ? bReadDataKey : (
((bReadAddr_out & 32'hffffc000) == 32'h00000000) ? bReadDataRam : (
- ((bReadAddr_out & 32'hffffff00) == 32'h00000100) ? bReadDataUart : (0)
+ ((bReadAddr_out & 32'hffffff00) == 32'hF0000100) ? bReadDataUart : (0)
)
);
@@ -150,12 +150,13 @@ module de1_riscv(
wire [31:0] regwrdata;
wire regwren;
wire [31:0] regrddata;
- wire [2:0] uartaddr;
- assign uartaddr = wWrite?bWriteAddr[4:2]:bReadAddr[4:2];
+/*
+ wire [31:0] uartaddr;
+ assign uartaddr = wWrite?bWriteAddr:bReadAddr;
altera_uart uart(
// inputs:
- .address(uartaddr),
- .begintransfer(SW[0]),
+ .address(uartaddr[4:2]),
+ .begintransfer(1'b1),
.chipselect((uartaddr & 32'hffffff00)==32'hf0000100),
.clk(wClk),
.read_n(~wRead),
@@ -171,6 +172,17 @@ module de1_riscv(
.readyfordata(LEDR[2]),
.txd(uart_tx)
);
+*/
+ uart_ctrl uart_ctrl(
+ wClk, nwReset,
+ ((bReadAddr & 32'hffffff00) == 32'hf0000100)?wRead:1'b0,
+ bReadAddr,
+ ((bWriteAddr & 32'hffffff00) == 32'hf0000100)?wWrite:1'b0,
+ bWriteAddr,
+ bWriteData,
+ bReadDataUart,
+ uart_tx, uart_rx
+ );
regfile regs(regno, regena, wClk, regwrdata, regwren, regrddata);
ram8kb ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hffffc000) == 0)?wWrite:1'b0, bReadDataRam);
diff --git a/examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml b/examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml
index 67f454926a64b3326025bf50e8a891475a5f0748..7eaf28c114f6415eec07a8ea2eca8f923b0f06cd 100644
--- a/examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml
+++ b/examples/hdl4se_riscv/de1/qsys/.qsys_edit/preferences.xml
@@ -16,5 +16,5 @@
+ expandedCategories="Project,Library/Interface Protocols,Library,Library/Interface Protocols/Serial" />
diff --git a/examples/hdl4se_riscv/de1/test.mif b/examples/hdl4se_riscv/de1/test.mif
index 3be96950ece943e9459b06ef4c134168fddde473..2f067adf03b9a5bb7becf603930eeeb5a470668e 100644
--- a/examples/hdl4se_riscv/de1/test.mif
+++ b/examples/hdl4se_riscv/de1/test.mif
@@ -36,31 +36,31 @@ BEGIN
001D : 00000793;
001E : 00078863;
001F : 00001537;
-0020 : B7850513;
-0021 : 3510006F;
+0020 : C1C50513;
+0021 : 3F50006F;
0022 : 00008067;
0023 : 00001197;
0024 : 7AC18193;
-0025 : C4418513;
-0026 : C6018613;
+0025 : C3418513;
+0026 : C5018613;
0027 : 40A60633;
0028 : 00000593;
-0029 : 0D9000EF;
+0029 : 17D000EF;
002A : 00001517;
-002B : B2C50513;
+002B : BD050513;
002C : 00050863;
002D : 00001517;
-002E : AC450513;
-002F : 319000EF;
-0030 : 021000EF;
+002E : B6850513;
+002F : 3BD000EF;
+0030 : 0C5000EF;
0031 : 00012503;
0032 : 00410593;
0033 : 00000613;
0034 : 0AC000EF;
-0035 : 7DC0006F;
+0035 : 0810006F;
0036 : FF010113;
0037 : 00812423;
-0038 : C441C783;
+0038 : C341C783;
0039 : 00112623;
003A : 02079263;
003B : 00000793;
@@ -70,7 +70,7 @@ BEGIN
003F : 00000097;
0040 : 000000E7;
0041 : 00100793;
-0042 : C4F18223;
+0042 : C2F18A23;
0043 : 00C12083;
0044 : 00812403;
0045 : 01010113;
@@ -78,7 +78,7 @@ BEGIN
0047 : 00000793;
0048 : 00078C63;
0049 : 00001537;
-004A : C4818593;
+004A : C3818593;
004B : 00050513;
004C : 00000317;
004D : 00000067;
@@ -90,8 +90,8 @@ BEGIN
0053 : FEC42703;
0054 : 00A00793;
0055 : 02F777B3;
-0056 : 00001717;
-0057 : 31472703;
+0056 : 00001737;
+0057 : D5C70713;
0058 : 00279793;
0059 : 00F707B3;
005A : 0007A783;
@@ -99,13 +99,13 @@ BEGIN
005C : 01C12403;
005D : 02010113;
005E : 00008067;
-005F : FC010113;
-0060 : 02112E23;
-0061 : 02812C23;
-0062 : 02912A23;
-0063 : 04010413;
-0064 : FCA42623;
-0065 : FCB42423;
+005F : FB010113;
+0060 : 04112623;
+0061 : 04812423;
+0062 : 04912223;
+0063 : 05010413;
+0064 : FAA42E23;
+0065 : FAB42C23;
0066 : 00100793;
0067 : FEF42223;
0068 : F00007B7;
@@ -113,827 +113,827 @@ BEGIN
006A : F00007B7;
006B : 01078793;
006C : FCF42E23;
-006D : 00000793;
-006E : 00000813;
-006F : FEF42423;
-0070 : FF042623;
-0071 : FDC42783;
-0072 : 6F7F0737;
-0073 : 77D70713;
-0074 : 00E7A023;
-0075 : FDC42783;
-0076 : 00478793;
-0077 : 6D665737;
-0078 : F5B70713;
-0079 : 00E7A023;
-007A : FE842603;
-007B : FEC42683;
-007C : 00100513;
-007D : 00000593;
-007E : 00A60733;
-007F : 00070813;
-0080 : 00C83833;
-0081 : 00B687B3;
-0082 : 00F806B3;
-0083 : 00068793;
-0084 : FEE42423;
-0085 : FEF42623;
-0086 : FE842703;
-0087 : FEC42783;
-0088 : FCE42823;
-0089 : FCF42A23;
-008A : FD042783;
-008B : 00078513;
-008C : F0DFF0EF;
-008D : 00050493;
-008E : FD042703;
-008F : FD442783;
-0090 : 00A00613;
-0091 : 00000693;
-0092 : 00070513;
-0093 : 00078593;
-0094 : 230000EF;
-0095 : 00050713;
-0096 : 00058793;
-0097 : 00070793;
-0098 : 00078513;
-0099 : ED9FF0EF;
-009A : 00050793;
-009B : 00879793;
-009C : 00F4E4B3;
-009D : FD042703;
-009E : FD442783;
-009F : 06400613;
-00A0 : 00000693;
-00A1 : 00070513;
-00A2 : 00078593;
-00A3 : 1F4000EF;
-00A4 : 00050713;
-00A5 : 00058793;
-00A6 : 00070793;
-00A7 : 00078513;
-00A8 : E9DFF0EF;
-00A9 : 00050793;
-00AA : 01079793;
-00AB : 00F4E4B3;
-00AC : FD042703;
-00AD : FD442783;
-00AE : 3E800613;
-00AF : 00000693;
-00B0 : 00070513;
-00B1 : 00078593;
-00B2 : 1B8000EF;
-00B3 : 00050713;
-00B4 : 00058793;
-00B5 : 00070793;
-00B6 : 00078513;
-00B7 : E61FF0EF;
-00B8 : 00050793;
-00B9 : 01879793;
-00BA : 00F4E733;
-00BB : FDC42783;
-00BC : 00E7A023;
-00BD : FD042703;
-00BE : FD442783;
-00BF : 00002637;
-00C0 : 71060613;
-00C1 : 00000693;
-00C2 : 00070513;
-00C3 : 00078593;
-00C4 : 170000EF;
-00C5 : 00050713;
-00C6 : 00058793;
-00C7 : FCE42823;
-00C8 : FCF42A23;
-00C9 : FD042783;
-00CA : 00078513;
-00CB : E11FF0EF;
-00CC : 00050493;
-00CD : FD042703;
-00CE : FD442783;
-00CF : 00A00613;
-00D0 : 00000693;
-00D1 : 00070513;
-00D2 : 00078593;
-00D3 : 134000EF;
-00D4 : 00050713;
-00D5 : 00058793;
-00D6 : 00070793;
-00D7 : 00078513;
-00D8 : DDDFF0EF;
-00D9 : 00050793;
-00DA : 00879793;
-00DB : 00F4E4B3;
-00DC : FD042703;
-00DD : FD442783;
-00DE : 06400613;
-00DF : 00000693;
-00E0 : 00070513;
-00E1 : 00078593;
-00E2 : 0F8000EF;
-00E3 : 00050713;
-00E4 : 00058793;
-00E5 : 00070793;
-00E6 : 00078513;
-00E7 : DA1FF0EF;
-00E8 : 00050793;
-00E9 : 01079793;
-00EA : 00F4E4B3;
-00EB : FD042703;
-00EC : FD442783;
-00ED : 3E800613;
-00EE : 00000693;
-00EF : 00070513;
-00F0 : 00078593;
-00F1 : 0BC000EF;
-00F2 : 00050713;
-00F3 : 00058793;
-00F4 : 00070793;
-00F5 : 00078513;
-00F6 : D65FF0EF;
-00F7 : 00050793;
-00F8 : 01879713;
-00F9 : FDC42783;
-00FA : 00478793;
-00FB : 00E4E733;
-00FC : 00E7A023;
-00FD : FD042703;
-00FE : FD442783;
-00FF : 00002637;
-0100 : 71060613;
-0101 : 00000693;
-0102 : 00070513;
-0103 : 00078593;
-0104 : 070000EF;
-0105 : 00050713;
-0106 : 00058793;
-0107 : FCE42823;
-0108 : FCF42A23;
-0109 : FD042783;
-010A : 00078513;
-010B : D11FF0EF;
-010C : 00050493;
-010D : FD042703;
-010E : FD442783;
-010F : 00A00613;
-0110 : 00000693;
-0111 : 00070513;
-0112 : 00078593;
-0113 : 034000EF;
-0114 : 00050713;
-0115 : 00058793;
-0116 : 00070793;
-0117 : 00078513;
-0118 : CDDFF0EF;
-0119 : 00050793;
-011A : 00879713;
-011B : FDC42783;
-011C : 00878793;
-011D : 00E4E733;
-011E : 00E7A023;
-011F : D6DFF06F;
-0120 : 00050313;
-0121 : 00058893;
-0122 : 00060713;
-0123 : 00050813;
-0124 : 00058793;
-0125 : 28069263;
-0126 : 000015B7;
-0127 : CE058593;
-0128 : 0EC8F663;
-0129 : 000106B7;
-012A : 0CD67863;
-012B : 10063693;
-012C : 0016C693;
-012D : 00369693;
-012E : 00D65533;
-012F : 00A585B3;
-0130 : 0005C583;
-0131 : 02000513;
-0132 : 00D586B3;
-0133 : 40D505B3;
-0134 : 00D50C63;
-0135 : 00B897B3;
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+03A0 : 08080808;
+03A1 : CD000000;
03A2 : CDCDCDCD;
03A3 : CDCDCDCD;
03A4 : CDCDCDCD;
@@ -1035,7 +1035,7 @@ BEGIN
0404 : 00020D1B;
0405 : 00000010;
0406 : 00000018;
-0407 : FFFFF464;
+0407 : FFFFF508;
0408 : 00000430;
0409 : 00000000;
040A : 00000000;
@@ -1308,17 +1308,17 @@ BEGIN
0515 : 00000000;
0516 : 00000000;
0517 : 00000000;
-0518 : FFFFFFFF;
+0518 : 00001038;
0519 : 00000000;
-051A : 00000000;
-051B : 00000CB8;
-051C : 00001038;
-051D : 00000000;
-051E : 00001038;
-051F : 00001038;
-0520 : 00000000;
-0521 : 00001038;
-0522 : CD000000;
+051A : 00001038;
+051B : 00001038;
+051C : 00000000;
+051D : 00001038;
+051E : CD000000;
+051F : CDCDCDCD;
+0520 : CDCDCDCD;
+0521 : CDCDCDCD;
+0522 : CDCDCDCD;
0523 : CDCDCDCD;
0524 : CDCDCDCD;
0525 : CDCDCDCD;
diff --git a/examples/hdl4se_riscv/de1/uart/uart_ctrl.v b/examples/hdl4se_riscv/de1/uart/uart_ctrl.v
new file mode 100644
index 0000000000000000000000000000000000000000..6826cb7a6f7b5b10cb3620953c00f3a67234b476
--- /dev/null
+++ b/examples/hdl4se_riscv/de1/uart/uart_ctrl.v
@@ -0,0 +1,131 @@
+
+module uart_ctrl(
+ input wClk,
+ input nwReset,
+ input wRead,
+ input [31:0] bReadAddr,
+ input wWrite,
+ input [31:0] bWriteAddr,
+ input [31:0] bWriteData,
+ output [31:0] bReadData,
+ output uart_tx,
+ input uart_rx
+ );
+
+ wire [31:0] ctl_state;
+
+ wire [7:0] send_buf_data, send_buf_q;
+ wire send_buf_full;
+ wire send_buf_empty;
+ wire [9:0] send_buf_used;
+ reg send_buf_read;
+ reg send_buf_write;
+ assign send_buf_data = bWriteData[7:0];
+ assign ctl_state[15:0] = {5'b0, send_buf_used, send_buf_full};
+
+ uart_fifo uart_send_buf(
+ .clock(wClk),
+ .data(send_buf_data),
+ .rdreq(send_buf_read),
+ .wrreq(send_buf_write),
+ .almost_full(send_buf_full),
+ .empty(send_buf_empty),
+ .full(),
+ .q(send_buf_q),
+ .usedw(send_buf_used));
+
+
+ wire [7:0] recv_buf_data, recv_buf_q;
+ wire recv_buf_empty;
+ wire recv_buf_full;
+ wire [9:0] recv_buf_used;
+ reg recv_buf_read;
+ reg recv_buf_write;
+ assign ctl_state[31:16] = {5'b0, recv_buf_used, recv_buf_empty};
+
+ uart_fifo uart_recv_buf(
+ .clock(wClk),
+ .data(recv_buf_data),
+ .rdreq(recv_buf_read),
+ .wrreq(recv_buf_write),
+ .almost_full(recv_buf_full),
+ .empty(recv_buf_empty),
+ .full(),
+ .q(recv_buf_q),
+ .usedw(recv_buf_used));
+
+ reg [2:0] uartaddr;
+ reg uart_read, uart_write;
+ reg [15:0] uart_write_data;
+ wire [15:0] uart_read_data;
+ wire uart_has_data;
+ wire uart_can_send;
+ altera_uart uart(
+ // inputs:
+ .address(uartaddr),
+ .begintransfer(1'b1),
+ .chipselect(1'b1),
+ .clk(wClk),
+ .read_n(~uart_read),
+ .reset_n(nwReset),
+ .rxd(uart_rx),
+ .write_n(uart_write),
+ .writedata(uart_write_data),
+
+ // outputs:
+ .dataavailable(uart_has_data),
+ .irq(),
+ .readdata(uart_read_data),
+ .readyfordata(uart_can_send),
+ .txd(uart_tx)
+ );
+
+ always @(posedge wClk)
+ if (~nwReset) begin
+ uart_read <= 1'b0;
+ uart_write < = 1'b0;
+ uart_addr <= 3'b0;
+ recv_buf_write <= 1'b0;
+ end else begin
+ uart_read <= 1'b0;
+ uart_write < = 1'b0;
+ uart_addr <= 3'b0;
+ recv_buf_write <= 1'b0;
+ if (uart_has_data && ~recv_buf_full) begin
+ recv_buf_write <= 1'b1;
+ recv_buf_data <=
+ end
+ end
+
+ /* ¶ÁÃüÁî´¦Àí */
+ reg [31:0] bReadData;
+ wire [1:0] readaddr = bReadAddr[3:2];
+ always @(posedge wClk)
+ if (~nwReset) begin
+ bReadData <= 32'h0;
+ recv_buf_read <= 1'b0;
+ end else begin
+ recv_buf_read <= 1'b0;
+ if (wRead) begin
+ if (readaddr == 0) begin /* state */
+ bReadData <= ctl_state;
+ end else if (readaddr == 1) begin
+ bReadData <= {24'b0, uartrecvdata};
+ recv_buf_read <= ~ctl_state[16]; /* empty */
+ end
+ end
+ end
+
+ /* дÃüÁî´¦Àí */
+ wire [1:0] writeaddr = bWriteAddr[3:2];
+ always @(posedge wClk)
+ if (~nwReset) begin
+ send_buf_write <= 1'b0;
+ end else begin
+ send_buf_write <= 1'b0;
+ if (wWrite && (writeaddr == 2)) begin
+ send_buf_write <= 1'b1;
+ end
+ end
+
+endmodule
\ No newline at end of file
diff --git a/examples/hdl4se_riscv/de1/uart/uart_fifo.qip b/examples/hdl4se_riscv/de1/uart/uart_fifo.qip
new file mode 100644
index 0000000000000000000000000000000000000000..f243d09646c10166a48bbc34f18cfc9a9ae81cc1
--- /dev/null
+++ b/examples/hdl4se_riscv/de1/uart/uart_fifo.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "FIFO"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "uart_fifo.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "uart_fifo_bb.v"]
diff --git a/examples/hdl4se_riscv/de1/uart/uart_fifo.v b/examples/hdl4se_riscv/de1/uart/uart_fifo.v
new file mode 100644
index 0000000000000000000000000000000000000000..d5251bdb7121d4c4a4cba53e8f72f9c4da378673
--- /dev/null
+++ b/examples/hdl4se_riscv/de1/uart/uart_fifo.v
@@ -0,0 +1,171 @@
+// megafunction wizard: %FIFO%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo
+
+// ============================================================
+// File Name: uart_fifo.v
+// Megafunction Name(s):
+// scfifo
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module uart_fifo (
+ clock,
+ data,
+ rdreq,
+ wrreq,
+ almost_full,
+ empty,
+ full,
+ q,
+ usedw);
+
+ input clock;
+ input [7:0] data;
+ input rdreq;
+ input wrreq;
+ output almost_full;
+ output empty;
+ output full;
+ output [7:0] q;
+ output [9:0] usedw;
+
+ wire [9:0] sub_wire0;
+ wire sub_wire1;
+ wire sub_wire2;
+ wire [7:0] sub_wire3;
+ wire sub_wire4;
+ wire [9:0] usedw = sub_wire0[9:0];
+ wire empty = sub_wire1;
+ wire full = sub_wire2;
+ wire [7:0] q = sub_wire3[7:0];
+ wire almost_full = sub_wire4;
+
+ scfifo scfifo_component (
+ .clock (clock),
+ .wrreq (wrreq),
+ .data (data),
+ .rdreq (rdreq),
+ .usedw (sub_wire0),
+ .empty (sub_wire1),
+ .full (sub_wire2),
+ .q (sub_wire3),
+ .almost_full (sub_wire4),
+ .aclr (),
+ .almost_empty (),
+ .sclr ());
+ defparam
+ scfifo_component.add_ram_output_register = "OFF",
+ scfifo_component.almost_full_value = 240,
+ scfifo_component.intended_device_family = "Cyclone V",
+ scfifo_component.lpm_numwords = 1024,
+ scfifo_component.lpm_showahead = "OFF",
+ scfifo_component.lpm_type = "scfifo",
+ scfifo_component.lpm_width = 8,
+ scfifo_component.lpm_widthu = 10,
+ scfifo_component.overflow_checking = "ON",
+ scfifo_component.underflow_checking = "ON",
+ scfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "240"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "8"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "8"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "240"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL "usedw[9..0]"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/examples/hdl4se_riscv/de1/uart/uart_fifo_bb.v b/examples/hdl4se_riscv/de1/uart/uart_fifo_bb.v
new file mode 100644
index 0000000000000000000000000000000000000000..3fe2bf020143287b620fa8b8382cb91f1d7452bc
--- /dev/null
+++ b/examples/hdl4se_riscv/de1/uart/uart_fifo_bb.v
@@ -0,0 +1,128 @@
+// megafunction wizard: %FIFO%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo
+
+// ============================================================
+// File Name: uart_fifo.v
+// Megafunction Name(s):
+// scfifo
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.0 Build 162 10/23/2013 SJ Full Version
+// ************************************************************
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+module uart_fifo (
+ clock,
+ data,
+ rdreq,
+ wrreq,
+ almost_full,
+ empty,
+ full,
+ q,
+ usedw);
+
+ input clock;
+ input [7:0] data;
+ input rdreq;
+ input wrreq;
+ output almost_full;
+ output empty;
+ output full;
+ output [7:0] q;
+ output [9:0] usedw;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "240"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "8"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+// Retrieval info: PRIVATE: output_width NUMERIC "8"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "240"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
+// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL "usedw[9..0]"
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL uart_fifo_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_ram8k.c b/examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_ram8k.c
index a0209be6fd5c0d4e4ab747796e172713add01f81..6bf1ddc60e9246312c35c09c74bbbb5aa142ca1b 100644
--- a/examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_ram8k.c
+++ b/examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_ram8k.c
@@ -144,7 +144,7 @@ static int loadExecImage(unsigned char* data, int maxlen)
unsigned int addr;
FILE* pFile = fopen(DATADIR"test_code/test.cod", "rt");
if (pFile == NULL) {
- printf("File %s can not open\n", DATADIR"test_code/test.bin");
+ printf("File %s can not open\n", DATADIR"test_code/test.cod");
exit(-1);
}
addr = 0;
diff --git a/examples/hdl4se_riscv/test_code/main_v2.c b/examples/hdl4se_riscv/test_code/main_v2.c
index f6f7bff8497cf82787e941cb6405ddd198419e0c..8032f4bafb2302b7744822cb19a15c5f4199bf2f 100644
--- a/examples/hdl4se_riscv/test_code/main_v2.c
+++ b/examples/hdl4se_riscv/test_code/main_v2.c
@@ -30,15 +30,16 @@ int main(int argc, char* argv[])
count = 0;
leddata[0] = 0x6f7f077d;
leddata[1] = 0x6d664f5b;
- uart[4] = 100000000 / 115200;/* set baudrate to 115200 */
- uart[1] = 'H';
- uart[1] = '\n';
+ //uart[4] = 100000000 / 115200;/* set baudrate to 115200 */
+ //uart[1] = 'H';
+ //uart[1] = '\n';
do {
unsigned int key;
unsigned int uartstate;
uartstate = uart[2];
if (uartstate & 0x80) { /*rrdy*/
uart[1] = uart[0]; /* writeback */
+ uart[2] = 0;
continue;
}
key = *ledkey;
diff --git a/examples/hdl4se_riscv/test_code/test.cod b/examples/hdl4se_riscv/test_code/test.cod
index 2df1edaf071f218b15c001db03163d5d9e9e3038..251fa411fade22b0c60098a5763fb73bd8049e99 100755
--- a/examples/hdl4se_riscv/test_code/test.cod
+++ b/examples/hdl4se_riscv/test_code/test.cod
@@ -1,11 +1,11 @@
@00000074
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diff --git a/examples/hdl4se_riscv/test_code/test.elf b/examples/hdl4se_riscv/test_code/test.elf
index b3a896d3af40829abf3d56c78c77b1a07a206872..8a2ae909011d85f5febfe17e39c9942094d7d4c0 100755
Binary files a/examples/hdl4se_riscv/test_code/test.elf and b/examples/hdl4se_riscv/test_code/test.elf differ
diff --git a/examples/hdl4se_riscv/test_code/test.hex b/examples/hdl4se_riscv/test_code/test.hex
index 64749331f20e593226ebd393c22fab01c455ce11..f3536ec9f2d89f4ff2c0b5579bb500d5e6469f9b 100644
--- a/examples/hdl4se_riscv/test_code/test.hex
+++ b/examples/hdl4se_riscv/test_code/test.hex
@@ -1,10 +1,10 @@
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diff --git a/examples/hdl4se_riscv/test_code/test.mif b/examples/hdl4se_riscv/test_code/test.mif
index 3be96950ece943e9459b06ef4c134168fddde473..2f067adf03b9a5bb7becf603930eeeb5a470668e 100644
--- a/examples/hdl4se_riscv/test_code/test.mif
+++ b/examples/hdl4se_riscv/test_code/test.mif
@@ -36,31 +36,31 @@ BEGIN
001D : 00000793;
001E : 00078863;
001F : 00001537;
-0020 : B7850513;
-0021 : 3510006F;
+0020 : C1C50513;
+0021 : 3F50006F;
0022 : 00008067;
0023 : 00001197;
0024 : 7AC18193;
-0025 : C4418513;
-0026 : C6018613;
+0025 : C3418513;
+0026 : C5018613;
0027 : 40A60633;
0028 : 00000593;
-0029 : 0D9000EF;
+0029 : 17D000EF;
002A : 00001517;
-002B : B2C50513;
+002B : BD050513;
002C : 00050863;
002D : 00001517;
-002E : AC450513;
-002F : 319000EF;
-0030 : 021000EF;
+002E : B6850513;
+002F : 3BD000EF;
+0030 : 0C5000EF;
0031 : 00012503;
0032 : 00410593;
0033 : 00000613;
0034 : 0AC000EF;
-0035 : 7DC0006F;
+0035 : 0810006F;
0036 : FF010113;
0037 : 00812423;
-0038 : C441C783;
+0038 : C341C783;
0039 : 00112623;
003A : 02079263;
003B : 00000793;
@@ -70,7 +70,7 @@ BEGIN
003F : 00000097;
0040 : 000000E7;
0041 : 00100793;
-0042 : C4F18223;
+0042 : C2F18A23;
0043 : 00C12083;
0044 : 00812403;
0045 : 01010113;
@@ -78,7 +78,7 @@ BEGIN
0047 : 00000793;
0048 : 00078C63;
0049 : 00001537;
-004A : C4818593;
+004A : C3818593;
004B : 00050513;
004C : 00000317;
004D : 00000067;
@@ -90,8 +90,8 @@ BEGIN
0053 : FEC42703;
0054 : 00A00793;
0055 : 02F777B3;
-0056 : 00001717;
-0057 : 31472703;
+0056 : 00001737;
+0057 : D5C70713;
0058 : 00279793;
0059 : 00F707B3;
005A : 0007A783;
@@ -99,13 +99,13 @@ BEGIN
005C : 01C12403;
005D : 02010113;
005E : 00008067;
-005F : FC010113;
-0060 : 02112E23;
-0061 : 02812C23;
-0062 : 02912A23;
-0063 : 04010413;
-0064 : FCA42623;
-0065 : FCB42423;
+005F : FB010113;
+0060 : 04112623;
+0061 : 04812423;
+0062 : 04912223;
+0063 : 05010413;
+0064 : FAA42E23;
+0065 : FAB42C23;
0066 : 00100793;
0067 : FEF42223;
0068 : F00007B7;
@@ -113,827 +113,827 @@ BEGIN
006A : F00007B7;
006B : 01078793;
006C : FCF42E23;
-006D : 00000793;
-006E : 00000813;
-006F : FEF42423;
-0070 : FF042623;
-0071 : FDC42783;
-0072 : 6F7F0737;
-0073 : 77D70713;
-0074 : 00E7A023;
-0075 : FDC42783;
-0076 : 00478793;
-0077 : 6D665737;
-0078 : F5B70713;
-0079 : 00E7A023;
-007A : FE842603;
-007B : FEC42683;
-007C : 00100513;
-007D : 00000593;
-007E : 00A60733;
-007F : 00070813;
-0080 : 00C83833;
-0081 : 00B687B3;
-0082 : 00F806B3;
-0083 : 00068793;
-0084 : FEE42423;
-0085 : FEF42623;
-0086 : FE842703;
-0087 : FEC42783;
-0088 : FCE42823;
-0089 : FCF42A23;
-008A : FD042783;
-008B : 00078513;
-008C : F0DFF0EF;
-008D : 00050493;
-008E : FD042703;
-008F : FD442783;
-0090 : 00A00613;
-0091 : 00000693;
-0092 : 00070513;
-0093 : 00078593;
-0094 : 230000EF;
-0095 : 00050713;
-0096 : 00058793;
-0097 : 00070793;
-0098 : 00078513;
-0099 : ED9FF0EF;
-009A : 00050793;
-009B : 00879793;
-009C : 00F4E4B3;
-009D : FD042703;
-009E : FD442783;
-009F : 06400613;
-00A0 : 00000693;
-00A1 : 00070513;
-00A2 : 00078593;
-00A3 : 1F4000EF;
-00A4 : 00050713;
-00A5 : 00058793;
-00A6 : 00070793;
-00A7 : 00078513;
-00A8 : E9DFF0EF;
-00A9 : 00050793;
-00AA : 01079793;
-00AB : 00F4E4B3;
-00AC : FD042703;
-00AD : FD442783;
-00AE : 3E800613;
-00AF : 00000693;
-00B0 : 00070513;
-00B1 : 00078593;
-00B2 : 1B8000EF;
-00B3 : 00050713;
-00B4 : 00058793;
-00B5 : 00070793;
-00B6 : 00078513;
-00B7 : E61FF0EF;
-00B8 : 00050793;
-00B9 : 01879793;
-00BA : 00F4E733;
-00BB : FDC42783;
-00BC : 00E7A023;
-00BD : FD042703;
-00BE : FD442783;
-00BF : 00002637;
-00C0 : 71060613;
-00C1 : 00000693;
-00C2 : 00070513;
-00C3 : 00078593;
-00C4 : 170000EF;
-00C5 : 00050713;
-00C6 : 00058793;
-00C7 : FCE42823;
-00C8 : FCF42A23;
-00C9 : FD042783;
-00CA : 00078513;
-00CB : E11FF0EF;
-00CC : 00050493;
-00CD : FD042703;
-00CE : FD442783;
-00CF : 00A00613;
-00D0 : 00000693;
-00D1 : 00070513;
-00D2 : 00078593;
-00D3 : 134000EF;
-00D4 : 00050713;
-00D5 : 00058793;
-00D6 : 00070793;
-00D7 : 00078513;
-00D8 : DDDFF0EF;
-00D9 : 00050793;
-00DA : 00879793;
-00DB : 00F4E4B3;
-00DC : FD042703;
-00DD : FD442783;
-00DE : 06400613;
-00DF : 00000693;
-00E0 : 00070513;
-00E1 : 00078593;
-00E2 : 0F8000EF;
-00E3 : 00050713;
-00E4 : 00058793;
-00E5 : 00070793;
-00E6 : 00078513;
-00E7 : DA1FF0EF;
-00E8 : 00050793;
-00E9 : 01079793;
-00EA : 00F4E4B3;
-00EB : FD042703;
-00EC : FD442783;
-00ED : 3E800613;
-00EE : 00000693;
-00EF : 00070513;
-00F0 : 00078593;
-00F1 : 0BC000EF;
-00F2 : 00050713;
-00F3 : 00058793;
-00F4 : 00070793;
-00F5 : 00078513;
-00F6 : D65FF0EF;
-00F7 : 00050793;
-00F8 : 01879713;
-00F9 : FDC42783;
-00FA : 00478793;
-00FB : 00E4E733;
-00FC : 00E7A023;
-00FD : FD042703;
-00FE : FD442783;
-00FF : 00002637;
-0100 : 71060613;
-0101 : 00000693;
-0102 : 00070513;
-0103 : 00078593;
-0104 : 070000EF;
-0105 : 00050713;
-0106 : 00058793;
-0107 : FCE42823;
-0108 : FCF42A23;
-0109 : FD042783;
-010A : 00078513;
-010B : D11FF0EF;
-010C : 00050493;
-010D : FD042703;
-010E : FD442783;
-010F : 00A00613;
-0110 : 00000693;
-0111 : 00070513;
-0112 : 00078593;
-0113 : 034000EF;
-0114 : 00050713;
-0115 : 00058793;
-0116 : 00070793;
-0117 : 00078513;
-0118 : CDDFF0EF;
-0119 : 00050793;
-011A : 00879713;
-011B : FDC42783;
-011C : 00878793;
-011D : 00E4E733;
-011E : 00E7A023;
-011F : D6DFF06F;
-0120 : 00050313;
-0121 : 00058893;
-0122 : 00060713;
-0123 : 00050813;
-0124 : 00058793;
-0125 : 28069263;
-0126 : 000015B7;
-0127 : CE058593;
-0128 : 0EC8F663;
-0129 : 000106B7;
-012A : 0CD67863;
-012B : 10063693;
-012C : 0016C693;
-012D : 00369693;
-012E : 00D65533;
-012F : 00A585B3;
-0130 : 0005C583;
-0131 : 02000513;
-0132 : 00D586B3;
-0133 : 40D505B3;
-0134 : 00D50C63;
-0135 : 00B897B3;
-0136 : 00D356B3;
-0137 : 00B61733;
-0138 : 00F6E7B3;
-0139 : 00B31833;
-013A : 01075593;
-013B : 02B7D333;
-013C : 01071613;
-013D : 01065613;
-013E : 02B7F7B3;
-013F : 00030513;
-0140 : 026608B3;
-0141 : 01079693;
-0142 : 01085793;
-0143 : 00D7E7B3;
-0144 : 0117FE63;
-0145 : 00E787B3;
-0146 : FFF30513;
-0147 : 00E7E863;
-0148 : 0117F663;
-0149 : FFE30513;
-014A : 00E787B3;
-014B : 411787B3;
-014C : 02B7D8B3;
-014D : 01081813;
-014E : 01085813;
-014F : 02B7F7B3;
-0150 : 031606B3;
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-0152 : 00F86833;
-0153 : 00088793;
-0154 : 00D87C63;
-0155 : 01070833;
-0156 : FFF88793;
-0157 : 00E86663;
-0158 : 00D87463;
-0159 : FFE88793;
-015A : 01051513;
-015B : 00F56533;
-015C : 00000593;
-015D : 00008067;
-015E : 01000537;
-015F : 01000693;
-0160 : F2A66CE3;
-0161 : 01800693;
-0162 : F31FF06F;
-0163 : 00061463;
-0164 : 00100073;
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-0166 : 0CF67063;
-0167 : 10063693;
-0168 : 0016C693;
-0169 : 00369693;
-016A : 00D657B3;
-016B : 00F585B3;
-016C : 0005C783;
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-016F : 40F685B3;
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-0178 : 0317F7B3;
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+01CA : 01071613;
+01CB : 00B898B3;
+01CC : 01065613;
+01CD : 0117E7B3;
+01CE : 02A6F6B3;
+01CF : 026608B3;
+01D0 : 01069593;
+01D1 : 0107D693;
+01D2 : 00B6E6B3;
+01D3 : 00030593;
+01D4 : 0116FE63;
+01D5 : 00E686B3;
+01D6 : FFF30593;
+01D7 : 00E6E863;
+01D8 : 0116F663;
+01D9 : FFE30593;
+01DA : 00E686B3;
+01DB : 411686B3;
+01DC : 02A6D8B3;
+01DD : 01079793;
+01DE : 0107D793;
+01DF : 02A6F6B3;
+01E0 : 03160633;
+01E1 : 01069693;
+01E2 : 00D7E7B3;
+01E3 : 00088693;
+01E4 : 00C7FE63;
+01E5 : 00E787B3;
+01E6 : FFF88693;
+01E7 : 00E7E863;
+01E8 : 00C7F663;
+01E9 : FFE88693;
+01EA : 00E787B3;
+01EB : 01059593;
+01EC : 40C787B3;
+01ED : 00D5E5B3;
+01EE : EB9FF06F;
+01EF : 18D5E663;
+01F0 : 000107B7;
+01F1 : 04F6F463;
+01F2 : 1006B713;
+01F3 : 00174713;
+01F4 : 00371713;
+01F5 : 000017B7;
+01F6 : 00E6D5B3;
+01F7 : D8478793;
+01F8 : 00B787B3;
+01F9 : 0007C783;
+01FA : 00E787B3;
+01FB : 02000713;
+01FC : 40F705B3;
+01FD : 02F71663;
+01FE : 00100513;
+01FF : E116EEE3;
+0200 : 00C33533;
+0201 : 00154513;
+0202 : 00008067;
+0203 : 010007B7;
+0204 : 01000713;
+0205 : FCF6E0E3;
+0206 : 01800713;
+0207 : FB9FF06F;
+0208 : 00F65733;
+0209 : 00B696B3;
+020A : 00D766B3;
+020B : 00F8D733;
+020C : 00B898B3;
+020D : 00F357B3;
+020E : 0117E7B3;
+020F : 0106D893;
+0210 : 03175EB3;
+0211 : 01069813;
+0212 : 01085813;
+0213 : 00B61633;
+0214 : 03177733;
+0215 : 03D80E33;
+0216 : 01071513;
+0217 : 0107D713;
+0218 : 00A76733;
+0219 : 000E8513;
+021A : 01C77E63;
+021B : 00D70733;
+021C : FFFE8513;
+021D : 00D76863;
+021E : 01C77663;
+021F : FFEE8513;
+0220 : 00D70733;
+0221 : 41C70733;
+0222 : 03175E33;
+0223 : 01079793;
+0224 : 0107D793;
+0225 : 03177733;
+0226 : 03C80833;
+0227 : 01071713;
+0228 : 00E7E7B3;
+0229 : 000E0713;
+022A : 0107FE63;
+022B : 00D787B3;
+022C : FFFE0713;
+022D : 00D7E863;
+022E : 0107F663;
+022F : FFEE0713;
+0230 : 00D787B3;
+0231 : 01051513;
+0232 : 00010E37;
+0233 : 00E56533;
+0234 : FFFE0693;
+0235 : 00D57733;
+0236 : 410787B3;
+0237 : 00D676B3;
+0238 : 01055813;
+0239 : 01065613;
+023A : 02D708B3;
+023B : 02D806B3;
+023C : 02C70733;
+023D : 02C80833;
+023E : 00D70633;
+023F : 0108D713;
+0240 : 00C70733;
+0241 : 00D77463;
+0242 : 01C80833;
+0243 : 01075693;
+0244 : 010686B3;
+0245 : 02D7E663;
+0246 : CED79EE3;
+0247 : 000107B7;
+0248 : FFF78793;
+0249 : 00F77733;
+024A : 01071713;
+024B : 00F8F8B3;
+024C : 00B31333;
+024D : 01170733;
+024E : 00000593;
+024F : CCE37EE3;
+0250 : FFF50513;
+0251 : CD1FF06F;
+0252 : 00000593;
+0253 : 00000513;
+0254 : 00008067;
+0255 : FF010113;
+0256 : 00000593;
+0257 : 00812423;
+0258 : 00112623;
+0259 : 00050413;
+025A : 194000EF;
+025B : C281A503;
+025C : 03C52783;
+025D : 00078463;
+025E : 000780E7;
+025F : 00040513;
+0260 : 3A4000EF;
+0261 : FF010113;
+0262 : 00812423;
+0263 : 01212023;
+0264 : 00001437;
+0265 : 00001937;
+0266 : 02C40793;
+0267 : 02C90913;
+0268 : 40F90933;
+0269 : 00112623;
+026A : 00912223;
+026B : 40295913;
+026C : 02090063;
+026D : 02C40413;
+026E : 00000493;
+026F : 00042783;
+0270 : 00148493;
+0271 : 00440413;
+0272 : 000780E7;
+0273 : FE9918E3;
+0274 : 00001437;
+0275 : 00001937;
+0276 : 02C40793;
+0277 : 03490913;
+0278 : 40F90933;
+0279 : 40295913;
+027A : 02090063;
+027B : 02C40413;
+027C : 00000493;
+027D : 00042783;
+027E : 00148493;
+027F : 00440413;
+0280 : 000780E7;
+0281 : FE9918E3;
+0282 : 00C12083;
+0283 : 00812403;
+0284 : 00412483;
+0285 : 00012903;
+0286 : 01010113;
+0287 : 00008067;
+0288 : 00F00313;
+0289 : 00050713;
+028A : 02C37E63;
+028B : 00F77793;
+028C : 0A079063;
+028D : 08059263;
+028E : FF067693;
+028F : 00F67613;
+0290 : 00E686B3;
+0291 : 00B72023;
+0292 : 00B72223;
+0293 : 00B72423;
+0294 : 00B72623;
+0295 : 01070713;
+0296 : FED766E3;
+0297 : 00061463;
+0298 : 00008067;
+0299 : 40C306B3;
+029A : 00269693;
+029B : 00000297;
+029C : 005686B3;
+029D : 00C68067;
+029E : 00B70723;
+029F : 00B706A3;
+02A0 : 00B70623;
+02A1 : 00B705A3;
+02A2 : 00B70523;
+02A3 : 00B704A3;
+02A4 : 00B70423;
+02A5 : 00B703A3;
+02A6 : 00B70323;
+02A7 : 00B702A3;
+02A8 : 00B70223;
+02A9 : 00B701A3;
+02AA : 00B70123;
+02AB : 00B700A3;
+02AC : 00B70023;
+02AD : 00008067;
+02AE : 0FF5F593;
+02AF : 00859693;
+02B0 : 00D5E5B3;
+02B1 : 01059693;
+02B2 : 00D5E5B3;
+02B3 : F6DFF06F;
+02B4 : 00279693;
+02B5 : 00000297;
+02B6 : 005686B3;
+02B7 : 00008293;
+02B8 : FA0680E7;
+02B9 : 00028093;
+02BA : FF078793;
+02BB : 40F70733;
+02BC : 00F60633;
+02BD : F6C378E3;
+02BE : F3DFF06F;
+02BF : FD010113;
+02C0 : 01412C23;
+02C1 : C281AA03;
+02C2 : 03212023;
+02C3 : 02112623;
+02C4 : 148A2903;
+02C5 : 02812423;
+02C6 : 02912223;
+02C7 : 01312E23;
+02C8 : 01512A23;
+02C9 : 01612823;
+02CA : 01712623;
+02CB : 01812423;
+02CC : 04090063;
+02CD : 00050B13;
+02CE : 00058B93;
+02CF : 00100A93;
+02D0 : FFF00993;
+02D1 : 00492483;
+02D2 : FFF48413;
+02D3 : 02044263;
+02D4 : 00249493;
+02D5 : 009904B3;
+02D6 : 040B8463;
+02D7 : 1044A783;
+02D8 : 05778063;
+02D9 : FFF40413;
+02DA : FFC48493;
+02DB : FF3416E3;
+02DC : 02C12083;
+02DD : 02812403;
+02DE : 02412483;
+02DF : 02012903;
+02E0 : 01C12983;
+02E1 : 01812A03;
+02E2 : 01412A83;
+02E3 : 01012B03;
+02E4 : 00C12B83;
+02E5 : 00812C03;
+02E6 : 03010113;
+02E7 : 00008067;
+02E8 : 00492783;
+02E9 : 0044A683;
+02EA : FFF78793;
+02EB : 04878E63;
+02EC : 0004A223;
+02ED : FA0688E3;
+02EE : 18892783;
+02EF : 008A9733;
+02F0 : 00492C03;
+02F1 : 00F777B3;
+02F2 : 02079263;
+02F3 : 000680E7;
+02F4 : 00492703;
+02F5 : 148A2783;
+02F6 : 01871463;
+02F7 : F92784E3;
+02F8 : F80788E3;
+02F9 : 00078913;
+02FA : F5DFF06F;
+02FB : 18C92783;
+02FC : 0844A583;
+02FD : 00F77733;
+02FE : 00071C63;
+02FF : 000B0513;
+0300 : 000680E7;
+0301 : FCDFF06F;
+0302 : 00892223;
+0303 : FA9FF06F;
+0304 : 00058513;
+0305 : 000680E7;
+0306 : FB9FF06F;
+0307 : FF010113;
+0308 : 00812423;
+0309 : 000017B7;
+030A : 00001437;
+030B : 03478793;
+030C : 03840413;
+030D : 40F40433;
+030E : 00912223;
+030F : 00112623;
+0310 : 40245493;
+0311 : 02048063;
+0312 : FFC40413;
+0313 : 00F40433;
+0314 : 00042783;
+0315 : FFF48493;
+0316 : FFC40413;
+0317 : 000780E7;
+0318 : FE0498E3;
+0319 : 00C12083;
+031A : 00812403;
+031B : 00412483;
+031C : 01010113;
031D : 00008067;
-031E : FFF00513;
-031F : 00008067;
-0320 : 05D00893;
-0321 : 00000073;
-0322 : 00054463;
-0323 : 0000006F;
-0324 : FF010113;
-0325 : 00812423;
-0326 : 00050413;
-0327 : 00112623;
-0328 : 40800433;
-0329 : 00C000EF;
-032A : 00852023;
-032B : 0000006F;
-032C : C401A503;
-032D : 00008067;
-032E : 0000003F;
-032F : 00000006;
-0330 : 0000005B;
-0331 : 0000004F;
-0332 : 00000066;
-0333 : 0000006D;
-0334 : 0000007D;
-0335 : 00000007;
-0336 : 0000007F;
-0337 : 0000006F;
-0338 : 02020100;
-0339 : 03030303;
-033A : 04040404;
-033B : 04040404;
-033C : 05050505;
-033D : 05050505;
-033E : 05050505;
-033F : 05050505;
-0340 : 06060606;
-0341 : 06060606;
-0342 : 06060606;
-0343 : 06060606;
-0344 : 06060606;
-0345 : 06060606;
-0346 : 06060606;
-0347 : 06060606;
-0348 : 07070707;
-0349 : 07070707;
-034A : 07070707;
-034B : 07070707;
-034C : 07070707;
-034D : 07070707;
-034E : 07070707;
-034F : 07070707;
-0350 : 07070707;
-0351 : 07070707;
-0352 : 07070707;
-0353 : 07070707;
-0354 : 07070707;
-0355 : 07070707;
-0356 : 07070707;
-0357 : 07070707;
-0358 : 08080808;
-0359 : 08080808;
-035A : 08080808;
-035B : 08080808;
-035C : 08080808;
-035D : 08080808;
-035E : 08080808;
-035F : 08080808;
-0360 : 08080808;
-0361 : 08080808;
-0362 : 08080808;
-0363 : 08080808;
-0364 : 08080808;
-0365 : 08080808;
-0366 : 08080808;
-0367 : 08080808;
-0368 : 08080808;
-0369 : 08080808;
-036A : 08080808;
-036B : 08080808;
-036C : 08080808;
-036D : 08080808;
-036E : 08080808;
-036F : 08080808;
-0370 : 08080808;
-0371 : 08080808;
-0372 : 08080808;
-0373 : 08080808;
-0374 : 08080808;
-0375 : 08080808;
-0376 : 08080808;
-0377 : 08080808;
-0378 : CD000000;
-0379 : CDCDCDCD;
-037A : CDCDCDCD;
-037B : CDCDCDCD;
-037C : CDCDCDCD;
-037D : CDCDCDCD;
-037E : CDCDCDCD;
-037F : CDCDCDCD;
-0380 : CDCDCDCD;
-0381 : CDCDCDCD;
-0382 : CDCDCDCD;
-0383 : CDCDCDCD;
-0384 : CDCDCDCD;
-0385 : CDCDCDCD;
-0386 : CDCDCDCD;
-0387 : CDCDCDCD;
-0388 : CDCDCDCD;
-0389 : CDCDCDCD;
-038A : CDCDCDCD;
-038B : CDCDCDCD;
-038C : CDCDCDCD;
-038D : CDCDCDCD;
-038E : CDCDCDCD;
-038F : CDCDCDCD;
-0390 : CDCDCDCD;
-0391 : CDCDCDCD;
-0392 : CDCDCDCD;
-0393 : CDCDCDCD;
-0394 : CDCDCDCD;
-0395 : CDCDCDCD;
-0396 : CDCDCDCD;
-0397 : CDCDCDCD;
-0398 : CDCDCDCD;
-0399 : CDCDCDCD;
-039A : CDCDCDCD;
-039B : CDCDCDCD;
-039C : CDCDCDCD;
-039D : CDCDCDCD;
-039E : CDCDCDCD;
-039F : CDCDCDCD;
-03A0 : CDCDCDCD;
-03A1 : CDCDCDCD;
+031E : 00050593;
+031F : 00000693;
+0320 : 00000613;
+0321 : 00000513;
+0322 : 0040006F;
+0323 : C281A703;
+0324 : 14872783;
+0325 : 04078C63;
+0326 : 0047A703;
+0327 : 01F00813;
+0328 : 06E84E63;
+0329 : 00271813;
+032A : 02050663;
+032B : 01078333;
+032C : 08C32423;
+032D : 1887A883;
+032E : 00100613;
+032F : 00E61633;
+0330 : 00C8E8B3;
+0331 : 1917A423;
+0332 : 10D32423;
+0333 : 00200693;
+0334 : 02D50463;
+0335 : 00170713;
+0336 : 00E7A223;
+0337 : 010787B3;
+0338 : 00B7A423;
+0339 : 00000513;
+033A : 00008067;
+033B : 14C70793;
+033C : 14F72423;
+033D : FA5FF06F;
+033E : 18C7A683;
+033F : 00170713;
+0340 : 00E7A223;
+0341 : 00C6E6B3;
+0342 : 18D7A623;
+0343 : 010787B3;
+0344 : 00B7A423;
+0345 : 00000513;
+0346 : 00008067;
+0347 : FFF00513;
+0348 : 00008067;
+0349 : 05D00893;
+034A : 00000073;
+034B : 00054463;
+034C : 0000006F;
+034D : FF010113;
+034E : 00812423;
+034F : 00050413;
+0350 : 00112623;
+0351 : 40800433;
+0352 : 00C000EF;
+0353 : 00852023;
+0354 : 0000006F;
+0355 : C301A503;
+0356 : 00008067;
+0357 : 0000003F;
+0358 : 00000006;
+0359 : 0000005B;
+035A : 0000004F;
+035B : 00000066;
+035C : 0000006D;
+035D : 0000007D;
+035E : 00000007;
+035F : 0000007F;
+0360 : 0000006F;
+0361 : 02020100;
+0362 : 03030303;
+0363 : 04040404;
+0364 : 04040404;
+0365 : 05050505;
+0366 : 05050505;
+0367 : 05050505;
+0368 : 05050505;
+0369 : 06060606;
+036A : 06060606;
+036B : 06060606;
+036C : 06060606;
+036D : 06060606;
+036E : 06060606;
+036F : 06060606;
+0370 : 06060606;
+0371 : 07070707;
+0372 : 07070707;
+0373 : 07070707;
+0374 : 07070707;
+0375 : 07070707;
+0376 : 07070707;
+0377 : 07070707;
+0378 : 07070707;
+0379 : 07070707;
+037A : 07070707;
+037B : 07070707;
+037C : 07070707;
+037D : 07070707;
+037E : 07070707;
+037F : 07070707;
+0380 : 07070707;
+0381 : 08080808;
+0382 : 08080808;
+0383 : 08080808;
+0384 : 08080808;
+0385 : 08080808;
+0386 : 08080808;
+0387 : 08080808;
+0388 : 08080808;
+0389 : 08080808;
+038A : 08080808;
+038B : 08080808;
+038C : 08080808;
+038D : 08080808;
+038E : 08080808;
+038F : 08080808;
+0390 : 08080808;
+0391 : 08080808;
+0392 : 08080808;
+0393 : 08080808;
+0394 : 08080808;
+0395 : 08080808;
+0396 : 08080808;
+0397 : 08080808;
+0398 : 08080808;
+0399 : 08080808;
+039A : 08080808;
+039B : 08080808;
+039C : 08080808;
+039D : 08080808;
+039E : 08080808;
+039F : 08080808;
+03A0 : 08080808;
+03A1 : CD000000;
03A2 : CDCDCDCD;
03A3 : CDCDCDCD;
03A4 : CDCDCDCD;
@@ -1035,7 +1035,7 @@ BEGIN
0404 : 00020D1B;
0405 : 00000010;
0406 : 00000018;
-0407 : FFFFF464;
+0407 : FFFFF508;
0408 : 00000430;
0409 : 00000000;
040A : 00000000;
@@ -1308,17 +1308,17 @@ BEGIN
0515 : 00000000;
0516 : 00000000;
0517 : 00000000;
-0518 : FFFFFFFF;
+0518 : 00001038;
0519 : 00000000;
-051A : 00000000;
-051B : 00000CB8;
-051C : 00001038;
-051D : 00000000;
-051E : 00001038;
-051F : 00001038;
-0520 : 00000000;
-0521 : 00001038;
-0522 : CD000000;
+051A : 00001038;
+051B : 00001038;
+051C : 00000000;
+051D : 00001038;
+051E : CD000000;
+051F : CDCDCDCD;
+0520 : CDCDCDCD;
+0521 : CDCDCDCD;
+0522 : CDCDCDCD;
0523 : CDCDCDCD;
0524 : CDCDCDCD;
0525 : CDCDCDCD;
diff --git a/examples/hdl4se_riscv/test_code/test.txt b/examples/hdl4se_riscv/test_code/test.txt
index b54ea5ce3335ddf43d21fe0c32371b3d85cd29f6..f8913b5d0c38defbf7a00527d641991f6f60d228 100644
--- a/examples/hdl4se_riscv/test_code/test.txt
+++ b/examples/hdl4se_riscv/test_code/test.txt
@@ -8,8 +8,8 @@ Disassembly of section .text:
74: 00000793 addi x15,x0,0
78: 00078863 beq x15,x0,88
7c: 00001537 lui x10,0x1
- 80: c4050513 addi x10,x10,-960 # c40 <__libc_fini_array>
- 84: 4190006f jal x0,c9c
+ 80: c1c50513 addi x10,x10,-996 # c1c <__libc_fini_array>
+ 84: 3f50006f jal x0,c78
88: 00008067 jalr x0,0(x1)
0000008c <_start>:
@@ -19,19 +19,19 @@ Disassembly of section .text:
98: c5018613 addi x12,x3,-944 # 1488 <__BSS_END__>
9c: 40a60633 sub x12,x12,x10
a0: 00000593 addi x11,x0,0
- a4: 1a1000ef jal x1,a44
+ a4: 17d000ef jal x1,a20
a8: 00001517 auipc x10,0x1
- ac: bf450513 addi x10,x10,-1036 # c9c
+ ac: bd050513 addi x10,x10,-1072 # c78
b0: 00050863 beq x10,x0,c0 <_start+0x34>
b4: 00001517 auipc x10,0x1
- b8: b8c50513 addi x10,x10,-1140 # c40 <__libc_fini_array>
- bc: 3e1000ef jal x1,c9c
- c0: 0e9000ef jal x1,9a8 <__libc_init_array>
+ b8: b6850513 addi x10,x10,-1176 # c1c <__libc_fini_array>
+ bc: 3bd000ef jal x1,c78
+ c0: 0c5000ef jal x1,984 <__libc_init_array>
c4: 00012503 lw x10,0(x2)
c8: 00410593 addi x11,x2,4
cc: 00000613 addi x12,x0,0
d0: 0ac000ef jal x1,17c
- d4: 0a50006f jal x0,978
+ d4: 0810006f jal x0,954
000000d8 <__do_global_dtors_aux>:
d8: ff010113 addi x2,x2,-16
@@ -71,7 +71,7 @@ Disassembly of section .text:
150: 00a00793 addi x15,x0,10
154: 02f777b3 remu x15,x14,x15
158: 00001737 lui x14,0x1
- 15c: d8070713 addi x14,x14,-640 # d80
+ 15c: d5c70713 addi x14,x14,-676 # d5c
160: 00279793 slli x15,x15,0x2
164: 00f707b3 add x15,x14,x15
168: 0007a783 lw x15,0(x15)
@@ -112,814 +112,814 @@ Disassembly of section .text:
1ec: f5b70713 addi x14,x14,-165 # 6d664f5b <__global_pointer$+0x6d663723>
1f0: 00e7a023 sw x14,0(x15)
1f4: fd842783 lw x15,-40(x8)
- 1f8: 01078793 addi x15,x15,16
- 1fc: 36400713 addi x14,x0,868
- 200: 00e7a023 sw x14,0(x15)
- 204: fd842783 lw x15,-40(x8)
- 208: 00478793 addi x15,x15,4
- 20c: 04800713 addi x14,x0,72
- 210: 00e7a023 sw x14,0(x15)
- 214: fd842783 lw x15,-40(x8)
- 218: 00478793 addi x15,x15,4
- 21c: 00a00713 addi x14,x0,10
- 220: 00e7a023 sw x14,0(x15)
- 224: fd842783 lw x15,-40(x8)
- 228: 0087a783 lw x15,8(x15)
- 22c: fcf42a23 sw x15,-44(x8)
- 230: fd442783 lw x15,-44(x8)
- 234: 0807f793 andi x15,x15,128
- 238: 00078e63 beq x15,x0,254
- 23c: fd842783 lw x15,-40(x8)
- 240: 00478793 addi x15,x15,4
- 244: fd842703 lw x14,-40(x8)
- 248: 00072703 lw x14,0(x14)
- 24c: 00e7a023 sw x14,0(x15)
- 250: 2f40006f jal x0,544
- 254: fe042783 lw x15,-32(x8)
- 258: 0007a783 lw x15,0(x15)
- 25c: fcf42823 sw x15,-48(x8)
- 260: fd042783 lw x15,-48(x8)
- 264: 0017f793 andi x15,x15,1
- 268: 00078c63 beq x15,x0,280
- 26c: 00000793 addi x15,x0,0
- 270: 00000813 addi x16,x0,0
- 274: fef42423 sw x15,-24(x8)
- 278: ff042623 sw x16,-20(x8)
- 27c: 02c0006f jal x0,2a8
- 280: fd042783 lw x15,-48(x8)
- 284: 0027f793 andi x15,x15,2
- 288: 00078663 beq x15,x0,294
- 28c: fe042223 sw x0,-28(x8)
- 290: 0180006f jal x0,2a8
- 294: fd042783 lw x15,-48(x8)
- 298: 0047f793 andi x15,x15,4
- 29c: 00078663 beq x15,x0,2a8
- 2a0: 00100793 addi x15,x0,1
- 2a4: fef42223 sw x15,-28(x8)
- 2a8: fe442783 lw x15,-28(x8)
- 2ac: 02078a63 beq x15,x0,2e0
- 2b0: fe842603 lw x12,-24(x8)
- 2b4: fec42683 lw x13,-20(x8)
- 2b8: 00100513 addi x10,x0,1
- 2bc: 00000593 addi x11,x0,0
- 2c0: 00a60733 add x14,x12,x10
- 2c4: 00070813 addi x16,x14,0
- 2c8: 00c83833 sltu x16,x16,x12
- 2cc: 00b687b3 add x15,x13,x11
- 2d0: 00f806b3 add x13,x16,x15
- 2d4: 00068793 addi x15,x13,0
- 2d8: fee42423 sw x14,-24(x8)
- 2dc: fef42623 sw x15,-20(x8)
- 2e0: fe842703 lw x14,-24(x8)
- 2e4: fec42783 lw x15,-20(x8)
- 2e8: fce42423 sw x14,-56(x8)
- 2ec: fcf42623 sw x15,-52(x8)
- 2f0: fc842783 lw x15,-56(x8)
- 2f4: 00078513 addi x10,x15,0
- 2f8: e45ff0ef jal x1,13c
- 2fc: 00050493 addi x9,x10,0
- 300: fc842703 lw x14,-56(x8)
- 304: fcc42783 lw x15,-52(x8)
- 308: 00a00613 addi x12,x0,10
- 30c: 00000693 addi x13,x0,0
- 310: 00070513 addi x10,x14,0
- 314: 00078593 addi x11,x15,0
- 318: 230000ef jal x1,548 <__udivdi3>
- 31c: 00050713 addi x14,x10,0
- 320: 00058793 addi x15,x11,0
- 324: 00070793 addi x15,x14,0
- 328: 00078513 addi x10,x15,0
- 32c: e11ff0ef jal x1,13c
- 330: 00050793 addi x15,x10,0
- 334: 00879793 slli x15,x15,0x8
- 338: 00f4e4b3 or x9,x9,x15
- 33c: fc842703 lw x14,-56(x8)
- 340: fcc42783 lw x15,-52(x8)
- 344: 06400613 addi x12,x0,100
- 348: 00000693 addi x13,x0,0
- 34c: 00070513 addi x10,x14,0
- 350: 00078593 addi x11,x15,0
- 354: 1f4000ef jal x1,548 <__udivdi3>
- 358: 00050713 addi x14,x10,0
- 35c: 00058793 addi x15,x11,0
- 360: 00070793 addi x15,x14,0
- 364: 00078513 addi x10,x15,0
- 368: dd5ff0ef jal x1,13c
- 36c: 00050793 addi x15,x10,0
- 370: 01079793 slli x15,x15,0x10
- 374: 00f4e4b3 or x9,x9,x15
- 378: fc842703 lw x14,-56(x8)
- 37c: fcc42783 lw x15,-52(x8)
- 380: 3e800613 addi x12,x0,1000
- 384: 00000693 addi x13,x0,0
- 388: 00070513 addi x10,x14,0
- 38c: 00078593 addi x11,x15,0
- 390: 1b8000ef jal x1,548 <__udivdi3>
- 394: 00050713 addi x14,x10,0
- 398: 00058793 addi x15,x11,0
- 39c: 00070793 addi x15,x14,0
- 3a0: 00078513 addi x10,x15,0
- 3a4: d99ff0ef jal x1,13c
- 3a8: 00050793 addi x15,x10,0
- 3ac: 01879793 slli x15,x15,0x18
- 3b0: 00f4e733 or x14,x9,x15
- 3b4: fdc42783 lw x15,-36(x8)
- 3b8: 00e7a023 sw x14,0(x15)
- 3bc: fc842703 lw x14,-56(x8)
- 3c0: fcc42783 lw x15,-52(x8)
- 3c4: 00002637 lui x12,0x2
- 3c8: 71060613 addi x12,x12,1808 # 2710 <__global_pointer$+0xed8>
- 3cc: 00000693 addi x13,x0,0
- 3d0: 00070513 addi x10,x14,0
- 3d4: 00078593 addi x11,x15,0
- 3d8: 170000ef jal x1,548 <__udivdi3>
- 3dc: 00050713 addi x14,x10,0
- 3e0: 00058793 addi x15,x11,0
- 3e4: fce42423 sw x14,-56(x8)
- 3e8: fcf42623 sw x15,-52(x8)
- 3ec: fc842783 lw x15,-56(x8)
- 3f0: 00078513 addi x10,x15,0
- 3f4: d49ff0ef jal x1,13c
- 3f8: 00050493 addi x9,x10,0
- 3fc: fc842703 lw x14,-56(x8)
- 400: fcc42783 lw x15,-52(x8)
- 404: 00a00613 addi x12,x0,10
- 408: 00000693 addi x13,x0,0
- 40c: 00070513 addi x10,x14,0
- 410: 00078593 addi x11,x15,0
- 414: 134000ef jal x1,548 <__udivdi3>
- 418: 00050713 addi x14,x10,0
- 41c: 00058793 addi x15,x11,0
- 420: 00070793 addi x15,x14,0
- 424: 00078513 addi x10,x15,0
- 428: d15ff0ef jal x1,13c
- 42c: 00050793 addi x15,x10,0
- 430: 00879793 slli x15,x15,0x8
- 434: 00f4e4b3 or x9,x9,x15
- 438: fc842703 lw x14,-56(x8)
- 43c: fcc42783 lw x15,-52(x8)
- 440: 06400613 addi x12,x0,100
- 444: 00000693 addi x13,x0,0
- 448: 00070513 addi x10,x14,0
- 44c: 00078593 addi x11,x15,0
- 450: 0f8000ef jal x1,548 <__udivdi3>
- 454: 00050713 addi x14,x10,0
- 458: 00058793 addi x15,x11,0
- 45c: 00070793 addi x15,x14,0
- 460: 00078513 addi x10,x15,0
- 464: cd9ff0ef jal x1,13c
- 468: 00050793 addi x15,x10,0
- 46c: 01079793 slli x15,x15,0x10
- 470: 00f4e4b3 or x9,x9,x15
- 474: fc842703 lw x14,-56(x8)
- 478: fcc42783 lw x15,-52(x8)
- 47c: 3e800613 addi x12,x0,1000
- 480: 00000693 addi x13,x0,0
- 484: 00070513 addi x10,x14,0
- 488: 00078593 addi x11,x15,0
- 48c: 0bc000ef jal x1,548 <__udivdi3>
- 490: 00050713 addi x14,x10,0
- 494: 00058793 addi x15,x11,0
- 498: 00070793 addi x15,x14,0
- 49c: 00078513 addi x10,x15,0
- 4a0: c9dff0ef jal x1,13c
- 4a4: 00050793 addi x15,x10,0
- 4a8: 01879713 slli x14,x15,0x18
- 4ac: fdc42783 lw x15,-36(x8)
- 4b0: 00478793 addi x15,x15,4
- 4b4: 00e4e733 or x14,x9,x14
- 4b8: 00e7a023 sw x14,0(x15)
- 4bc: fc842703 lw x14,-56(x8)
- 4c0: fcc42783 lw x15,-52(x8)
- 4c4: 00002637 lui x12,0x2
- 4c8: 71060613 addi x12,x12,1808 # 2710 <__global_pointer$+0xed8>
- 4cc: 00000693 addi x13,x0,0
- 4d0: 00070513 addi x10,x14,0
- 4d4: 00078593 addi x11,x15,0
- 4d8: 070000ef jal x1,548 <__udivdi3>
- 4dc: 00050713 addi x14,x10,0
- 4e0: 00058793 addi x15,x11,0
- 4e4: fce42423 sw x14,-56(x8)
- 4e8: fcf42623 sw x15,-52(x8)
- 4ec: fc842783 lw x15,-56(x8)
- 4f0: 00078513 addi x10,x15,0
- 4f4: c49ff0ef jal x1,13c
- 4f8: 00050493 addi x9,x10,0
- 4fc: fc842703 lw x14,-56(x8)
- 500: fcc42783 lw x15,-52(x8)
- 504: 00a00613 addi x12,x0,10
- 508: 00000693 addi x13,x0,0
- 50c: 00070513 addi x10,x14,0
- 510: 00078593 addi x11,x15,0
- 514: 034000ef jal x1,548 <__udivdi3>
- 518: 00050713 addi x14,x10,0
- 51c: 00058793 addi x15,x11,0
- 520: 00070793 addi x15,x14,0
- 524: 00078513 addi x10,x15,0
- 528: c15ff0ef jal x1,13c
- 52c: 00050793 addi x15,x10,0
- 530: 00879713 slli x14,x15,0x8
- 534: fdc42783 lw x15,-36(x8)
- 538: 00878793 addi x15,x15,8
- 53c: 00e4e733 or x14,x9,x14
- 540: 00e7a023 sw x14,0(x15)
- 544: ce1ff06f jal x0,224
+ 1f8: 0087a783 lw x15,8(x15)
+ 1fc: fcf42a23 sw x15,-44(x8)
+ 200: fd442783 lw x15,-44(x8)
+ 204: 0807f793 andi x15,x15,128
+ 208: 02078463 beq x15,x0,230
+ 20c: fd842783 lw x15,-40(x8)
+ 210: 00478793 addi x15,x15,4
+ 214: fd842703 lw x14,-40(x8)
+ 218: 00072703 lw x14,0(x14)
+ 21c: 00e7a023 sw x14,0(x15)
+ 220: fd842783 lw x15,-40(x8)
+ 224: 00878793 addi x15,x15,8
+ 228: 0007a023 sw x0,0(x15)
+ 22c: 2f40006f jal x0,520
+ 230: fe042783 lw x15,-32(x8)
+ 234: 0007a783 lw x15,0(x15)
+ 238: fcf42823 sw x15,-48(x8)
+ 23c: fd042783 lw x15,-48(x8)
+ 240: 0017f793 andi x15,x15,1
+ 244: 00078c63 beq x15,x0,25c
+ 248: 00000793 addi x15,x0,0
+ 24c: 00000813 addi x16,x0,0
+ 250: fef42423 sw x15,-24(x8)
+ 254: ff042623 sw x16,-20(x8)
+ 258: 02c0006f jal x0,284
+ 25c: fd042783 lw x15,-48(x8)
+ 260: 0027f793 andi x15,x15,2
+ 264: 00078663 beq x15,x0,270
+ 268: fe042223 sw x0,-28(x8)
+ 26c: 0180006f jal x0,284
+ 270: fd042783 lw x15,-48(x8)
+ 274: 0047f793 andi x15,x15,4
+ 278: 00078663 beq x15,x0,284
+ 27c: 00100793 addi x15,x0,1
+ 280: fef42223 sw x15,-28(x8)
+ 284: fe442783 lw x15,-28(x8)
+ 288: 02078a63 beq x15,x0,2bc
+ 28c: fe842603 lw x12,-24(x8)
+ 290: fec42683 lw x13,-20(x8)
+ 294: 00100513 addi x10,x0,1
+ 298: 00000593 addi x11,x0,0
+ 29c: 00a60733 add x14,x12,x10
+ 2a0: 00070813 addi x16,x14,0
+ 2a4: 00c83833 sltu x16,x16,x12
+ 2a8: 00b687b3 add x15,x13,x11
+ 2ac: 00f806b3 add x13,x16,x15
+ 2b0: 00068793 addi x15,x13,0
+ 2b4: fee42423 sw x14,-24(x8)
+ 2b8: fef42623 sw x15,-20(x8)
+ 2bc: fe842703 lw x14,-24(x8)
+ 2c0: fec42783 lw x15,-20(x8)
+ 2c4: fce42423 sw x14,-56(x8)
+ 2c8: fcf42623 sw x15,-52(x8)
+ 2cc: fc842783 lw x15,-56(x8)
+ 2d0: 00078513 addi x10,x15,0
+ 2d4: e69ff0ef jal x1,13c
+ 2d8: 00050493 addi x9,x10,0
+ 2dc: fc842703 lw x14,-56(x8)
+ 2e0: fcc42783 lw x15,-52(x8)
+ 2e4: 00a00613 addi x12,x0,10
+ 2e8: 00000693 addi x13,x0,0
+ 2ec: 00070513 addi x10,x14,0
+ 2f0: 00078593 addi x11,x15,0
+ 2f4: 230000ef jal x1,524 <__udivdi3>
+ 2f8: 00050713 addi x14,x10,0
+ 2fc: 00058793 addi x15,x11,0
+ 300: 00070793 addi x15,x14,0
+ 304: 00078513 addi x10,x15,0
+ 308: e35ff0ef jal x1,13c
+ 30c: 00050793 addi x15,x10,0
+ 310: 00879793 slli x15,x15,0x8
+ 314: 00f4e4b3 or x9,x9,x15
+ 318: fc842703 lw x14,-56(x8)
+ 31c: fcc42783 lw x15,-52(x8)
+ 320: 06400613 addi x12,x0,100
+ 324: 00000693 addi x13,x0,0
+ 328: 00070513 addi x10,x14,0
+ 32c: 00078593 addi x11,x15,0
+ 330: 1f4000ef jal x1,524 <__udivdi3>
+ 334: 00050713 addi x14,x10,0
+ 338: 00058793 addi x15,x11,0
+ 33c: 00070793 addi x15,x14,0
+ 340: 00078513 addi x10,x15,0
+ 344: df9ff0ef jal x1,13c
+ 348: 00050793 addi x15,x10,0
+ 34c: 01079793 slli x15,x15,0x10
+ 350: 00f4e4b3 or x9,x9,x15
+ 354: fc842703 lw x14,-56(x8)
+ 358: fcc42783 lw x15,-52(x8)
+ 35c: 3e800613 addi x12,x0,1000
+ 360: 00000693 addi x13,x0,0
+ 364: 00070513 addi x10,x14,0
+ 368: 00078593 addi x11,x15,0
+ 36c: 1b8000ef jal x1,524 <__udivdi3>
+ 370: 00050713 addi x14,x10,0
+ 374: 00058793 addi x15,x11,0
+ 378: 00070793 addi x15,x14,0
+ 37c: 00078513 addi x10,x15,0
+ 380: dbdff0ef jal x1,13c
+ 384: 00050793 addi x15,x10,0
+ 388: 01879793 slli x15,x15,0x18
+ 38c: 00f4e733 or x14,x9,x15
+ 390: fdc42783 lw x15,-36(x8)
+ 394: 00e7a023 sw x14,0(x15)
+ 398: fc842703 lw x14,-56(x8)
+ 39c: fcc42783 lw x15,-52(x8)
+ 3a0: 00002637 lui x12,0x2
+ 3a4: 71060613 addi x12,x12,1808 # 2710 <__global_pointer$+0xed8>
+ 3a8: 00000693 addi x13,x0,0
+ 3ac: 00070513 addi x10,x14,0
+ 3b0: 00078593 addi x11,x15,0
+ 3b4: 170000ef jal x1,524 <__udivdi3>
+ 3b8: 00050713 addi x14,x10,0
+ 3bc: 00058793 addi x15,x11,0
+ 3c0: fce42423 sw x14,-56(x8)
+ 3c4: fcf42623 sw x15,-52(x8)
+ 3c8: fc842783 lw x15,-56(x8)
+ 3cc: 00078513 addi x10,x15,0
+ 3d0: d6dff0ef jal x1,13c
+ 3d4: 00050493 addi x9,x10,0
+ 3d8: fc842703 lw x14,-56(x8)
+ 3dc: fcc42783 lw x15,-52(x8)
+ 3e0: 00a00613 addi x12,x0,10
+ 3e4: 00000693 addi x13,x0,0
+ 3e8: 00070513 addi x10,x14,0
+ 3ec: 00078593 addi x11,x15,0
+ 3f0: 134000ef jal x1,524 <__udivdi3>
+ 3f4: 00050713 addi x14,x10,0
+ 3f8: 00058793 addi x15,x11,0
+ 3fc: 00070793 addi x15,x14,0
+ 400: 00078513 addi x10,x15,0
+ 404: d39ff0ef jal x1,13c
+ 408: 00050793 addi x15,x10,0
+ 40c: 00879793 slli x15,x15,0x8
+ 410: 00f4e4b3 or x9,x9,x15
+ 414: fc842703 lw x14,-56(x8)
+ 418: fcc42783 lw x15,-52(x8)
+ 41c: 06400613 addi x12,x0,100
+ 420: 00000693 addi x13,x0,0
+ 424: 00070513 addi x10,x14,0
+ 428: 00078593 addi x11,x15,0
+ 42c: 0f8000ef jal x1,524 <__udivdi3>
+ 430: 00050713 addi x14,x10,0
+ 434: 00058793 addi x15,x11,0
+ 438: 00070793 addi x15,x14,0
+ 43c: 00078513 addi x10,x15,0
+ 440: cfdff0ef jal x1,13c
+ 444: 00050793 addi x15,x10,0
+ 448: 01079793 slli x15,x15,0x10
+ 44c: 00f4e4b3 or x9,x9,x15
+ 450: fc842703 lw x14,-56(x8)
+ 454: fcc42783 lw x15,-52(x8)
+ 458: 3e800613 addi x12,x0,1000
+ 45c: 00000693 addi x13,x0,0
+ 460: 00070513 addi x10,x14,0
+ 464: 00078593 addi x11,x15,0
+ 468: 0bc000ef jal x1,524 <__udivdi3>
+ 46c: 00050713 addi x14,x10,0
+ 470: 00058793 addi x15,x11,0
+ 474: 00070793 addi x15,x14,0
+ 478: 00078513 addi x10,x15,0
+ 47c: cc1ff0ef jal x1,13c
+ 480: 00050793 addi x15,x10,0
+ 484: 01879713 slli x14,x15,0x18
+ 488: fdc42783 lw x15,-36(x8)
+ 48c: 00478793 addi x15,x15,4
+ 490: 00e4e733 or x14,x9,x14
+ 494: 00e7a023 sw x14,0(x15)
+ 498: fc842703 lw x14,-56(x8)
+ 49c: fcc42783 lw x15,-52(x8)
+ 4a0: 00002637 lui x12,0x2
+ 4a4: 71060613 addi x12,x12,1808 # 2710 <__global_pointer$+0xed8>
+ 4a8: 00000693 addi x13,x0,0
+ 4ac: 00070513 addi x10,x14,0
+ 4b0: 00078593 addi x11,x15,0
+ 4b4: 070000ef jal x1,524 <__udivdi3>
+ 4b8: 00050713 addi x14,x10,0
+ 4bc: 00058793 addi x15,x11,0
+ 4c0: fce42423 sw x14,-56(x8)
+ 4c4: fcf42623 sw x15,-52(x8)
+ 4c8: fc842783 lw x15,-56(x8)
+ 4cc: 00078513 addi x10,x15,0
+ 4d0: c6dff0ef jal x1,13c
+ 4d4: 00050493 addi x9,x10,0
+ 4d8: fc842703 lw x14,-56(x8)
+ 4dc: fcc42783 lw x15,-52(x8)
+ 4e0: 00a00613 addi x12,x0,10
+ 4e4: 00000693 addi x13,x0,0
+ 4e8: 00070513 addi x10,x14,0
+ 4ec: 00078593 addi x11,x15,0
+ 4f0: 034000ef jal x1,524 <__udivdi3>
+ 4f4: 00050713 addi x14,x10,0
+ 4f8: 00058793 addi x15,x11,0
+ 4fc: 00070793 addi x15,x14,0
+ 500: 00078513 addi x10,x15,0
+ 504: c39ff0ef jal x1,13c
+ 508: 00050793 addi x15,x10,0
+ 50c: 00879713 slli x14,x15,0x8
+ 510: fdc42783 lw x15,-36(x8)
+ 514: 00878793 addi x15,x15,8
+ 518: 00e4e733 or x14,x9,x14
+ 51c: 00e7a023 sw x14,0(x15)
+ 520: cd5ff06f jal x0,1f4
-00000548 <__udivdi3>:
- 548: 00050313 addi x6,x10,0
- 54c: 00058893 addi x17,x11,0
- 550: 00060713 addi x14,x12,0
- 554: 00050813 addi x16,x10,0
- 558: 00058793 addi x15,x11,0
- 55c: 28069263 bne x13,x0,7e0 <__udivdi3+0x298>
- 560: 000015b7 lui x11,0x1
- 564: da858593 addi x11,x11,-600 # da8 <__clz_tab>
- 568: 0ec8f663 bgeu x17,x12,654 <__udivdi3+0x10c>
- 56c: 000106b7 lui x13,0x10
- 570: 0cd67863 bgeu x12,x13,640 <__udivdi3+0xf8>
- 574: 10063693 sltiu x13,x12,256
- 578: 0016c693 xori x13,x13,1
- 57c: 00369693 slli x13,x13,0x3
- 580: 00d65533 srl x10,x12,x13
- 584: 00a585b3 add x11,x11,x10
- 588: 0005c583 lbu x11,0(x11)
- 58c: 02000513 addi x10,x0,32
- 590: 00d586b3 add x13,x11,x13
- 594: 40d505b3 sub x11,x10,x13
- 598: 00d50c63 beq x10,x13,5b0 <__udivdi3+0x68>
- 59c: 00b897b3 sll x15,x17,x11
- 5a0: 00d356b3 srl x13,x6,x13
- 5a4: 00b61733 sll x14,x12,x11
- 5a8: 00f6e7b3 or x15,x13,x15
- 5ac: 00b31833 sll x16,x6,x11
- 5b0: 01075593 srli x11,x14,0x10
- 5b4: 02b7d333 divu x6,x15,x11
- 5b8: 01071613 slli x12,x14,0x10
- 5bc: 01065613 srli x12,x12,0x10
- 5c0: 02b7f7b3 remu x15,x15,x11
- 5c4: 00030513 addi x10,x6,0 # 130
- 5c8: 026608b3 mul x17,x12,x6
- 5cc: 01079693 slli x13,x15,0x10
- 5d0: 01085793 srli x15,x16,0x10
- 5d4: 00d7e7b3 or x15,x15,x13
- 5d8: 0117fe63 bgeu x15,x17,5f4 <__udivdi3+0xac>
- 5dc: 00e787b3 add x15,x15,x14
- 5e0: fff30513 addi x10,x6,-1
- 5e4: 00e7e863 bltu x15,x14,5f4 <__udivdi3+0xac>
- 5e8: 0117f663 bgeu x15,x17,5f4 <__udivdi3+0xac>
- 5ec: ffe30513 addi x10,x6,-2
- 5f0: 00e787b3 add x15,x15,x14
- 5f4: 411787b3 sub x15,x15,x17
- 5f8: 02b7d8b3 divu x17,x15,x11
- 5fc: 01081813 slli x16,x16,0x10
- 600: 01085813 srli x16,x16,0x10
- 604: 02b7f7b3 remu x15,x15,x11
- 608: 031606b3 mul x13,x12,x17
- 60c: 01079793 slli x15,x15,0x10
- 610: 00f86833 or x16,x16,x15
- 614: 00088793 addi x15,x17,0
- 618: 00d87c63 bgeu x16,x13,630 <__udivdi3+0xe8>
- 61c: 01070833 add x16,x14,x16
- 620: fff88793 addi x15,x17,-1
- 624: 00e86663 bltu x16,x14,630 <__udivdi3+0xe8>
- 628: 00d87463 bgeu x16,x13,630 <__udivdi3+0xe8>
- 62c: ffe88793 addi x15,x17,-2
- 630: 01051513 slli x10,x10,0x10
- 634: 00f56533 or x10,x10,x15
- 638: 00000593 addi x11,x0,0
- 63c: 00008067 jalr x0,0(x1)
- 640: 01000537 lui x10,0x1000
- 644: 01000693 addi x13,x0,16
- 648: f2a66ce3 bltu x12,x10,580 <__udivdi3+0x38>
- 64c: 01800693 addi x13,x0,24
- 650: f31ff06f jal x0,580 <__udivdi3+0x38>
- 654: 00061463 bne x12,x0,65c <__udivdi3+0x114>
- 658: 00100073 ebreak
- 65c: 000107b7 lui x15,0x10
- 660: 0cf67063 bgeu x12,x15,720 <__udivdi3+0x1d8>
- 664: 10063693 sltiu x13,x12,256
- 668: 0016c693 xori x13,x13,1
- 66c: 00369693 slli x13,x13,0x3
- 670: 00d657b3 srl x15,x12,x13
- 674: 00f585b3 add x11,x11,x15
- 678: 0005c783 lbu x15,0(x11)
- 67c: 00d787b3 add x15,x15,x13
- 680: 02000693 addi x13,x0,32
- 684: 40f685b3 sub x11,x13,x15
- 688: 0af69663 bne x13,x15,734 <__udivdi3+0x1ec>
- 68c: 40c887b3 sub x15,x17,x12
- 690: 00100593 addi x11,x0,1
- 694: 01075893 srli x17,x14,0x10
- 698: 0317de33 divu x28,x15,x17
- 69c: 01071613 slli x12,x14,0x10
- 6a0: 01065613 srli x12,x12,0x10
- 6a4: 01085693 srli x13,x16,0x10
- 6a8: 0317f7b3 remu x15,x15,x17
- 6ac: 000e0513 addi x10,x28,0
- 6b0: 03c60333 mul x6,x12,x28
- 6b4: 01079793 slli x15,x15,0x10
- 6b8: 00f6e7b3 or x15,x13,x15
- 6bc: 0067fe63 bgeu x15,x6,6d8 <__udivdi3+0x190>
- 6c0: 00e787b3 add x15,x15,x14
- 6c4: fffe0513 addi x10,x28,-1
- 6c8: 00e7e863 bltu x15,x14,6d8 <__udivdi3+0x190>
- 6cc: 0067f663 bgeu x15,x6,6d8 <__udivdi3+0x190>
- 6d0: ffee0513 addi x10,x28,-2
- 6d4: 00e787b3 add x15,x15,x14
- 6d8: 406787b3 sub x15,x15,x6
- 6dc: 0317d333 divu x6,x15,x17
- 6e0: 01081813 slli x16,x16,0x10
- 6e4: 01085813 srli x16,x16,0x10
- 6e8: 0317f7b3 remu x15,x15,x17
- 6ec: 026606b3 mul x13,x12,x6
- 6f0: 01079793 slli x15,x15,0x10
- 6f4: 00f86833 or x16,x16,x15
- 6f8: 00030793 addi x15,x6,0
- 6fc: 00d87c63 bgeu x16,x13,714 <__udivdi3+0x1cc>
- 700: 01070833 add x16,x14,x16
- 704: fff30793 addi x15,x6,-1
- 708: 00e86663 bltu x16,x14,714 <__udivdi3+0x1cc>
- 70c: 00d87463 bgeu x16,x13,714 <__udivdi3+0x1cc>
- 710: ffe30793 addi x15,x6,-2
- 714: 01051513 slli x10,x10,0x10
- 718: 00f56533 or x10,x10,x15
- 71c: 00008067 jalr x0,0(x1)
- 720: 010007b7 lui x15,0x1000
- 724: 01000693 addi x13,x0,16
- 728: f4f664e3 bltu x12,x15,670 <__udivdi3+0x128>
- 72c: 01800693 addi x13,x0,24
- 730: f41ff06f jal x0,670 <__udivdi3+0x128>
- 734: 00b61733 sll x14,x12,x11
- 738: 00f8d6b3 srl x13,x17,x15
- 73c: 01075513 srli x10,x14,0x10
- 740: 00f357b3 srl x15,x6,x15
- 744: 00b31833 sll x16,x6,x11
- 748: 02a6d333 divu x6,x13,x10
- 74c: 01071613 slli x12,x14,0x10
- 750: 00b898b3 sll x17,x17,x11
- 754: 01065613 srli x12,x12,0x10
- 758: 0117e7b3 or x15,x15,x17
- 75c: 02a6f6b3 remu x13,x13,x10
- 760: 026608b3 mul x17,x12,x6
- 764: 01069593 slli x11,x13,0x10
- 768: 0107d693 srli x13,x15,0x10
- 76c: 00b6e6b3 or x13,x13,x11
- 770: 00030593 addi x11,x6,0
- 774: 0116fe63 bgeu x13,x17,790 <__udivdi3+0x248>
- 778: 00e686b3 add x13,x13,x14
- 77c: fff30593 addi x11,x6,-1
- 780: 00e6e863 bltu x13,x14,790 <__udivdi3+0x248>
- 784: 0116f663 bgeu x13,x17,790 <__udivdi3+0x248>
- 788: ffe30593 addi x11,x6,-2
- 78c: 00e686b3 add x13,x13,x14
- 790: 411686b3 sub x13,x13,x17
- 794: 02a6d8b3 divu x17,x13,x10
- 798: 01079793 slli x15,x15,0x10
- 79c: 0107d793 srli x15,x15,0x10
- 7a0: 02a6f6b3 remu x13,x13,x10
- 7a4: 03160633 mul x12,x12,x17
- 7a8: 01069693 slli x13,x13,0x10
- 7ac: 00d7e7b3 or x15,x15,x13
- 7b0: 00088693 addi x13,x17,0
- 7b4: 00c7fe63 bgeu x15,x12,7d0 <__udivdi3+0x288>
- 7b8: 00e787b3 add x15,x15,x14
- 7bc: fff88693 addi x13,x17,-1
- 7c0: 00e7e863 bltu x15,x14,7d0 <__udivdi3+0x288>
- 7c4: 00c7f663 bgeu x15,x12,7d0 <__udivdi3+0x288>
- 7c8: ffe88693 addi x13,x17,-2
- 7cc: 00e787b3 add x15,x15,x14
- 7d0: 01059593 slli x11,x11,0x10
- 7d4: 40c787b3 sub x15,x15,x12
- 7d8: 00d5e5b3 or x11,x11,x13
- 7dc: eb9ff06f jal x0,694 <__udivdi3+0x14c>
- 7e0: 18d5e663 bltu x11,x13,96c <__udivdi3+0x424>
- 7e4: 000107b7 lui x15,0x10
- 7e8: 04f6f463 bgeu x13,x15,830 <__udivdi3+0x2e8>
- 7ec: 1006b713 sltiu x14,x13,256
- 7f0: 00174713 xori x14,x14,1
- 7f4: 00371713 slli x14,x14,0x3
- 7f8: 000017b7 lui x15,0x1
- 7fc: 00e6d5b3 srl x11,x13,x14
- 800: da878793 addi x15,x15,-600 # da8 <__clz_tab>
- 804: 00b787b3 add x15,x15,x11
- 808: 0007c783 lbu x15,0(x15)
- 80c: 00e787b3 add x15,x15,x14
- 810: 02000713 addi x14,x0,32
- 814: 40f705b3 sub x11,x14,x15
- 818: 02f71663 bne x14,x15,844 <__udivdi3+0x2fc>
- 81c: 00100513 addi x10,x0,1
- 820: e116eee3 bltu x13,x17,63c <__udivdi3+0xf4>
- 824: 00c33533 sltu x10,x6,x12
- 828: 00154513 xori x10,x10,1
- 82c: 00008067 jalr x0,0(x1)
- 830: 010007b7 lui x15,0x1000
- 834: 01000713 addi x14,x0,16
- 838: fcf6e0e3 bltu x13,x15,7f8 <__udivdi3+0x2b0>
- 83c: 01800713 addi x14,x0,24
- 840: fb9ff06f jal x0,7f8 <__udivdi3+0x2b0>
- 844: 00f65733 srl x14,x12,x15
- 848: 00b696b3 sll x13,x13,x11
- 84c: 00d766b3 or x13,x14,x13
- 850: 00f8d733 srl x14,x17,x15
- 854: 00b898b3 sll x17,x17,x11
- 858: 00f357b3 srl x15,x6,x15
- 85c: 0117e7b3 or x15,x15,x17
- 860: 0106d893 srli x17,x13,0x10
- 864: 03175eb3 divu x29,x14,x17
- 868: 01069813 slli x16,x13,0x10
- 86c: 01085813 srli x16,x16,0x10
- 870: 00b61633 sll x12,x12,x11
- 874: 03177733 remu x14,x14,x17
- 878: 03d80e33 mul x28,x16,x29
- 87c: 01071513 slli x10,x14,0x10
- 880: 0107d713 srli x14,x15,0x10
- 884: 00a76733 or x14,x14,x10
- 888: 000e8513 addi x10,x29,0
- 88c: 01c77e63 bgeu x14,x28,8a8 <__udivdi3+0x360>
- 890: 00d70733 add x14,x14,x13
- 894: fffe8513 addi x10,x29,-1
- 898: 00d76863 bltu x14,x13,8a8 <__udivdi3+0x360>
- 89c: 01c77663 bgeu x14,x28,8a8 <__udivdi3+0x360>
- 8a0: ffee8513 addi x10,x29,-2
- 8a4: 00d70733 add x14,x14,x13
- 8a8: 41c70733 sub x14,x14,x28
- 8ac: 03175e33 divu x28,x14,x17
- 8b0: 01079793 slli x15,x15,0x10
- 8b4: 0107d793 srli x15,x15,0x10
- 8b8: 03177733 remu x14,x14,x17
- 8bc: 03c80833 mul x16,x16,x28
- 8c0: 01071713 slli x14,x14,0x10
- 8c4: 00e7e7b3 or x15,x15,x14
- 8c8: 000e0713 addi x14,x28,0
- 8cc: 0107fe63 bgeu x15,x16,8e8 <__udivdi3+0x3a0>
- 8d0: 00d787b3 add x15,x15,x13
- 8d4: fffe0713 addi x14,x28,-1
- 8d8: 00d7e863 bltu x15,x13,8e8 <__udivdi3+0x3a0>
- 8dc: 0107f663 bgeu x15,x16,8e8 <__udivdi3+0x3a0>
- 8e0: ffee0713 addi x14,x28,-2
- 8e4: 00d787b3 add x15,x15,x13
- 8e8: 01051513 slli x10,x10,0x10
- 8ec: 00010e37 lui x28,0x10
- 8f0: 00e56533 or x10,x10,x14
- 8f4: fffe0693 addi x13,x28,-1 # ffff <__global_pointer$+0xe7c7>
- 8f8: 00d57733 and x14,x10,x13
- 8fc: 410787b3 sub x15,x15,x16
- 900: 00d676b3 and x13,x12,x13
- 904: 01055813 srli x16,x10,0x10
- 908: 01065613 srli x12,x12,0x10
- 90c: 02d708b3 mul x17,x14,x13
- 910: 02d806b3 mul x13,x16,x13
- 914: 02c70733 mul x14,x14,x12
- 918: 02c80833 mul x16,x16,x12
- 91c: 00d70633 add x12,x14,x13
- 920: 0108d713 srli x14,x17,0x10
- 924: 00c70733 add x14,x14,x12
- 928: 00d77463 bgeu x14,x13,930 <__udivdi3+0x3e8>
- 92c: 01c80833 add x16,x16,x28
- 930: 01075693 srli x13,x14,0x10
- 934: 010686b3 add x13,x13,x16
- 938: 02d7e663 bltu x15,x13,964 <__udivdi3+0x41c>
- 93c: ced79ee3 bne x15,x13,638 <__udivdi3+0xf0>
- 940: 000107b7 lui x15,0x10
- 944: fff78793 addi x15,x15,-1 # ffff <__global_pointer$+0xe7c7>
- 948: 00f77733 and x14,x14,x15
- 94c: 01071713 slli x14,x14,0x10
- 950: 00f8f8b3 and x17,x17,x15
- 954: 00b31333 sll x6,x6,x11
- 958: 01170733 add x14,x14,x17
- 95c: 00000593 addi x11,x0,0
- 960: cce37ee3 bgeu x6,x14,63c <__udivdi3+0xf4>
- 964: fff50513 addi x10,x10,-1 # ffffff <__global_pointer$+0xffe7c7>
- 968: cd1ff06f jal x0,638 <__udivdi3+0xf0>
- 96c: 00000593 addi x11,x0,0
- 970: 00000513 addi x10,x0,0
- 974: 00008067 jalr x0,0(x1)
+00000524 <__udivdi3>:
+ 524: 00050313 addi x6,x10,0
+ 528: 00058893 addi x17,x11,0
+ 52c: 00060713 addi x14,x12,0
+ 530: 00050813 addi x16,x10,0
+ 534: 00058793 addi x15,x11,0
+ 538: 28069263 bne x13,x0,7bc <__udivdi3+0x298>
+ 53c: 000015b7 lui x11,0x1
+ 540: d8458593 addi x11,x11,-636 # d84 <__clz_tab>
+ 544: 0ec8f663 bgeu x17,x12,630 <__udivdi3+0x10c>
+ 548: 000106b7 lui x13,0x10
+ 54c: 0cd67863 bgeu x12,x13,61c <__udivdi3+0xf8>
+ 550: 10063693 sltiu x13,x12,256
+ 554: 0016c693 xori x13,x13,1
+ 558: 00369693 slli x13,x13,0x3
+ 55c: 00d65533 srl x10,x12,x13
+ 560: 00a585b3 add x11,x11,x10
+ 564: 0005c583 lbu x11,0(x11)
+ 568: 02000513 addi x10,x0,32
+ 56c: 00d586b3 add x13,x11,x13
+ 570: 40d505b3 sub x11,x10,x13
+ 574: 00d50c63 beq x10,x13,58c <__udivdi3+0x68>
+ 578: 00b897b3 sll x15,x17,x11
+ 57c: 00d356b3 srl x13,x6,x13
+ 580: 00b61733 sll x14,x12,x11
+ 584: 00f6e7b3 or x15,x13,x15
+ 588: 00b31833 sll x16,x6,x11
+ 58c: 01075593 srli x11,x14,0x10
+ 590: 02b7d333 divu x6,x15,x11
+ 594: 01071613 slli x12,x14,0x10
+ 598: 01065613 srli x12,x12,0x10
+ 59c: 02b7f7b3 remu x15,x15,x11
+ 5a0: 00030513 addi x10,x6,0 # 130
+ 5a4: 026608b3 mul x17,x12,x6
+ 5a8: 01079693 slli x13,x15,0x10
+ 5ac: 01085793 srli x15,x16,0x10
+ 5b0: 00d7e7b3 or x15,x15,x13
+ 5b4: 0117fe63 bgeu x15,x17,5d0 <__udivdi3+0xac>
+ 5b8: 00e787b3 add x15,x15,x14
+ 5bc: fff30513 addi x10,x6,-1
+ 5c0: 00e7e863 bltu x15,x14,5d0 <__udivdi3+0xac>
+ 5c4: 0117f663 bgeu x15,x17,5d0 <__udivdi3+0xac>
+ 5c8: ffe30513 addi x10,x6,-2
+ 5cc: 00e787b3 add x15,x15,x14
+ 5d0: 411787b3 sub x15,x15,x17
+ 5d4: 02b7d8b3 divu x17,x15,x11
+ 5d8: 01081813 slli x16,x16,0x10
+ 5dc: 01085813 srli x16,x16,0x10
+ 5e0: 02b7f7b3 remu x15,x15,x11
+ 5e4: 031606b3 mul x13,x12,x17
+ 5e8: 01079793 slli x15,x15,0x10
+ 5ec: 00f86833 or x16,x16,x15
+ 5f0: 00088793 addi x15,x17,0
+ 5f4: 00d87c63 bgeu x16,x13,60c <__udivdi3+0xe8>
+ 5f8: 01070833 add x16,x14,x16
+ 5fc: fff88793 addi x15,x17,-1
+ 600: 00e86663 bltu x16,x14,60c <__udivdi3+0xe8>
+ 604: 00d87463 bgeu x16,x13,60c <__udivdi3+0xe8>
+ 608: ffe88793 addi x15,x17,-2
+ 60c: 01051513 slli x10,x10,0x10
+ 610: 00f56533 or x10,x10,x15
+ 614: 00000593 addi x11,x0,0
+ 618: 00008067 jalr x0,0(x1)
+ 61c: 01000537 lui x10,0x1000
+ 620: 01000693 addi x13,x0,16
+ 624: f2a66ce3 bltu x12,x10,55c <__udivdi3+0x38>
+ 628: 01800693 addi x13,x0,24
+ 62c: f31ff06f jal x0,55c <__udivdi3+0x38>
+ 630: 00061463 bne x12,x0,638 <__udivdi3+0x114>
+ 634: 00100073 ebreak
+ 638: 000107b7 lui x15,0x10
+ 63c: 0cf67063 bgeu x12,x15,6fc <__udivdi3+0x1d8>
+ 640: 10063693 sltiu x13,x12,256
+ 644: 0016c693 xori x13,x13,1
+ 648: 00369693 slli x13,x13,0x3
+ 64c: 00d657b3 srl x15,x12,x13
+ 650: 00f585b3 add x11,x11,x15
+ 654: 0005c783 lbu x15,0(x11)
+ 658: 00d787b3 add x15,x15,x13
+ 65c: 02000693 addi x13,x0,32
+ 660: 40f685b3 sub x11,x13,x15
+ 664: 0af69663 bne x13,x15,710 <__udivdi3+0x1ec>
+ 668: 40c887b3 sub x15,x17,x12
+ 66c: 00100593 addi x11,x0,1
+ 670: 01075893 srli x17,x14,0x10
+ 674: 0317de33 divu x28,x15,x17
+ 678: 01071613 slli x12,x14,0x10
+ 67c: 01065613 srli x12,x12,0x10
+ 680: 01085693 srli x13,x16,0x10
+ 684: 0317f7b3 remu x15,x15,x17
+ 688: 000e0513 addi x10,x28,0
+ 68c: 03c60333 mul x6,x12,x28
+ 690: 01079793 slli x15,x15,0x10
+ 694: 00f6e7b3 or x15,x13,x15
+ 698: 0067fe63 bgeu x15,x6,6b4 <__udivdi3+0x190>
+ 69c: 00e787b3 add x15,x15,x14
+ 6a0: fffe0513 addi x10,x28,-1
+ 6a4: 00e7e863 bltu x15,x14,6b4 <__udivdi3+0x190>
+ 6a8: 0067f663 bgeu x15,x6,6b4 <__udivdi3+0x190>
+ 6ac: ffee0513 addi x10,x28,-2
+ 6b0: 00e787b3 add x15,x15,x14
+ 6b4: 406787b3 sub x15,x15,x6
+ 6b8: 0317d333 divu x6,x15,x17
+ 6bc: 01081813 slli x16,x16,0x10
+ 6c0: 01085813 srli x16,x16,0x10
+ 6c4: 0317f7b3 remu x15,x15,x17
+ 6c8: 026606b3 mul x13,x12,x6
+ 6cc: 01079793 slli x15,x15,0x10
+ 6d0: 00f86833 or x16,x16,x15
+ 6d4: 00030793 addi x15,x6,0
+ 6d8: 00d87c63 bgeu x16,x13,6f0 <__udivdi3+0x1cc>
+ 6dc: 01070833 add x16,x14,x16
+ 6e0: fff30793 addi x15,x6,-1
+ 6e4: 00e86663 bltu x16,x14,6f0 <__udivdi3+0x1cc>
+ 6e8: 00d87463 bgeu x16,x13,6f0 <__udivdi3+0x1cc>
+ 6ec: ffe30793 addi x15,x6,-2
+ 6f0: 01051513 slli x10,x10,0x10
+ 6f4: 00f56533 or x10,x10,x15
+ 6f8: 00008067 jalr x0,0(x1)
+ 6fc: 010007b7 lui x15,0x1000
+ 700: 01000693 addi x13,x0,16
+ 704: f4f664e3 bltu x12,x15,64c <__udivdi3+0x128>
+ 708: 01800693 addi x13,x0,24
+ 70c: f41ff06f jal x0,64c <__udivdi3+0x128>
+ 710: 00b61733 sll x14,x12,x11
+ 714: 00f8d6b3 srl x13,x17,x15
+ 718: 01075513 srli x10,x14,0x10
+ 71c: 00f357b3 srl x15,x6,x15
+ 720: 00b31833 sll x16,x6,x11
+ 724: 02a6d333 divu x6,x13,x10
+ 728: 01071613 slli x12,x14,0x10
+ 72c: 00b898b3 sll x17,x17,x11
+ 730: 01065613 srli x12,x12,0x10
+ 734: 0117e7b3 or x15,x15,x17
+ 738: 02a6f6b3 remu x13,x13,x10
+ 73c: 026608b3 mul x17,x12,x6
+ 740: 01069593 slli x11,x13,0x10
+ 744: 0107d693 srli x13,x15,0x10
+ 748: 00b6e6b3 or x13,x13,x11
+ 74c: 00030593 addi x11,x6,0
+ 750: 0116fe63 bgeu x13,x17,76c <__udivdi3+0x248>
+ 754: 00e686b3 add x13,x13,x14
+ 758: fff30593 addi x11,x6,-1
+ 75c: 00e6e863 bltu x13,x14,76c <__udivdi3+0x248>
+ 760: 0116f663 bgeu x13,x17,76c <__udivdi3+0x248>
+ 764: ffe30593 addi x11,x6,-2
+ 768: 00e686b3 add x13,x13,x14
+ 76c: 411686b3 sub x13,x13,x17
+ 770: 02a6d8b3 divu x17,x13,x10
+ 774: 01079793 slli x15,x15,0x10
+ 778: 0107d793 srli x15,x15,0x10
+ 77c: 02a6f6b3 remu x13,x13,x10
+ 780: 03160633 mul x12,x12,x17
+ 784: 01069693 slli x13,x13,0x10
+ 788: 00d7e7b3 or x15,x15,x13
+ 78c: 00088693 addi x13,x17,0
+ 790: 00c7fe63 bgeu x15,x12,7ac <__udivdi3+0x288>
+ 794: 00e787b3 add x15,x15,x14
+ 798: fff88693 addi x13,x17,-1
+ 79c: 00e7e863 bltu x15,x14,7ac <__udivdi3+0x288>
+ 7a0: 00c7f663 bgeu x15,x12,7ac <__udivdi3+0x288>
+ 7a4: ffe88693 addi x13,x17,-2
+ 7a8: 00e787b3 add x15,x15,x14
+ 7ac: 01059593 slli x11,x11,0x10
+ 7b0: 40c787b3 sub x15,x15,x12
+ 7b4: 00d5e5b3 or x11,x11,x13
+ 7b8: eb9ff06f jal x0,670 <__udivdi3+0x14c>
+ 7bc: 18d5e663 bltu x11,x13,948 <__udivdi3+0x424>
+ 7c0: 000107b7 lui x15,0x10
+ 7c4: 04f6f463 bgeu x13,x15,80c <__udivdi3+0x2e8>
+ 7c8: 1006b713 sltiu x14,x13,256
+ 7cc: 00174713 xori x14,x14,1
+ 7d0: 00371713 slli x14,x14,0x3
+ 7d4: 000017b7 lui x15,0x1
+ 7d8: 00e6d5b3 srl x11,x13,x14
+ 7dc: d8478793 addi x15,x15,-636 # d84 <__clz_tab>
+ 7e0: 00b787b3 add x15,x15,x11
+ 7e4: 0007c783 lbu x15,0(x15)
+ 7e8: 00e787b3 add x15,x15,x14
+ 7ec: 02000713 addi x14,x0,32
+ 7f0: 40f705b3 sub x11,x14,x15
+ 7f4: 02f71663 bne x14,x15,820 <__udivdi3+0x2fc>
+ 7f8: 00100513 addi x10,x0,1
+ 7fc: e116eee3 bltu x13,x17,618 <__udivdi3+0xf4>
+ 800: 00c33533 sltu x10,x6,x12
+ 804: 00154513 xori x10,x10,1
+ 808: 00008067 jalr x0,0(x1)
+ 80c: 010007b7 lui x15,0x1000
+ 810: 01000713 addi x14,x0,16
+ 814: fcf6e0e3 bltu x13,x15,7d4 <__udivdi3+0x2b0>
+ 818: 01800713 addi x14,x0,24
+ 81c: fb9ff06f jal x0,7d4 <__udivdi3+0x2b0>
+ 820: 00f65733 srl x14,x12,x15
+ 824: 00b696b3 sll x13,x13,x11
+ 828: 00d766b3 or x13,x14,x13
+ 82c: 00f8d733 srl x14,x17,x15
+ 830: 00b898b3 sll x17,x17,x11
+ 834: 00f357b3 srl x15,x6,x15
+ 838: 0117e7b3 or x15,x15,x17
+ 83c: 0106d893 srli x17,x13,0x10
+ 840: 03175eb3 divu x29,x14,x17
+ 844: 01069813 slli x16,x13,0x10
+ 848: 01085813 srli x16,x16,0x10
+ 84c: 00b61633 sll x12,x12,x11
+ 850: 03177733 remu x14,x14,x17
+ 854: 03d80e33 mul x28,x16,x29
+ 858: 01071513 slli x10,x14,0x10
+ 85c: 0107d713 srli x14,x15,0x10
+ 860: 00a76733 or x14,x14,x10
+ 864: 000e8513 addi x10,x29,0
+ 868: 01c77e63 bgeu x14,x28,884 <__udivdi3+0x360>
+ 86c: 00d70733 add x14,x14,x13
+ 870: fffe8513 addi x10,x29,-1
+ 874: 00d76863 bltu x14,x13,884 <__udivdi3+0x360>
+ 878: 01c77663 bgeu x14,x28,884 <__udivdi3+0x360>
+ 87c: ffee8513 addi x10,x29,-2
+ 880: 00d70733 add x14,x14,x13
+ 884: 41c70733 sub x14,x14,x28
+ 888: 03175e33 divu x28,x14,x17
+ 88c: 01079793 slli x15,x15,0x10
+ 890: 0107d793 srli x15,x15,0x10
+ 894: 03177733 remu x14,x14,x17
+ 898: 03c80833 mul x16,x16,x28
+ 89c: 01071713 slli x14,x14,0x10
+ 8a0: 00e7e7b3 or x15,x15,x14
+ 8a4: 000e0713 addi x14,x28,0
+ 8a8: 0107fe63 bgeu x15,x16,8c4 <__udivdi3+0x3a0>
+ 8ac: 00d787b3 add x15,x15,x13
+ 8b0: fffe0713 addi x14,x28,-1
+ 8b4: 00d7e863 bltu x15,x13,8c4 <__udivdi3+0x3a0>
+ 8b8: 0107f663 bgeu x15,x16,8c4 <__udivdi3+0x3a0>
+ 8bc: ffee0713 addi x14,x28,-2
+ 8c0: 00d787b3 add x15,x15,x13
+ 8c4: 01051513 slli x10,x10,0x10
+ 8c8: 00010e37 lui x28,0x10
+ 8cc: 00e56533 or x10,x10,x14
+ 8d0: fffe0693 addi x13,x28,-1 # ffff <__global_pointer$+0xe7c7>
+ 8d4: 00d57733 and x14,x10,x13
+ 8d8: 410787b3 sub x15,x15,x16
+ 8dc: 00d676b3 and x13,x12,x13
+ 8e0: 01055813 srli x16,x10,0x10
+ 8e4: 01065613 srli x12,x12,0x10
+ 8e8: 02d708b3 mul x17,x14,x13
+ 8ec: 02d806b3 mul x13,x16,x13
+ 8f0: 02c70733 mul x14,x14,x12
+ 8f4: 02c80833 mul x16,x16,x12
+ 8f8: 00d70633 add x12,x14,x13
+ 8fc: 0108d713 srli x14,x17,0x10
+ 900: 00c70733 add x14,x14,x12
+ 904: 00d77463 bgeu x14,x13,90c <__udivdi3+0x3e8>
+ 908: 01c80833 add x16,x16,x28
+ 90c: 01075693 srli x13,x14,0x10
+ 910: 010686b3 add x13,x13,x16
+ 914: 02d7e663 bltu x15,x13,940 <__udivdi3+0x41c>
+ 918: ced79ee3 bne x15,x13,614 <__udivdi3+0xf0>
+ 91c: 000107b7 lui x15,0x10
+ 920: fff78793 addi x15,x15,-1 # ffff <__global_pointer$+0xe7c7>
+ 924: 00f77733 and x14,x14,x15
+ 928: 01071713 slli x14,x14,0x10
+ 92c: 00f8f8b3 and x17,x17,x15
+ 930: 00b31333 sll x6,x6,x11
+ 934: 01170733 add x14,x14,x17
+ 938: 00000593 addi x11,x0,0
+ 93c: cce37ee3 bgeu x6,x14,618 <__udivdi3+0xf4>
+ 940: fff50513 addi x10,x10,-1 # ffffff <__global_pointer$+0xffe7c7>
+ 944: cd1ff06f jal x0,614 <__udivdi3+0xf0>
+ 948: 00000593 addi x11,x0,0
+ 94c: 00000513 addi x10,x0,0
+ 950: 00008067 jalr x0,0(x1)
-00000978 :
- 978: ff010113 addi x2,x2,-16
- 97c: 00000593 addi x11,x0,0
- 980: 00812423 sw x8,8(x2)
- 984: 00112623 sw x1,12(x2)
- 988: 00050413 addi x8,x10,0
- 98c: 194000ef jal x1,b20 <__call_exitprocs>
- 990: c281a503 lw x10,-984(x3) # 1460 <_global_impure_ptr>
- 994: 03c52783 lw x15,60(x10)
- 998: 00078463 beq x15,x0,9a0
- 99c: 000780e7 jalr x1,0(x15)
- 9a0: 00040513 addi x10,x8,0
- 9a4: 3a4000ef jal x1,d48 <_exit>
+00000954 :
+ 954: ff010113 addi x2,x2,-16
+ 958: 00000593 addi x11,x0,0
+ 95c: 00812423 sw x8,8(x2)
+ 960: 00112623 sw x1,12(x2)
+ 964: 00050413 addi x8,x10,0
+ 968: 194000ef jal x1,afc <__call_exitprocs>
+ 96c: c281a503 lw x10,-984(x3) # 1460 <_global_impure_ptr>
+ 970: 03c52783 lw x15,60(x10)
+ 974: 00078463 beq x15,x0,97c
+ 978: 000780e7 jalr x1,0(x15)
+ 97c: 00040513 addi x10,x8,0
+ 980: 3a4000ef jal x1,d24 <_exit>
-000009a8 <__libc_init_array>:
- 9a8: ff010113 addi x2,x2,-16
- 9ac: 00812423 sw x8,8(x2)
- 9b0: 01212023 sw x18,0(x2)
- 9b4: 00001437 lui x8,0x1
- 9b8: 00001937 lui x18,0x1
- 9bc: 02c40793 addi x15,x8,44 # 102c <__init_array_start>
- 9c0: 02c90913 addi x18,x18,44 # 102c <__init_array_start>
- 9c4: 40f90933 sub x18,x18,x15
- 9c8: 00112623 sw x1,12(x2)
- 9cc: 00912223 sw x9,4(x2)
- 9d0: 40295913 srai x18,x18,0x2
- 9d4: 02090063 beq x18,x0,9f4 <__libc_init_array+0x4c>
- 9d8: 02c40413 addi x8,x8,44
- 9dc: 00000493 addi x9,x0,0
- 9e0: 00042783 lw x15,0(x8)
- 9e4: 00148493 addi x9,x9,1
- 9e8: 00440413 addi x8,x8,4
- 9ec: 000780e7 jalr x1,0(x15)
- 9f0: fe9918e3 bne x18,x9,9e0 <__libc_init_array+0x38>
- 9f4: 00001437 lui x8,0x1
- 9f8: 00001937 lui x18,0x1
- 9fc: 02c40793 addi x15,x8,44 # 102c <__init_array_start>
- a00: 03490913 addi x18,x18,52 # 1034 <__do_global_dtors_aux_fini_array_entry>
- a04: 40f90933 sub x18,x18,x15
- a08: 40295913 srai x18,x18,0x2
- a0c: 02090063 beq x18,x0,a2c <__libc_init_array+0x84>
- a10: 02c40413 addi x8,x8,44
- a14: 00000493 addi x9,x0,0
- a18: 00042783 lw x15,0(x8)
- a1c: 00148493 addi x9,x9,1
- a20: 00440413 addi x8,x8,4
- a24: 000780e7 jalr x1,0(x15)
- a28: fe9918e3 bne x18,x9,a18 <__libc_init_array+0x70>
- a2c: 00c12083 lw x1,12(x2)
- a30: 00812403 lw x8,8(x2)
- a34: 00412483 lw x9,4(x2)
- a38: 00012903 lw x18,0(x2)
- a3c: 01010113 addi x2,x2,16
- a40: 00008067 jalr x0,0(x1)
+00000984 <__libc_init_array>:
+ 984: ff010113 addi x2,x2,-16
+ 988: 00812423 sw x8,8(x2)
+ 98c: 01212023 sw x18,0(x2)
+ 990: 00001437 lui x8,0x1
+ 994: 00001937 lui x18,0x1
+ 998: 02c40793 addi x15,x8,44 # 102c <__init_array_start>
+ 99c: 02c90913 addi x18,x18,44 # 102c <__init_array_start>
+ 9a0: 40f90933 sub x18,x18,x15
+ 9a4: 00112623 sw x1,12(x2)
+ 9a8: 00912223 sw x9,4(x2)
+ 9ac: 40295913 srai x18,x18,0x2
+ 9b0: 02090063 beq x18,x0,9d0 <__libc_init_array+0x4c>
+ 9b4: 02c40413 addi x8,x8,44
+ 9b8: 00000493 addi x9,x0,0
+ 9bc: 00042783 lw x15,0(x8)
+ 9c0: 00148493 addi x9,x9,1
+ 9c4: 00440413 addi x8,x8,4
+ 9c8: 000780e7 jalr x1,0(x15)
+ 9cc: fe9918e3 bne x18,x9,9bc <__libc_init_array+0x38>
+ 9d0: 00001437 lui x8,0x1
+ 9d4: 00001937 lui x18,0x1
+ 9d8: 02c40793 addi x15,x8,44 # 102c <__init_array_start>
+ 9dc: 03490913 addi x18,x18,52 # 1034 <__do_global_dtors_aux_fini_array_entry>
+ 9e0: 40f90933 sub x18,x18,x15
+ 9e4: 40295913 srai x18,x18,0x2
+ 9e8: 02090063 beq x18,x0,a08 <__libc_init_array+0x84>
+ 9ec: 02c40413 addi x8,x8,44
+ 9f0: 00000493 addi x9,x0,0
+ 9f4: 00042783 lw x15,0(x8)
+ 9f8: 00148493 addi x9,x9,1
+ 9fc: 00440413 addi x8,x8,4
+ a00: 000780e7 jalr x1,0(x15)
+ a04: fe9918e3 bne x18,x9,9f4 <__libc_init_array+0x70>
+ a08: 00c12083 lw x1,12(x2)
+ a0c: 00812403 lw x8,8(x2)
+ a10: 00412483 lw x9,4(x2)
+ a14: 00012903 lw x18,0(x2)
+ a18: 01010113 addi x2,x2,16
+ a1c: 00008067 jalr x0,0(x1)
-00000a44 :
- a44: 00f00313 addi x6,x0,15
- a48: 00050713 addi x14,x10,0
- a4c: 02c37e63 bgeu x6,x12,a88
- a50: 00f77793 andi x15,x14,15
- a54: 0a079063 bne x15,x0,af4
- a58: 08059263 bne x11,x0,adc
- a5c: ff067693 andi x13,x12,-16
- a60: 00f67613 andi x12,x12,15
- a64: 00e686b3 add x13,x13,x14
- a68: 00b72023 sw x11,0(x14)
- a6c: 00b72223 sw x11,4(x14)
- a70: 00b72423 sw x11,8(x14)
- a74: 00b72623 sw x11,12(x14)
- a78: 01070713 addi x14,x14,16
- a7c: fed766e3 bltu x14,x13,a68
- a80: 00061463 bne x12,x0,a88
- a84: 00008067 jalr x0,0(x1)
- a88: 40c306b3 sub x13,x6,x12
- a8c: 00269693 slli x13,x13,0x2
- a90: 00000297 auipc x5,0x0
- a94: 005686b3 add x13,x13,x5
- a98: 00c68067 jalr x0,12(x13) # 1000c <__global_pointer$+0xe7d4>
- a9c: 00b70723 sb x11,14(x14)
- aa0: 00b706a3 sb x11,13(x14)
- aa4: 00b70623 sb x11,12(x14)
- aa8: 00b705a3 sb x11,11(x14)
- aac: 00b70523 sb x11,10(x14)
- ab0: 00b704a3 sb x11,9(x14)
- ab4: 00b70423 sb x11,8(x14)
- ab8: 00b703a3 sb x11,7(x14)
- abc: 00b70323 sb x11,6(x14)
- ac0: 00b702a3 sb x11,5(x14)
- ac4: 00b70223 sb x11,4(x14)
- ac8: 00b701a3 sb x11,3(x14)
- acc: 00b70123 sb x11,2(x14)
- ad0: 00b700a3 sb x11,1(x14)
- ad4: 00b70023 sb x11,0(x14)
- ad8: 00008067 jalr x0,0(x1)
- adc: 0ff5f593 andi x11,x11,255
- ae0: 00859693 slli x13,x11,0x8
- ae4: 00d5e5b3 or x11,x11,x13
- ae8: 01059693 slli x13,x11,0x10
- aec: 00d5e5b3 or x11,x11,x13
- af0: f6dff06f jal x0,a5c
- af4: 00279693 slli x13,x15,0x2
- af8: 00000297 auipc x5,0x0
- afc: 005686b3 add x13,x13,x5
- b00: 00008293 addi x5,x1,0
- b04: fa0680e7 jalr x1,-96(x13)
- b08: 00028093 addi x1,x5,0 # af8
- b0c: ff078793 addi x15,x15,-16
- b10: 40f70733 sub x14,x14,x15
- b14: 00f60633 add x12,x12,x15
- b18: f6c378e3 bgeu x6,x12,a88
- b1c: f3dff06f jal x0,a58
+00000a20 :
+ a20: 00f00313 addi x6,x0,15
+ a24: 00050713 addi x14,x10,0
+ a28: 02c37e63 bgeu x6,x12,a64
+ a2c: 00f77793 andi x15,x14,15
+ a30: 0a079063 bne x15,x0,ad0
+ a34: 08059263 bne x11,x0,ab8
+ a38: ff067693 andi x13,x12,-16
+ a3c: 00f67613 andi x12,x12,15
+ a40: 00e686b3 add x13,x13,x14
+ a44: 00b72023 sw x11,0(x14)
+ a48: 00b72223 sw x11,4(x14)
+ a4c: 00b72423 sw x11,8(x14)
+ a50: 00b72623 sw x11,12(x14)
+ a54: 01070713 addi x14,x14,16
+ a58: fed766e3 bltu x14,x13,a44
+ a5c: 00061463 bne x12,x0,a64
+ a60: 00008067 jalr x0,0(x1)
+ a64: 40c306b3 sub x13,x6,x12
+ a68: 00269693 slli x13,x13,0x2
+ a6c: 00000297 auipc x5,0x0
+ a70: 005686b3 add x13,x13,x5
+ a74: 00c68067 jalr x0,12(x13) # 1000c <__global_pointer$+0xe7d4>
+ a78: 00b70723 sb x11,14(x14)
+ a7c: 00b706a3 sb x11,13(x14)
+ a80: 00b70623 sb x11,12(x14)
+ a84: 00b705a3 sb x11,11(x14)
+ a88: 00b70523 sb x11,10(x14)
+ a8c: 00b704a3 sb x11,9(x14)
+ a90: 00b70423 sb x11,8(x14)
+ a94: 00b703a3 sb x11,7(x14)
+ a98: 00b70323 sb x11,6(x14)
+ a9c: 00b702a3 sb x11,5(x14)
+ aa0: 00b70223 sb x11,4(x14)
+ aa4: 00b701a3 sb x11,3(x14)
+ aa8: 00b70123 sb x11,2(x14)
+ aac: 00b700a3 sb x11,1(x14)
+ ab0: 00b70023 sb x11,0(x14)
+ ab4: 00008067 jalr x0,0(x1)
+ ab8: 0ff5f593 andi x11,x11,255
+ abc: 00859693 slli x13,x11,0x8
+ ac0: 00d5e5b3 or x11,x11,x13
+ ac4: 01059693 slli x13,x11,0x10
+ ac8: 00d5e5b3 or x11,x11,x13
+ acc: f6dff06f jal x0,a38
+ ad0: 00279693 slli x13,x15,0x2
+ ad4: 00000297 auipc x5,0x0
+ ad8: 005686b3 add x13,x13,x5
+ adc: 00008293 addi x5,x1,0
+ ae0: fa0680e7 jalr x1,-96(x13)
+ ae4: 00028093 addi x1,x5,0 # ad4
+ ae8: ff078793 addi x15,x15,-16
+ aec: 40f70733 sub x14,x14,x15
+ af0: 00f60633 add x12,x12,x15
+ af4: f6c378e3 bgeu x6,x12,a64
+ af8: f3dff06f jal x0,a34
-00000b20 <__call_exitprocs>:
- b20: fd010113 addi x2,x2,-48
- b24: 01412c23 sw x20,24(x2)
- b28: c281aa03 lw x20,-984(x3) # 1460 <_global_impure_ptr>
- b2c: 03212023 sw x18,32(x2)
- b30: 02112623 sw x1,44(x2)
- b34: 148a2903 lw x18,328(x20)
- b38: 02812423 sw x8,40(x2)
- b3c: 02912223 sw x9,36(x2)
- b40: 01312e23 sw x19,28(x2)
- b44: 01512a23 sw x21,20(x2)
- b48: 01612823 sw x22,16(x2)
- b4c: 01712623 sw x23,12(x2)
- b50: 01812423 sw x24,8(x2)
- b54: 04090063 beq x18,x0,b94 <__call_exitprocs+0x74>
- b58: 00050b13 addi x22,x10,0
- b5c: 00058b93 addi x23,x11,0
- b60: 00100a93 addi x21,x0,1
- b64: fff00993 addi x19,x0,-1
- b68: 00492483 lw x9,4(x18)
- b6c: fff48413 addi x8,x9,-1
- b70: 02044263 blt x8,x0,b94 <__call_exitprocs+0x74>
- b74: 00249493 slli x9,x9,0x2
- b78: 009904b3 add x9,x18,x9
- b7c: 040b8463 beq x23,x0,bc4 <__call_exitprocs+0xa4>
- b80: 1044a783 lw x15,260(x9)
- b84: 05778063 beq x15,x23,bc4 <__call_exitprocs+0xa4>
- b88: fff40413 addi x8,x8,-1
- b8c: ffc48493 addi x9,x9,-4
- b90: ff3416e3 bne x8,x19,b7c <__call_exitprocs+0x5c>
- b94: 02c12083 lw x1,44(x2)
- b98: 02812403 lw x8,40(x2)
- b9c: 02412483 lw x9,36(x2)
- ba0: 02012903 lw x18,32(x2)
- ba4: 01c12983 lw x19,28(x2)
- ba8: 01812a03 lw x20,24(x2)
- bac: 01412a83 lw x21,20(x2)
- bb0: 01012b03 lw x22,16(x2)
- bb4: 00c12b83 lw x23,12(x2)
- bb8: 00812c03 lw x24,8(x2)
- bbc: 03010113 addi x2,x2,48
- bc0: 00008067 jalr x0,0(x1)
- bc4: 00492783 lw x15,4(x18)
- bc8: 0044a683 lw x13,4(x9)
- bcc: fff78793 addi x15,x15,-1
- bd0: 04878e63 beq x15,x8,c2c <__call_exitprocs+0x10c>
- bd4: 0004a223 sw x0,4(x9)
- bd8: fa0688e3 beq x13,x0,b88 <__call_exitprocs+0x68>
- bdc: 18892783 lw x15,392(x18)
- be0: 008a9733 sll x14,x21,x8
- be4: 00492c03 lw x24,4(x18)
- be8: 00f777b3 and x15,x14,x15
- bec: 02079263 bne x15,x0,c10 <__call_exitprocs+0xf0>
- bf0: 000680e7 jalr x1,0(x13)
- bf4: 00492703 lw x14,4(x18)
- bf8: 148a2783 lw x15,328(x20)
- bfc: 01871463 bne x14,x24,c04 <__call_exitprocs+0xe4>
- c00: f92784e3 beq x15,x18,b88 <__call_exitprocs+0x68>
- c04: f80788e3 beq x15,x0,b94 <__call_exitprocs+0x74>
- c08: 00078913 addi x18,x15,0
- c0c: f5dff06f jal x0,b68 <__call_exitprocs+0x48>
- c10: 18c92783 lw x15,396(x18)
- c14: 0844a583 lw x11,132(x9)
- c18: 00f77733 and x14,x14,x15
- c1c: 00071c63 bne x14,x0,c34 <__call_exitprocs+0x114>
- c20: 000b0513 addi x10,x22,0
- c24: 000680e7 jalr x1,0(x13)
- c28: fcdff06f jal x0,bf4 <__call_exitprocs+0xd4>
- c2c: 00892223 sw x8,4(x18)
- c30: fa9ff06f jal x0,bd8 <__call_exitprocs+0xb8>
- c34: 00058513 addi x10,x11,0
- c38: 000680e7 jalr x1,0(x13)
- c3c: fb9ff06f jal x0,bf4 <__call_exitprocs+0xd4>
+00000afc <__call_exitprocs>:
+ afc: fd010113 addi x2,x2,-48
+ b00: 01412c23 sw x20,24(x2)
+ b04: c281aa03 lw x20,-984(x3) # 1460 <_global_impure_ptr>
+ b08: 03212023 sw x18,32(x2)
+ b0c: 02112623 sw x1,44(x2)
+ b10: 148a2903 lw x18,328(x20)
+ b14: 02812423 sw x8,40(x2)
+ b18: 02912223 sw x9,36(x2)
+ b1c: 01312e23 sw x19,28(x2)
+ b20: 01512a23 sw x21,20(x2)
+ b24: 01612823 sw x22,16(x2)
+ b28: 01712623 sw x23,12(x2)
+ b2c: 01812423 sw x24,8(x2)
+ b30: 04090063 beq x18,x0,b70 <__call_exitprocs+0x74>
+ b34: 00050b13 addi x22,x10,0
+ b38: 00058b93 addi x23,x11,0
+ b3c: 00100a93 addi x21,x0,1
+ b40: fff00993 addi x19,x0,-1
+ b44: 00492483 lw x9,4(x18)
+ b48: fff48413 addi x8,x9,-1
+ b4c: 02044263 blt x8,x0,b70 <__call_exitprocs+0x74>
+ b50: 00249493 slli x9,x9,0x2
+ b54: 009904b3 add x9,x18,x9
+ b58: 040b8463 beq x23,x0,ba0 <__call_exitprocs+0xa4>
+ b5c: 1044a783 lw x15,260(x9)
+ b60: 05778063 beq x15,x23,ba0 <__call_exitprocs+0xa4>
+ b64: fff40413 addi x8,x8,-1
+ b68: ffc48493 addi x9,x9,-4
+ b6c: ff3416e3 bne x8,x19,b58 <__call_exitprocs+0x5c>
+ b70: 02c12083 lw x1,44(x2)
+ b74: 02812403 lw x8,40(x2)
+ b78: 02412483 lw x9,36(x2)
+ b7c: 02012903 lw x18,32(x2)
+ b80: 01c12983 lw x19,28(x2)
+ b84: 01812a03 lw x20,24(x2)
+ b88: 01412a83 lw x21,20(x2)
+ b8c: 01012b03 lw x22,16(x2)
+ b90: 00c12b83 lw x23,12(x2)
+ b94: 00812c03 lw x24,8(x2)
+ b98: 03010113 addi x2,x2,48
+ b9c: 00008067 jalr x0,0(x1)
+ ba0: 00492783 lw x15,4(x18)
+ ba4: 0044a683 lw x13,4(x9)
+ ba8: fff78793 addi x15,x15,-1
+ bac: 04878e63 beq x15,x8,c08 <__call_exitprocs+0x10c>
+ bb0: 0004a223 sw x0,4(x9)
+ bb4: fa0688e3 beq x13,x0,b64 <__call_exitprocs+0x68>
+ bb8: 18892783 lw x15,392(x18)
+ bbc: 008a9733 sll x14,x21,x8
+ bc0: 00492c03 lw x24,4(x18)
+ bc4: 00f777b3 and x15,x14,x15
+ bc8: 02079263 bne x15,x0,bec <__call_exitprocs+0xf0>
+ bcc: 000680e7 jalr x1,0(x13)
+ bd0: 00492703 lw x14,4(x18)
+ bd4: 148a2783 lw x15,328(x20)
+ bd8: 01871463 bne x14,x24,be0 <__call_exitprocs+0xe4>
+ bdc: f92784e3 beq x15,x18,b64 <__call_exitprocs+0x68>
+ be0: f80788e3 beq x15,x0,b70 <__call_exitprocs+0x74>
+ be4: 00078913 addi x18,x15,0
+ be8: f5dff06f jal x0,b44 <__call_exitprocs+0x48>
+ bec: 18c92783 lw x15,396(x18)
+ bf0: 0844a583 lw x11,132(x9)
+ bf4: 00f77733 and x14,x14,x15
+ bf8: 00071c63 bne x14,x0,c10 <__call_exitprocs+0x114>
+ bfc: 000b0513 addi x10,x22,0
+ c00: 000680e7 jalr x1,0(x13)
+ c04: fcdff06f jal x0,bd0 <__call_exitprocs+0xd4>
+ c08: 00892223 sw x8,4(x18)
+ c0c: fa9ff06f jal x0,bb4 <__call_exitprocs+0xb8>
+ c10: 00058513 addi x10,x11,0
+ c14: 000680e7 jalr x1,0(x13)
+ c18: fb9ff06f jal x0,bd0 <__call_exitprocs+0xd4>
-00000c40 <__libc_fini_array>:
- c40: ff010113 addi x2,x2,-16
- c44: 00812423 sw x8,8(x2)
- c48: 000017b7 lui x15,0x1
- c4c: 00001437 lui x8,0x1
- c50: 03478793 addi x15,x15,52 # 1034 <__do_global_dtors_aux_fini_array_entry>
- c54: 03840413 addi x8,x8,56 # 1038
- c58: 40f40433 sub x8,x8,x15
- c5c: 00912223 sw x9,4(x2)
- c60: 00112623 sw x1,12(x2)
- c64: 40245493 srai x9,x8,0x2
- c68: 02048063 beq x9,x0,c88 <__libc_fini_array+0x48>
- c6c: ffc40413 addi x8,x8,-4
- c70: 00f40433 add x8,x8,x15
- c74: 00042783 lw x15,0(x8)
- c78: fff48493 addi x9,x9,-1
- c7c: ffc40413 addi x8,x8,-4
- c80: 000780e7 jalr x1,0(x15)
- c84: fe0498e3 bne x9,x0,c74 <__libc_fini_array+0x34>
- c88: 00c12083 lw x1,12(x2)
- c8c: 00812403 lw x8,8(x2)
- c90: 00412483 lw x9,4(x2)
- c94: 01010113 addi x2,x2,16
- c98: 00008067 jalr x0,0(x1)
+00000c1c <__libc_fini_array>:
+ c1c: ff010113 addi x2,x2,-16
+ c20: 00812423 sw x8,8(x2)
+ c24: 000017b7 lui x15,0x1
+ c28: 00001437 lui x8,0x1
+ c2c: 03478793 addi x15,x15,52 # 1034 <__do_global_dtors_aux_fini_array_entry>
+ c30: 03840413 addi x8,x8,56 # 1038
+ c34: 40f40433 sub x8,x8,x15
+ c38: 00912223 sw x9,4(x2)
+ c3c: 00112623 sw x1,12(x2)
+ c40: 40245493 srai x9,x8,0x2
+ c44: 02048063 beq x9,x0,c64 <__libc_fini_array+0x48>
+ c48: ffc40413 addi x8,x8,-4
+ c4c: 00f40433 add x8,x8,x15
+ c50: 00042783 lw x15,0(x8)
+ c54: fff48493 addi x9,x9,-1
+ c58: ffc40413 addi x8,x8,-4
+ c5c: 000780e7 jalr x1,0(x15)
+ c60: fe0498e3 bne x9,x0,c50 <__libc_fini_array+0x34>
+ c64: 00c12083 lw x1,12(x2)
+ c68: 00812403 lw x8,8(x2)
+ c6c: 00412483 lw x9,4(x2)
+ c70: 01010113 addi x2,x2,16
+ c74: 00008067 jalr x0,0(x1)
-00000c9c :
- c9c: 00050593 addi x11,x10,0
- ca0: 00000693 addi x13,x0,0
- ca4: 00000613 addi x12,x0,0
- ca8: 00000513 addi x10,x0,0
- cac: 0040006f jal x0,cb0 <__register_exitproc>
+00000c78 :
+ c78: 00050593 addi x11,x10,0
+ c7c: 00000693 addi x13,x0,0
+ c80: 00000613 addi x12,x0,0
+ c84: 00000513 addi x10,x0,0
+ c88: 0040006f jal x0,c8c <__register_exitproc>
-00000cb0 <__register_exitproc>:
- cb0: c281a703 lw x14,-984(x3) # 1460 <_global_impure_ptr>
- cb4: 14872783 lw x15,328(x14)
- cb8: 04078c63 beq x15,x0,d10 <__register_exitproc+0x60>
- cbc: 0047a703 lw x14,4(x15)
- cc0: 01f00813 addi x16,x0,31
- cc4: 06e84e63 blt x16,x14,d40 <__register_exitproc+0x90>
- cc8: 00271813 slli x16,x14,0x2
- ccc: 02050663 beq x10,x0,cf8 <__register_exitproc+0x48>
- cd0: 01078333 add x6,x15,x16
- cd4: 08c32423 sw x12,136(x6)
- cd8: 1887a883 lw x17,392(x15)
- cdc: 00100613 addi x12,x0,1
- ce0: 00e61633 sll x12,x12,x14
- ce4: 00c8e8b3 or x17,x17,x12
- ce8: 1917a423 sw x17,392(x15)
- cec: 10d32423 sw x13,264(x6)
- cf0: 00200693 addi x13,x0,2
- cf4: 02d50463 beq x10,x13,d1c <__register_exitproc+0x6c>
- cf8: 00170713 addi x14,x14,1
- cfc: 00e7a223 sw x14,4(x15)
- d00: 010787b3 add x15,x15,x16
- d04: 00b7a423 sw x11,8(x15)
- d08: 00000513 addi x10,x0,0
- d0c: 00008067 jalr x0,0(x1)
- d10: 14c70793 addi x15,x14,332
- d14: 14f72423 sw x15,328(x14)
- d18: fa5ff06f jal x0,cbc <__register_exitproc+0xc>
- d1c: 18c7a683 lw x13,396(x15)
- d20: 00170713 addi x14,x14,1
- d24: 00e7a223 sw x14,4(x15)
- d28: 00c6e6b3 or x13,x13,x12
- d2c: 18d7a623 sw x13,396(x15)
- d30: 010787b3 add x15,x15,x16
- d34: 00b7a423 sw x11,8(x15)
- d38: 00000513 addi x10,x0,0
- d3c: 00008067 jalr x0,0(x1)
- d40: fff00513 addi x10,x0,-1
- d44: 00008067 jalr x0,0(x1)
+00000c8c <__register_exitproc>:
+ c8c: c281a703 lw x14,-984(x3) # 1460 <_global_impure_ptr>
+ c90: 14872783 lw x15,328(x14)
+ c94: 04078c63 beq x15,x0,cec <__register_exitproc+0x60>
+ c98: 0047a703 lw x14,4(x15)
+ c9c: 01f00813 addi x16,x0,31
+ ca0: 06e84e63 blt x16,x14,d1c <__register_exitproc+0x90>
+ ca4: 00271813 slli x16,x14,0x2
+ ca8: 02050663 beq x10,x0,cd4 <__register_exitproc+0x48>
+ cac: 01078333 add x6,x15,x16
+ cb0: 08c32423 sw x12,136(x6)
+ cb4: 1887a883 lw x17,392(x15)
+ cb8: 00100613 addi x12,x0,1
+ cbc: 00e61633 sll x12,x12,x14
+ cc0: 00c8e8b3 or x17,x17,x12
+ cc4: 1917a423 sw x17,392(x15)
+ cc8: 10d32423 sw x13,264(x6)
+ ccc: 00200693 addi x13,x0,2
+ cd0: 02d50463 beq x10,x13,cf8 <__register_exitproc+0x6c>
+ cd4: 00170713 addi x14,x14,1
+ cd8: 00e7a223 sw x14,4(x15)
+ cdc: 010787b3 add x15,x15,x16
+ ce0: 00b7a423 sw x11,8(x15)
+ ce4: 00000513 addi x10,x0,0
+ ce8: 00008067 jalr x0,0(x1)
+ cec: 14c70793 addi x15,x14,332
+ cf0: 14f72423 sw x15,328(x14)
+ cf4: fa5ff06f jal x0,c98 <__register_exitproc+0xc>
+ cf8: 18c7a683 lw x13,396(x15)
+ cfc: 00170713 addi x14,x14,1
+ d00: 00e7a223 sw x14,4(x15)
+ d04: 00c6e6b3 or x13,x13,x12
+ d08: 18d7a623 sw x13,396(x15)
+ d0c: 010787b3 add x15,x15,x16
+ d10: 00b7a423 sw x11,8(x15)
+ d14: 00000513 addi x10,x0,0
+ d18: 00008067 jalr x0,0(x1)
+ d1c: fff00513 addi x10,x0,-1
+ d20: 00008067 jalr x0,0(x1)
-00000d48 <_exit>:
- d48: 05d00893 addi x17,x0,93
- d4c: 00000073 ecall
- d50: 00054463 blt x10,x0,d58 <_exit+0x10>
- d54: 0000006f jal x0,d54 <_exit+0xc>
- d58: ff010113 addi x2,x2,-16
- d5c: 00812423 sw x8,8(x2)
- d60: 00050413 addi x8,x10,0
- d64: 00112623 sw x1,12(x2)
- d68: 40800433 sub x8,x0,x8
- d6c: 00c000ef jal x1,d78 <__errno>
- d70: 00852023 sw x8,0(x10)
- d74: 0000006f jal x0,d74 <_exit+0x2c>
+00000d24 <_exit>:
+ d24: 05d00893 addi x17,x0,93
+ d28: 00000073 ecall
+ d2c: 00054463 blt x10,x0,d34 <_exit+0x10>
+ d30: 0000006f jal x0,d30 <_exit+0xc>
+ d34: ff010113 addi x2,x2,-16
+ d38: 00812423 sw x8,8(x2)
+ d3c: 00050413 addi x8,x10,0
+ d40: 00112623 sw x1,12(x2)
+ d44: 40800433 sub x8,x0,x8
+ d48: 00c000ef jal x1,d54 <__errno>
+ d4c: 00852023 sw x8,0(x10)
+ d50: 0000006f jal x0,d50 <_exit+0x2c>
-00000d78 <__errno>:
- d78: c301a503 lw x10,-976(x3) # 1468 <_impure_ptr>
- d7c: 00008067 jalr x0,0(x1)
+00000d54 <__errno>:
+ d54: c301a503 lw x10,-976(x3) # 1468 <_impure_ptr>
+ d58: 00008067 jalr x0,0(x1)
Disassembly of section .rodata:
-00000d80 :
- d80: 0000003f 00000006 0x60000003f
- d88: 0000005b 0x5b
- d8c: 0000004f fnmadd.s f0,f0,f0,f0,rne
- d90: 0066 c.slli x0,0x19
- d92: 0000 c.unimp
- d94: 006d c.addi x0,27
- d96: 0000 c.unimp
- d98: 007d c.addi x0,31
- d9a: 0000 c.unimp
- d9c: 00000007 0x7
- da0: 007f 0x7f
- da2: 0000 c.unimp
- da4: 0000006f jal x0,da4
+00000d5c :
+ d5c: 0000003f 00000006 0x60000003f
+ d64: 0000005b 0x5b
+ d68: 0000004f fnmadd.s f0,f0,f0,f0,rne
+ d6c: 0066 c.slli x0,0x19
+ d6e: 0000 c.unimp
+ d70: 006d c.addi x0,27
+ d72: 0000 c.unimp
+ d74: 007d c.addi x0,31
+ d76: 0000 c.unimp
+ d78: 00000007 0x7
+ d7c: 007f 0x7f
+ d7e: 0000 c.unimp
+ d80: 0000006f jal x0,d80
-00000da8 <__clz_tab>:
- da8: 0100 c.addi4spn x8,x2,128
- daa: 0202 c.slli64 x4
- dac: 03030303 lb x6,48(x6)
- db0: 0404 c.addi4spn x9,x2,512
- db2: 0404 c.addi4spn x9,x2,512
- db4: 0404 c.addi4spn x9,x2,512
- db6: 0404 c.addi4spn x9,x2,512
- db8: 0505 c.addi x10,1
- dba: 0505 c.addi x10,1
- dbc: 0505 c.addi x10,1
- dbe: 0505 c.addi x10,1
- dc0: 0505 c.addi x10,1
- dc2: 0505 c.addi x10,1
- dc4: 0505 c.addi x10,1
- dc6: 0505 c.addi x10,1
- dc8: 0606 c.slli x12,0x1
- dca: 0606 c.slli x12,0x1
- dcc: 0606 c.slli x12,0x1
- dce: 0606 c.slli x12,0x1
- dd0: 0606 c.slli x12,0x1
- dd2: 0606 c.slli x12,0x1
- dd4: 0606 c.slli x12,0x1
- dd6: 0606 c.slli x12,0x1
- dd8: 0606 c.slli x12,0x1
- dda: 0606 c.slli x12,0x1
- ddc: 0606 c.slli x12,0x1
- dde: 0606 c.slli x12,0x1
- de0: 0606 c.slli x12,0x1
- de2: 0606 c.slli x12,0x1
- de4: 0606 c.slli x12,0x1
- de6: 0606 c.slli x12,0x1
+00000d84 <__clz_tab>:
+ d84: 0100 c.addi4spn x8,x2,128
+ d86: 0202 c.slli64 x4
+ d88: 03030303 lb x6,48(x6)
+ d8c: 0404 c.addi4spn x9,x2,512
+ d8e: 0404 c.addi4spn x9,x2,512
+ d90: 0404 c.addi4spn x9,x2,512
+ d92: 0404 c.addi4spn x9,x2,512
+ d94: 0505 c.addi x10,1
+ d96: 0505 c.addi x10,1
+ d98: 0505 c.addi x10,1
+ d9a: 0505 c.addi x10,1
+ d9c: 0505 c.addi x10,1
+ d9e: 0505 c.addi x10,1
+ da0: 0505 c.addi x10,1
+ da2: 0505 c.addi x10,1
+ da4: 0606 c.slli x12,0x1
+ da6: 0606 c.slli x12,0x1
+ da8: 0606 c.slli x12,0x1
+ daa: 0606 c.slli x12,0x1
+ dac: 0606 c.slli x12,0x1
+ dae: 0606 c.slli x12,0x1
+ db0: 0606 c.slli x12,0x1
+ db2: 0606 c.slli x12,0x1
+ db4: 0606 c.slli x12,0x1
+ db6: 0606 c.slli x12,0x1
+ db8: 0606 c.slli x12,0x1
+ dba: 0606 c.slli x12,0x1
+ dbc: 0606 c.slli x12,0x1
+ dbe: 0606 c.slli x12,0x1
+ dc0: 0606 c.slli x12,0x1
+ dc2: 0606 c.slli x12,0x1
+ dc4: 07070707 0x7070707
+ dc8: 07070707 0x7070707
+ dcc: 07070707 0x7070707
+ dd0: 07070707 0x7070707
+ dd4: 07070707 0x7070707
+ dd8: 07070707 0x7070707
+ ddc: 07070707 0x7070707
+ de0: 07070707 0x7070707
+ de4: 07070707 0x7070707
de8: 07070707 0x7070707
dec: 07070707 0x7070707
df0: 07070707 0x7070707
@@ -927,15 +927,24 @@ Disassembly of section .rodata:
df8: 07070707 0x7070707
dfc: 07070707 0x7070707
e00: 07070707 0x7070707
- e04: 07070707 0x7070707
- e08: 07070707 0x7070707
- e0c: 07070707 0x7070707
- e10: 07070707 0x7070707
- e14: 07070707 0x7070707
- e18: 07070707 0x7070707
- e1c: 07070707 0x7070707
- e20: 07070707 0x7070707
- e24: 07070707 0x7070707
+ e04: 0808 c.addi4spn x10,x2,16
+ e06: 0808 c.addi4spn x10,x2,16
+ e08: 0808 c.addi4spn x10,x2,16
+ e0a: 0808 c.addi4spn x10,x2,16
+ e0c: 0808 c.addi4spn x10,x2,16
+ e0e: 0808 c.addi4spn x10,x2,16
+ e10: 0808 c.addi4spn x10,x2,16
+ e12: 0808 c.addi4spn x10,x2,16
+ e14: 0808 c.addi4spn x10,x2,16
+ e16: 0808 c.addi4spn x10,x2,16
+ e18: 0808 c.addi4spn x10,x2,16
+ e1a: 0808 c.addi4spn x10,x2,16
+ e1c: 0808 c.addi4spn x10,x2,16
+ e1e: 0808 c.addi4spn x10,x2,16
+ e20: 0808 c.addi4spn x10,x2,16
+ e22: 0808 c.addi4spn x10,x2,16
+ e24: 0808 c.addi4spn x10,x2,16
+ e26: 0808 c.addi4spn x10,x2,16
e28: 0808 c.addi4spn x10,x2,16
e2a: 0808 c.addi4spn x10,x2,16
e2c: 0808 c.addi4spn x10,x2,16
@@ -982,24 +991,6 @@ Disassembly of section .rodata:
e7e: 0808 c.addi4spn x10,x2,16
e80: 0808 c.addi4spn x10,x2,16
e82: 0808 c.addi4spn x10,x2,16
- e84: 0808 c.addi4spn x10,x2,16
- e86: 0808 c.addi4spn x10,x2,16
- e88: 0808 c.addi4spn x10,x2,16
- e8a: 0808 c.addi4spn x10,x2,16
- e8c: 0808 c.addi4spn x10,x2,16
- e8e: 0808 c.addi4spn x10,x2,16
- e90: 0808 c.addi4spn x10,x2,16
- e92: 0808 c.addi4spn x10,x2,16
- e94: 0808 c.addi4spn x10,x2,16
- e96: 0808 c.addi4spn x10,x2,16
- e98: 0808 c.addi4spn x10,x2,16
- e9a: 0808 c.addi4spn x10,x2,16
- e9c: 0808 c.addi4spn x10,x2,16
- e9e: 0808 c.addi4spn x10,x2,16
- ea0: 0808 c.addi4spn x10,x2,16
- ea2: 0808 c.addi4spn x10,x2,16
- ea4: 0808 c.addi4spn x10,x2,16
- ea6: 0808 c.addi4spn x10,x2,16
Disassembly of section .eh_frame:
@@ -1016,7 +1007,7 @@ Disassembly of section .eh_frame:
1016: 0000 c.unimp
1018: 0018 0x18
101a: 0000 c.unimp
- 101c: f52c c.fsw f11,104(x10)
+ 101c: f508 c.fsw f10,40(x10)
101e: ffff 0xffff
1020: 0430 c.addi4spn x12,x2,520
1022: 0000 c.unimp
@@ -1105,7 +1096,7 @@ Disassembly of section .comment:
Disassembly of section .riscv.attributes:
00000000 <.riscv.attributes>:
- 0: 2541 c.jal 680 <__udivdi3+0x138>
+ 0: 2541 c.jal 680 <__udivdi3+0x15c>
2: 0000 c.unimp
4: 7200 c.flw f8,32(x12)
6: 7369 c.lui x6,0xffffa
@@ -1132,7 +1123,7 @@ Disassembly of section .debug_aranges:
a: 0004 0x4
c: 0000 c.unimp
e: 0000 c.unimp
- 10: 0548 c.addi4spn x10,x2,644
+ 10: 0524 c.addi4spn x9,x2,648
12: 0000 c.unimp
14: 0430 c.addi4spn x12,x2,520
...
@@ -1161,7 +1152,7 @@ Disassembly of section .debug_info:
14: 0000 c.unimp
16: 0000 c.unimp
18: 0000 c.unimp
- 1a: 0548 c.addi4spn x10,x2,644
+ 1a: 0524 c.addi4spn x9,x2,648
1c: 0000 c.unimp
1e: 0430 c.addi4spn x12,x2,520
20: 0000 c.unimp
@@ -1312,9 +1303,9 @@ Disassembly of section .debug_info:
158: 0000081b 0x81b
15c: 0100 c.addi4spn x8,x2,128
15e: 0512 c.slli x10,0x4
- 160: ab01 c.j 670 <__udivdi3+0x128>
+ 160: ab01 c.j 670 <__udivdi3+0x14c>
162: 0000 c.unimp
- 164: 4800 c.lw x8,16(x8)
+ 164: 2400 c.fld f8,8(x8)
166: 0005 c.addi x0,1
168: 3000 c.fld f8,32(x8)
16a: 0004 0x4
@@ -1334,7 +1325,7 @@ Disassembly of section .debug_info:
18a: 1c00 c.addi4spn x8,x2,560
18c: 042e c.slli x8,0xb
18e: 0000 c.unimp
- 190: 0548 c.addi4spn x10,x2,644
+ 190: 0524 c.addi4spn x9,x2,648
192: 0000 c.unimp
194: 000c 0xc
196: 0000 c.unimp
@@ -1419,7 +1410,7 @@ Disassembly of section .debug_info:
240: 0e00 c.addi4spn x8,x2,784
242: 0505 c.addi x10,1
244: 0000 c.unimp
- 246: 05b0 c.addi4spn x12,x2,712
+ 246: 058c c.addi4spn x11,x2,704
248: 0000 c.unimp
24a: 0088 c.addi4spn x10,x2,64
24c: 0000 c.unimp
@@ -1494,7 +1485,7 @@ Disassembly of section .debug_info:
2dc: 0000 c.unimp
2de: 0700 c.addi4spn x8,x2,896
2e0: 0000 c.unimp
- 2e2: ad01 c.j 8f2 <__udivdi3+0x3aa>
+ 2e2: ad01 c.j 8f2 <__udivdi3+0x3ce>
2e4: 0006 c.slli x0,0x1
2e6: 1700 c.addi4spn x8,x2,928
2e8: 01000007 0x1000007
@@ -1532,7 +1523,7 @@ Disassembly of section .debug_info:
33c: 0100 c.addi4spn x8,x2,128
33e: 071f 0000 0857 0x8570000071f
344: 0000 c.unimp
- 346: 2b01 c.jal 856 <__udivdi3+0x30e>
+ 346: 2b01 c.jal 856 <__udivdi3+0x332>
348: 81000007 0x81000007
34c: 0008 0x8
34e: 0000 c.unimp
@@ -1552,7 +1543,7 @@ Disassembly of section .debug_info:
36e: 0000 c.unimp
370: 0e00 c.addi4spn x8,x2,784
372: 000005d7 0x5d7
- 376: 0694 c.addi4spn x13,x2,832
+ 376: 0670 c.addi4spn x12,x2,780
378: 0000 c.unimp
37a: 008c c.addi4spn x11,x2,64
37c: 0000 c.unimp
@@ -1585,7 +1576,7 @@ Disassembly of section .debug_info:
3b2: 0000 c.unimp
3b4: 0951 c.addi x18,20
3b6: 0000 c.unimp
- 3b8: 2401 c.jal 5b8 <__udivdi3+0x70>
+ 3b8: 2401 c.jal 5b8 <__udivdi3+0x94>
3ba: 0006 c.slli x0,0x1
3bc: 7800 c.flw f8,48(x8)
3be: 0009 c.addi x0,2
@@ -1607,7 +1598,7 @@ Disassembly of section .debug_info:
3e4: 0000 c.unimp
3e6: 09c8 c.addi4spn x10,x2,212
3e8: 0000 c.unimp
- 3ea: a601 c.j 6ea <__udivdi3+0x1a2>
+ 3ea: a601 c.j 6ea <__udivdi3+0x1c6>
3ec: 0005 c.addi x0,1
3ee: df00 c.sw x8,56(x14)
3f0: 0009 c.addi x0,2
@@ -1901,7 +1892,7 @@ Disassembly of section .debug_info:
672: 1304 c.addi4spn x9,x2,416
674: 0095 c.addi x1,5
676: 0000 c.unimp
- 678: d205 c.beqz x12,598 <__udivdi3+0x50>
+ 678: d205 c.beqz x12,598 <__udivdi3+0x74>
67a: 0006 c.slli x0,0x1
67c: 0200 c.addi4spn x8,x2,256
67e: 0000002f 0x2f
@@ -2078,7 +2069,7 @@ Disassembly of section .debug_info:
7fa: 0310 c.addi4spn x12,x2,384
7fc: 0198 c.addi4spn x14,x2,192
7fe: 0000 c.unimp
- 800: 2001 c.jal 800 <__udivdi3+0x2b8>
+ 800: 2001 c.jal 800 <__udivdi3+0x2dc>
802: 0001b903 0x1b903
806: 0600 c.addi4spn x8,x2,768
808: 007e c.slli x0,0x1f
@@ -2101,7 +2092,7 @@ Disassembly of section .debug_info:
82e: 9e02 c.jalr x28
830: 0f02 c.slli64 x30
832: 0305 c.addi x6,1
- 834: 0da8 c.addi4spn x10,x2,728
+ 834: 0d84 c.addi4spn x9,x2,720
836: 0000 c.unimp
...
@@ -2178,7 +2169,7 @@ Disassembly of section .debug_abbrev:
b8: 1000 c.addi4spn x8,x2,32
ba: 0000010b 0x10b
be: 1111 c.addi x2,-28
- c0: 2501 c.jal 6c0 <__udivdi3+0x178>
+ c0: 2501 c.jal 6c0 <__udivdi3+0x19c>
c2: 130e c.slli x6,0x23
c4: 1b1f030b 0x1b1f030b
c8: 111f 1201 1006 0x10061201111f
@@ -2218,7 +2209,7 @@ Disassembly of section .debug_abbrev:
130: 1349 c.addi x6,-14
132: 1301 c.addi x6,-32
134: 0000 c.unimp
- 136: 2119 c.jal 53c
+ 136: 2119 c.jal 53c <__udivdi3+0x18>
138: 4900 c.lw x8,16(x10)
13a: 000b2f13 slti x30,x22,0
13e: 1a00 c.addi4spn x8,x2,304
@@ -2326,7 +2317,7 @@ Disassembly of section .debug_line:
3e: 0501 c.addi x10,0
40: 0001 c.addi x0,0
42: 0205 c.addi x4,1
- 44: 0548 c.addi4spn x10,x2,644
+ 44: 0524 c.addi4spn x9,x2,648
46: 0000 c.unimp
48: 010a9203 lh x4,16(x21)
4c: 0305 c.addi x6,1
@@ -3112,7 +3103,7 @@ Disassembly of section .debug_str:
70: 6e75 c.lui x28,0x1d
72: 3d65 c.jal ffffff2a <__global_pointer$+0xffffe6f2>
74: 6f72 c.flwsp f30,28(x2)
- 76: 74656b63 bltu x10,x6,7cc <__udivdi3+0x284>
+ 76: 74656b63 bltu x10,x6,7cc <__udivdi3+0x2a8>
7a: 2d20 c.fld f8,88(x10)
7c: 616d c.addi16sp x2,240
7e: 6372 c.flwsp f6,28(x2)
@@ -3128,7 +3119,7 @@ Disassembly of section .debug_str:
94: 2032 c.fldsp f0,264(x2)
96: 6d2d c.lui x26,0xb
98: 7261 c.lui x4,0xffff8
- 9a: 723d6863 bltu x26,x3,7ca <__udivdi3+0x282>
+ 9a: 723d6863 bltu x26,x3,7ca <__udivdi3+0x2a6>
9e: 3376 c.fldsp f6,376(x2)
a0: 6932 c.flwsp f18,12(x2)
a2: 616d c.addi16sp x2,240
@@ -3149,10 +3140,10 @@ Disassembly of section .debug_str:
c8: 6f6e c.flwsp f30,216(x2)
ca: 732d c.lui x6,0xfffeb
cc: 6174 c.flw f13,68(x10)
- ce: 702d6b63 bltu x26,x2,7e4 <__udivdi3+0x29c>
+ ce: 702d6b63 bltu x26,x2,7e4 <__udivdi3+0x2c0>
d2: 6f72 c.flwsp f30,28(x2)
d4: 6574 c.flw f13,76(x10)
- d6: 726f7463 bgeu x30,x6,7fe <__udivdi3+0x2b6>
+ d6: 726f7463 bgeu x30,x6,7fe <__udivdi3+0x2da>
da: 2d20 c.fld f8,88(x10)
dc: 6166 c.flwsp f2,88(x2)
de: 636e7973 csrrci x18,0x636,28
@@ -3209,7 +3200,7 @@ Disassembly of section .debug_str:
168: 0065 c.addi x0,25
16a: 5744 c.lw x9,44(x14)
16c: 75727473 csrrci x8,0x757,4
- 170: 73007463 bgeu x0,x16,898 <__udivdi3+0x350>
+ 170: 73007463 bgeu x0,x16,898 <__udivdi3+0x374>
174: 6f68 c.flw f10,92(x14)
176: 7472 c.flwsp f8,60(x2)
178: 7520 c.flw f8,104(x10)
@@ -3264,13 +3255,13 @@ Disassembly of section .debug_str:
1f4: 2e31 c.jal 510
1f6: 2030 c.fld f12,64(x8)
1f8: 6d2d c.lui x26,0xb
- 1fa: 646f6d63 bltu x30,x6,854 <__udivdi3+0x30c>
+ 1fa: 646f6d63 bltu x30,x6,854 <__udivdi3+0x330>
1fe: 6c65 c.lui x24,0x19
200: 6d3d c.lui x26,0xf
202: 6465 c.lui x8,0x19
204: 6f6c c.flw f11,92(x14)
206: 6d2d2077 0x6d2d2077
- 20a: 646f6d63 bltu x30,x6,864 <__udivdi3+0x31c>
+ 20a: 646f6d63 bltu x30,x6,864 <__udivdi3+0x340>
20e: 6c65 c.lui x24,0x19
210: 6d3d c.lui x26,0xf
212: 6465 c.lui x8,0x19
@@ -3283,7 +3274,7 @@ Disassembly of section .debug_str:
224: 2074 c.fld f13,192(x8)
226: 6d2d c.lui x26,0xb
228: 7261 c.lui x4,0xffff8
- 22a: 723d6863 bltu x26,x3,95a <__udivdi3+0x412>
+ 22a: 723d6863 bltu x26,x3,95a
22e: 3376 c.fldsp f6,376(x2)
230: 6932 c.flwsp f18,12(x2)
232: 616d c.addi16sp x2,240
@@ -3310,7 +3301,7 @@ Disassembly of section .debug_str:
266: 6e69 c.lui x28,0x1a
268: 696c2d67 0x696c2d67
26c: 6762 c.flwsp f14,24(x2)
- 26e: 2d206363 bltu x0,x18,534
+ 26e: 2d206363 bltu x0,x18,534 <__udivdi3+0x10>
272: 6e66 c.flwsp f28,88(x2)
274: 74732d6f jal x26,331ba <__global_pointer$+0x31982>
278: 6361 c.lui x6,0x18
@@ -3332,14 +3323,14 @@ Disassembly of section .debug_line_str:
00000000 <.debug_line_str>:
0: 6d6f682f 0x6d6f682f
- 4: 2f65 c.jal 7bc <__udivdi3+0x274>
+ 4: 2f65 c.jal 7bc <__udivdi3+0x298>
6: 6172 c.flwsp f2,28(x2)
8: 6169786f jal x16,9761e <__global_pointer$+0x95de6>
c: 686e c.flwsp f16,216(x2)
e: 2f676e6f jal x28,76304 <__global_pointer$+0x74acc>
12: 6b726f77 0x6b726f77
16: 7369722f 0x7369722f
- 1a: 672d7663 bgeu x26,x18,686 <__udivdi3+0x13e>
+ 1a: 672d7663 bgeu x26,x18,686 <__udivdi3+0x162>
1e: 756e c.flwsp f10,248(x2)
20: 742d c.lui x8,0xfffeb
22: 636c6f6f jal x30,c6658 <__global_pointer$+0xc4e20>
@@ -3348,7 +3339,7 @@ Disassembly of section .debug_line_str:
2a: 6975622f 0x6975622f
2e: 646c c.flw f11,76(x8)
30: 672d c.lui x14,0xb
- 32: 6e2d6363 bltu x26,x2,718 <__udivdi3+0x1d0>
+ 32: 6e2d6363 bltu x26,x2,718 <__udivdi3+0x1f4>
36: 7765 c.lui x14,0xffff9
38: 696c c.flw f11,84(x10)
3a: 2d62 c.fldsp f26,24(x2)
@@ -3368,8 +3359,8 @@ Disassembly of section .debug_line_str:
64: 2e2e c.fldsp f28,200(x2)
66: 722f2e2f 0x722f2e2f
6a: 7369 c.lui x6,0xffffa
- 6c: 672d7663 bgeu x26,x18,6d8 <__udivdi3+0x190>
- 70: 6c2f6363 bltu x30,x2,736 <__udivdi3+0x1ee>
+ 6c: 672d7663 bgeu x26,x18,6d8 <__udivdi3+0x1b4>
+ 70: 6c2f6363 bltu x30,x2,736 <__udivdi3+0x212>
74: 6269 c.lui x4,0x1a
76: 2f636367 0x2f636367
7a: 696c c.flw f11,84(x10)
@@ -3380,8 +3371,8 @@ Disassembly of section .debug_line_str:
8a: 2e2e c.fldsp f28,200(x2)
8c: 722f2e2f 0x722f2e2f
90: 7369 c.lui x6,0xffffa
- 92: 672d7663 bgeu x26,x18,6fe <__udivdi3+0x1b6>
- 96: 6c2f6363 bltu x30,x2,75c <__udivdi3+0x214>
+ 92: 672d7663 bgeu x26,x18,6fe <__udivdi3+0x1da>
+ 96: 6c2f6363 bltu x30,x2,75c <__udivdi3+0x238>
9a: 6269 c.lui x4,0x1a
9c: 00636367 0x636367
a0: 696c c.flw f11,84(x10)
@@ -3398,686 +3389,685 @@ Disassembly of section .debug_loclists:
6: 0004 0x4
8: 0000 c.unimp
a: 0000 c.unimp
- c: 00054807 flq f16,0(x10) # fffeb000 <__global_pointer$+0xfffe97c8>
- 10: 8000 0x8000
+ c: 00052407 flw f8,0(x10) # fffeb000 <__global_pointer$+0xfffe97c8>
+ 10: 5c00 c.lw x8,56(x8)
12: 0005 c.addi x0,1
14: 0600 c.addi4spn x8,x2,768
16: 935a c.add x6,x22
18: 5b04 c.lw x9,48(x14)
- 1a: 80070493 addi x9,x14,-2048 # ffff8800 <__global_pointer$+0xffff6fc8>
+ 1a: 5c070493 addi x9,x14,1472 # ffff95c0 <__global_pointer$+0xffff7d88>
1e: 0005 c.addi x0,1
- 20: 4000 c.lw x8,0(x8)
+ 20: 1c00 c.addi4spn x8,x2,560
22: 0006 c.slli x0,0x1
24: 0600 c.addi4spn x8,x2,768
26: 0aa503a3 sb x10,167(x10)
2a: 9f26 c.add x30,x9
- 2c: 00064007 flq f0,0(x12) # b000 <__global_pointer$+0x97c8>
- 30: 4400 c.lw x8,8(x8)
+ 2c: 00061c07 0x61c07
+ 30: 2000 c.fld f8,0(x8)
32: 0006 c.slli x0,0x1
34: 0600 c.addi4spn x8,x2,768
36: 935a c.add x6,x22
38: 5b04 c.lw x9,48(x14)
- 3a: 44070493 addi x9,x14,1088
+ 3a: 20070493 addi x9,x14,512
3e: 0006 c.slli x0,0x1
- 40: 5400 c.lw x8,40(x8)
+ 40: 3000 c.fld f8,32(x8)
42: 0006 c.slli x0,0x1
44: 0600 c.addi4spn x8,x2,768
46: 0aa503a3 sb x10,167(x10)
4a: 9f26 c.add x30,x9
- 4c: 00065407 0x65407
- 50: 9400 0x9400
+ 4c: 00063007 fld f0,0(x12) # b000 <__global_pointer$+0x97c8>
+ 50: 7000 c.flw f8,32(x8)
52: 0006 c.slli x0,0x1
54: 0600 c.addi4spn x8,x2,768
56: 935a c.add x6,x22
58: 5b04 c.lw x9,48(x14)
- 5a: 94070493 addi x9,x14,-1728
+ 5a: 70070493 addi x9,x14,1792
5e: 0006 c.slli x0,0x1
- 60: 2000 c.fld f8,0(x8)
- 62: 06000007 0x6000007
+ 60: fc00 c.fsw f8,56(x8)
+ 62: 0006 c.slli x0,0x1
+ 64: 0600 c.addi4spn x8,x2,768
66: 0aa503a3 sb x10,167(x10)
6a: 9f26 c.add x30,x9
- 6c: 00072007 flw f0,0(x14)
- 70: 4000 c.lw x8,0(x8)
+ 6c: 0006fc07 0x6fc07
+ 70: 1c00 c.addi4spn x8,x2,560
72: 06000007 0x6000007
76: 935a c.add x6,x22
78: 5b04 c.lw x9,48(x14)
- 7a: 40070493 addi x9,x14,1024
- 7e: e0000007 0xe0000007
+ 7a: 1c070493 addi x9,x14,448
+ 7e: bc000007 0xbc000007
82: 06000007 0x6000007
86: 0aa503a3 sb x10,167(x10)
8a: 9f26 c.add x30,x9
- 8c: 0007e007 0x7e007
- 90: 2000 c.fld f8,0(x8)
- 92: 0008 0x8
- 94: 0600 c.addi4spn x8,x2,768
+ 8c: 0007bc07 fld f24,0(x15)
+ 90: fc00 c.fsw f8,56(x8)
+ 92: 06000007 0x6000007
96: 935a c.add x6,x22
98: 5b04 c.lw x9,48(x14)
- 9a: 20070493 addi x9,x14,512
- 9e: 0008 0x8
- a0: 3000 c.fld f8,32(x8)
+ 9a: fc070493 addi x9,x14,-64
+ 9e: 0c000007 0xc000007
a2: 0008 0x8
a4: 0600 c.addi4spn x8,x2,768
a6: 0aa503a3 sb x10,167(x10)
aa: 9f26 c.add x30,x9
- ac: 00083007 fld f0,0(x16) # f000 <__global_pointer$+0xd7c8>
- b0: 8000 0x8000
+ ac: 00080c07 0x80c07
+ b0: 5c00 c.lw x8,56(x8)
b2: 0008 0x8
b4: 0600 c.addi4spn x8,x2,768
b6: 935a c.add x6,x22
b8: 5b04 c.lw x9,48(x14)
- ba: 80070493 addi x9,x14,-2048
+ ba: 5c070493 addi x9,x14,1472
be: 0008 0x8
- c0: 6c00 c.flw f8,24(x8)
+ c0: 4800 c.lw x8,16(x8)
c2: 0009 c.addi x0,2
c4: 0600 c.addi4spn x8,x2,768
c6: 0aa503a3 sb x10,167(x10)
ca: 9f26 c.add x30,x9
- cc: 00096c07 0x96c07
- d0: 7400 c.flw f8,40(x8)
+ cc: 00094807 flq f16,0(x18) # 1d000 <__global_pointer$+0x1b7c8>
+ d0: 5000 c.lw x8,32(x8)
d2: 0009 c.addi x0,2
d4: 0600 c.addi4spn x8,x2,768
d6: 935a c.add x6,x22
d8: 5b04 c.lw x9,48(x14)
- da: 74070493 addi x9,x14,1856
+ da: 50070493 addi x9,x14,1280
de: 0009 c.addi x0,2
- e0: 7800 c.flw f8,48(x8)
+ e0: 5400 c.lw x8,40(x8)
e2: 0009 c.addi x0,2
e4: 0600 c.addi4spn x8,x2,768
e6: 0aa503a3 sb x10,167(x10)
ea: 9f26 c.add x30,x9
ec: 0700 c.addi4spn x8,x2,896
- ee: 0548 c.addi4spn x10,x2,644
+ ee: 0524 c.addi4spn x9,x2,648
f0: 0000 c.unimp
- f2: 05bc c.addi4spn x15,x2,712
+ f2: 0598 c.addi4spn x14,x2,704
f4: 0000 c.unimp
f6: 5c06 c.lwsp x24,96(x2)
f8: 935d0493 addi x9,x26,-1739 # a935 <__global_pointer$+0x90fd>
fc: 0704 c.addi4spn x9,x2,896
- fe: 05bc c.addi4spn x15,x2,712
+ fe: 0598 c.addi4spn x14,x2,704
100: 0000 c.unimp
- 102: 0640 c.addi4spn x8,x2,772
+ 102: 061c c.addi4spn x15,x2,768
104: 0000 c.unimp
106: a306 c.fsdsp f1,384(x2)
108: 260ca503 lw x10,608(x25)
- 10c: 079f 0640 0000 0x640079f
- 112: 0694 c.addi4spn x13,x2,832
+ 10c: 079f 061c 0000 0x61c079f
+ 112: 0670 c.addi4spn x12,x2,780
114: 0000 c.unimp
116: 5c06 c.lwsp x24,96(x2)
118: 935d0493 addi x9,x26,-1739
11c: 0704 c.addi4spn x9,x2,896
- 11e: 0694 c.addi4spn x13,x2,832
+ 11e: 0670 c.addi4spn x12,x2,780
120: 0000 c.unimp
- 122: 0720 c.addi4spn x8,x2,904
+ 122: 06fc c.addi4spn x15,x2,844
124: 0000 c.unimp
126: a306 c.fsdsp f1,384(x2)
128: 260ca503 lw x10,608(x25)
- 12c: 079f 0720 0000 0x720079f
- 132: 0750 c.addi4spn x12,x2,900
+ 12c: 079f 06fc 0000 0x6fc079f
+ 132: 072c c.addi4spn x11,x2,904
134: 0000 c.unimp
136: 5c06 c.lwsp x24,96(x2)
138: 935d0493 addi x9,x26,-1739
13c: 0704 c.addi4spn x9,x2,896
- 13e: 0750 c.addi4spn x12,x2,900
+ 13e: 072c c.addi4spn x11,x2,904
140: 0000 c.unimp
- 142: 07e0 c.addi4spn x8,x2,972
+ 142: 07bc c.addi4spn x15,x2,968
144: 0000 c.unimp
146: a306 c.fsdsp f1,384(x2)
148: 260ca503 lw x10,608(x25)
- 14c: 079f 07e0 0000 0x7e0079f
- 152: 0874 c.addi4spn x13,x2,28
+ 14c: 079f 07bc 0000 0x7bc079f
+ 152: 0850 c.addi4spn x12,x2,20
154: 0000 c.unimp
156: 5c06 c.lwsp x24,96(x2)
158: 935d0493 addi x9,x26,-1739
15c: 0704 c.addi4spn x9,x2,896
- 15e: 0874 c.addi4spn x13,x2,28
+ 15e: 0850 c.addi4spn x12,x2,20
160: 0000 c.unimp
- 162: 096c c.addi4spn x11,x2,156
+ 162: 0948 c.addi4spn x10,x2,148
164: 0000 c.unimp
166: a306 c.fsdsp f1,384(x2)
168: 260ca503 lw x10,608(x25)
- 16c: 079f 096c 0000 0x96c079f
- 172: 0978 c.addi4spn x14,x2,156
+ 16c: 079f 0948 0000 0x948079f
+ 172: 0954 c.addi4spn x13,x2,148
174: 0000 c.unimp
176: 5c06 c.lwsp x24,96(x2)
178: 935d0493 addi x9,x26,-1739
17c: 0004 0x4
- 17e: 00054807 flq f16,0(x10)
- 182: 3c00 c.fld f8,56(x8)
+ 17e: 00052407 flw f8,0(x10)
+ 182: 1800 c.addi4spn x8,x2,48
184: 0006 c.slli x0,0x1
186: 0200 c.addi4spn x8,x2,256
188: 9f30 0x9f30
- 18a: 00064007 flq f0,0(x12)
- 18e: 7800 c.flw f8,48(x8)
+ 18a: 00061c07 0x61c07
+ 18e: 5400 c.lw x8,40(x8)
190: 0009 c.addi x0,2
192: 0200 c.addi4spn x8,x2,256
194: 9f30 0x9f30
196: 0700 c.addi4spn x8,x2,896
- 198: 0548 c.addi4spn x10,x2,644
+ 198: 0524 c.addi4spn x9,x2,648
19a: 0000 c.unimp
- 19c: 0570 c.addi4spn x12,x2,652
+ 19c: 054c c.addi4spn x11,x2,644
19e: 0000 c.unimp
1a0: 5c06 c.lwsp x24,96(x2)
1a2: 935d0493 addi x9,x26,-1739
1a6: 0704 c.addi4spn x9,x2,896
- 1a8: 0654 c.addi4spn x13,x2,772
+ 1a8: 0630 c.addi4spn x12,x2,776
1aa: 0000 c.unimp
- 1ac: 0668 c.addi4spn x10,x2,780
+ 1ac: 0644 c.addi4spn x9,x2,772
1ae: 0000 c.unimp
1b0: 5c06 c.lwsp x24,96(x2)
1b2: 935d0493 addi x9,x26,-1739
1b6: 0704 c.addi4spn x9,x2,896
- 1b8: 0720 c.addi4spn x8,x2,904
+ 1b8: 06fc c.addi4spn x15,x2,844
1ba: 0000 c.unimp
- 1bc: 0728 c.addi4spn x10,x2,904
+ 1bc: 0704 c.addi4spn x9,x2,896
1be: 0000 c.unimp
1c0: 5c06 c.lwsp x24,96(x2)
1c2: 935d0493 addi x9,x26,-1739
1c6: 0704 c.addi4spn x9,x2,896
- 1c8: 07e0 c.addi4spn x8,x2,972
+ 1c8: 07bc c.addi4spn x15,x2,968
1ca: 0000 c.unimp
- 1cc: 084c c.addi4spn x11,x2,20
+ 1cc: 0828 c.addi4spn x10,x2,24
1ce: 0000 c.unimp
1d0: 5c06 c.lwsp x24,96(x2)
1d2: 935d0493 addi x9,x26,-1739
1d6: 0704 c.addi4spn x9,x2,896
- 1d8: 096c c.addi4spn x11,x2,156
+ 1d8: 0948 c.addi4spn x10,x2,148
1da: 0000 c.unimp
- 1dc: 0978 c.addi4spn x14,x2,156
+ 1dc: 0954 c.addi4spn x13,x2,148
1de: 0000 c.unimp
1e0: 5c06 c.lwsp x24,96(x2)
1e2: 935d0493 addi x9,x26,-1739
1e6: 0004 0x4
- 1e8: 00054807 flq f16,0(x10)
- 1ec: 6400 c.flw f8,8(x8)
+ 1e8: 00052407 flw f8,0(x10)
+ 1ec: 4000 c.lw x8,0(x8)
1ee: 0005 c.addi x0,1
1f0: 0600 c.addi4spn x8,x2,768
1f2: 935a c.add x6,x22
1f4: 5b04 c.lw x9,48(x14)
- 1f6: 64070493 addi x9,x14,1600
+ 1f6: 40070493 addi x9,x14,1024
1fa: 0005 c.addi x0,1
- 1fc: 8000 0x8000
+ 1fc: 5c00 c.lw x8,56(x8)
1fe: 0005 c.addi x0,1
200: 0600 c.addi4spn x8,x2,768
202: 935a c.add x6,x22
204: 5f04 c.lw x9,56(x14)
- 206: 80070493 addi x9,x14,-2048
+ 206: 5c070493 addi x9,x14,1472
20a: 0005 c.addi x0,1
- 20c: a000 c.fsd f8,0(x8)
+ 20c: 7c00 c.flw f8,56(x8)
20e: 0005 c.addi x0,1
210: 0600 c.addi4spn x8,x2,768
212: 9356 c.add x6,x21
214: 5f04 c.lw x9,56(x14)
- 216: a0070493 addi x9,x14,-1536
+ 216: 7c070493 addi x9,x14,1984
21a: 0005 c.addi x0,1
- 21c: b800 c.fsd f8,48(x8)
+ 21c: 9400 0x9400
21e: 0005 c.addi x0,1
220: 0600 c.addi4spn x8,x2,768
222: 9356 c.add x6,x21
224: 6104 c.flw f9,0(x10)
- 226: 40070493 addi x9,x14,1024
+ 226: 1c070493 addi x9,x14,448
22a: 0006 c.slli x0,0x1
- 22c: 6000 c.flw f8,0(x8)
+ 22c: 3c00 c.fld f8,56(x8)
22e: 0006 c.slli x0,0x1
230: 0600 c.addi4spn x8,x2,768
232: 9356 c.add x6,x21
234: 5f04 c.lw x9,56(x14)
- 236: 60070493 addi x9,x14,1536
+ 236: 3c070493 addi x9,x14,960
23a: 0006 c.slli x0,0x1
- 23c: 9400 0x9400
+ 23c: 7000 c.flw f8,32(x8)
23e: 0006 c.slli x0,0x1
240: 0600 c.addi4spn x8,x2,768
242: 9356 c.add x6,x21
244: 6104 c.flw f9,0(x10)
- 246: 20070493 addi x9,x14,512
- 24a: 4c000007 0x4c000007
+ 246: fc070493 addi x9,x14,-64
+ 24a: 0006 c.slli x0,0x1
+ 24c: 2800 c.fld f8,16(x8)
24e: 06000007 0x6000007
252: 9356 c.add x6,x21
254: 6104 c.flw f9,0(x10)
- 256: e0070493 addi x9,x14,-512
- 25a: 00000007 0x7
- 25e: 0008 0x8
- 260: 0600 c.addi4spn x8,x2,768
+ 256: bc070493 addi x9,x14,-1088
+ 25a: dc000007 0xdc000007
+ 25e: 06000007 0x6000007
262: 9356 c.add x6,x21
264: 5b04 c.lw x9,48(x14)
- 266: 00070493 addi x9,x14,0
- 26a: 0008 0x8
- 26c: 3000 c.fld f8,32(x8)
+ 266: dc070493 addi x9,x14,-576
+ 26a: 0c000007 0xc000007
26e: 0008 0x8
270: 0600 c.addi4spn x8,x2,768
272: 9356 c.add x6,x21
274: 6104 c.flw f9,0(x10)
- 276: 30070493 addi x9,x14,768
+ 276: 0c070493 addi x9,x14,192
27a: 0008 0x8
- 27c: 4400 c.lw x8,8(x8)
+ 27c: 2000 c.fld f8,0(x8)
27e: 0008 0x8
280: 0600 c.addi4spn x8,x2,768
282: 9356 c.add x6,x21
284: 5b04 c.lw x9,48(x14)
- 286: 44070493 addi x9,x14,1088
+ 286: 20070493 addi x9,x14,512
28a: 0008 0x8
- 28c: 5800 c.lw x8,48(x8)
+ 28c: 3400 c.fld f8,40(x8)
28e: 0008 0x8
290: 0600 c.addi4spn x8,x2,768
292: 9356 c.add x6,x21
294: 6104 c.flw f9,0(x10)
- 296: 6c070493 addi x9,x14,1728
+ 296: 48070493 addi x9,x14,1152
29a: 0009 c.addi x0,2
- 29c: 7000 c.flw f8,32(x8)
+ 29c: 4c00 c.lw x8,24(x8)
29e: 0009 c.addi x0,2
2a0: 0600 c.addi4spn x8,x2,768
2a2: 9356 c.add x6,x21
2a4: 5b04 c.lw x9,48(x14)
- 2a6: 70070493 addi x9,x14,1792
+ 2a6: 4c070493 addi x9,x14,1216
2aa: 0009 c.addi x0,2
- 2ac: 7800 c.flw f8,48(x8)
+ 2ac: 5400 c.lw x8,40(x8)
2ae: 0009 c.addi x0,2
2b0: 0600 c.addi4spn x8,x2,768
2b2: 9356 c.add x6,x21
2b4: 5f04 c.lw x9,56(x14)
2b6: 07000493 addi x9,x0,112
- 2ba: 0554 c.addi4spn x13,x2,644
+ 2ba: 0530 c.addi4spn x12,x2,648
2bc: 0000 c.unimp
- 2be: 059c c.addi4spn x15,x2,704
+ 2be: 0578 c.addi4spn x14,x2,652
2c0: 0000 c.unimp
2c2: 5c01 c.li x24,-32
- 2c4: 00059c07 0x59c07
- 2c8: a800 c.fsd f8,16(x8)
+ 2c4: 00057807 0x57807
+ 2c8: 8400 0x8400
2ca: 0005 c.addi x0,1
2cc: 0900 c.addi4spn x8,x2,144
2ce: 007c c.addi4spn x15,x2,12
2d0: ff08007b 0xff08007b
2d4: 241a c.fldsp f8,384(x2)
- 2d6: 079f 05a8 0000 0x5a8079f
- 2dc: 0638 c.addi4spn x14,x2,776
+ 2d6: 079f 0584 0000 0x584079f
+ 2dc: 0614 c.addi4spn x13,x2,768
2de: 0000 c.unimp
2e0: 5e01 c.li x28,-32
- 2e2: 00064007 flq f0,0(x12)
- 2e6: 9400 0x9400
+ 2e2: 00061c07 0x61c07
+ 2e6: 7000 c.flw f8,32(x8)
2e8: 0006 c.slli x0,0x1
2ea: 0100 c.addi4spn x8,x2,128
2ec: 075c c.addi4spn x15,x2,900
- 2ee: 0694 c.addi4spn x13,x2,832
+ 2ee: 0670 c.addi4spn x12,x2,780
2f0: 0000 c.unimp
- 2f2: 0720 c.addi4spn x8,x2,904
+ 2f2: 06fc c.addi4spn x15,x2,844
2f4: 0000 c.unimp
2f6: 5e01 c.li x28,-32
- 2f8: 00072007 flw f0,0(x14)
- 2fc: 3400 c.fld f8,40(x8)
+ 2f8: 0006fc07 0x6fc07
+ 2fc: 1000 c.addi4spn x8,x2,32
2fe: 01000007 0x1000007
302: 075c c.addi4spn x15,x2,900
- 304: 0734 c.addi4spn x13,x2,904
+ 304: 0710 c.addi4spn x12,x2,896
306: 0000 c.unimp
- 308: 0738 c.addi4spn x14,x2,904
+ 308: 0714 c.addi4spn x13,x2,896
30a: 0000 c.unimp
30c: 7c09 c.lui x24,0xfffe2
30e: 7b00 c.flw f8,48(x14)
310: 0800 c.addi4spn x8,x2,16
312: 1aff 0x1aff
314: 9f24 0x9f24
- 316: 00073807 fld f16,0(x14)
- 31a: e000 c.fsw f8,0(x8)
+ 316: 00071407 0x71407
+ 31a: bc00 c.fsd f8,56(x8)
31c: 01000007 0x1000007
320: 075e c.slli x14,0x17
- 322: 07e0 c.addi4spn x8,x2,972
+ 322: 07bc c.addi4spn x15,x2,968
324: 0000 c.unimp
- 326: 090c c.addi4spn x11,x2,144
+ 326: 08e8 c.addi4spn x10,x2,92
328: 0000 c.unimp
32a: 5c01 c.li x24,-32
- 32c: 00096c07 0x96c07
- 330: 7800 c.flw f8,48(x8)
+ 32c: 00094807 flq f16,0(x18)
+ 330: 5400 c.lw x8,40(x8)
332: 0009 c.addi x0,2
334: 0100 c.addi4spn x8,x2,128
336: 005c c.addi4spn x15,x2,4
- 338: 00055407 0x55407
- 33c: 7000 c.flw f8,32(x8)
+ 338: 00053007 fld f0,0(x10)
+ 33c: 4c00 c.lw x8,24(x8)
33e: 0005 c.addi x0,1
340: 0100 c.addi4spn x8,x2,128
342: 075d c.addi x14,23
- 344: 0654 c.addi4spn x13,x2,772
+ 344: 0630 c.addi4spn x12,x2,776
346: 0000 c.unimp
- 348: 0668 c.addi4spn x10,x2,780
+ 348: 0644 c.addi4spn x9,x2,772
34a: 0000 c.unimp
34c: 5d01 c.li x26,-32
- 34e: 00072007 flw f0,0(x14)
- 352: 2800 c.fld f8,16(x8)
+ 34e: 0006fc07 0x6fc07
+ 352: 0400 c.addi4spn x8,x2,512
354: 01000007 0x1000007
358: 075d c.addi x14,23
- 35a: 07e0 c.addi4spn x8,x2,972
+ 35a: 07bc c.addi4spn x15,x2,968
35c: 0000 c.unimp
- 35e: 084c c.addi4spn x11,x2,20
+ 35e: 0828 c.addi4spn x10,x2,24
360: 0000 c.unimp
362: 5d01 c.li x26,-32
- 364: 00085007 0x85007
- 368: f800 c.fsw f8,48(x8)
+ 364: 00082c07 flw f24,0(x16) # f000 <__global_pointer$+0xd7c8>
+ 368: d400 c.sw x8,40(x8)
36a: 0008 0x8
36c: 0100 c.addi4spn x8,x2,128
36e: 075d c.addi x14,23
- 370: 096c c.addi4spn x11,x2,156
+ 370: 0948 c.addi4spn x10,x2,148
372: 0000 c.unimp
- 374: 0978 c.addi4spn x14,x2,156
+ 374: 0954 c.addi4spn x13,x2,148
376: 0000 c.unimp
378: 5d01 c.li x26,-32
37a: 0700 c.addi4spn x8,x2,896
- 37c: 0558 c.addi4spn x14,x2,644
+ 37c: 0534 c.addi4spn x13,x2,648
37e: 0000 c.unimp
- 380: 0580 c.addi4spn x8,x2,704
+ 380: 055c c.addi4spn x15,x2,644
382: 0000 c.unimp
384: 5a01 c.li x20,-32
- 386: 00058007 0x58007
- 38a: b000 c.fsd f8,32(x8)
+ 386: 00055c07 0x55c07
+ 38a: 8c00 0x8c00
38c: 0005 c.addi x0,1
38e: 0100 c.addi4spn x8,x2,128
390: 0756 c.slli x14,0x15
- 392: 05b0 c.addi4spn x12,x2,712
+ 392: 058c c.addi4spn x11,x2,704
394: 0000 c.unimp
- 396: 0600 c.addi4spn x8,x2,768
+ 396: 05dc c.addi4spn x15,x2,708
398: 0000 c.unimp
39a: 6001 0x6001
- 39c: 00064007 flq f0,0(x12)
- 3a0: 9400 0x9400
+ 39c: 00061c07 0x61c07
+ 3a0: 7000 c.flw f8,32(x8)
3a2: 0006 c.slli x0,0x1
3a4: 0100 c.addi4spn x8,x2,128
3a6: 0756 c.slli x14,0x15
- 3a8: 0694 c.addi4spn x13,x2,832
+ 3a8: 0670 c.addi4spn x12,x2,780
3aa: 0000 c.unimp
- 3ac: 06e4 c.addi4spn x9,x2,844
+ 3ac: 06c0 c.addi4spn x8,x2,836
3ae: 0000 c.unimp
3b0: 6001 0x6001
- 3b2: 00072007 flw f0,0(x14)
- 3b6: 4c00 c.lw x8,24(x8)
+ 3b2: 0006fc07 0x6fc07
+ 3b6: 2800 c.fld f8,16(x8)
3b8: 01000007 0x1000007
3bc: 0756 c.slli x14,0x15
- 3be: 075c c.addi4spn x15,x2,900
+ 3be: 0738 c.addi4spn x14,x2,904
3c0: 0000 c.unimp
- 3c2: 07e0 c.addi4spn x8,x2,972
+ 3c2: 07bc c.addi4spn x15,x2,968
3c4: 0000 c.unimp
3c6: 6001 0x6001
- 3c8: 0007e007 0x7e007
- 3cc: 7400 c.flw f8,40(x8)
+ 3c8: 0007bc07 fld f24,0(x15)
+ 3cc: 5000 c.lw x8,32(x8)
3ce: 0008 0x8
3d0: 0100 c.addi4spn x8,x2,128
3d2: 0756 c.slli x14,0x15
- 3d4: 0874 c.addi4spn x13,x2,28
+ 3d4: 0850 c.addi4spn x12,x2,20
3d6: 0000 c.unimp
- 3d8: 0958 c.addi4spn x14,x2,148
+ 3d8: 0934 c.addi4spn x13,x2,152
3da: 0000 c.unimp
3dc: 7606 c.flwsp f12,96(x2)
3de: 7b00 c.flw f8,48(x14)
3e0: 2400 c.fld f8,8(x8)
- 3e2: 079f 096c 0000 0x96c079f
- 3e8: 0978 c.addi4spn x14,x2,156
+ 3e2: 079f 0948 0000 0x948079f
+ 3e8: 0954 c.addi4spn x13,x2,148
3ea: 0000 c.unimp
3ec: 5601 c.li x12,-32
3ee: 0700 c.addi4spn x8,x2,896
- 3f0: 055c c.addi4spn x15,x2,644
+ 3f0: 0538 c.addi4spn x14,x2,648
3f2: 0000 c.unimp
- 3f4: 0564 c.addi4spn x9,x2,652
+ 3f4: 0540 c.addi4spn x8,x2,644
3f6: 0000 c.unimp
3f8: 5b01 c.li x22,-32
- 3fa: 00056407 0x56407
- 3fe: a000 c.fsd f8,0(x8)
+ 3fa: 00054007 flq f0,0(x10)
+ 3fe: 7c00 c.flw f8,56(x8)
400: 0005 c.addi x0,1
402: 0100 c.addi4spn x8,x2,128
- 404: 075f 05a0 0000 0x5a0075f
- 40a: 05ac c.addi4spn x11,x2,712
+ 404: 075f 057c 0000 0x57c075f
+ 40a: 0588 c.addi4spn x10,x2,704
40c: 0000 c.unimp
40e: 6101 c.addi16sp x2,0
- 410: 0005ac07 flw f24,0(x11)
- 414: c400 c.sw x8,8(x8)
+ 410: 00058807 0x58807
+ 414: a000 c.fsd f8,0(x8)
416: 0005 c.addi x0,1
418: 0100 c.addi4spn x8,x2,128
- 41a: 075f 0640 0000 0x640075f
- 420: 0660 c.addi4spn x8,x2,780
+ 41a: 075f 061c 0000 0x61c075f
+ 420: 063c c.addi4spn x15,x2,776
422: 0000 c.unimp
424: 5f01 c.li x30,-32
- 426: 00066007 0x66007
- 42a: 9000 0x9000
+ 426: 00063c07 fld f24,0(x12)
+ 42a: 6c00 c.flw f8,24(x8)
42c: 0006 c.slli x0,0x1
42e: 0100 c.addi4spn x8,x2,128
430: 0761 c.addi x14,24
- 432: 0690 c.addi4spn x12,x2,832
+ 432: 066c c.addi4spn x11,x2,780
434: 0000 c.unimp
- 436: 06ac c.addi4spn x11,x2,840
+ 436: 0688 c.addi4spn x10,x2,832
438: 0000 c.unimp
43a: 5f01 c.li x30,-32
- 43c: 00072007 flw f0,0(x14)
- 440: 5400 c.lw x8,40(x8)
+ 43c: 0006fc07 0x6fc07
+ 440: 3000 c.fld f8,32(x8)
442: 01000007 0x1000007
446: 0761 c.addi x14,24
- 448: 075c c.addi4spn x15,x2,900
+ 448: 0738 c.addi4spn x14,x2,904
44a: 0000 c.unimp
- 44c: 079c c.addi4spn x15,x2,960
+ 44c: 0778 c.addi4spn x14,x2,908
44e: 0000 c.unimp
450: 5f01 c.li x30,-32
- 452: 0007dc07 0x7dc07
- 456: e000 c.fsw f8,0(x8)
+ 452: 0007b807 fld f16,0(x15)
+ 456: bc00 c.fsd f8,56(x8)
458: 01000007 0x1000007
- 45c: 075f 07e0 0000 0x7e0075f
- 462: 0800 c.addi4spn x8,x2,16
+ 45c: 075f 07bc 0000 0x7bc075f
+ 462: 07dc c.addi4spn x15,x2,964
464: 0000 c.unimp
466: 5b01 c.li x22,-32
- 468: 00080007 0x80007
- 46c: 3000 c.fld f8,32(x8)
+ 468: 0007dc07 0x7dc07
+ 46c: 0c00 c.addi4spn x8,x2,528
46e: 0008 0x8
470: 0100 c.addi4spn x8,x2,128
472: 0761 c.addi x14,24
- 474: 0830 c.addi4spn x12,x2,24
+ 474: 080c c.addi4spn x11,x2,16
476: 0000 c.unimp
- 478: 0844 c.addi4spn x9,x2,20
+ 478: 0820 c.addi4spn x8,x2,24
47a: 0000 c.unimp
47c: 5b01 c.li x22,-32
- 47e: 00084407 flq f8,0(x16)
- 482: 5800 c.lw x8,48(x8)
+ 47e: 00082007 flw f0,0(x16)
+ 482: 3400 c.fld f8,40(x8)
484: 0008 0x8
486: 0100 c.addi4spn x8,x2,128
488: 0761 c.addi x14,24
- 48a: 0874 c.addi4spn x13,x2,28
+ 48a: 0850 c.addi4spn x12,x2,20
48c: 0000 c.unimp
- 48e: 08b4 c.addi4spn x13,x2,88
+ 48e: 0890 c.addi4spn x12,x2,80
490: 0000 c.unimp
492: 5f01 c.li x30,-32
- 494: 00090007 0x90007
- 498: 4400 c.lw x8,8(x8)
+ 494: 0008dc07 0x8dc07
+ 498: 2000 c.fld f8,0(x8)
49a: 0009 c.addi x0,2
49c: 0100 c.addi4spn x8,x2,128
- 49e: 075f 096c 0000 0x96c075f
- 4a4: 0970 c.addi4spn x12,x2,156
+ 49e: 075f 0948 0000 0x948075f
+ 4a4: 094c c.addi4spn x11,x2,148
4a6: 0000 c.unimp
4a8: 5b01 c.li x22,-32
- 4aa: 00097007 0x97007
- 4ae: 7800 c.flw f8,48(x8)
+ 4aa: 00094c07 flq f24,0(x18)
+ 4ae: 5400 c.lw x8,40(x8)
4b0: 0009 c.addi x0,2
4b2: 0100 c.addi4spn x8,x2,128
- 4b4: 005f 3c07 0007 0x73c07005f
- 4ba: 6000 c.flw f8,0(x8)
+ 4b4: 005f 1807 0007 0x71807005f
+ 4ba: 3c00 c.fld f8,56(x8)
4bc: 01000007 0x1000007
4c0: 075d c.addi x14,23
- 4c2: 0874 c.addi4spn x13,x2,28
+ 4c2: 0850 c.addi4spn x12,x2,20
4c4: 0000 c.unimp
- 4c6: 0878 c.addi4spn x14,x2,28
+ 4c6: 0854 c.addi4spn x13,x2,20
4c8: 0000 c.unimp
4ca: 5e01 c.li x28,-32
4cc: 0700 c.addi4spn x8,x2,896
- 4ce: 0638 c.addi4spn x14,x2,776
+ 4ce: 0614 c.addi4spn x13,x2,768
4d0: 0000 c.unimp
- 4d2: 063c c.addi4spn x15,x2,776
+ 4d2: 0618 c.addi4spn x14,x2,768
4d4: 0000 c.unimp
4d6: 5a01 c.li x20,-32
- 4d8: 00071c07 0x71c07
- 4dc: 2000 c.fld f8,0(x8)
- 4de: 01000007 0x1000007
+ 4d8: 0006f807 0x6f807
+ 4dc: fc00 c.fsw f8,56(x8)
+ 4de: 0006 c.slli x0,0x1
+ 4e0: 0100 c.addi4spn x8,x2,128
4e2: 075a c.slli x14,0x16
- 4e4: 0900 c.addi4spn x8,x2,144
+ 4e4: 08dc c.addi4spn x15,x2,84
4e6: 0000 c.unimp
- 4e8: 096c c.addi4spn x11,x2,156
+ 4e8: 0948 c.addi4spn x10,x2,148
4ea: 0000 c.unimp
4ec: 5a01 c.li x20,-32
4ee: 0700 c.addi4spn x8,x2,896
- 4f0: 0690 c.addi4spn x12,x2,832
+ 4f0: 066c c.addi4spn x11,x2,780
4f2: 0000 c.unimp
- 4f4: 0694 c.addi4spn x13,x2,832
+ 4f4: 0670 c.addi4spn x12,x2,780
4f6: 0000 c.unimp
4f8: 3102 c.fldsp f2,32(x2)
- 4fa: 079f 0694 0000 0x694079f
- 500: 0720 c.addi4spn x8,x2,904
+ 4fa: 079f 0670 0000 0x670079f
+ 500: 06fc c.addi4spn x15,x2,844
502: 0000 c.unimp
504: 5b01 c.li x22,-32
- 506: 0007dc07 0x7dc07
- 50a: e000 c.fsw f8,0(x8)
+ 506: 0007b807 fld f16,0(x15)
+ 50a: bc00 c.fsd f8,56(x8)
50c: 01000007 0x1000007
- 510: 3407005b 0x3407005b
- 514: 44000007 0x44000007
+ 510: 1007005b 0x1007005b
+ 514: 20000007 0x20000007
518: 01000007 0x1000007
- 51c: 075f 0844 0000 0x844075f
- 522: 085c c.addi4spn x15,x2,20
+ 51c: 075f 0820 0000 0x820075f
+ 522: 0838 c.addi4spn x14,x2,24
524: 0000 c.unimp
526: 5f01 c.li x30,-32
528: 0700 c.addi4spn x8,x2,896
- 52a: 0598 c.addi4spn x14,x2,704
+ 52a: 0574 c.addi4spn x13,x2,652
52c: 0000 c.unimp
- 52e: 05b4 c.addi4spn x13,x2,712
+ 52e: 0590 c.addi4spn x12,x2,704
530: 0000 c.unimp
532: 5b01 c.li x22,-32
- 534: 00068807 0x68807
- 538: 9400 0x9400
+ 534: 00066407 0x66407
+ 538: 7000 c.flw f8,32(x8)
53a: 0006 c.slli x0,0x1
53c: 0100 c.addi4spn x8,x2,128
- 53e: 0734075b 0x734075b
+ 53e: 0710075b 0x710075b
542: 0000 c.unimp
- 544: 0768 c.addi4spn x10,x2,908
+ 544: 0744 c.addi4spn x9,x2,900
546: 0000 c.unimp
548: 5b01 c.li x22,-32
- 54a: 00081807 0x81807
- 54e: 3000 c.fld f8,32(x8)
+ 54a: 0007f407 0x7f407
+ 54e: 0c00 c.addi4spn x8,x2,528
550: 0008 0x8
552: 0100 c.addi4spn x8,x2,128
- 554: 0844075b 0x844075b
+ 554: 0820075b 0x820075b
558: 0000 c.unimp
- 55a: 0960 c.addi4spn x8,x2,156
+ 55a: 093c c.addi4spn x15,x2,152
55c: 0000 c.unimp
55e: 5b01 c.li x22,-32
560: 0700 c.addi4spn x8,x2,896
- 562: 056c c.addi4spn x11,x2,652
+ 562: 0548 c.addi4spn x10,x2,644
564: 0000 c.unimp
- 566: 059c c.addi4spn x15,x2,704
+ 566: 0578 c.addi4spn x14,x2,652
568: 0000 c.unimp
56a: 5c01 c.li x24,-32
- 56c: 00059c07 0x59c07
- 570: a800 c.fsd f8,16(x8)
+ 56c: 00057807 0x57807
+ 570: 8400 0x8400
572: 0005 c.addi x0,1
574: 0900 c.addi4spn x8,x2,144
576: 007c c.addi4spn x15,x2,12
578: ff08007b 0xff08007b
57c: 241a c.fldsp f8,384(x2)
- 57e: 079f 05a8 0000 0x5a8079f
- 584: 0638 c.addi4spn x14,x2,776
+ 57e: 079f 0584 0000 0x584079f
+ 584: 0614 c.addi4spn x13,x2,768
586: 0000 c.unimp
588: 5e01 c.li x28,-32
- 58a: 00064007 flq f0,0(x12)
- 58e: 5400 c.lw x8,40(x8)
+ 58a: 00061c07 0x61c07
+ 58e: 3000 c.fld f8,32(x8)
590: 0006 c.slli x0,0x1
592: 0100 c.addi4spn x8,x2,128
594: 005c c.addi4spn x15,x2,4
- 596: 00058007 0x58007
- 59a: 9400 0x9400
+ 596: 00055c07 0x55c07
+ 59a: 7000 c.flw f8,32(x8)
59c: 0005 c.addi x0,1
59e: 0100 c.addi4spn x8,x2,128
5a0: 005d c.addi x0,23
- 5a2: 0005b407 fld f8,0(x11)
- 5a6: 3800 c.fld f8,48(x8)
+ 5a2: 00059007 0x59007
+ 5a6: 1400 c.addi4spn x8,x2,544
5a8: 0006 c.slli x0,0x1
5aa: 0100 c.addi4spn x8,x2,128
- 5ac: c007005b 0xc007005b
+ 5ac: 9c07005b 0x9c07005b
5b0: 0005 c.addi x0,1
- 5b2: 3800 c.fld f8,48(x8)
+ 5b2: 1400 c.addi4spn x8,x2,544
5b4: 0006 c.slli x0,0x1
5b6: 0100 c.addi4spn x8,x2,128
5b8: 005c c.addi4spn x15,x2,4
- 5ba: 0005c007 flq f0,0(x11)
- 5be: e400 c.fsw f8,8(x8)
+ 5ba: 00059c07 0x59c07
+ 5be: c000 c.sw x8,0(x8)
5c0: 0005 c.addi x0,1
5c2: 0100 c.addi4spn x8,x2,128
5c4: 0756 c.slli x14,0x15
- 5c6: 05e4 c.addi4spn x9,x2,716
+ 5c6: 05c0 c.addi4spn x8,x2,708
5c8: 0000 c.unimp
- 5ca: 0634 c.addi4spn x13,x2,776
+ 5ca: 0610 c.addi4spn x12,x2,768
5cc: 0000 c.unimp
5ce: 5a01 c.li x20,-32
5d0: 0700 c.addi4spn x8,x2,896
- 5d2: 05fc c.addi4spn x15,x2,716
+ 5d2: 05d8 c.addi4spn x14,x2,708
5d4: 0000 c.unimp
- 5d6: 0624 c.addi4spn x9,x2,776
+ 5d6: 0600 c.addi4spn x8,x2,768
5d8: 0000 c.unimp
5da: 6101 c.addi16sp x2,0
- 5dc: 00062407 flw f8,0(x12)
- 5e0: 3800 c.fld f8,48(x8)
+ 5dc: 00060007 0x60007
+ 5e0: 1400 c.addi4spn x8,x2,544
5e2: 0006 c.slli x0,0x1
5e4: 0100 c.addi4spn x8,x2,128
- 5e6: 005f c007 0005 0x5c007005f
- 5ec: c400 c.sw x8,8(x8)
+ 5e6: 005f 9c07 0005 0x59c07005f
+ 5ec: a000 c.fsd f8,0(x8)
5ee: 0005 c.addi x0,1
5f0: 0600 c.addi4spn x8,x2,768
5f2: 007f 0x7f
5f4: 9f1d007b 0x9f1d007b
- 5f8: 0005c407 flq f8,0(x11)
- 5fc: d400 c.sw x8,40(x8)
+ 5f8: 0005a007 flw f0,0(x11)
+ 5fc: b000 c.fsd f8,32(x8)
5fe: 0005 c.addi x0,1
600: 0100 c.addi4spn x8,x2,128
- 602: 075f 05d8 0000 0x5d8075f
- 608: 05e0 c.addi4spn x8,x2,716
+ 602: 075f 05b4 0000 0x5b4075f
+ 608: 05bc c.addi4spn x15,x2,712
60a: 0000 c.unimp
60c: 5f01 c.li x30,-32
- 60e: 0005e007 0x5e007
- 612: e400 c.fsw f8,8(x8)
+ 60e: 0005bc07 fld f24,0(x11)
+ 612: c000 c.sw x8,0(x8)
614: 0005 c.addi x0,1
616: 0800 c.addi4spn x8,x2,16
618: 0080 c.addi4spn x8,x2,64
61a: 2540 c.fld f8,136(x10)
61c: 007d c.addi x0,31
61e: 9f21 0x9f21
- 620: 0005e407 0x5e407
- 624: 0800 c.addi4spn x8,x2,16
- 626: 0006 c.slli x0,0x1
+ 620: 0005c007 flq f0,0(x11)
+ 624: e400 c.fsw f8,8(x8)
+ 626: 0005 c.addi x0,1
628: 0100 c.addi4spn x8,x2,128
- 62a: 005f f807 0005 0x5f807005f
- 630: 0800 c.addi4spn x8,x2,16
- 632: 0006 c.slli x0,0x1
+ 62a: 005f d407 0005 0x5d407005f
+ 630: e400 c.fsw f8,8(x8)
+ 632: 0005 c.addi x0,1
634: 0600 c.addi4spn x8,x2,768
636: 007f 0x7f
638: 9f1d007b 0x9f1d007b
- 63c: 00060807 0x60807
- 640: 1000 c.addi4spn x8,x2,32
- 642: 0006 c.slli x0,0x1
+ 63c: 0005e407 0x5e407
+ 640: ec00 c.fsw f8,24(x8)
+ 642: 0005 c.addi x0,1
644: 0100 c.addi4spn x8,x2,128
- 646: 075f 0614 0000 0x614075f
- 64c: 0620 c.addi4spn x8,x2,776
+ 646: 075f 05f0 0000 0x5f0075f
+ 64c: 05fc c.addi4spn x15,x2,716
64e: 0000 c.unimp
650: 6001 0x6001
652: 0700 c.addi4spn x8,x2,896
- 654: 05cc c.addi4spn x11,x2,708
+ 654: 05a8 c.addi4spn x10,x2,712
656: 0000 c.unimp
- 658: 05fc c.addi4spn x15,x2,716
+ 658: 05d8 c.addi4spn x14,x2,708
65a: 0000 c.unimp
65c: 6101 c.addi16sp x2,0
- 65e: 0005fc07 0x5fc07
- 662: 0c00 c.addi4spn x8,x2,528
- 664: 0006 c.slli x0,0x1
+ 65e: 0005d807 0x5d807
+ 662: e800 c.fsw f8,16(x8)
+ 664: 0005 c.addi x0,1
666: 0600 c.addi4spn x8,x2,768
668: 007c c.addi4spn x15,x2,12
66a: 0076 c.slli x0,0x1d
66c: 9f1e c.add x30,x7
- 66e: 00060c07 0x60c07
- 672: 3800 c.fld f8,48(x8)
+ 66e: 0005e807 0x5e807
+ 672: 1400 c.addi4spn x8,x2,544
674: 0006 c.slli x0,0x1
676: 0100 c.addi4spn x8,x2,128
678: 005d c.addi x0,23
- 67a: 00093807 fld f16,0(x18) # 1d000 <__global_pointer$+0x1b7c8>
- 67e: 6800 c.flw f8,16(x8)
+ 67a: 00091407 0x91407
+ 67e: 4400 c.lw x8,8(x8)
680: 0009 c.addi x0,2
682: 0100 c.addi4spn x8,x2,128
684: 005d c.addi x0,23
- 686: 00093807 fld f16,0(x18)
- 68a: 4c00 c.lw x8,24(x8)
+ 686: 00091407 0x91407
+ 68a: 2800 c.fld f8,16(x8)
68c: 0009 c.addi x0,2
68e: 1000 c.addi4spn x8,x2,32
690: 0081 c.addi x1,0
@@ -4088,8 +4078,8 @@ Disassembly of section .debug_loclists:
69a: 1aff 0x1aff
69c: 2440 c.fld f8,136(x8)
69e: 9f22 c.add x30,x8
- 6a0: 00094c07 flq f24,0(x18)
- 6a4: 5400 c.lw x8,40(x8)
+ 6a0: 00092807 flw f16,0(x18)
+ 6a4: 3000 c.fld f8,32(x8)
6a6: 0009 c.addi x0,2
6a8: 1500 c.addi4spn x8,x2,672
6aa: 0081 c.addi x1,0
@@ -4102,128 +4092,128 @@ Disassembly of section .debug_loclists:
6b8: ffff 0xffff
6ba: 401a 0x401a
6bc: 2224 c.fld f9,64(x12)
- 6be: 009f 7407 0008 0x87407009f
- 6c4: 1000 c.addi4spn x8,x2,32
- 6c6: 0009 c.addi x0,2
+ 6be: 009f 5007 0008 0x85007009f
+ 6c4: ec00 c.fsw f8,24(x8)
+ 6c6: 0008 0x8
6c8: 0100 c.addi4spn x8,x2,128
6ca: 0061 c.addi x0,24
- 6cc: 00087407 0x87407
- 6d0: c000 c.sw x8,0(x8)
+ 6cc: 00085007 0x85007
+ 6d0: 9c00 0x9c00
6d2: 0008 0x8
6d4: 0100 c.addi4spn x8,x2,128
6d6: 0760 c.addi4spn x8,x2,908
- 6d8: 08c0 c.addi4spn x8,x2,84
+ 6d8: 089c c.addi4spn x15,x2,80
6da: 0000 c.unimp
- 6dc: 08f8 c.addi4spn x14,x2,92
+ 6dc: 08d4 c.addi4spn x13,x2,84
6de: 0000 c.unimp
6e0: 40007d07 0x40007d07
6e4: 4024 c.lw x9,64(x8)
6e6: 9f25 0x9f25
6e8: 0700 c.addi4spn x8,x2,896
- 6ea: 0874 c.addi4spn x13,x2,28
+ 6ea: 0850 c.addi4spn x12,x2,20
6ec: 0000 c.unimp
- 6ee: 0898 c.addi4spn x14,x2,80
+ 6ee: 0874 c.addi4spn x13,x2,28
6f0: 0000 c.unimp
6f2: 6d01 0x6d01
- 6f4: 00089807 0x89807
- 6f8: ec00 c.fsw f8,24(x8)
+ 6f4: 00087407 0x87407
+ 6f8: c800 c.sw x8,16(x8)
6fa: 0008 0x8
6fc: 0100 c.addi4spn x8,x2,128
6fe: 005a c.slli x0,0x16
- 700: 0008b007 fld f0,0(x17)
- 704: d800 c.sw x8,48(x8)
+ 700: 00088c07 0x88c07
+ 704: b400 c.fsd f8,40(x8)
706: 0008 0x8
708: 0100 c.addi4spn x8,x2,128
70a: 076c c.addi4spn x11,x2,908
- 70c: 08d8 c.addi4spn x14,x2,84
+ 70c: 08b4 c.addi4spn x13,x2,88
70e: 0000 c.unimp
- 710: 08fc c.addi4spn x15,x2,92
+ 710: 08d8 c.addi4spn x14,x2,84
712: 0000 c.unimp
714: 5e01 c.li x28,-32
716: 0700 c.addi4spn x8,x2,896
- 718: 0874 c.addi4spn x13,x2,28
+ 718: 0850 c.addi4spn x12,x2,20
71a: 0000 c.unimp
- 71c: 0878 c.addi4spn x14,x2,28
+ 71c: 0854 c.addi4spn x13,x2,20
71e: 0000 c.unimp
720: 7e06 c.flwsp f28,96(x2)
722: 8100 0x8100
724: 1d00 c.addi4spn x8,x2,688
- 726: 079f 0878 0000 0x878079f
- 72c: 0884 c.addi4spn x9,x2,80
+ 726: 079f 0854 0000 0x854079f
+ 72c: 0860 c.addi4spn x8,x2,28
72e: 0000 c.unimp
730: 5e01 c.li x28,-32
- 732: 00088807 0x88807
- 736: 9400 0x9400
+ 732: 00086407 0x86407
+ 736: 7000 c.flw f8,32(x8)
738: 0008 0x8
73a: 0100 c.addi4spn x8,x2,128
73c: 075e c.slli x14,0x17
- 73e: 0898 c.addi4spn x14,x2,80
+ 73e: 0874 c.addi4spn x13,x2,28
740: 0000 c.unimp
- 742: 08bc c.addi4spn x15,x2,88
+ 742: 0898 c.addi4spn x14,x2,80
744: 0000 c.unimp
746: 5e01 c.li x28,-32
748: 0700 c.addi4spn x8,x2,896
- 74a: 08ac c.addi4spn x11,x2,88
+ 74a: 0888 c.addi4spn x10,x2,80
74c: 0000 c.unimp
- 74e: 08bc c.addi4spn x15,x2,88
+ 74e: 0898 c.addi4spn x14,x2,80
750: 0000 c.unimp
752: 7e06 c.flwsp f28,96(x2)
754: 8100 0x8100
756: 1d00 c.addi4spn x8,x2,688
- 758: 079f 08bc 0000 0x8bc079f
- 75e: 08c4 c.addi4spn x9,x2,84
+ 758: 079f 0898 0000 0x898079f
+ 75e: 08a0 c.addi4spn x8,x2,88
760: 0000 c.unimp
762: 5e01 c.li x28,-32
- 764: 0008c807 flq f16,0(x17)
- 768: d400 c.sw x8,40(x8)
+ 764: 0008a407 flw f8,0(x17)
+ 768: b000 c.fsd f8,32(x8)
76a: 0008 0x8
76c: 0100 c.addi4spn x8,x2,128
- 76e: 075f 08d8 0000 0x8d8075f
- 774: 0944 c.addi4spn x9,x2,148
+ 76e: 075f 08b4 0000 0x8b4075f
+ 774: 0920 c.addi4spn x8,x2,152
776: 0000 c.unimp
778: 5f01 c.li x30,-32
77a: 0700 c.addi4spn x8,x2,896
- 77c: 087c c.addi4spn x15,x2,28
+ 77c: 0858 c.addi4spn x14,x2,20
77e: 0000 c.unimp
- 780: 08b0 c.addi4spn x12,x2,88
+ 780: 088c c.addi4spn x11,x2,80
782: 0000 c.unimp
784: 6c01 0x6c01
- 786: 0008b007 fld f0,0(x17)
- 78a: c000 c.sw x8,0(x8)
+ 786: 00088c07 0x88c07
+ 78a: 9c00 0x9c00
78c: 0008 0x8
78e: 0600 c.addi4spn x8,x2,768
790: 0080 c.addi4spn x8,x2,64
792: 008d c.addi x1,3
794: 9f1e c.add x30,x7
- 796: 0008c007 flq f0,0(x17)
- 79a: 0800 c.addi4spn x8,x2,16
- 79c: 0009 c.addi x0,2
+ 796: 00089c07 0x89c07
+ 79a: e400 c.fsw f8,8(x8)
+ 79c: 0008 0x8
79e: 0100 c.addi4spn x8,x2,128
7a0: 0060 c.addi4spn x8,x2,12
- 7a2: 00091007 0x91007
- 7a6: 5400 c.lw x8,40(x8)
+ 7a2: 0008ec07 0x8ec07
+ 7a6: 3000 c.fld f8,32(x8)
7a8: 0009 c.addi x0,2
7aa: 0100 c.addi4spn x8,x2,128
7ac: 0061 c.addi x0,24
- 7ae: 00091007 0x91007
- 7b2: 1800 c.addi4spn x8,x2,48
- 7b4: 0009 c.addi x0,2
+ 7ae: 0008ec07 0x8ec07
+ 7b2: f400 c.fsw f8,40(x8)
+ 7b4: 0008 0x8
7b6: 0600 c.addi4spn x8,x2,768
7b8: 007e c.slli x0,0x1f
7ba: 007c c.addi4spn x15,x2,12
7bc: 9f1e c.add x30,x7
- 7be: 00091807 0x91807
- 7c2: 2000 c.fld f8,0(x8)
- 7c4: 0009 c.addi x0,2
+ 7be: 0008f407 0x8f407
+ 7c2: fc00 c.fsw f8,56(x8)
+ 7c4: 0008 0x8
7c6: 0100 c.addi4spn x8,x2,128
7c8: 075e c.slli x14,0x17
- 7ca: 0928 c.addi4spn x10,x2,152
+ 7ca: 0904 c.addi4spn x9,x2,144
7cc: 0000 c.unimp
- 7ce: 094c c.addi4spn x11,x2,148
+ 7ce: 0928 c.addi4spn x10,x2,152
7d0: 0000 c.unimp
7d2: 5e01 c.li x28,-32
- 7d4: 00094c07 flq f24,0(x18)
- 7d8: 5400 c.lw x8,40(x8)
+ 7d4: 00092807 flw f16,0(x18)
+ 7d8: 3000 c.fld f8,32(x8)
7da: 0009 c.addi x0,2
7dc: 0800 c.addi4spn x8,x2,16
7de: 0081 c.addi x1,0
@@ -4231,294 +4221,298 @@ Disassembly of section .debug_loclists:
7e2: 007c c.addi4spn x15,x2,12
7e4: 9f22 c.add x30,x8
7e6: 0700 c.addi4spn x8,x2,896
- 7e8: 0914 c.addi4spn x13,x2,144
+ 7e8: 08f0 c.addi4spn x12,x2,92
7ea: 0000 c.unimp
- 7ec: 0934 c.addi4spn x13,x2,152
+ 7ec: 0910 c.addi4spn x12,x2,144
7ee: 0000 c.unimp
7f0: 5d01 c.li x26,-32
7f2: 0700 c.addi4spn x8,x2,896
- 7f4: 091c c.addi4spn x15,x2,144
+ 7f4: 08f8 c.addi4spn x14,x2,92
7f6: 0000 c.unimp
- 7f8: 096c c.addi4spn x11,x2,156
+ 7f8: 0948 c.addi4spn x10,x2,148
7fa: 0000 c.unimp
7fc: 6001 0x6001
7fe: 0700 c.addi4spn x8,x2,896
- 800: 0900 c.addi4spn x8,x2,144
+ 800: 08dc c.addi4spn x15,x2,84
802: 0000 c.unimp
- 804: 0918 c.addi4spn x14,x2,144
+ 804: 08f4 c.addi4spn x13,x2,92
806: 0000 c.unimp
808: 5e01 c.li x28,-32
- 80a: 00091807 0x91807
- 80e: 4800 c.lw x8,16(x8)
+ 80a: 0008f407 0x8f407
+ 80e: 2400 c.fld f8,8(x8)
810: 0009 c.addi x0,2
812: 0600 c.addi4spn x8,x2,768
814: 7f8c c.flw f11,56(x15)
816: 007a c.slli x0,0x1e
818: 9f1a c.add x30,x6
- 81a: 00094807 flq f16,0(x18)
- 81e: 6400 c.flw f8,8(x8)
+ 81a: 00092407 flw f8,0(x18)
+ 81e: 4000 c.lw x8,0(x8)
820: 0009 c.addi x0,2
822: 0600 c.addi4spn x8,x2,768
824: 007a c.slli x0,0x1e
826: 007f 0x7f
828: 9f1a c.add x30,x6
- 82a: 00096407 0x96407
- 82e: 6800 c.flw f8,16(x8)
+ 82a: 00094007 flq f0,0(x18)
+ 82e: 4400 c.lw x8,8(x8)
830: 0009 c.addi x0,2
832: 0600 c.addi4spn x8,x2,768
834: 7f8c c.flw f11,56(x15)
836: 007a c.slli x0,0x1e
838: 9f1a c.add x30,x6
- 83a: 00096807 0x96807
- 83e: 6c00 c.flw f8,24(x8)
+ 83a: 00094407 flq f8,0(x18)
+ 83e: 4800 c.lw x8,16(x8)
840: 0009 c.addi x0,2
842: 0600 c.addi4spn x8,x2,768
844: 017a c.slli x2,0x1e
846: 7f8c c.flw f11,56(x15)
848: 9f1a c.add x30,x6
84a: 0700 c.addi4spn x8,x2,896
- 84c: 0908 c.addi4spn x10,x2,144
+ 84c: 08e4 c.addi4spn x9,x2,92
84e: 0000 c.unimp
- 850: 0914 c.addi4spn x13,x2,144
+ 850: 08f0 c.addi4spn x12,x2,92
852: 0000 c.unimp
854: 5d01 c.li x26,-32
856: 0700 c.addi4spn x8,x2,896
- 858: 0908 c.addi4spn x10,x2,144
+ 858: 08e4 c.addi4spn x9,x2,92
85a: 0000 c.unimp
- 85c: 091c c.addi4spn x15,x2,144
+ 85c: 08f8 c.addi4spn x14,x2,92
85e: 0000 c.unimp
860: 6001 0x6001
- 862: 00091c07 0x91c07
- 866: 6800 c.flw f8,16(x8)
+ 862: 0008f807 0x8f807
+ 866: 4400 c.lw x8,8(x8)
868: 0009 c.addi x0,2
86a: 0500 c.addi4spn x8,x2,640
86c: 007a c.slli x0,0x1e
86e: 2540 c.fld f8,136(x10)
- 870: 079f 0968 0000 0x968079f
- 876: 096c c.addi4spn x11,x2,156
+ 870: 079f 0944 0000 0x944079f
+ 876: 0948 c.addi4spn x10,x2,148
878: 0000 c.unimp
87a: 7a05 c.lui x20,0xfffe1
87c: 4001 c.li x0,0
87e: 9f25 0x9f25
880: 0700 c.addi4spn x8,x2,896
- 882: 090c c.addi4spn x11,x2,144
+ 882: 08e8 c.addi4spn x10,x2,92
884: 0000 c.unimp
- 886: 0920 c.addi4spn x8,x2,152
+ 886: 08fc c.addi4spn x15,x2,92
888: 0000 c.unimp
88a: 5c01 c.li x24,-32
88c: 0700 c.addi4spn x8,x2,896
- 88e: 065c c.addi4spn x15,x2,772
+ 88e: 0638 c.addi4spn x14,x2,776
890: 0000 c.unimp
- 892: 0694 c.addi4spn x13,x2,832
+ 892: 0670 c.addi4spn x12,x2,780
894: 0000 c.unimp
896: 5c01 c.li x24,-32
- 898: 00069407 0x69407
- 89c: 2000 c.fld f8,0(x8)
- 89e: 01000007 0x1000007
+ 898: 00067007 0x67007
+ 89c: fc00 c.fsw f8,56(x8)
+ 89e: 0006 c.slli x0,0x1
+ 8a0: 0100 c.addi4spn x8,x2,128
8a2: 075e c.slli x14,0x17
- 8a4: 0720 c.addi4spn x8,x2,904
+ 8a4: 06fc c.addi4spn x15,x2,844
8a6: 0000 c.unimp
- 8a8: 0734 c.addi4spn x13,x2,904
+ 8a8: 0710 c.addi4spn x12,x2,896
8aa: 0000 c.unimp
8ac: 5c01 c.li x24,-32
- 8ae: 00073407 fld f8,0(x14)
- 8b2: 3800 c.fld f8,48(x8)
+ 8ae: 00071007 0x71007
+ 8b2: 1400 c.addi4spn x8,x2,544
8b4: 09000007 0x9000007
8b8: 007c c.addi4spn x15,x2,12
8ba: ff08007b 0xff08007b
8be: 241a c.fldsp f8,384(x2)
- 8c0: 079f 0738 0000 0x738079f
- 8c6: 07e0 c.addi4spn x8,x2,972
+ 8c0: 079f 0714 0000 0x714079f
+ 8c6: 07bc c.addi4spn x15,x2,968
8c8: 0000 c.unimp
8ca: 5e01 c.li x28,-32
8cc: 0700 c.addi4spn x8,x2,896
- 8ce: 0670 c.addi4spn x12,x2,780
+ 8ce: 064c c.addi4spn x11,x2,772
8d0: 0000 c.unimp
- 8d2: 0684 c.addi4spn x9,x2,832
+ 8d2: 0660 c.addi4spn x8,x2,780
8d4: 0000 c.unimp
8d6: 5d01 c.li x26,-32
8d8: 0700 c.addi4spn x8,x2,896
- 8da: 0698 c.addi4spn x14,x2,832
+ 8da: 0674 c.addi4spn x13,x2,780
8dc: 0000 c.unimp
- 8de: 0720 c.addi4spn x8,x2,904
+ 8de: 06fc c.addi4spn x15,x2,844
8e0: 0000 c.unimp
8e2: 6101 c.addi16sp x2,0
8e4: 0700 c.addi4spn x8,x2,896
- 8e6: 06a4 c.addi4spn x9,x2,840
+ 8e6: 0680 c.addi4spn x8,x2,832
8e8: 0000 c.unimp
- 8ea: 0720 c.addi4spn x8,x2,904
+ 8ea: 06fc c.addi4spn x15,x2,844
8ec: 0000 c.unimp
8ee: 5c01 c.li x24,-32
8f0: 0700 c.addi4spn x8,x2,896
- 8f2: 06a4 c.addi4spn x9,x2,840
+ 8f2: 0680 c.addi4spn x8,x2,832
8f4: 0000 c.unimp
- 8f6: 06c8 c.addi4spn x10,x2,836
+ 8f6: 06a4 c.addi4spn x9,x2,840
8f8: 0000 c.unimp
8fa: 6c01 0x6c01
- 8fc: 0006c807 flq f16,0(x13)
- 900: 1800 c.addi4spn x8,x2,48
- 902: 01000007 0x1000007
+ 8fc: 0006a407 flw f8,0(x13)
+ 900: f400 c.fsw f8,40(x8)
+ 902: 0006 c.slli x0,0x1
+ 904: 0100 c.addi4spn x8,x2,128
906: 005a c.slli x0,0x16
- 908: 0006e007 0x6e007
- 90c: 0800 c.addi4spn x8,x2,16
- 90e: 01000007 0x1000007
+ 908: 0006bc07 fld f24,0(x13)
+ 90c: e400 c.fsw f8,8(x8)
+ 90e: 0006 c.slli x0,0x1
+ 910: 0100 c.addi4spn x8,x2,128
912: 0756 c.slli x14,0x15
- 914: 0708 c.addi4spn x10,x2,896
+ 914: 06e4 c.addi4spn x9,x2,844
916: 0000 c.unimp
- 918: 0720 c.addi4spn x8,x2,904
+ 918: 06fc c.addi4spn x15,x2,844
91a: 0000 c.unimp
91c: 5f01 c.li x30,-32
91e: 0700 c.addi4spn x8,x2,896
- 920: 06a4 c.addi4spn x9,x2,840
+ 920: 0680 c.addi4spn x8,x2,832
922: 0000 c.unimp
- 924: 06ac c.addi4spn x11,x2,840
+ 924: 0688 c.addi4spn x10,x2,832
926: 0000 c.unimp
928: 7f06 c.flwsp f30,96(x2)
92a: 8100 0x8100
92c: 1d00 c.addi4spn x8,x2,688
- 92e: 079f 06ac 0000 0x6ac079f
- 934: 06b8 c.addi4spn x14,x2,840
+ 92e: 079f 0688 0000 0x688079f
+ 934: 0694 c.addi4spn x13,x2,832
936: 0000 c.unimp
938: 5f01 c.li x30,-32
- 93a: 0006bc07 fld f24,0(x13)
- 93e: c400 c.sw x8,8(x8)
+ 93a: 00069807 0x69807
+ 93e: a000 c.fsd f8,0(x8)
940: 0006 c.slli x0,0x1
942: 0100 c.addi4spn x8,x2,128
- 944: 075f 06c8 0000 0x6c8075f
- 94a: 06ec c.addi4spn x11,x2,844
+ 944: 075f 06a4 0000 0x6a4075f
+ 94a: 06c8 c.addi4spn x10,x2,836
94c: 0000 c.unimp
94e: 5f01 c.li x30,-32
950: 0700 c.addi4spn x8,x2,896
- 952: 06dc c.addi4spn x15,x2,836
+ 952: 06b8 c.addi4spn x14,x2,840
954: 0000 c.unimp
- 956: 06ec c.addi4spn x11,x2,844
+ 956: 06c8 c.addi4spn x10,x2,836
958: 0000 c.unimp
95a: 7f06 c.flwsp f30,96(x2)
95c: 8100 0x8100
95e: 1d00 c.addi4spn x8,x2,688
- 960: 079f 06ec 0000 0x6ec079f
- 966: 06f4 c.addi4spn x13,x2,844
+ 960: 079f 06c8 0000 0x6c8079f
+ 966: 06d0 c.addi4spn x12,x2,836
968: 0000 c.unimp
96a: 5f01 c.li x30,-32
- 96c: 0006f807 0x6f807
- 970: 0400 c.addi4spn x8,x2,512
- 972: 01000007 0x1000007
+ 96c: 0006d407 0x6d407
+ 970: e000 c.fsw f8,0(x8)
+ 972: 0006 c.slli x0,0x1
+ 974: 0100 c.addi4spn x8,x2,128
976: 0060 c.addi4spn x8,x2,12
- 978: 0006b407 fld f8,0(x13)
- 97c: e000 c.fsw f8,0(x8)
+ 978: 00069007 0x69007
+ 97c: bc00 c.fsd f8,56(x8)
97e: 0006 c.slli x0,0x1
980: 0100 c.addi4spn x8,x2,128
982: 0756 c.slli x14,0x15
- 984: 06e0 c.addi4spn x8,x2,844
+ 984: 06bc c.addi4spn x15,x2,840
986: 0000 c.unimp
- 988: 06f0 c.addi4spn x12,x2,844
+ 988: 06cc c.addi4spn x11,x2,836
98a: 0000 c.unimp
98c: 7c06 c.flwsp f24,96(x2)
98e: 8c00 0x8c00
990: 1e00 c.addi4spn x8,x2,816
- 992: 079f 06f0 0000 0x6f0079f
- 998: 0720 c.addi4spn x8,x2,904
+ 992: 079f 06cc 0000 0x6cc079f
+ 998: 06fc c.addi4spn x15,x2,844
99a: 0000 c.unimp
99c: 5d01 c.li x26,-32
99e: 0700 c.addi4spn x8,x2,896
- 9a0: 075c c.addi4spn x15,x2,900
+ 9a0: 0738 c.addi4spn x14,x2,904
9a2: 0000 c.unimp
- 9a4: 07e0 c.addi4spn x8,x2,972
+ 9a4: 07bc c.addi4spn x15,x2,968
9a6: 0000 c.unimp
9a8: 5a01 c.li x20,-32
9aa: 0700 c.addi4spn x8,x2,896
- 9ac: 075c c.addi4spn x15,x2,900
+ 9ac: 0738 c.addi4spn x14,x2,904
9ae: 0000 c.unimp
- 9b0: 07a8 c.addi4spn x10,x2,968
+ 9b0: 0784 c.addi4spn x9,x2,960
9b2: 0000 c.unimp
9b4: 5c01 c.li x24,-32
- 9b6: 0007a807 flw f16,0(x15)
- 9ba: e000 c.fsw f8,0(x8)
+ 9b6: 00078407 0x78407
+ 9ba: bc00 c.fsd f8,56(x8)
9bc: 07000007 0x7000007
9c0: 007e c.slli x0,0x1f
9c2: 2440 c.fld f8,136(x8)
9c4: 2540 c.fld f8,136(x10)
- 9c6: 009f 5c07 0007 0x75c07009f
- 9cc: 8000 0x8000
+ 9c6: 009f 3807 0007 0x73807009f
+ 9cc: 5c00 c.lw x8,56(x8)
9ce: 01000007 0x1000007
9d2: 0756 c.slli x14,0x15
- 9d4: 0780 c.addi4spn x8,x2,960
+ 9d4: 075c c.addi4spn x15,x2,900
9d6: 0000 c.unimp
- 9d8: 07d4 c.addi4spn x13,x2,964
+ 9d8: 07b0 c.addi4spn x12,x2,968
9da: 0000 c.unimp
9dc: 5b01 c.li x22,-32
9de: 0700 c.addi4spn x8,x2,896
- 9e0: 0798 c.addi4spn x14,x2,960
+ 9e0: 0774 c.addi4spn x13,x2,908
9e2: 0000 c.unimp
- 9e4: 07c0 c.addi4spn x8,x2,964
+ 9e4: 079c c.addi4spn x15,x2,960
9e6: 0000 c.unimp
9e8: 6101 c.addi16sp x2,0
- 9ea: 0007c007 flq f0,0(x15)
- 9ee: e000 c.fsw f8,0(x8)
+ 9ea: 00079c07 0x79c07
+ 9ee: bc00 c.fsd f8,56(x8)
9f0: 01000007 0x1000007
9f4: 005d c.addi x0,23
- 9f6: 00075c07 0x75c07
- 9fa: 6000 c.flw f8,0(x8)
+ 9f6: 00073807 fld f16,0(x14)
+ 9fa: 3c00 c.fld f8,56(x8)
9fc: 06000007 0x6000007
a00: 007d c.addi x0,31
a02: 007a c.slli x0,0x1e
a04: 9f1d 0x9f1d
- a06: 00076007 0x76007
- a0a: 6c00 c.flw f8,24(x8)
+ a06: 00073c07 fld f24,0(x14)
+ a0a: 4800 c.lw x8,16(x8)
a0c: 01000007 0x1000007
a10: 075d c.addi x14,23
- a12: 0770 c.addi4spn x12,x2,908
+ a12: 074c c.addi4spn x11,x2,900
a14: 0000 c.unimp
- a16: 077c c.addi4spn x15,x2,908
+ a16: 0758 c.addi4spn x14,x2,900
a18: 0000 c.unimp
a1a: 5d01 c.li x26,-32
- a1c: 00078007 0x78007
- a20: a400 c.fsd f8,8(x8)
+ a1c: 00075c07 0x75c07
+ a20: 8000 0x8000
a22: 01000007 0x1000007
a26: 005d c.addi x0,23
- a28: 00079407 0x79407
- a2c: a400 c.fsd f8,8(x8)
+ a28: 00077007 0x77007
+ a2c: 8000 0x8000
a2e: 06000007 0x6000007
a32: 007d c.addi x0,31
a34: 007a c.slli x0,0x1e
a36: 9f1d 0x9f1d
- a38: 0007a407 flw f8,0(x15)
- a3c: ac00 c.fsd f8,24(x8)
+ a38: 00078007 0x78007
+ a3c: 8800 0x8800
a3e: 01000007 0x1000007
a42: 075d c.addi x14,23
- a44: 07b0 c.addi4spn x12,x2,968
+ a44: 078c c.addi4spn x11,x2,960
a46: 0000 c.unimp
- a48: 07bc c.addi4spn x15,x2,968
+ a48: 0798 c.addi4spn x14,x2,960
a4a: 0000 c.unimp
a4c: 5f01 c.li x30,-32
- a4e: 0007c007 flq f0,0(x15)
- a52: e000 c.fsw f8,0(x8)
+ a4e: 00079c07 0x79c07
+ a52: bc00 c.fsd f8,56(x8)
a54: 01000007 0x1000007
- a58: 005f 6407 0007 0x76407005f
- a5e: 9800 0x9800
+ a58: 005f 4007 0007 0x74007005f
+ a5e: 7400 c.flw f8,40(x8)
a60: 01000007 0x1000007
a64: 0761 c.addi x14,24
- a66: 0798 c.addi4spn x14,x2,960
+ a66: 0774 c.addi4spn x13,x2,908
a68: 0000 c.unimp
- a6a: 07a8 c.addi4spn x10,x2,968
+ a6a: 0784 c.addi4spn x9,x2,960
a6c: 0000 c.unimp
a6e: 7c06 c.flwsp f24,96(x2)
a70: 7600 c.flw f8,40(x12)
a72: 1e00 c.addi4spn x8,x2,816
- a74: 079f 07a8 0000 0x7a8079f
- a7a: 07e0 c.addi4spn x8,x2,972
+ a74: 079f 0784 0000 0x784079f
+ a7a: 07bc c.addi4spn x15,x2,968
a7c: 0000 c.unimp
a7e: 5c01 c.li x24,-32
a80: 0700 c.addi4spn x8,x2,896
- a82: 07e4 c.addi4spn x9,x2,972
+ a82: 07c0 c.addi4spn x8,x2,964
a84: 0000 c.unimp
- a86: 084c c.addi4spn x11,x2,20
+ a86: 0828 c.addi4spn x10,x2,24
a88: 0000 c.unimp
a8a: 5d01 c.li x26,-32
a8c: 0700 c.addi4spn x8,x2,896
- a8e: 07f8 c.addi4spn x14,x2,972
+ a8e: 07d4 c.addi4spn x13,x2,964
a90: 0000 c.unimp
- a92: 0814 c.addi4spn x13,x2,16
+ a92: 07f0 c.addi4spn x12,x2,972
a94: 0000 c.unimp
a96: 5e01 c.li x28,-32
...
@@ -4532,129 +4526,128 @@ Disassembly of section .debug_rnglists:
6: 0004 0x4
8: 0000 c.unimp
a: 0000 c.unimp
- c: 4806 c.lwsp x16,64(x2)
+ c: 2406 c.fldsp f8,64(x2)
e: 0005 c.addi x0,1
- 10: 4800 c.lw x8,16(x8)
+ 10: 2400 c.fld f8,8(x8)
12: 0005 c.addi x0,1
14: 0600 c.addi4spn x8,x2,768
- 16: 0550 c.addi4spn x12,x2,644
+ 16: 052c c.addi4spn x11,x2,648
18: 0000 c.unimp
- 1a: 063c c.addi4spn x15,x2,776
+ 1a: 0618 c.addi4spn x14,x2,768
1c: 0000 c.unimp
- 1e: 4006 0x4006
+ 1e: 1c06 c.slli x24,0x21
20: 0006 c.slli x0,0x1
- 22: 7800 c.flw f8,48(x8)
+ 22: 5400 c.lw x8,40(x8)
24: 0009 c.addi x0,2
26: 0000 c.unimp
- 28: 4806 c.lwsp x16,64(x2)
+ 28: 2406 c.fldsp f8,64(x2)
2a: 0005 c.addi x0,1
- 2c: 4800 c.lw x8,16(x8)
+ 2c: 2400 c.fld f8,8(x8)
2e: 0005 c.addi x0,1
30: 0600 c.addi4spn x8,x2,768
- 32: 0550 c.addi4spn x12,x2,644
+ 32: 052c c.addi4spn x11,x2,648
34: 0000 c.unimp
- 36: 063c c.addi4spn x15,x2,776
+ 36: 0618 c.addi4spn x14,x2,768
38: 0000 c.unimp
- 3a: 4006 0x4006
+ 3a: 1c06 c.slli x24,0x21
3c: 0006 c.slli x0,0x1
- 3e: 6800 c.flw f8,16(x8)
+ 3e: 4400 c.lw x8,8(x8)
40: 0009 c.addi x0,2
42: 0600 c.addi4spn x8,x2,768
- 44: 096c c.addi4spn x11,x2,156
+ 44: 0948 c.addi4spn x10,x2,148
46: 0000 c.unimp
- 48: 0978 c.addi4spn x14,x2,156
+ 48: 0954 c.addi4spn x13,x2,148
4a: 0000 c.unimp
4c: 0600 c.addi4spn x8,x2,768
- 4e: 056c c.addi4spn x11,x2,652
+ 4e: 0548 c.addi4spn x10,x2,644
50: 0000 c.unimp
- 52: 0598 c.addi4spn x14,x2,704
+ 52: 0574 c.addi4spn x13,x2,652
54: 0000 c.unimp
- 56: 4006 0x4006
+ 56: 1c06 c.slli x24,0x21
58: 0006 c.slli x0,0x1
- 5a: 5400 c.lw x8,40(x8)
+ 5a: 3000 c.fld f8,32(x8)
5c: 0006 c.slli x0,0x1
5e: 0000 c.unimp
- 60: 3806 c.fldsp f16,96(x2)
+ 60: 1406 c.slli x8,0x21
62: 0006 c.slli x0,0x1
- 64: 3c00 c.fld f8,56(x8)
+ 64: 1800 c.addi4spn x8,x2,48
66: 0006 c.slli x0,0x1
68: 0600 c.addi4spn x8,x2,768
- 6a: 0844 c.addi4spn x9,x2,20
+ 6a: 0820 c.addi4spn x8,x2,24
6c: 0000 c.unimp
- 6e: 0968 c.addi4spn x10,x2,156
+ 6e: 0944 c.addi4spn x9,x2,148
70: 0000 c.unimp
72: 0600 c.addi4spn x8,x2,768
- 74: 0860 c.addi4spn x8,x2,28
+ 74: 083c c.addi4spn x15,x2,24
76: 0000 c.unimp
- 78: 0870 c.addi4spn x12,x2,28
+ 78: 084c c.addi4spn x11,x2,20
7a: 0000 c.unimp
- 7c: 7406 c.flwsp f8,96(x2)
+ 7c: 5006 0x5006
7e: 0008 0x8
- 80: ec00 c.fsw f8,24(x8)
+ 80: c800 c.sw x8,16(x8)
82: 0008 0x8
84: 0600 c.addi4spn x8,x2,768
- 86: 08f0 c.addi4spn x12,x2,92
+ 86: 08cc c.addi4spn x11,x2,84
88: 0000 c.unimp
- 8a: 08f4 c.addi4spn x13,x2,92
+ 8a: 08d0 c.addi4spn x12,x2,84
8c: 0000 c.unimp
- 8e: fc06 c.fswsp f1,56(x2)
+ 8e: d806 c.swsp x1,48(x2)
90: 0008 0x8
- 92: 0000 c.unimp
- 94: 0009 c.addi x0,2
+ 92: dc00 c.sw x8,56(x8)
+ 94: 0008 0x8
96: 0000 c.unimp
- 98: ec06 c.fswsp f1,24(x2)
+ 98: c806 c.swsp x1,16(x2)
9a: 0008 0x8
- 9c: f000 c.fsw f8,32(x8)
+ 9c: cc00 c.sw x8,24(x8)
9e: 0008 0x8
a0: 0600 c.addi4spn x8,x2,768
- a2: 08f4 c.addi4spn x13,x2,92
+ a2: 08d0 c.addi4spn x12,x2,84
a4: 0000 c.unimp
- a6: 08fc c.addi4spn x15,x2,92
+ a6: 08d8 c.addi4spn x14,x2,84
a8: 0000 c.unimp
- aa: 0006 c.slli x0,0x1
- ac: 0009 c.addi x0,2
- ae: 3800 c.fld f8,48(x8)
+ aa: dc06 c.swsp x1,56(x2)
+ ac: 0008 0x8
+ ae: 1400 c.addi4spn x8,x2,544
b0: 0009 c.addi x0,2
b2: 0600 c.addi4spn x8,x2,768
- b4: 0940 c.addi4spn x8,x2,148
+ b4: 091c c.addi4spn x15,x2,144
b6: 0000 c.unimp
- b8: 0954 c.addi4spn x13,x2,148
+ b8: 0930 c.addi4spn x12,x2,152
ba: 0000 c.unimp
- bc: 5806 c.lwsp x16,96(x2)
+ bc: 3406 c.fldsp f8,96(x2)
be: 0009 c.addi x0,2
- c0: 5c00 c.lw x8,56(x8)
+ c0: 3800 c.fld f8,48(x8)
c2: 0009 c.addi x0,2
c4: 0000 c.unimp
- c6: 5c06 c.lwsp x24,96(x2)
+ c6: 3806 c.fldsp f16,96(x2)
c8: 0006 c.slli x0,0x1
- ca: 8800 0x8800
+ ca: 6400 c.flw f8,8(x8)
cc: 0006 c.slli x0,0x1
ce: 0600 c.addi4spn x8,x2,768
- d0: 0720 c.addi4spn x8,x2,904
+ d0: 06fc c.addi4spn x15,x2,844
d2: 0000 c.unimp
- d4: 0734 c.addi4spn x13,x2,904
+ d4: 0710 c.addi4spn x12,x2,896
d6: 0000 c.unimp
d8: 0600 c.addi4spn x8,x2,768
- da: 073c c.addi4spn x15,x2,904
+ da: 0718 c.addi4spn x14,x2,896
dc: 0000 c.unimp
- de: 0740 c.addi4spn x8,x2,900
+ de: 071c c.addi4spn x15,x2,896
e0: 0000 c.unimp
- e2: 4806 c.lwsp x16,64(x2)
- e4: 50000007 0x50000007
+ e2: 2406 c.fldsp f8,64(x2)
+ e4: 2c000007 0x2c000007
e8: 06000007 0x6000007
- ec: 0754 c.addi4spn x13,x2,900
+ ec: 0730 c.addi4spn x12,x2,904
ee: 0000 c.unimp
- f0: 0758 c.addi4spn x14,x2,900
+ f0: 0734 c.addi4spn x13,x2,904
f2: 0000 c.unimp
- f4: 5c06 c.lwsp x24,96(x2)
- f6: e0000007 0xe0000007
+ f4: 3806 c.fldsp f16,96(x2)
+ f6: bc000007 0xbc000007
fa: 00000007 0x7
- fe: e406 c.fswsp f1,8(x2)
- 100: 18000007 0x18000007
- 104: 0008 0x8
- 106: 0600 c.addi4spn x8,x2,768
- 108: 0830 c.addi4spn x12,x2,24
+ fe: c006 c.swsp x1,0(x2)
+ 100: f4000007 0xf4000007
+ 104: 06000007 0x6000007
+ 108: 080c c.addi4spn x11,x2,16
10a: 0000 c.unimp
- 10c: 0844 c.addi4spn x9,x2,20
+ 10c: 0820 c.addi4spn x8,x2,24
10e: 0000 c.unimp
...