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提交 a94aaacd 编写于 作者: 饶先宏's avatar 饶先宏
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202109090950

上级 63097abc
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Showing with 899 addition and 5400 deletion
examples/hdl4se_riscv/de1/de1_riscv_v4.qsf
浏览文件 @ a94aaacd
......@@ -5,7 +5,7 @@
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEMA5F31C6
set_global_assignment -name TOP_LEVEL_ENTITY "de1_riscv_v4"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "15.1.0"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:23:33 SEPTEMBER 02,2021"
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
......@@ -488,9 +488,6 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE ../verilog/alex_uart/rtl/uart_tx.v
set_global_assignment -name VERILOG_FILE ../verilog/alex_uart/rtl/uart_rx.v
set_global_assignment -name VERILOG_FILE ../verilog/alex_uart/rtl/uart.v
set_global_assignment -name VERILOG_FILE ../verilog/altera/ram/ram4kB.v
set_global_assignment -name VERILOG_FILE ../verilog/alu/div32.v
set_global_assignment -name VERILOG_FILE ../verilog/alu/mul32.v
......
examples/hdl4se_riscv/de1/test.hex 已删除 100644 → 0
浏览文件 @ 63097abc
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examples/hdl4se_riscv/de1/test.ver 已删除 100644 → 0
浏览文件 @ 63097abc
此差异已折叠。
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_core_v4.c
浏览文件 @ a94aaacd
......@@ -101,8 +101,6 @@ IDLIST
END_IDLIST
enum riscv_core_state {
RISCVSTATE_INIT_REGX1,
RISCVSTATE_INIT_REGX2,
RISCVSTATE_READ_INST,
RISCVSTATE_READ_REGS,
RISCVSTATE_EXEC_INST,
......@@ -138,16 +136,15 @@ DEFINE_FUNC(riscv_core_read_sig, "state, pc, instr, bReadData, regrddata, regrdd
unsigned int state;
state = vget(state);
vput(wRead, 0);
if (state == RISCVSTATE_INIT_REGX2) {
vput(wRead, 1);
vput(bReadAddr, vget(pc));
}
else
if (state == RISCVSTATE_READ_INST) {
vput(bReadAddr, 0);
switch (state) {
case RISCVSTATE_WAIT_ST2:
case RISCVSTATE_WAIT_LD2:
case RISCVSTATE_READ_INST: {
vput(wRead, 1);
vput(bReadAddr, vget(pc));
}
else if (state == RISCVSTATE_EXEC_INST) {
} break;
case RISCVSTATE_EXEC_INST: {
unsigned int instr;
unsigned int opcode;
instr = vget(instr);
......@@ -208,8 +205,8 @@ DEFINE_FUNC(riscv_core_read_sig, "state, pc, instr, bReadData, regrddata, regrdd
vput(wRead, 1);
vput(bReadAddr, newpc);
}
}
else if (state == RISCVSTATE_WAIT_LD) {
} break;
case RISCVSTATE_WAIT_LD: {
unsigned int instr = vget(instr);
unsigned int func3 = (instr >> 12) & 0x7;
unsigned int ldaddr = vget(ldaddr);
......@@ -227,29 +224,17 @@ DEFINE_FUNC(riscv_core_read_sig, "state, pc, instr, bReadData, regrddata, regrdd
vput(bReadAddr, ldaddr + 4);
}
else {
vput(wRead, 0);
vput(bReadAddr, 0);
vput(wRead, 1);
vput(bReadAddr, vget(pc));
}
}
/*else if (state == RISCVSTATE_WRITE_RD) {
vput(wRead, 1);
vput(bReadAddr, vget(pc));
}
*/
/*
else if (state == RISCVSTATE_WAIT_ST2) {
vput(wRead, 1);
vput(bReadAddr, vget(pc));
}
else if (state == RISCVSTATE_WAIT_ST) {
}break;
case RISCVSTATE_WAIT_ST: {
unsigned int instr = vget(instr);
unsigned int lastaddr = vget(lastaddr);
unsigned int opcode = instr & 0x7f;
unsigned int func3;
func3 = (instr >> 12) & 0x7;
opcode >>= 2;
vput(wRead, 1);
vput(bReadAddr, vget(pc));
if (opcode == 0x08) {
if (func3 == 1 && (lastaddr & 3) == 3) { // sh
vput(wRead, 0);
......@@ -257,9 +242,13 @@ DEFINE_FUNC(riscv_core_read_sig, "state, pc, instr, bReadData, regrddata, regrdd
else if (func3 == 2 && (lastaddr & 3) != 0) {
vput(wRead, 0);
}
else {
vput(wRead, 1);
vput(bReadAddr, vget(pc));
}
}
}break;
}
*/
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_core_gen_ldaddr, "state, pc, instr, regrddata") {
......@@ -319,26 +308,6 @@ DEFINE_FUNC(riscv_core_reg_wr_sig, "state, dstreg, dstvalue, bReadData, instr, r
vput(regena2, 0xf);
vput(regwrdata2, vget(dstvalue));
}break;
case RISCVSTATE_INIT_REGX1: {
vput(regwren, 1);
vput(regno, 1);
vput(regena, 0xf);
vput(regwrdata, 0x8c);
vput(regwren2, 1);
vput(regno2, 1);
vput(regena2, 0xf);
vput(regwrdata2, 0x8c);
}break;
case RISCVSTATE_INIT_REGX2: {
vput(regwren, 1);
vput(regno, 2);
vput(regena, 0xf);
vput(regwrdata, RAMSIZE * 4 - 16);
vput(regwren2, 1);
vput(regno2, 2);
vput(regena2, 0xf);
vput(regwrdata2, RAMSIZE * 4 - 16);
}break;
default: {
vput(regwren, 0);
vput(regno, 0);
......@@ -556,12 +525,6 @@ DEFINE_FUNC(riscv_core_exec_inst, "") {
DEFINE_FUNC(riscv_core_gen_dstreg, "state, instr, ldaddr, readreg, bReadData, pc, rs1, rs2, divclk, regrddata, imm") {
switch (vget(state)) {
case RISCVSTATE_INIT_REGX1: {
RISCV_SETDSTREG(1, 0x8c);
}break;
case RISCVSTATE_INIT_REGX2: {
RISCV_SETDSTREG(2, RAMSIZE * 4 - 16);
}break;
case RISCVSTATE_WAIT_LD: {
unsigned int instr = vget(instr);
unsigned int func3 = (instr >> 12) & 0x7;
......@@ -781,26 +744,17 @@ DEFINE_FUNC(riscv_core_gen_imm, "instr, state") {
DEFINE_FUNC(riscv_core_gen_state, "state, instr, nwReset, imm, ldaddr, lastaddr, lastv") {
if (vget(nwReset) == 0) {
vput(state, RISCVSTATE_INIT_REGX1);
vput(state, RISCVSTATE_READ_INST);
}
else {
int state = vget(state);
switch (state) {
case RISCVSTATE_INIT_REGX1: {
vput(state, RISCVSTATE_INIT_REGX2);
}break;
case RISCVSTATE_INIT_REGX2: {
vput(state, RISCVSTATE_READ_REGS);
}break;
case RISCVSTATE_READ_INST: {
vput(state, RISCVSTATE_READ_REGS);
}break;
case RISCVSTATE_READ_REGS: {
vput(state, RISCVSTATE_EXEC_INST);
}break;
/*case RISCVSTATE_WRITE_RD: {
vput(state, RISCVSTATE_READ_REGS);
}break;*/
case RISCVSTATE_EXEC_INST: {
unsigned int instr = vget(instr);
unsigned int opcode = instr & 0x7f;
......@@ -832,11 +786,11 @@ DEFINE_FUNC(riscv_core_gen_state, "state, instr, nwReset, imm, ldaddr, lastaddr,
vput(state, RISCVSTATE_WAIT_LD2);
}
else {
vput(state, RISCVSTATE_READ_INST);
vput(state, RISCVSTATE_READ_REGS);
}
}break;
case RISCVSTATE_WAIT_LD2: {
vput(state, RISCVSTATE_READ_INST);
vput(state, RISCVSTATE_READ_REGS);
}break;
case RISCVSTATE_WAIT_ST: {
unsigned int instr = vget(instr);
......@@ -845,7 +799,7 @@ DEFINE_FUNC(riscv_core_gen_state, "state, instr, nwReset, imm, ldaddr, lastaddr,
unsigned int func3;
func3 = (instr >> 12) & 0x7;
opcode >>= 2;
vput(state, RISCVSTATE_READ_INST);
vput(state, RISCVSTATE_READ_REGS);
if (opcode == 0x08) {
if (func3 == 1 && (lastaddr & 3) == 3) { /* sh */
vput(state, RISCVSTATE_WAIT_ST2);
......@@ -856,11 +810,11 @@ DEFINE_FUNC(riscv_core_gen_state, "state, instr, nwReset, imm, ldaddr, lastaddr,
}
}break;
case RISCVSTATE_WAIT_ST2: {
vput(state, RISCVSTATE_READ_INST);
vput(state, RISCVSTATE_READ_REGS);
}break;
case RISCVSTATE_WAIT_DIV: {
if (vget(divclk) == 0)
vput(state, RISCVSTATE_READ_INST);
vput(state, RISCVSTATE_READ_REGS);
}break;
}
}
......@@ -956,7 +910,7 @@ DEFINE_FUNC(riscv_core_gen_write, "nwReset, state, pc, instr, regrddata, regrdda
}
break;
}
vput(writeaddr, lastaddr + 4);
vput(writeaddr, (lastaddr & 0xfffffffc) + 4);
vput(writedata, writedata);
vput(writemask, writemask);
}
......@@ -1230,10 +1184,10 @@ MODULE_INIT(riscv_core)
PORT_IN(regrddata2, 32);
GREG(pc, 32, riscv_core_reg_gen_pc);
GREG(instr, 32, riscv_core_reg_gen_instr);
GREG(write, 1, riscv_core_gen_write);
GREG(writeaddr, 32, riscv_core_gen_write);
GREG(writedata, 32, riscv_core_gen_write);
GREG(writemask, 4, riscv_core_gen_write);
GWIRE(write, 1, riscv_core_gen_write);
GWIRE(writeaddr, 32, riscv_core_gen_write);
GWIRE(writedata, 32, riscv_core_gen_write);
GWIRE(writemask, 4, riscv_core_gen_write);
GREG(readreg, 5, riscv_core_reg_gen_readreg);
GREG(state, 4, riscv_core_gen_state);
GREG(imm, 32, riscv_core_gen_imm);
......
examples/hdl4se_riscv/hdl4se_riscv_sim/riscv_sim_main_v4.c
浏览文件 @ a94aaacd
......@@ -92,7 +92,7 @@ DEFINE_FUNC(top_gen_ram_dot_wren, "bWriteAddr, wWrite, ") { /* port:ram(ram8kb).
} END_DEFINE_FUNC
DEFINE_FUNC(top_gen_bReadData, "bReadAddr_out, bReadDataKey, bReadDataRam, ") {
vputs(bReadData, (((vgets(bReadAddr_out)) & (0xffffff00)) == (0xf0000000))?(vgets(bReadDataKey)):((((vgets(bReadAddr_out)) & (0xff000000)) == (0))?(vgets(bReadDataRam)):(0xffffffff)));
vputs(bReadData, (((vgets(bReadAddr_out)) & (0xffffff00)) == (0xf0000000))?(vgets(bReadDataKey)):((((vgets(bReadAddr_out)) & (0xff000000)) == (0))?(vgets(bReadDataRam)):(0)));
} END_DEFINE_FUNC
DEFINE_FUNC(top_gen_ramaddr, "wWrite, bWriteAddr, bReadAddr, ") {
......
examples/hdl4se_riscv/test_code/console.c
浏览文件 @ a94aaacd
......@@ -500,10 +500,12 @@ static void testmad()
static void printhelp()
{
/*
_puts(" d <addr> \n");
_puts(" b <baudrate> \n");
_puts(" r <addr> <width>\n");
_puts(" w <addr> <value> <width>\n");
*/
}
#define TESTISA 0
......@@ -569,16 +571,6 @@ void testisa()
int main(int argc, char* argv[])
{
#if 0
volatile unsigned int* ledkey = (unsigned int*)0xF0000000;
volatile unsigned int* leddata = (unsigned int*)0xf0000010;
unsigned char ledd[20];
unsigned int count0 = 0;
unsigned int count1 = 0;
unsigned int ctemp;
#endif
*(unsigned int*)0xf0000010 = 0x3f3f0707;
_buadrateset(115200);
do {
......
examples/hdl4se_riscv/test_code/test.cod
浏览文件 @ a94aaacd
@00000000
37 11 00 00 EF 00 50 29 6F F0 9F FF
37 11 00 00 EF 00 D0 25 6F F0 9F FF
@0000000C
13 01 01 FF 23 26 81 00 13 04 01 01 B7 17 00 00
83 A7 47 EE 93 87 87 00 03 A7 07 00 B7 17 00 00
23 A6 E7 EE B7 17 00 00 83 A7 C7 EE 93 F7 17 00
83 A7 07 E6 93 87 87 00 03 A7 07 00 B7 17 00 00
23 A4 E7 E6 B7 17 00 00 83 A7 87 E6 93 F7 17 00
93 B7 17 00 93 F7 F7 0F 13 85 07 00 03 24 C1 00
13 01 01 01 67 80 00 00
@00000054
13 01 01 FF 23 26 81 00 13 04 01 01 B7 17 00 00
83 A7 47 EE 93 87 87 00 03 A7 07 00 B7 17 00 00
23 A6 E7 EE B7 17 00 00 03 A7 C7 EE B7 07 01 00
83 A7 07 E6 93 87 87 00 03 A7 07 00 B7 17 00 00
23 A4 E7 E6 B7 17 00 00 03 A7 87 E6 B7 07 01 00
B3 77 F7 00 93 B7 17 00 93 F7 F7 0F 13 85 07 00
03 24 C1 00 13 01 01 01 67 80 00 00
@000000A0
13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE
B7 17 00 00 83 A7 47 EE 93 87 87 00 03 A7 07 00
B7 17 00 00 23 A6 E7 EE B7 17 00 00 83 A7 C7 EE
93 F7 17 00 63 90 07 02 B7 17 00 00 83 A7 47 EE
B7 17 00 00 83 A7 07 E6 93 87 87 00 03 A7 07 00
B7 17 00 00 23 A4 E7 E6 B7 17 00 00 83 A7 87 E6
93 F7 17 00 63 90 07 02 B7 17 00 00 83 A7 07 E6
93 87 47 00 03 27 C4 FE 23 A0 E7 00 93 07 00 00
6F 00 80 00 93 07 F0 FF 13 85 07 00 03 24 C1 01
13 01 01 02 67 80 00 00
@00000108
13 01 01 FF 23 26 81 00 13 04 01 01 B7 17 00 00
83 A7 47 EE 93 87 87 00 03 A7 07 00 B7 17 00 00
23 A6 E7 EE B7 17 00 00 03 A7 C7 EE B7 07 01 00
B3 77 F7 00 63 9A 07 00 B7 17 00 00 83 A7 47 EE
83 A7 07 E6 93 87 87 00 03 A7 07 00 B7 17 00 00
23 A4 E7 E6 B7 17 00 00 03 A7 87 E6 B7 07 01 00
B3 77 F7 00 63 9A 07 00 B7 17 00 00 83 A7 07 E6
83 A7 07 00 6F 00 80 00 93 07 F0 FF 13 85 07 00
03 24 C1 00 13 01 01 01 67 80 00 00
@00000164
......@@ -145,24 +145,24 @@ B3 07 F7 00 93 87 97 FC 23 24 F4 FE 6F 00 40 01
@00000804
13 01 01 FB 23 26 11 04 23 24 81 04 23 22 21 05
23 20 31 05 23 2E 41 03 23 2C 51 03 13 04 01 05
B7 17 00 00 83 A7 87 EE 93 F7 07 FF 23 2A F4 FC
B7 17 00 00 83 A7 47 E6 93 F7 07 FF 23 2A F4 FC
23 2C 04 FC 6F 00 C0 1B 83 27 44 FD 13 89 07 00
93 09 00 00 93 07 C4 FB 13 07 00 03 93 06 80 00
93 05 09 00 13 86 09 00 13 85 07 00 EF F0 9F BC
93 07 C4 FB 13 85 07 00 EF F0 9F 8F B7 17 00 00
13 85 87 E4 EF F0 DF 8E 23 2E 04 FC 6F 00 40 0A
13 85 87 E1 EF F0 DF 8E 23 2E 04 FC 6F 00 40 0A
83 27 44 FD 23 26 F4 FC 03 27 C4 FD 83 27 44 FD
33 07 F7 00 B7 17 00 00 83 A7 87 EE 63 7A F7 00
B7 17 00 00 13 85 C7 E4 EF F0 9F 8B 6F 00 00 05
33 07 F7 00 B7 17 00 00 83 A7 47 E6 63 7A F7 00
B7 17 00 00 13 85 C7 E1 EF F0 9F 8B 6F 00 00 05
83 27 C4 FD 03 27 C4 FC B3 07 F7 00 83 C7 07 00
13 8A 07 00 93 0A 00 00 93 07 C4 FB 13 07 00 03
93 06 20 00 93 05 0A 00 13 86 0A 00 13 85 07 00
EF F0 5F B4 93 07 C4 FB 13 85 07 00 EF F0 5F 87
B7 17 00 00 13 85 07 E5 EF F0 9F 86 03 27 C4 FD
93 07 70 00 63 18 F7 00 B7 17 00 00 13 85 47 E5
B7 17 00 00 13 85 07 E2 EF F0 9F 86 03 27 C4 FD
93 07 70 00 63 18 F7 00 B7 17 00 00 13 85 47 E2
EF F0 1F 85 83 27 C4 FD 93 87 17 00 23 2E F4 FC
03 27 C4 FD 93 07 F0 00 E3 DC E7 F4 B7 17 00 00
13 85 87 E5 EF F0 DF 82 23 2E 04 FC 6F 00 80 07
13 85 87 E2 EF F0 DF 82 23 2E 04 FC 6F 00 80 07
83 27 44 FD 23 28 F4 FC 83 27 C4 FD 03 27 04 FD
B3 07 F7 00 03 C7 07 00 93 07 F0 01 63 FA E7 02
83 27 C4 FD 03 27 04 FD B3 07 F7 00 03 C7 07 00
......@@ -171,93 +171,85 @@ B3 07 F7 00 83 C7 07 00 23 0E F4 FA 6F 00 C0 00
93 07 E0 02 23 0E F4 FA A3 0E 04 FA 93 07 C4 FB
13 85 07 00 EF F0 CF FB 83 27 C4 FD 93 87 17 00
23 2E F4 FC 03 27 C4 FD 93 07 F0 00 E3 D2 E7 F8
B7 17 00 00 13 85 C7 E5 EF F0 8F F9 83 27 44 FD
B7 17 00 00 13 85 C7 E2 EF F0 8F F9 83 27 44 FD
93 87 07 01 23 2A F4 FC 83 27 44 FD 93 F7 F7 0F
63 80 07 02 83 27 84 FD 93 87 17 00 23 2C F4 FC
03 27 84 FD 93 07 F0 00 E3 D0 E7 E4 6F 00 80 00
13 00 00 00 B7 17 00 00 13 85 07 E6 EF F0 4F F5
B7 17 00 00 03 27 44 FD 23 A4 E7 EE 13 00 00 00
13 00 00 00 B7 17 00 00 13 85 07 E3 EF F0 4F F5
B7 17 00 00 03 27 44 FD 23 A2 E7 E6 13 00 00 00
83 20 C1 04 03 24 81 04 03 29 41 04 83 29 01 04
03 2A C1 03 83 2A 81 03 13 01 01 05 67 80 00 00
@00000A44
13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01
B7 17 00 00 13 85 47 E6 EF F0 8F F0 B7 17 00 00
13 85 47 E7 EF F0 CF EF B7 17 00 00 13 85 87 E8
EF F0 0F EF B7 17 00 00 13 85 C7 E9 EF F0 4F EE
13 00 00 00 83 20 C1 00 03 24 81 00 13 01 01 01
67 80 00 00
@00000A98
13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00
03 24 C1 00 13 01 01 01 67 80 00 00
@00000A60
13 01 01 F8 23 2E 11 06 23 2C 81 06 23 2A 21 07
23 28 31 07 23 26 41 07 23 24 51 07 13 04 01 08
23 26 A4 F8 23 24 B4 F8 B7 07 00 F0 93 87 07 01
37 07 3F 3F 13 07 77 70 23 A0 E7 00 B7 17 00 00
83 A7 47 EE 93 87 07 01 13 07 20 1B 23 A0 E7 00
EF F0 4F D2 93 07 05 00 63 88 07 00 B7 17 00 00
13 85 87 EB EF F0 8F E6 EF F0 4F D5 93 07 05 00
83 A7 07 E6 93 87 07 01 13 07 20 1B 23 A0 E7 00
EF F0 CF D5 93 07 05 00 63 88 07 00 B7 17 00 00
13 85 47 E3 EF F0 0F EA EF F0 CF D8 93 07 05 00
E3 8C 07 FE 93 07 04 F9 93 05 70 02 13 85 07 00
EF F0 4F EB 13 00 00 00 B7 17 00 00 13 85 C7 EB
EF F0 CF E3 93 07 04 F9 13 85 07 00 EF F0 0F E3
B7 17 00 00 13 85 07 E6 EF F0 4F E2 03 47 04 F9
EF F0 CF EE 13 00 00 00 B7 17 00 00 13 85 87 E3
EF F0 4F E7 93 07 04 F9 13 85 07 00 EF F0 8F E6
B7 17 00 00 13 85 07 E3 EF F0 CF E5 03 47 04 F9
93 07 20 06 63 18 F7 04 93 07 04 F9 93 87 27 00
93 05 00 00 13 85 07 00 EF F0 1F A7 23 20 A4 FC
93 05 00 00 13 85 07 00 EF F0 9F AA 23 20 A4 FC
83 27 04 FC 63 54 F0 02 B7 F7 FA 02 13 87 07 08
83 27 04 FC 33 47 F7 02 B7 17 00 00 83 A7 47 EE
93 87 07 01 23 A0 E7 00 6F 00 40 2A EF F0 1F EB
6F 00 C0 29 03 47 04 F9 93 07 40 06 63 1C F7 02
83 27 04 FC 33 47 F7 02 B7 17 00 00 83 A7 07 E6
93 87 07 01 23 A0 E7 00 6F 00 C0 2A EF F0 9F EE
6F 00 40 2A 03 47 04 F9 93 07 40 06 63 1C F7 02
93 07 04 F9 93 87 27 00 93 05 00 00 13 85 07 00
EF F0 5F B1 23 22 A4 FC 83 27 44 FC 63 58 F0 00
03 27 44 FC B7 17 00 00 23 A4 E7 EE EF F0 1F C3
6F 00 C0 25 03 47 04 F9 93 07 70 07 63 1C F7 0A
EF F0 DF B4 23 22 A4 FC 83 27 44 FC 63 58 F0 00
03 27 44 FC B7 17 00 00 23 A2 E7 E6 EF F0 9F C6
6F 00 40 26 03 47 04 F9 93 07 70 07 63 1C F7 0A
93 07 04 F9 93 87 27 00 13 07 C4 FB 93 05 07 00
13 85 07 00 EF F0 1F AD 23 28 A4 FC 83 27 C4 FB
13 07 C4 FB 93 05 07 00 13 85 07 00 EF F0 9F AB
13 85 07 00 EF F0 9F B0 23 28 A4 FC 83 27 C4 FB
13 07 C4 FB 93 05 07 00 13 85 07 00 EF F0 1F AF
23 26 A4 FC 83 27 C4 FB 13 07 C4 FB 93 05 07 00
13 85 07 00 EF F0 1F AA 23 24 A4 FC 03 27 84 FC
13 85 07 00 EF F0 9F AD 23 24 A4 FC 03 27 84 FC
93 07 10 00 63 1C F7 00 83 27 04 FD 03 27 C4 FC
13 77 F7 0F 23 80 E7 00 6F 00 40 1E 03 27 84 FC
13 77 F7 0F 23 80 E7 00 6F 00 C0 1E 03 27 84 FC
93 07 20 00 63 1E F7 00 83 27 04 FD 03 27 C4 FC
13 17 07 01 13 57 07 41 23 90 E7 00 6F 00 00 1C
13 17 07 01 13 57 07 41 23 90 E7 00 6F 00 80 1C
03 27 84 FC 93 07 40 00 63 1A F7 00 83 27 04 FD
03 27 C4 FC 23 A0 E7 00 6F 00 40 1A EF F0 1F DB
6F 00 C0 19 03 47 04 F9 93 07 20 07 63 18 F7 18
03 27 C4 FC 23 A0 E7 00 6F 00 C0 1A EF F0 9F DE
6F 00 40 1A 03 47 04 F9 93 07 20 07 63 1A F7 18
23 2E 04 FC 93 07 04 F9 93 87 27 00 13 07 84 FB
93 05 07 00 13 85 07 00 EF F0 DF A0 23 2C A4 FC
93 05 07 00 13 85 07 00 EF F0 5F A4 23 2C A4 FC
83 27 84 FB 13 07 84 FB 93 05 07 00 13 85 07 00
EF F0 5F 9F 23 2A A4 FC 03 27 44 FD 93 07 10 00
EF F0 DF A2 23 2A A4 FC 03 27 44 FD 93 07 10 00
63 10 F7 02 83 27 84 FD 83 C7 07 00 23 2E F4 FC
B7 17 00 00 13 85 07 EC EF F0 4F C6 6F 00 80 05
B7 17 00 00 13 85 C7 E3 EF F0 CF C9 6F 00 80 05
03 27 44 FD 93 07 20 00 63 10 F7 02 83 27 84 FD
83 97 07 00 23 2E F4 FC B7 17 00 00 13 85 87 EC
EF F0 CF C3 6F 00 00 03 03 27 44 FD 93 07 40 00
83 97 07 00 23 2E F4 FC B7 17 00 00 13 85 47 E4
EF F0 4F C7 6F 00 00 03 03 27 44 FD 93 07 40 00
63 10 F7 02 83 27 84 FD 83 A7 07 00 23 2E F4 FC
B7 17 00 00 13 85 07 ED EF F0 4F C1 6F 00 80 00
EF F0 DF CE 03 27 44 FD 93 07 10 00 63 0E F7 00
B7 17 00 00 13 85 C7 E4 EF F0 CF C4 6F 00 80 00
EF F0 5F D2 03 27 44 FD 93 07 10 00 63 0E F7 00
03 27 44 FD 93 07 20 00 63 08 F7 00 03 27 44 FD
93 07 40 00 63 1C F7 0A 83 27 84 FD 13 89 07 00
93 07 40 00 63 10 F7 0C 83 27 84 FD 13 89 07 00
93 D7 F7 41 93 89 07 00 93 07 04 F9 13 07 00 03
93 06 80 00 93 05 09 00 13 86 09 00 13 85 07 00
EF F0 0F E8 93 07 04 F9 13 85 07 00 EF F0 0F BB
B7 17 00 00 13 85 87 ED EF F0 4F BA 93 07 04 F9
83 25 C4 FD 13 85 07 00 EF F0 4F CD 93 07 04 F9
13 85 07 00 EF F0 8F B8 B7 17 00 00 13 85 C7 ED
EF F0 CF B7 83 27 C4 FD 13 8A 07 00 93 D7 F7 41
EF F0 8F EB 93 07 04 F9 13 85 07 00 EF F0 8F BE
B7 17 00 00 13 85 47 E5 EF F0 CF BD 93 07 04 F9
83 25 C4 FD 13 85 07 00 EF F0 CF D0 93 07 04 F9
13 85 07 00 EF F0 0F BC B7 17 00 00 13 85 87 E5
EF F0 4F BB 83 27 C4 FD 13 8A 07 00 93 D7 F7 41
93 8A 07 00 83 27 44 FD 93 96 17 00 93 07 04 F9
13 07 00 03 93 05 0A 00 13 86 0A 00 13 85 07 00
EF F0 0F E1 93 07 04 F9 13 85 07 00 EF F0 0F B4
B7 17 00 00 13 85 07 EE EF F0 4F B3 13 00 00 00
EF F0 4F 9D 93 07 05 00 E3 8C 07 FE 6F F0 5F CA
@00000E48
EF F0 8F E4 93 07 04 F9 13 85 07 00 EF F0 8F B7
B7 17 00 00 13 85 C7 E5 EF F0 CF B6 6F 00 80 00
EF F0 5F C4 13 00 00 00 EF F0 4F A0 93 07 05 00
E3 8C 07 FE 6F F0 DF C9
@00000E18
20 20 00 00 20 20 20 00 20 00 00 00 2D 20 00 00
20 20 7C 00 7C 0A 00 00 0A 0D 00 00 20 20 64 20
3C 61 64 64 72 3E 20 0A 00 00 00 00 20 20 62 20
3C 62 61 75 64 72 61 74 65 3E 20 0A 00 00 00 00
20 20 72 20 3C 61 64 64 72 3E 20 3C 77 69 64 74
68 3E 0A 00 20 20 77 20 3C 61 64 64 72 3E 20 3C
76 61 6C 75 65 3E 20 3C 77 69 64 74 68 3E 0A 00
3E 3E 00 00 0A 0D 3A 00 63 68 61 72 20 40 00 00
73 68 6F 72 74 20 40 00 69 6E 74 20 40 00 00 00
20 3D 20 00 28 00 00 00 29 0A 0D 00
@00000EE4
20 20 7C 00 7C 0A 00 00 0A 0D 00 00 3E 3E 00 00
0A 0D 3A 00 63 68 61 72 20 40 00 00 73 68 6F 72
74 20 40 00 69 6E 74 20 40 00 00 00 20 3D 20 00
28 00 00 00 29 0A 0D 00
@00000E60
00 01 00 F0
@00000EE8
@00000E64
01 00 00 00
examples/hdl4se_riscv/test_code/test.info
浏览文件 @ a94aaacd
......@@ -10,7 +10,7 @@ ELF Header:
Version: 0x1
Entry point address: 0x0
Start of program headers: 52 (bytes into file)
Start of section headers: 9044 (bytes into file)
Start of section headers: 8912 (bytes into file)
Flags: 0x0
Size of this header: 52 (bytes)
Size of program headers: 32 (bytes)
......@@ -34,17 +34,17 @@ Section Headers:
[10] .text._s2d PROGBITS 000005d0 0015d0 0000fc 00 AX 0 0 4
[11] .text._s2h PROGBITS 000006cc 0016cc 000138 00 AX 0 0 4
[12] .text.dispmem PROGBITS 00000804 001804 000240 00 AX 0 0 4
[13] .text.printhelp PROGBITS 00000a44 001a44 000054 00 AX 0 0 4
[14] .text.main PROGBITS 00000a98 001a98 0003b0 00 AX 0 0 4
[15] .rodata PROGBITS 00000e48 001e48 00009c 00 A 0 0 4
[16] .sdata._uartaddr PROGBITS 00000ee4 001ee4 000004 00 WA 0 0 4
[17] .sdata.displ[...] PROGBITS 00000ee8 001ee8 000004 00 WA 0 0 4
[18] .sbss NOBITS 00000eec 001eec 000004 00 WA 0 0 4
[19] .comment PROGBITS 00000000 001eec 000012 01 MS 0 0 1
[20] .riscv.attributes RISCV_ATTRIBUTE 00000000 001efe 000021 00 0 0 1
[21] .symtab SYMTAB 00000000 001f20 000280 10 22 37 4
[22] .strtab STRTAB 00000000 0021a0 000097 00 0 0 1
[23] .shstrtab STRTAB 00000000 002237 00011a 00 0 0 1
[13] .text.printhelp PROGBITS 00000a44 001a44 00001c 00 AX 0 0 4
[14] .text.main PROGBITS 00000a60 001a60 0003b8 00 AX 0 0 4
[15] .rodata PROGBITS 00000e18 001e18 000048 00 A 0 0 4
[16] .sdata._uartaddr PROGBITS 00000e60 001e60 000004 00 WA 0 0 4
[17] .sdata.displ[...] PROGBITS 00000e64 001e64 000004 00 WA 0 0 4
[18] .sbss NOBITS 00000e68 001e68 000004 00 WA 0 0 4
[19] .comment PROGBITS 00000000 001e68 000012 01 MS 0 0 1
[20] .riscv.attributes RISCV_ATTRIBUTE 00000000 001e7a 000021 00 0 0 1
[21] .symtab SYMTAB 00000000 001e9c 000280 10 22 37 4
[22] .strtab STRTAB 00000000 00211c 000097 00 0 0 1
[23] .shstrtab STRTAB 00000000 0021b3 00011a 00 0 0 1
Key to Flags:
W (write), A (alloc), X (execute), M (merge), S (strings), I (info),
L (link order), O (extra OS processing required), G (group), T (TLS),
......@@ -55,7 +55,7 @@ There are no section groups in this file.
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x001000 0x00000000 0x00000000 0x00eec 0x00ef0 RWE 0x1000
LOAD 0x001000 0x00000000 0x00000000 0x00e68 0x00e6c RWE 0x1000
Section to Segment mapping:
Segment Sections...
......@@ -83,16 +83,16 @@ Symbol table '.symtab' contains 40 entries:
11: 000006cc 0 SECTION LOCAL DEFAULT 11 .text._s2h
12: 00000804 0 SECTION LOCAL DEFAULT 12 .text.dispmem
13: 00000a44 0 SECTION LOCAL DEFAULT 13 .text.printhelp
14: 00000a98 0 SECTION LOCAL DEFAULT 14 .text.main
15: 00000e48 0 SECTION LOCAL DEFAULT 15 .rodata
16: 00000ee4 0 SECTION LOCAL DEFAULT 16 .sdata._uartaddr
17: 00000ee8 0 SECTION LOCAL DEFAULT 17 .sdata.displayaddr
18: 00000eec 0 SECTION LOCAL DEFAULT 18 .sbss
14: 00000a60 0 SECTION LOCAL DEFAULT 14 .text.main
15: 00000e18 0 SECTION LOCAL DEFAULT 15 .rodata
16: 00000e60 0 SECTION LOCAL DEFAULT 16 .sdata._uartaddr
17: 00000e64 0 SECTION LOCAL DEFAULT 17 .sdata.displayaddr
18: 00000e68 0 SECTION LOCAL DEFAULT 18 .sbss
19: 00000000 0 SECTION LOCAL DEFAULT 19 .comment
20: 00000000 0 SECTION LOCAL DEFAULT 20 .riscv.attributes
21: 00000000 0 FILE LOCAL DEFAULT ABS console.c
22: 00000ee4 4 OBJECT LOCAL DEFAULT 16 _uartaddr
23: 00000eec 4 OBJECT LOCAL DEFAULT 18 _uartstate
22: 00000e60 4 OBJECT LOCAL DEFAULT 16 _uartaddr
23: 00000e68 4 OBJECT LOCAL DEFAULT 18 _uartstate
24: 0000000c 72 FUNC LOCAL DEFAULT 2 _canputchar
25: 00000054 76 FUNC LOCAL DEFAULT 3 _haschar
26: 000000a0 104 FUNC LOCAL DEFAULT 4 _putchar
......@@ -103,12 +103,12 @@ Symbol table '.symtab' contains 40 entries:
31: 00000428 424 FUNC LOCAL DEFAULT 9 _h2s
32: 000005d0 252 FUNC LOCAL DEFAULT 10 _s2d
33: 000006cc 312 FUNC LOCAL DEFAULT 11 _s2h
34: 00000ee8 4 OBJECT LOCAL DEFAULT 17 displayaddr
34: 00000e64 4 OBJECT LOCAL DEFAULT 17 displayaddr
35: 00000804 576 FUNC LOCAL DEFAULT 12 dispmem
36: 00000a44 84 FUNC LOCAL DEFAULT 13 printhelp
36: 00000a44 28 FUNC LOCAL DEFAULT 13 printhelp
37: 00000000 12 FUNC GLOBAL DEFAULT 1 __start
38: 00000a98 944 FUNC GLOBAL DEFAULT 14 main
39: 00000ef0 0 NOTYPE GLOBAL DEFAULT 18 _end
38: 00000a60 952 FUNC GLOBAL DEFAULT 14 main
39: 00000e6c 0 NOTYPE GLOBAL DEFAULT 18 _end
No version information found in this file.
Attribute Section: riscv
......
examples/hdl4se_riscv/verilog/altera/ram/ram4kB.v
浏览文件 @ a94aaacd
......@@ -90,7 +90,7 @@ module ram4kB (
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../../../test_code/test.mif",
altsyncram_component.init_file = "../test_code/test.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
......@@ -129,7 +129,7 @@ endmodule
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../../../test_code/test.mif"
// Retrieval info: PRIVATE: MIFfilename STRING "../test_code/test.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
......@@ -147,7 +147,7 @@ endmodule
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../../../test_code/test.mif"
// Retrieval info: CONSTANT: INIT_FILE STRING "../test_code/test.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
......
examples/hdl4se_riscv/verilog/altera/ram/ram4kB_bb.v
浏览文件 @ a94aaacd
......@@ -78,7 +78,7 @@ endmodule
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../../../test_code/test.mif"
// Retrieval info: PRIVATE: MIFfilename STRING "../test_code/test.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
......@@ -96,7 +96,7 @@ endmodule
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../../../test_code/test.mif"
// Retrieval info: CONSTANT: INIT_FILE STRING "../test_code/test.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
......
examples/hdl4se_riscv/verilog/riscv_sim_v4.v
浏览文件 @ a94aaacd
......@@ -107,7 +107,7 @@ module top(input wClk, nwReset);
assign bReadData =
((bReadAddr_out & 32'hffffff00) == 32'hf0000000) ? bReadDataKey : (
((bReadAddr_out & 32'hff000000) == 32'h00000000) ? bReadDataRam : (32'hffffffff)
((bReadAddr_out & 32'hff000000) == 32'h00000000) ? bReadDataRam : (32'h0)
);
wire [29:0] ramaddr;
......
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