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提交 7fff4014 编写于 作者: 饶先宏's avatar 饶先宏
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202106261536

上级 48e2955c
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Showing with 608 addition and 245 deletion
examples/terris/src/canblocksetto.c
浏览文件 @ 7fff4014
......@@ -255,8 +255,8 @@ static int terris_canblocksetto_hdl4se_unit_GetValue(HOBJECT object, int index,
return -1;
objectCall3(pobj->input_unit[3], GetValue, pobj->input_index[3], 16, pobj->inputdata);
objectCall1(pobj->inputdata, GetUint32, &blockpos);
blockx = (char)(blockpos & 0xff);
blocky = (char)((blockpos >> 8) & 0xff);
blockx = (blockpos & 0xff);
blocky = ((blockpos >> 8) & 0xff);
if (index == 2) { /* wCtrlStateComplete */
objectCall1(value, AssignUint32, (pobj->readindex_1 > 4 || pobj->cansetto == 0)?1:0);
}
......
examples/terris/src/flushtodisp.c
浏览文件 @ 7fff4014
......@@ -300,7 +300,10 @@ static int terris_flushtodisp_hdl4se_unit_GetValue(HOBJECT object, int index, in
objectCall1(value, AssignUint32, (pobj->flushreadaddr >> 1));
}
else if (index == 5) {/* wWrite */
objectCall1(value, AssignUint32, (ctrlstate == ST_FLUSHTODISP ? 1 : 0));
if (ctrlstate == ST_FLUSHTODISP && (pobj->flushreadaddr_last < 48 || (pobj->flushreadaddr_last >= 52 && pobj->flushreadaddr_last <= 58)))
objectCall1(value, AssignUint32, 1);
else
objectCall1(value, AssignUint32, 0);
}
else if (index == 6) {/* wWriteAddr */
objectCall1(value, AssignUint32, 0xf0000010 + pobj->flushreadaddr_last * 4);
......
examples/terris/src/main.c
浏览文件 @ 7fff4014
......@@ -95,18 +95,24 @@ int main(int argc, char* argv[])
objectCall2(vcdfile, AddSignal, "/simulator/main", "bWriteAddr");
objectCall2(vcdfile, AddSignal, "/simulator/main", "bWriteData");
objectCall2(vcdfile, AddSignal, "/simulator/main/bCtrlState", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/bram_WriteData", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/bInitWriteData", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/bram_WriteAddr", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/wram_Write", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/wCtrlStateComplete", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/flusher/wirein_readaddr", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/flusher/wireout_readaddr", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/flusher/wireout_readaddr_delay_1", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/flusher/bWriteDataSel", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/flusher/curblockline", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/flusher/line", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/wFlushCtrlStateComplete", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/wirein_cansetto", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/wireout_cansetto", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/wCanSetCurrentPre", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/wCanSetCurrent", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/wCanSetCurrent_1", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/wCanSetCurrent_2", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/wCanSetCurrent_3", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/blockx", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/blocky", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/_bCBWReadAddr", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/readdata", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/curblockline", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/curblockline_0", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/curblockline_1", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/curblockline_2", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/curblockline_3", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/blocksetto/curblockline_mask", "out");
objectCall2(vcdfile, AddSignal, "/simulator/main/bram_ReadData", "out");
objectCall1(vcdfile, SetTopModule, sim);
objectCall0(vcdfile, StartRecord);
......
examples/terris/verilog/canblocksetto.v
浏览文件 @ 7fff4014
......@@ -32,7 +32,7 @@
/* canblocksetto.v */
(*
HDL4SE="LCOM",
//HDL4SE="LCOM",
CLSID="90e0e478-1b32-417e-ab32-e5bdec608431",
softmodule="hdl4se"
*)
......@@ -47,21 +47,21 @@ module canblocksetto(
output wCanSet
);
wire [5:0] wirein_readaddr, wireout_readaddr, wireout_readaddr_delay_1;
wire [7:0] wirein_readaddr, wireout_readaddr, wireout_readaddr_delay_1;
wire wirein_cansetto, wireout_cansetto;
wire [7:0] blockx = bSetToPos[7:0];
wire [7:0] blocky = bSetToPos[15:8];
hdl4se_reg #(6) ramreadaddr(wClk, wirein_readaddr, wireout_readaddr);
hdl4se_reg #(6) ramreadaddr_delay_1(wClk, wireout_readaddr, wireout_readaddr_delay_1);
hdl4se_reg #(1) cansetto(wClk, wirein_cansetto, wireout_cansetto);
assign wirein_readaddr = (bCtrlState == `ST_CHECKBLOCKCANSETTO)? (wireout_readaddr + 1) : 0;
hdl4se_reg #(8) reg_readaddr(wClk, wirein_readaddr, wireout_readaddr);
hdl4se_reg #(8) reg_readaddr_delay_1(wClk, wireout_readaddr, wireout_readaddr_delay_1);
hdl4se_reg #(1) reg_cansetto(wClk, wirein_cansetto, wireout_cansetto);
wire [63:0] readdata = bCBWReadData;
wire [7:0] _bCBWReadAddr = wireout_readaddr + blocky - 4;
assign wCanSet = wireout_cansetto;
assign bCBWReadAddr = wireout_readaddr + blocky - 4;
assign wCtrlStateComplete = wireout_readaddr_delay_1 > 4 || wireout_cansetto == 0;
assign bCBWReadAddr = _bCBWReadAddr;
assign wCtrlStateComplete = (wireout_readaddr_delay_1 > 4) || (wireout_cansetto == 0);
wire wCanSetCurrent, wCanSetCurrentPre;
......@@ -71,19 +71,21 @@ module canblocksetto(
assign wCanSetCurrentPre = ((wireout_readaddr > 0) && (wCanSetCurrent==0)) ? 0 : wireout_cansetto;
wire [7:0] y = wireout_readaddr_delay_1 + blocky;
wire wCanSetCurrent_1, wCanSetCurrent_2, wCanSetCurrent_3;
wire wCanSetCurrent_1, wCanSetCurrent_1_1, wCanSetCurrent_1_2, wCanSetCurrent_1_3, wCanSetCurrent_2, wCanSetCurrent_3;
wire [63:0] curblockline = (bCurBlock >> ((3 - wireout_readaddr_delay_1) * 16)) & 16'hffff;
wire [63:0] curblockline = (bCurBlock >> ((8'd3 - wireout_readaddr_delay_1) * 16));
assign wCanSetCurrent = ((wireout_readaddr_delay_1 > 4) || (y >= (`YCOUNT+4)) || (curblockline == 0)) ? 1 : wCanSetCurrent_1;
assign wCanSetCurrent = (wireout_readaddr_delay_1 >= 4) ? 1 : wCanSetCurrent_1_1;
assign wCanSetCurrent_1_1 = (y >= (`YCOUNT+4))?1 : wCanSetCurrent_1_2;
assign wCanSetCurrent_1_2 = (curblockline == 0) ? 1 : wCanSetCurrent_1;
assign wCanSetCurrent_1 = (curblockline != 0 && y < 4) ? 0 : wCanSetCurrent_2;
wire [63:0] curblockline_0, curblockline_1, curblockline_2, curblockline_3, curblockline_mask, curblockline_mask_1;
assign curblockline_0 = (curblockline & 64'hf)?64'hf:64'h0;
assign curblockline_1 = (curblockline & 64'hf0)?64'hf0:64'h0;
assign curblockline_2 = (curblockline & 64'hf00)?64'hf00:64'h0;
assign curblockline_3 = (curblockline & 64'hf000)?64'hf000:64'h0;
assign curblockline_0 = ((curblockline[3:0]) != 0 )?64'hf:64'h0;
assign curblockline_1 = ( (curblockline[7:4]) != 0)?64'hf0:64'h0;
assign curblockline_2 = ((curblockline [11:8]) != 0)?64'hf00:64'h0;
assign curblockline_3 = ( (curblockline [15:12])!= 0)?64'hf000:64'h0;
assign curblockline_mask = curblockline_0 | curblockline_1 | curblockline_2 | curblockline_3;
assign wCanSetCurrent_2 = (blockx < 3) ? (((curblockline_mask & (64'hffffffff_ffffffff >> (64 - ((3 - blockx) * 4)))) != 0) ? 0 : wCanSetCurrent_3)
......
examples/terris/verilog/flushtodisp.v
浏览文件 @ 7fff4014
......@@ -37,7 +37,7 @@
这一行如果存在，连接的就是c语言版本。
*/
(*
//HDL4SE="LCOM",
HDL4SE="LCOM",
CLSID="d588064-fcd3-43cc-b131-1a64c74d9e86",
softmodule="hdl4se"
*)
......@@ -60,22 +60,26 @@ module flushtodisp(
wire [31:0] bNextBlockLo = bNextBlock[31:0];
wire [31:0] bNextBlockHi = bNextBlock[63:32];
wire [31:0] bCurBlockLo = bCurBlock[31:0];
wire [31:0] bCurBlockHi = bCurBlock[63:32];
wire [4:0] bCurBlockX = bCurBlockPos[4:0];
wire [4:0] bCurBlockY = bCurBlockPos[12:8];
wire [7:0] blockx = bCurBlockPos[7:0];
wire [7:0] blocky = bCurBlockPos[15:8];
/* 目前编译器还不支持reg和always块，因此直接用基本单元来做寄存器 */
wire [7:0] wirein_readaddr, wireout_readaddr, wireout_readaddr_delay_1;
wire[31:0] wireout_readaddr2;
hdl4se_reg #(6) ramreadaddr(wClk, wirein_readaddr, wireout_readaddr);
hdl4se_reg #(6) ramreadaddr_delay_1(wClk, wireout_readaddr, wireout_readaddr_delay_1);
wire [9:0] wirein_readaddr, wireout_readaddr, wireout_readaddr_delay_1;
wire[31:0] selecteddata;
hdl4se_reg #(10) reg_readaddr(wClk, wirein_readaddr, wireout_readaddr);
hdl4se_reg #(10) reg_readaddr_delay_1(wClk, wireout_readaddr, wireout_readaddr_delay_1);
assign wirein_readaddr = (bCtrlState == `ST_FLUSHTODISP) ? wireout_readaddr + 1 : 6'b0;
assign bFlushReadAddr = wireout_readaddr[6:1];
assign wCtrlStateComplete = wireout_readaddr == 8'd60;
assign bWriteAddr = 32'hf000_0010 + wireout_readaddr_delay_1 * 4;
assign wWrite = (bCtrlState == `ST_FLUSHTODISP) ? 1 : 0;
wire [2:0] bWriteDataSel = (wireout_readaddr_delay_1 < 8'd52)?3'd7:(wireout_readaddr_delay_1 - 8'd52);
assign bFlushReadAddr = wireout_readaddr[6:1];
wire _wWrite = (bCtrlState == `ST_FLUSHTODISP) && (bWriteDataSel <= 7);
wire [31:0] _bWriteAddr = 32'hf000_0010 + (wireout_readaddr_delay_1 * 4);
wire [31:0] _bWriteData = selecteddata;
assign wWrite = _wWrite;
assign bWriteAddr = _bWriteAddr;
assign bWriteData = _bWriteData;
wire [9:0] bWriteDataSel = (wireout_readaddr_delay_1 < 8'd52)?8'd7:(wireout_readaddr_delay_1 - 8'd52);
/*
0 -- 47，面板内容， --> 7
52, 53: nextblock0, 1 --> 0, 1
......@@ -83,94 +87,16 @@ module flushtodisp(
57 : level --> 5
58 : speed --> 6
*/
wire [4:0] line = wireout_readaddr_delay_1[5:1];
wire right = wireout_readaddr_delay_1[0];
wire [15:0] line3 = ((line + 2) == bCurBlockY) ? 16'hffff:16'b0;
wire [15:0] line2 = ((line + 1) == bCurBlockY) ? 16'hffff:16'b0;
wire [15:0] line1 = (line == bCurBlockY) ? 16'hffff:16'b0;
wire [15:0] line0 = (line == (bCurBlockY+1)) ? 16'hffff:16'b0;
wire [15:0] curblockline = (line0 & bCurBlock[15:0]) | (line1 & bCurBlock[31:16]) | (line2 & bCurBlock[47:32]) | (line3 & bCurBlock[63:48]);
wire [31:0] curline;
wire [31:0] selecteddata;
hdl4se_bind2 #(16, 16) curlinebind(curblockline, selecteddata[31:16], curline);
wire [31:0] leftline_0_15;
wire [31:0] leftline = bCurBlockX[5:4]?selecteddata:(leftline_0_15 | selecteddata);
wire [31:0] leftline_1, leftline0, leftline1, leftline2, leftline3, leftline4, leftline5, leftline6, leftline7, leftline8, leftline9;
hdl4se_bind2 #(4, 28) leftline_1_gen(curblockline[15:12], 28'b0, leftline_1);
hdl4se_bind2 #(8, 24) leftline0_gen(curblockline[15:8], 24'b0, leftline0);
hdl4se_bind2 #(12, 20) leftline1_gen(curblockline[15:4], 20'b0, leftline1);
hdl4se_bind2 #(16, 16) leftline2_gen(curblockline[15:0], 16'b0, leftline2);
hdl4se_bind3 #(4, 16, 12) leftline3_gen(4'b0, curblockline[15:0], 12'b0, leftline3);
hdl4se_bind3 #(8, 16, 8) leftline4_gen(8'b0, curblockline[15:0], 8'b0, leftline4);
hdl4se_bind3 #(12,16, 4) leftline5_gen(12'b0, curblockline[15:0], 4'b0, leftline5);
hdl4se_bind2 #(16, 16) leftline6_gen(16'b0, curblockline[15:0], leftline6);
hdl4se_bind2 #(20, 12) leftline7_gen(20'b0, curblockline[11:0], leftline7);
hdl4se_bind2 #(24, 8) leftline8_gen(24'b0, curblockline[7:0], leftline8);
hdl4se_bind2 #(28, 4) leftline9_gen(28'b0, curblockline[3:0], leftline9);
wire [7:0] y = wireout_readaddr_delay_1[7:1];
wire [63:0] curblockline_0 = ((blocky >= y) && (blocky < 4 + y)) ? ((bCurBlock >> ((blocky - y) * 16)) & 64'hffff) : 64'h0;
wire [63:0] curblockline = (blockx < 3) ? (curblockline_0 >> ((3 - blockx) * 4))
: (curblockline_0 << ((blockx - 3) * 4));
wire [63:0] data = bFlushReadData | curblockline;
wire right = wireout_readaddr_delay_1[0];
hdl4se_mux16 #(32) selectleftline(
bCurBlockX[3:0],
leftline_1,
leftline0,
leftline1,
leftline2,
leftline3,
leftline4,
leftline5,
leftline6,
leftline7,
leftline8,
leftline9,
selecteddata,
selecteddata,
selecteddata,
selecteddata,
selecteddata,
leftline_0_15
);
wire [31:0] rightline_3_18;
wire [31:0] rightline = (bCurBlockX[5:0]>=3)?(rightline_3_18|selecteddata):selecteddata;
wire [31:0] rightline0, rightline1, rightline2, rightline3, rightline4, rightline5, rightline6, rightline7, rightline8, rightline9, rightline10;
hdl4se_bind2 #(4, 28) rightline0_gen(curblockline[15:12], 28'b0, rightline0);
hdl4se_bind2 #(8, 24) rightline1_gen(curblockline[15:8], 24'b0, rightline1);
hdl4se_bind2 #(12, 20) rightline2_gen(curblockline[15:4], 20'b0, rightline2);
hdl4se_bind2 #(16, 16) rightline3_gen(curblockline[15:0], 16'b0,rightline3);
hdl4se_bind3 #(4, 16, 12) rightline4_gen(4'b0, curblockline[15:0], 12'b0, rightline4);
hdl4se_bind3 #(8, 16, 8) rightline5_gen(8'b0, curblockline[15:0], 8'b0, rightline5);
hdl4se_bind3 #(12, 16, 4) rightline6_gen(12'b0, curblockline[15:0], 4'b0, rightline6);
hdl4se_bind2 #(16, 16) rightline7_gen(16'b0, curblockline[15:0], rightline7);
hdl4se_bind2 #(20, 12) rightline8_gen(20'b0, curblockline[11:0], rightline8);
hdl4se_bind2 #(24, 8) rightline9_gen(24'b0, curblockline[7:0], rightline9);
hdl4se_bind2 #(28, 4) rightline10_gen(28'b0, curblockline[3:0], rightline10);
wire [5:0] blockx_3 = bCurBlockX[5:0] - 6'd3;
hdl4se_mux16 #(32) selectrightline(
blockx_3[3:0],
selecteddata,
selecteddata,
selecteddata,
selecteddata,
selecteddata,
rightline0,
rightline1,
rightline2,
rightline3,
rightline4,
rightline5,
rightline6,
rightline7,
rightline8,
rightline9,
rightline10,
rightline_3_18
);
assign bWriteData = (curblockline != 16'b0)?(right?rightline:leftline):selecteddata;
hdl4se_mux8 #(32) writedatasel(
bWriteDataSel,
bWriteDataSel[2:0],
bNextBlockLo,
bNextBlockHi,
32'b0,
......@@ -178,7 +104,9 @@ module flushtodisp(
bCtrlScore,
bCtrlLevel,
bCtrlSpeed,
right?bFlushReadData[63:32]:bFlushReadData[31:0],
right?data[63:32]:data[31:0],
selecteddata
);
endmodule
examples/terris/verilog/terris_main_asm.v
浏览文件 @ 7fff4014
......@@ -502,109 +502,44 @@ module flushtodisp
;
wire [31:0] bNextBlockLo;
wire [31:0] bNextBlockHi;
wire [31:0] bCurBlockLo;
wire [31:0] bCurBlockHi;
wire [4:0] bCurBlockX;
wire [4:0] bCurBlockY;
wire [7:0] wirein_readaddr;
wire [7:0] wireout_readaddr;
wire [7:0] wireout_readaddr_delay_1;
wire [31:0] wireout_readaddr2;
wire [2:0] bWriteDataSel;
wire [4:0] line;
wire right;
wire [15:0] line3;
wire [15:0] line2;
wire [15:0] line1;
wire [15:0] line0;
wire [15:0] curblockline;
wire [31:0] curline;
wire [7:0] blockx;
wire [7:0] blocky;
wire [9:0] wirein_readaddr;
wire [9:0] wireout_readaddr;
wire [9:0] wireout_readaddr_delay_1;
wire [31:0] selecteddata;
wire [31:0] leftline_0_15;
wire [31:0] leftline;
wire [31:0] leftline_1;
wire [31:0] leftline0;
wire [31:0] leftline1;
wire [31:0] leftline2;
wire [31:0] leftline3;
wire [31:0] leftline4;
wire [31:0] leftline5;
wire [31:0] leftline6;
wire [31:0] leftline7;
wire [31:0] leftline8;
wire [31:0] leftline9;
wire [31:0] rightline_3_18;
wire [31:0] rightline;
wire [31:0] rightline0;
wire [31:0] rightline1;
wire [31:0] rightline2;
wire [31:0] rightline3;
wire [31:0] rightline4;
wire [31:0] rightline5;
wire [31:0] rightline6;
wire [31:0] rightline7;
wire [31:0] rightline8;
wire [31:0] rightline9;
wire [31:0] rightline10;
wire [5:0] blockx_3;
wire _wWrite;
wire [31:0] _bWriteAddr;
wire [31:0] _bWriteData;
wire [9:0] bWriteDataSel;
wire [7:0] y;
wire [63:0] curblockline_0;
wire [63:0] curblockline;
wire [63:0] data;
wire right;
assign wirein_readaddr = (((bCtrlState==1))?((wireout_readaddr+1)):(6'b0));
assign bFlushReadAddr = wireout_readaddr [6:1] ;
assign wCtrlStateComplete = (wireout_readaddr==8'd60);
assign bWriteAddr = (32'hf0000010+(wireout_readaddr_delay_1*4));
assign wWrite = (((bCtrlState==1))?(1):(0));
assign bWriteData = (((curblockline!=16'b0))?(((right)?(rightline):(leftline))):(selecteddata));
assign bFlushReadAddr = wireout_readaddr [6:1] ;
assign wWrite = _wWrite;
assign bWriteAddr = _bWriteAddr;
assign bWriteData = _bWriteData;
assign bNextBlockLo = bNextBlock [31:0] ;
assign bNextBlockHi = bNextBlock [63:32] ;
assign bCurBlockLo = bCurBlock [31:0] ;
assign bCurBlockHi = bCurBlock [63:32] ;
assign bCurBlockX = bCurBlockPos [4:0] ;
assign bCurBlockY = bCurBlockPos [12:8] ;
assign bWriteDataSel = (((wireout_readaddr_delay_1<8'd52))?(3'd7):((wireout_readaddr_delay_1-8'd52)));
assign line = wireout_readaddr_delay_1 [5:1] ;
assign blockx = bCurBlockPos [7:0] ;
assign blocky = bCurBlockPos [15:8] ;
assign _wWrite = ((bCtrlState==1)&&(bWriteDataSel<=7));
assign _bWriteAddr = (32'hf0000010+(wireout_readaddr_delay_1*4));
assign _bWriteData = selecteddata;
assign bWriteDataSel = (((wireout_readaddr_delay_1<8'd52))?(8'd7):((wireout_readaddr_delay_1-8'd52)));
assign y = wireout_readaddr_delay_1 [7:1] ;
assign curblockline_0 = ((((blocky>=y)&&(blocky<(4+y))))?(((bCurBlock>>((blocky-y)*16))&64'hffff)):(64'h0));
assign curblockline = (((blockx<3))?((curblockline_0>>((3-blockx)*4))):((curblockline_0<<((blockx-3)*4))));
assign data = (bFlushReadData|curblockline);
assign right = wireout_readaddr_delay_1 [0] ;
assign line3 = ((((line+2)==bCurBlockY))?(16'hffff):(16'b0));
assign line2 = ((((line+1)==bCurBlockY))?(16'hffff):(16'b0));
assign line1 = (((line==bCurBlockY))?(16'hffff):(16'b0));
assign line0 = (((line==(bCurBlockY+1)))?(16'hffff):(16'b0));
assign curblockline = ((line0&bCurBlock [15:0] )|((line1&bCurBlock [31:16] )|((line2&bCurBlock [47:32] )|(line3&bCurBlock [63:48] ))));
assign leftline = ((bCurBlockX [5:4] )?(selecteddata):((leftline_0_15|selecteddata)));
assign rightline = (((bCurBlockX [5:0] >=3))?((rightline_3_18|selecteddata)):(selecteddata));
assign blockx_3 = (bCurBlockX [5:0] -6'd3);
hdl4se_reg #( 6 ) ramreadaddr( wClk, wirein_readaddr, wireout_readaddr );
hdl4se_reg #( 6 ) ramreadaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 );
hdl4se_bind2 #( 16, 16 ) curlinebind( curblockline, selecteddata [31:16] , curline );
hdl4se_bind2 #( 4, 28 ) leftline_1_gen( curblockline [15:12] , 0, leftline_1 );
hdl4se_bind2 #( 8, 24 ) leftline0_gen( curblockline [15:8] , 0, leftline0 );
hdl4se_bind2 #( 12, 20 ) leftline1_gen( curblockline [15:4] , 0, leftline1 );
hdl4se_bind2 #( 16, 16 ) leftline2_gen( curblockline [15:0] , 0, leftline2 );
hdl4se_bind3 #( 4, 16, 12 ) leftline3_gen( 0, curblockline [15:0] , 0, leftline3 );
hdl4se_bind3 #( 8, 16, 8 ) leftline4_gen( 0, curblockline [15:0] , 0, leftline4 );
hdl4se_bind3 #( 12, 16, 4 ) leftline5_gen( 0, curblockline [15:0] , 0, leftline5 );
hdl4se_bind2 #( 16, 16 ) leftline6_gen( 0, curblockline [15:0] , leftline6 );
hdl4se_bind2 #( 20, 12 ) leftline7_gen( 0, curblockline [11:0] , leftline7 );
hdl4se_bind2 #( 24, 8 ) leftline8_gen( 0, curblockline [7:0] , leftline8 );
hdl4se_bind2 #( 28, 4 ) leftline9_gen( 0, curblockline [3:0] , leftline9 );
hdl4se_mux16 #( 32 ) selectleftline( bCurBlockX [3:0] , leftline_1, leftline0, leftline1, leftline2, leftline3
, leftline4, leftline5, leftline6, leftline7, leftline8
, leftline9, selecteddata, selecteddata, selecteddata, selecteddata
, selecteddata, leftline_0_15 );
hdl4se_bind2 #( 4, 28 ) rightline0_gen( curblockline [15:12] , 0, rightline0 );
hdl4se_bind2 #( 8, 24 ) rightline1_gen( curblockline [15:8] , 0, rightline1 );
hdl4se_bind2 #( 12, 20 ) rightline2_gen( curblockline [15:4] , 0, rightline2 );
hdl4se_bind2 #( 16, 16 ) rightline3_gen( curblockline [15:0] , 0, rightline3 );
hdl4se_bind3 #( 4, 16, 12 ) rightline4_gen( 0, curblockline [15:0] , 0, rightline4 );
hdl4se_bind3 #( 8, 16, 8 ) rightline5_gen( 0, curblockline [15:0] , 0, rightline5 );
hdl4se_bind3 #( 12, 16, 4 ) rightline6_gen( 0, curblockline [15:0] , 0, rightline6 );
hdl4se_bind2 #( 16, 16 ) rightline7_gen( 0, curblockline [15:0] , rightline7 );
hdl4se_bind2 #( 20, 12 ) rightline8_gen( 0, curblockline [11:0] , rightline8 );
hdl4se_bind2 #( 24, 8 ) rightline9_gen( 0, curblockline [7:0] , rightline9 );
hdl4se_bind2 #( 28, 4 ) rightline10_gen( 0, curblockline [3:0] , rightline10 );
hdl4se_mux16 #( 32 ) selectrightline( blockx_3 [3:0] , selecteddata, selecteddata, selecteddata, selecteddata, selecteddata
, rightline0, rightline1, rightline2, rightline3, rightline4
, rightline5, rightline6, rightline7, rightline8, rightline9
, rightline10, rightline_3_18 );
hdl4se_mux8 #( 32 ) writedatasel( bWriteDataSel, bNextBlockLo, bNextBlockHi, 32'h0, 32'h0, bCtrlScore
, bCtrlLevel, bCtrlSpeed, ((right)?(bFlushReadData [63:32] ):(bFlushReadData [31:0] )), selecteddata );
hdl4se_reg #( 10 ) reg_readaddr( wClk, wirein_readaddr, wireout_readaddr );
hdl4se_reg #( 10 ) reg_readaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 );
hdl4se_mux8 #( 32 ) writedatasel( bWriteDataSel [2:0] , bNextBlockLo, bNextBlockHi, 32'h0, 32'h0, bCtrlScore
, bCtrlLevel, bCtrlSpeed, ((right)?(data [63:32] ):(data [31:0] )), selecteddata );
endmodule
......@@ -650,7 +585,6 @@ endmodule
(*
HDL4SE = "LCOM",
CLSID = "90e0e478-1b32-417e-ab32-e5bdec608431",
softmodule = "hdl4se"
*)
......@@ -666,17 +600,22 @@ module canblocksetto
output wCanSet
)
;
wire [5:0] wirein_readaddr;
wire [5:0] wireout_readaddr;
wire [5:0] wireout_readaddr_delay_1;
wire [7:0] wirein_readaddr;
wire [7:0] wireout_readaddr;
wire [7:0] wireout_readaddr_delay_1;
wire wirein_cansetto;
wire wireout_cansetto;
wire [7:0] blockx;
wire [7:0] blocky;
wire [63:0] readdata;
wire [7:0] _bCBWReadAddr;
wire wCanSetCurrent;
wire wCanSetCurrentPre;
wire [7:0] y;
wire wCanSetCurrent_1;
wire wCanSetCurrent_1_1;
wire wCanSetCurrent_1_2;
wire wCanSetCurrent_1_3;
wire wCanSetCurrent_2;
wire wCanSetCurrent_3;
wire [63:0] curblockline;
......@@ -686,30 +625,33 @@ module canblocksetto
wire [63:0] curblockline_3;
wire [63:0] curblockline_mask;
wire [63:0] curblockline_mask_1;
assign wirein_readaddr = (((bCtrlState==3))?((wireout_readaddr+1)):(0));
assign wCanSet = wireout_cansetto;
assign bCBWReadAddr = (wireout_readaddr+(blocky-4));
assign wCtrlStateComplete = (wireout_readaddr_delay_1>(4||(wireout_cansetto==0)));
assign bCBWReadAddr = _bCBWReadAddr;
assign wCtrlStateComplete = ((wireout_readaddr_delay_1>4)||(wireout_cansetto==0));
assign wirein_readaddr = (((bCtrlState==3))?((wireout_readaddr+1)):(0));
assign wirein_cansetto = (((bCtrlState==3))?(wCanSetCurrentPre):(1));
assign wCanSetCurrentPre = ((((wireout_readaddr>0)&&(wCanSetCurrent==0)))?(0):(wireout_cansetto));
assign wCanSetCurrent = ((((wireout_readaddr_delay_1>4)||((y>=(24+4))||(curblockline==0))))?(1):(wCanSetCurrent_1));
assign wCanSetCurrent = (((wireout_readaddr_delay_1>=4))?(1):(wCanSetCurrent_1_1));
assign wCanSetCurrent_1_1 = (((y>=(24+4)))?(1):(wCanSetCurrent_1_2));
assign wCanSetCurrent_1_2 = (((curblockline==0))?(1):(wCanSetCurrent_1));
assign wCanSetCurrent_1 = (((curblockline!=(0&&(y<4))))?(0):(wCanSetCurrent_2));
assign curblockline_0 = (((curblockline&64'hf))?(64'hf):(64'h0));
assign curblockline_1 = (((curblockline&64'hf0))?(64'hf0):(64'h0));
assign curblockline_2 = (((curblockline&64'hf00))?(64'hf00):(64'h0));
assign curblockline_3 = (((curblockline&64'hf000))?(64'hf000):(64'h0));
assign curblockline_0 = (((curblockline [3:0] !=0))?(64'hf):(64'h0));
assign curblockline_1 = (((curblockline [7:4] !=0))?(64'hf0):(64'h0));
assign curblockline_2 = (((curblockline [11:8] !=0))?(64'hf00):(64'h0));
assign curblockline_3 = (((curblockline [15:12] !=0))?(64'hf000):(64'h0));
assign curblockline_mask = (curblockline_0|(curblockline_1|(curblockline_2|curblockline_3)));
assign wCanSetCurrent_2 = (((blockx<3))?(((((curblockline_mask&(64'hffffffff_ffffffff>>(64-((3-blockx)*4))))!=0))?(0):(wCanSetCurrent_3))):((((((curblockline_mask&(64'hffffffff_ffffffff<<(64-((blockx-3)*4))))!=0)&&(blockx>3)))?(0):(wCanSetCurrent_3))));
assign curblockline_mask_1 = (((blockx<3))?((curblockline_mask>>((3-blockx)*4))):((curblockline_mask<<((blockx-3)*4))));
assign wCanSetCurrent_3 = ((bCBWReadData&curblockline_mask_1)==0);
assign blockx = bSetToPos [7:0] ;
assign blocky = bSetToPos [15:8] ;
assign readdata = bCBWReadData;
assign _bCBWReadAddr = (wireout_readaddr+(blocky-4));
assign y = (wireout_readaddr_delay_1+blocky);
assign curblockline = ((bCurBlock>>((3-wireout_readaddr_delay_1)*16))&16'hffff);
hdl4se_reg #( 6 ) ramreadaddr( wClk, wirein_readaddr, wireout_readaddr );
hdl4se_reg #( 6 ) ramreadaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 );
hdl4se_reg #( 1 ) cansetto( wClk, wirein_cansetto, wireout_cansetto );
assign curblockline = (bCurBlock>>((8'd3-wireout_readaddr_delay_1)*16));
hdl4se_reg #( 8 ) reg_readaddr( wClk, wirein_readaddr, wireout_readaddr );
hdl4se_reg #( 8 ) reg_readaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 );
hdl4se_reg #( 1 ) reg_cansetto( wClk, wirein_cansetto, wireout_cansetto );
endmodule
......
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