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202108251726

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examples/hdl4se_riscv/de1/regfile/regfile.qip 0 → 100644
浏览文件 @ 55792653
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "regfile.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "regfile_bb.v"]
examples/hdl4se_riscv/de1/regfile/regfile.v 0 → 100644
浏览文件 @ 55792653
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: regfile.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module regfile (
address,
byteena,
clock,
data,
wren,
q);
input [4:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 5,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
// Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
examples/hdl4se_riscv/de1/regfile/regfile_bb.v 0 → 100644
浏览文件 @ 55792653
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: regfile.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module regfile (
address,
byteena,
clock,
data,
wren,
q);
input [4:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
// Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
examples/hdl4se_riscv/hdl4se_riscv_sim/CMakeLists.txt
浏览文件 @ 55792653
......@@ -3,19 +3,33 @@
#
cmake_minimum_required (VERSION 3.8)
add_executable(riscv_sim
"hdl4se_riscv_core.c"
"riscv_sim_main.c"
"main.c"
"hdl4se_riscv_core_v2.c" "hdl4se_riscv_ram8k.c")
add_executable(riscv_sim_v2
"riscv_sim_main_v2.c"
"main_v2.c"
"hdl4se_riscv_core_v2.c"
"hdl4se_riscv_ram8k.c"
"hdl4se_riscv_regfile.c"
)
add_executable(riscv_sim
"riscv_sim_main.c"
"main.c"
"hdl4se_riscv_core.c"
)
add_definitions(-D_CRT_SECURE_NO_WARNINGS)
if(WIN32)
target_link_libraries(riscv_sim_v2 hdl4sesim hdl4secell bignumber digitled hdl4seutils verilog_parser verilog_preprocess glfw lcom)
else()
target_link_libraries(riscv_sim_v2 hdl4sesim hdl4secell bignumber digitled hdl4seutils verilog_parser verilog_preprocess glfw lcom pthread)
endif()
if(WIN32)
target_link_libraries(riscv_sim hdl4sesim hdl4secell bignumber digitled hdl4seutils verilog_parser verilog_preprocess glfw lcom)
else()
target_link_libraries(riscv_sim hdl4sesim hdl4secell bignumber digitled hdl4seutils verilog_parser verilog_preprocess glfw lcom pthread)
endif()
set(CMAKE_CXX_FLAGS_RELEASE "/MT")
set(CMAKE_CXX_FLAGS_DEBUG "/MTd")
......
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv.h
浏览文件 @ 55792653
......@@ -48,6 +48,10 @@ extern "C" {
DEFINE_GUID(CLSID_HDL4SE_RISCV_CORE, 0x638e8bc3, 0xb0e0, 0x41dc, 0x9e, 0xdd, 0xd3, 0x5a, 0x39, 0xfd, 0x80, 0x51);
// {EE3409B2-6D04-42B3-A44D-7F2444DDC00D}
DEFINE_GUID(CLSID_HDL4SE_RISCV_RAM, 0xee3409b2, 0x6d04, 0x42b3, 0xa4, 0x4d, 0x7f, 0x24, 0x44, 0xdd, 0xc0, 0xd);
// {2E577C6B-2FF1-425E-90B3-947EB523B863}
DEFINE_GUID(CLSID_HDL4SE_RISCV_REGFILE, 0x2e577c6b, 0x2ff1, 0x425e, 0x90, 0xb3, 0x94, 0x7e, 0xb5, 0x23, 0xb8, 0x63);
#define RAMSIZE 2048
#endif
......
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_core.c
浏览文件 @ 55792653
......@@ -649,7 +649,7 @@ int loadExecImage(unsigned char* data, int maxlen)
MODULE_INIT(riscv_core)
int i;
pobj->ramsize = 8 * 1024;
pobj->ramsize = RAMSIZE * 4;
pobj->ram = malloc(pobj->ramsize);
loadExecImage(pobj->ram, pobj->ramsize);
pobj->ramdstaddr = 0;
......
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_core_v2.c
浏览文件 @ 55792653
......@@ -69,94 +69,100 @@ IDLIST
VID(wRead),
VID(bReadAddr),
VID(bReadData),
VID(regno),
VID(regena),
VID(regwrdata),
VID(regwren),
VID(regrddata),
VID(pc),
VID(instr),
VID(rs1),
VID(rs2),
VID(write),
VID(writeaddr),
VID(writedata),
VID(read),
VID(readaddr),
VID(writemask),
VID(readreg),
VID(state),
VID(x1),
VID(x2),
VID(x3),
VID(x4),
VID(x5),
VID(x6),
VID(x7),
VID(x8),
VID(x9),
VID(x10),
VID(x11),
VID(x12),
VID(x13),
VID(x14),
VID(x15),
VID(x16),
VID(x17),
VID(x18),
VID(x19),
VID(x20),
VID(x21),
VID(x22),
VID(x23),
VID(x24),
VID(x25),
VID(x26),
VID(x27),
VID(x28),
VID(x29),
VID(x30),
VID(x31),
END_IDLIST
enum riscv_core_state {
RISCVSTATE_INIT_REGX1,
RISCVSTATE_INIT_REGX2,
RISCVSTATE_READ_INST,
RISCVSTATE_READ_RS1,
RISCVSTATE_READ_RS2,
RISCVSTATE_WRITE_RD,
RISCVSTATE_EXEC_INST,
RISCVSTATE_WAIT_LD,
RISCVSTATE_WAIT_ST,
};
MODULE_DECLARE(riscv_core)
unsigned int *ram;
unsigned int regs[32];
unsigned int ramsize;
unsigned int dstreg;
unsigned int dstvalue;
unsigned int ramdstaddr;
unsigned int ramdstvalue;
unsigned int ramdstwidth; /* 1, 2, 4 */
END_MODULE_DECLARE(riscv_core)
DEFINE_FUNC(riscv_core_rw_sig, "write, writeaddr, writedata, read, readaddr") {
static unsigned int sign_expand(unsigned int v, int bit)
{
int i;
if (v & (1 << bit)) {
for (i = bit + 1; i < 32; i++) {
v |= 1 << i;
}
}
return v;
}
DEFINE_FUNC(riscv_core_wr_sig, "write, writeaddr, writedata, writemask") {
VAssign(wWrite, write);
VAssign(bWriteAddr, writeaddr);
VAssign(bWriteData, writedata);
VAssign(wRead, read);
VAssign(bReadAddr, readaddr);
vput(bWriteMask, 0x0);
VAssign(bWriteMask, writemask);
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_core_register, "pc") {
int i;
for (i = 1;i<32;i++)
vput_idx(VID(x1)+i-1, pobj->regs[i]);
DEFINE_FUNC(riscv_core_read_sig, "state, pc, instr, bReadData") {
unsigned int state;
state = vget(state);
vput(wRead, 0);
if (state == RISCVSTATE_READ_INST) {
vput(wRead, 1);
vput(bReadAddr, vget(pc));
}
else if (state == RISCVSTATE_EXEC_INST) {
unsigned int instr;
instr = vget(bReadData);
if ((instr & 0x7f) == 0x03) {
/* ld inst */
unsigned int imm;
unsigned int rs1;
unsigned int rdaddr;
imm = instr >> 20;
rs1 = (instr >> 15) & 0x1f;
if (rs1 != 0)
rs1 = pobj->regs[rs1];
imm = sign_expand(imm, 11);
rdaddr = rs1 + imm;
vput(wRead, 1);
vput(bReadAddr, rdaddr);
}
}
} END_DEFINE_FUNC
enum riscv_core_state {
RISCVSTATE_READ_INST,
RISCVSTATE_WAIT_LD,
};
DEFINE_FUNC(riscv_core_reg_wr_sig, "write, writeaddr, writedata, writemask") {
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_core_instr, "bReadData") {
VAssign(instr, bReadData);
} END_DEFINE_FUNC
FILE* recordfileGet();
#define DEBUG_CODE_FUNC fprintf(recordfileGet(), "%30s: %08x: %08x\n", __FUNCTION__, pc, instr)
#define DEBUG_CODE_DECODE fprintf(recordfileGet(),
#define INSTR_FORMAT_ERROR fprintf(recordfileGet(), "instruction format error, we support rv32im only: pc=%08x: %x\n", pc, instr);
static unsigned int sign_expand(unsigned int v, int bit)
{
int i;
if (v & (1 << bit)) {
for (i = bit + 1; i < 32; i++) {
v |= 1 << i;
}
}
return v;
}
#define RISCV_SETREG(rd, rst) \
do { \
......@@ -272,44 +278,9 @@ void riscv_core_exec_ld_inst(MODULE_DATA_TYPE* pobj, unsigned int pc, unsigned i
func3 = (instr >> 12) & 0x7;
rd = (instr >> 7) & 0x1f;
imm = sign_expand(imm, 11);
v = 0;
/* riscv支持地址不对齐访问 */
rdaddr = rs1 + imm;
if (rdaddr < pobj->ramsize) {
switch (func3) {
case 0:/*lb*/
memcpy(&v, ((char*)pobj->ram) + rdaddr, 1);
v = sign_expand(v, 7);
RISCV_SETREG(rd, v);
break;
case 1:/*lh*/
memcpy(&v, ((char*)pobj->ram) + rdaddr, 2);
v = sign_expand(v, 15);
RISCV_SETREG(rd, v);
break;
case 2:/*lw*/
memcpy(&v, ((char*)pobj->ram) + rdaddr, 4);
RISCV_SETREG(rd, v);
break;
case 4:/*lbu*/
memcpy(&v, ((char*)pobj->ram) + rdaddr, 1);
RISCV_SETREG(rd, v);
break;
case 5:/*lhu*/
memcpy(&v, ((char*)pobj->ram) + rdaddr, 2);
RISCV_SETREG(rd, v);
break;
default:
DEBUG_CODE_FUNC;
break;
}
}
else {
vput(read, 1);
vput(readaddr, rdaddr);
vput(readreg, rd);
vput(state, RISCVSTATE_WAIT_LD);
}
vput(readreg, rd);
vput(state, RISCVSTATE_WAIT_LD);
}
void riscv_core_exec_st_inst(MODULE_DATA_TYPE* pobj, unsigned int pc, unsigned int instr) {
......@@ -320,6 +291,8 @@ void riscv_core_exec_st_inst(MODULE_DATA_TYPE* pobj, unsigned int pc, unsigned i
unsigned int func3;
unsigned int v;
unsigned int writeaddr;
unsigned int writemask;
unsigned int writedata;
imm = ((instr >> 20) & 0xfe0) | ((instr >> 7) & 0x1f);
rs1 = (instr >> 15) & 0x1f;
if (rs1 != 0)
......@@ -330,36 +303,46 @@ void riscv_core_exec_st_inst(MODULE_DATA_TYPE* pobj, unsigned int pc, unsigned i
func3 = (instr >> 12) & 0x7;
imm = sign_expand(imm, 11);
v = 0;
/* riscv支持地址不对齐访问 */
/* riscv支持地址不对齐访问，但是假定写在一个32位字中 */
writeaddr = rs1 + imm;
if (writeaddr < pobj->ramsize) {
switch (func3) {
writemask = 0;
writedata = rs2;
switch (func3) {
case 0:/*sb*/
pobj->ramdstaddr = writeaddr;
pobj->ramdstvalue = rs2;
pobj->ramdstwidth = 1;
switch (writeaddr & 3) {
case 0: writemask = 0xe; writedata <<= 0; break; //1110
case 1: writemask = 0xd; writedata <<= 8; break; //1101
case 2: writemask = 0xb; writedata <<= 16; break; //1011
case 3: writemask = 0x7; writedata <<= 24; break; //0111
}
break;
case 1:/*sh*/
pobj->ramdstaddr = writeaddr;
pobj->ramdstvalue = rs2;
pobj->ramdstwidth = 2;
switch (writeaddr & 3) {
case 0: writemask = 0xc; writedata <<= 0; break; //1100
case 1: writemask = 0x9; writedata <<= 8; break; //1001
case 2: writemask = 0x3; writedata <<= 16; break; //0011
case 3: {
printf("we support store instruction write in one word only %08x: %08x\n", pc, instr);
exit(-6);
}break;
}
break;
case 2:/*sw*/
pobj->ramdstaddr = writeaddr;
pobj->ramdstvalue = rs2;
pobj->ramdstwidth = 4;
if (writeaddr & 3) {
printf("we support store instruction write in one word only %08x: %08x\n", pc, instr);
exit(-6);
}
break;
default:
pobj->ramdstaddr = 0; /* no write */
DEBUG_CODE_FUNC;
exit(-7);
break;
}
}
else {
vput(writeaddr, writeaddr);
vput(write, 1);
vput(writedata, rs2);
}
vput(writeaddr, writeaddr);
vput(write, 1);
vput(writedata, writedata);
vput(writemask, writemask);
vput(state, RISCVSTATE_WAIT_ST);
}
void riscv_core_exec_alui_inst(MODULE_DATA_TYPE* pobj, unsigned int pc, unsigned int instr) {
......@@ -522,13 +505,9 @@ void riscv_core_exec_sys_inst(MODULE_DATA_TYPE* pobj, unsigned int pc, unsigned
DEBUG_CODE_FUNC;
}
DEFINE_FUNC(riscv_core_read_inst, "") {
DEFINE_FUNC(riscv_core_exec_inst, "") {
unsigned int pc = vget(pc);
if (pc > pobj->ramsize) {
printf("exception: pc[%08x] overflow [ramsize=%d]\n", pc, pobj->ramsize);
exit(-3);
}
unsigned int instr = pobj->ram[pc/4];
unsigned int instr = vget(bReadData);
unsigned int opcode = instr & 0x7f;
if ( ((opcode & 0x3) != 3) || ( (opcode >> 2) & 0x7) == 0x7) {
printf("instruction format error, we support 32bit instruction only: pc=%08x: %x", pc, instr);
......@@ -557,158 +536,89 @@ DEFINE_FUNC(riscv_core_read_inst, "") {
DEFINE_FUNC(riscv_core_ld_done_inst, "") {
RISCV_SETREG(vget(readreg), vget(bReadData));
vput(state, RISCVSTATE_READ_INST);
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_core_instr, "pc") {
vput(instr, pobj->ram[vget(pc)/4]);
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_core_clktick, "") {
if (vget(nwReset) == 0) {
vput(pc, 0x74);
vput(write, 0);
vput(read, 0);
vput(state, RISCVSTATE_READ_INST);
vput(state, RISCVSTATE_INIT_REGX1);
}
else {
int state = vget(state);
vput(write, 0);
vput(read, 0);
if (state == RISCVSTATE_READ_INST) {
CALL_FUNC(riscv_core_read_inst);
switch (state) {
case RISCVSTATE_INIT_REGX1: {
RISCV_SETREG(1, 0x8c);
vput(state, RISCVSTATE_INIT_REGX2);
}break;
case RISCVSTATE_INIT_REGX2: {
RISCV_SETREG(2, RAMSIZE * 4 - 16);
vput(state, RISCVSTATE_READ_INST);
}break;
case RISCVSTATE_READ_INST: {
vput(state, RISCVSTATE_READ_RS1);
}break;
case RISCVSTATE_READ_RS1: {
vput(state, RISCVSTATE_READ_RS2);
}break;
case RISCVSTATE_READ_RS2: {
vput(state, RISCVSTATE_EXEC_INST);
}break;
case RISCVSTATE_WRITE_RD: {
vput(state, RISCVSTATE_READ_INST);
}break;
case RISCVSTATE_EXEC_INST: {
vput(state, RISCVSTATE_WRITE_RD);
CALL_FUNC(riscv_core_exec_inst);
}break;
case RISCVSTATE_WAIT_LD: {
RISCV_SETREG(vget(readreg), vget(bReadData));
vput(state, RISCVSTATE_WRITE_RD);
}break;
case RISCVSTATE_WAIT_ST: {
vput(state, RISCVSTATE_READ_INST);
}
else if (state == RISCVSTATE_WAIT_LD){
CALL_FUNC(riscv_core_ld_done_inst);
}
}
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_core_deinit, "") {
if (pobj->ram != NULL)
free(pobj->ram);
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_core_setup, "") {
if (pobj->dstreg != 0) {
pobj->regs[pobj->dstreg] = pobj->dstvalue;
}
pobj->dstreg = 0;
if ( (pobj->ramdstaddr != 0) && (pobj->ramdstwidth > 0) && (pobj->ramdstaddr + pobj->ramdstwidth < pobj->ramsize)) {
memcpy(((char *)pobj->ram)+ pobj->ramdstaddr, &pobj->ramdstvalue, pobj->ramdstwidth);
}
pobj->ramdstaddr = 0;
} END_DEFINE_FUNC
int loadExecImage(unsigned char* data, int maxlen)
{
unsigned int addr;
FILE* pFile = fopen(DATADIR"test_code/test.cod", "rt");
if (pFile == NULL) {
printf("File %s can not open\n", DATADIR"test_code/test.bin");
exit(-1);
}
addr = 0;
while (!feof(pFile)) {
char line[256];
fgets(line, 256, pFile);
if (strlen(line) < 2)
break;
if (line[0] == '@') {
sscanf(line+1, "%08x", &addr);
}
else {
int len;
if (addr >= maxlen - 16) {
printf("loadExecImage failed, address [%08x] overflow\n", addr);
exit(-5);
}
len = sscanf(line, "%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X",
data + addr + 0,
data + addr + 1,
data + addr + 2,
data + addr + 3,
data + addr + 4,
data + addr + 5,
data + addr + 6,
data + addr + 7,
data + addr + 8,
data + addr + 9,
data + addr + 10,
data + addr + 11,
data + addr + 12,
data + addr + 13,
data + addr + 14,
data + addr + 15
);
addr += len;
}
}
fclose(pFile);
}
MODULE_INIT(riscv_core)
int i;
pobj->ramsize = 8 * 1024;
pobj->ram = malloc(pobj->ramsize);
loadExecImage(pobj->ram, pobj->ramsize);
pobj->ramdstaddr = 0;
pobj->dstreg = 0;
pobj->regs[1] = 0x8c; /* 入口地址 */
pobj->regs[2] = pobj->ramsize - 16;
pobj->regs[0] = 0; /* 硬连接到0上 */
PORT_IN(wClk, 1);
PORT_IN(nwReset, 1);
GPORT_OUT(wWrite, 1, riscv_core_rw_sig);
GPORT_OUT(bWriteAddr, 32, riscv_core_rw_sig);
GPORT_OUT(bWriteData, 32, riscv_core_rw_sig);
GPORT_OUT(bWriteMask, 4, riscv_core_rw_sig);
GPORT_OUT(wRead, 1, riscv_core_rw_sig);
GPORT_OUT(bReadAddr, 32, riscv_core_rw_sig);
GPORT_OUT(wWrite, 1, riscv_core_wr_sig);
GPORT_OUT(bWriteAddr, 32, riscv_core_wr_sig);
GPORT_OUT(bWriteData, 32, riscv_core_wr_sig);
GPORT_OUT(bWriteMask, 4, riscv_core_wr_sig);
GPORT_OUT(wRead, 1, riscv_core_read_sig);
GPORT_OUT(bReadAddr, 32, riscv_core_read_sig);
PORT_IN(bReadData, 32);
GPORT_OUT(regno, 5, riscv_core_reg_wr_sig);
GPORT_OUT(regena, 4, riscv_core_reg_wr_sig);
GPORT_OUT(regwrdata, 31, riscv_core_reg_wr_sig);
GPORT_OUT(regwren, 1, riscv_core_reg_wr_sig);
PORT_IN(regrddata, 32);
REG(pc, 32);
GWIRE(instr, 32, riscv_core_instr);
REG(instr, 32);
REG(rs1, 32);
REG(rs2, 32);
REG(write, 1);
REG(writeaddr, 32);
REG(writedata, 32);
REG(read, 1);
REG(readaddr, 32);
REG(writemask, 4);
REG(readreg, 5);
REG(state, 10);
GWIRE(x1, 32, riscv_core_register);
GWIRE(x2, 32, riscv_core_register);
GWIRE(x3, 32, riscv_core_register);
GWIRE(x4, 32, riscv_core_register);
GWIRE(x5, 32, riscv_core_register);
GWIRE(x6, 32, riscv_core_register);
GWIRE(x7, 32, riscv_core_register);
GWIRE(x8, 32, riscv_core_register);
GWIRE(x9, 32, riscv_core_register);
GWIRE(x10, 32, riscv_core_register);
GWIRE(x11, 32, riscv_core_register);
GWIRE(x12, 32, riscv_core_register);
GWIRE(x13, 32, riscv_core_register);
GWIRE(x14, 32, riscv_core_register);
GWIRE(x15, 32, riscv_core_register);
GWIRE(x16, 32, riscv_core_register);
GWIRE(x17, 32, riscv_core_register);
GWIRE(x18, 32, riscv_core_register);
GWIRE(x19, 32, riscv_core_register);
GWIRE(x20, 32, riscv_core_register);
GWIRE(x21, 32, riscv_core_register);
GWIRE(x22, 32, riscv_core_register);
GWIRE(x23, 32, riscv_core_register);
GWIRE(x24, 32, riscv_core_register);
GWIRE(x25, 32, riscv_core_register);
GWIRE(x26, 32, riscv_core_register);
GWIRE(x27, 32, riscv_core_register);
GWIRE(x28, 32, riscv_core_register);
GWIRE(x29, 32, riscv_core_register);
GWIRE(x30, 32, riscv_core_register);
GWIRE(x31, 32, riscv_core_register);
REG(state, 4);
CLKTICK_FUNC(riscv_core_clktick);
SETUP_FUNC(riscv_core_setup);
DEINIT_FUNC(riscv_core_deinit);
END_MODULE_INIT(riscv_core)
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_ram8k.c
浏览文件 @ 55792653
......@@ -42,10 +42,8 @@
#include "stdarg.h"
#include "bignumber.h"
#include "hdl4secell.h"
#define IMPLEMENT_GUID
#include "hdl4se_riscv.h"
#undef IMPLEMENT_GUID
#ifdef WIN32
#define DATADIR "d:/gitwork/hdl4se/examples/hdl4se_riscv/"
......@@ -60,7 +58,7 @@
#define M_ID(id) riscv_ram##id
/*
跟alter生成的端口一致
跟altera生成的端口一致
module ram8kb (
address,
byteena,
......@@ -87,8 +85,6 @@ module ram8kb (
endmodule
*/
#define RAMSIZE 2048
IDLIST
VID(address),
VID(byteena),
......@@ -143,7 +139,7 @@ DEFINE_FUNC(riscv_ram_setup, "") {
pobj->ramwren = 0;
} END_DEFINE_FUNC
int loadExecImage(unsigned char* data, int maxlen)
static int loadExecImage(unsigned char* data, int maxlen)
{
unsigned int addr;
FILE* pFile = fopen(DATADIR"test_code/test.cod", "rt");
......@@ -167,22 +163,22 @@ int loadExecImage(unsigned char* data, int maxlen)
exit(-5);
}
len = sscanf(line, "%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X",
data + addr + 0,
data + addr + 1,
data + addr + 2,
data + addr + 3,
data + addr + 4,
data + addr + 5,
data + addr + 6,
data + addr + 7,
data + addr + 8,
data + addr + 9,
data + addr + 10,
data + addr + 11,
data + addr + 12,
data + addr + 13,
data + addr + 14,
data + addr + 15
(unsigned int*)(data + addr + 0),
(unsigned int*)(data + addr + 1),
(unsigned int*)(data + addr + 2),
(unsigned int*)(data + addr + 3),
(unsigned int*)(data + addr + 4),
(unsigned int*)(data + addr + 5),
(unsigned int*)(data + addr + 6),
(unsigned int*)(data + addr + 7),
(unsigned int*)(data + addr + 8),
(unsigned int*)(data + addr + 9),
(unsigned int*)(data + addr + 10),
(unsigned int*)(data + addr + 11),
(unsigned int*)(data + addr + 12),
(unsigned int*)(data + addr + 13),
(unsigned int*)(data + addr + 14),
(unsigned int*)(data + addr + 15)
);
addr += len;
}
......
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_regfile.c 0 → 100644
浏览文件 @ 55792653
/*
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
** derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* hdl4se_riscv_regfile.c
202108251540: rxh, initial version
*/
#include "stdlib.h"
#include "stdio.h"
#include "object.h"
#include "dlist.h"
#include "string.h"
#include "stdarg.h"
#include "bignumber.h"
#include "hdl4secell.h"
#include "hdl4se_riscv.h"
#define riscv_regfile_MODULE_VERSION_STRING "0.4.0-20210825.1540 RISCV REGFILE cell"
#define riscv_regfile_MODULE_CLSID CLSID_HDL4SE_RISCV_REGFILE
#define M_ID(id) riscv_regfile##id
/*
跟altera生成的端口一致
module regfile (
address,
byteena,
clock,
data,
wren,
q);
input [4:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
*/
IDLIST
VID(address),
VID(byteena),
VID(clock),
VID(data),
VID(wren),
VID(q),
VID(lastaddr),
VID(x1),
VID(x2),
VID(x3),
VID(x4),
VID(x5),
VID(x6),
VID(x7),
VID(x8),
VID(x9),
VID(x10),
VID(x11),
VID(x12),
VID(x13),
VID(x14),
VID(x15),
VID(x16),
VID(x17),
VID(x18),
VID(x19),
VID(x20),
VID(x21),
VID(x22),
VID(x23),
VID(x24),
VID(x25),
VID(x26),
VID(x27),
VID(x28),
VID(x29),
VID(x30),
VID(x31),
END_IDLIST
#define REGCOUNT 32
MODULE_DECLARE(riscv_regfile)
unsigned int ram[REGCOUNT];
unsigned int ramaddr;
unsigned int ramwrdata;
unsigned int ramwren;
unsigned int rambyteena;
END_MODULE_DECLARE(riscv_regfile)
DEFINE_FUNC(riscv_regfile_gen_q, "address, byteena, data, wren, lastaddr") {
unsigned int lastaddr;
lastaddr = vget(lastaddr);
if (lastaddr == 0)
vput(q, 0);
else
if (lastaddr < REGCOUNT)
vput(q, pobj->ram[vget(lastaddr)]);
else {
printf("We have %d registers only, but you want to read %d\n", REGCOUNT, lastaddr);
}
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_regfile_clktick, "") {
pobj->ramwren = vget(wren);
pobj->ramwrdata = vget(data);
pobj->rambyteena = vget(byteena);
pobj->ramaddr = vget(address);
vput(lastaddr, vget(address));
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_regfile_setup, "") {
if (pobj->ramwren) {
unsigned int mask =
(pobj->rambyteena & 1 ? 0x000000ff : 0)
| (pobj->rambyteena & 2 ? 0x0000ff00 : 0)
| (pobj->rambyteena & 4 ? 0x00ff0000 : 0)
| (pobj->rambyteena & 8 ? 0xff000000 : 0);
pobj->ram[pobj->ramaddr] = (pobj->ram[pobj->ramaddr] & (~mask))
| (pobj->ramwrdata & mask);
}
pobj->ramwren = 0;
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_regfile_register, "wren, data, byteena, address") {
int i;
for (i = 1; i < 32; i++)
vput_idx(VID(x1) + i - 1, pobj->ram[i]);
} END_DEFINE_FUNC
MODULE_INIT(riscv_regfile)
pobj->ram[0] = 0;
pobj->ram[1] = 0x8c;
pobj->ram[2] = RAMSIZE * 4-16;
pobj->ramwren = 0;
PORT_IN(clock, 1);
PORT_IN(wren, 1);
PORT_IN(address, 5);
PORT_IN(data, 32);
PORT_IN(byteena, 4);
GPORT_OUT(q, 32, riscv_regfile_gen_q);
REG(lastaddr, 5);
GWIRE(x1, 32, riscv_regfile_register);
GWIRE(x2, 32, riscv_regfile_register);
GWIRE(x3, 32, riscv_regfile_register);
GWIRE(x4, 32, riscv_regfile_register);
GWIRE(x5, 32, riscv_regfile_register);
GWIRE(x6, 32, riscv_regfile_register);
GWIRE(x7, 32, riscv_regfile_register);
GWIRE(x8, 32, riscv_regfile_register);
GWIRE(x9, 32, riscv_regfile_register);
GWIRE(x10, 32, riscv_regfile_register);
GWIRE(x11, 32, riscv_regfile_register);
GWIRE(x12, 32, riscv_regfile_register);
GWIRE(x13, 32, riscv_regfile_register);
GWIRE(x14, 32, riscv_regfile_register);
GWIRE(x15, 32, riscv_regfile_register);
GWIRE(x16, 32, riscv_regfile_register);
GWIRE(x17, 32, riscv_regfile_register);
GWIRE(x18, 32, riscv_regfile_register);
GWIRE(x19, 32, riscv_regfile_register);
GWIRE(x20, 32, riscv_regfile_register);
GWIRE(x21, 32, riscv_regfile_register);
GWIRE(x22, 32, riscv_regfile_register);
GWIRE(x23, 32, riscv_regfile_register);
GWIRE(x24, 32, riscv_regfile_register);
GWIRE(x25, 32, riscv_regfile_register);
GWIRE(x26, 32, riscv_regfile_register);
GWIRE(x27, 32, riscv_regfile_register);
GWIRE(x28, 32, riscv_regfile_register);
GWIRE(x29, 32, riscv_regfile_register);
GWIRE(x30, 32, riscv_regfile_register);
GWIRE(x31, 32, riscv_regfile_register);
CLKTICK_FUNC(riscv_regfile_clktick);
SETUP_FUNC(riscv_regfile_setup);
END_MODULE_INIT(riscv_regfile)
examples/hdl4se_riscv/hdl4se_riscv_sim/main.c
浏览文件 @ 55792653
......@@ -46,7 +46,7 @@ IHDL4SESimulator** sim;
IHDL4SEModuleVar* topmodule;
unsigned long long clocks = 0;
#define RECORDVCD 0
#define RECORDVCD 1
static int running = 1;
int StopRunning()
......@@ -93,6 +93,9 @@ int main(int argc, char* argv[])
vcdfile = hdl4sesimCreateVCDFile("riscv.vcd");
objectCall2(vcdfile, AddSignal, "/top/core", "pc");
objectCall2(vcdfile, AddSignal, "/top/core", "instr");
objectCall2(vcdfile, AddSignal, "/top/core", "state");
objectCall2(vcdfile, AddSignal, "/top/core", "wRead");
objectCall2(vcdfile, AddSignal, "/top/core", "bReadData");
objectCall2(vcdfile, AddSignal, "/top/core", "wWrite");
objectCall2(vcdfile, AddSignal, "/top/core", "bWriteAddr");
objectCall2(vcdfile, AddSignal, "/top/core", "bWriteData");
......
examples/hdl4se_riscv/hdl4se_riscv_sim/main_v2.c 0 → 100644
浏览文件 @ 55792653
/*
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
** derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "stdlib.h"
#include "stdio.h"
#include "string.h"
#include "object.h"
#include "bignumber.h"
#include "hdl4secell.h"
#include "hdl4sesim.h"
#include "hdl4sevcdfile.h"
#include "counter.h"
#include "digitled.h"
#include "threadlock.h"
IHDL4SESimulator** sim;
IHDL4SEModuleVar* topmodule;
unsigned long long clocks = 0;
#define RECORDVCD 1
static int running = 1;
int StopRunning()
{
running = 0;
return 0;
}
IHDL4SEModuleVar* hdl4seCreate_main(IHDL4SEModuleVar* parent, const char* instanceparam, const char* name);
extern int (*A_u_t_o_registor_digitled)();
extern int (*A_u_t_o_registor_riscv_core)();
extern int (*A_u_t_o_registor_riscv_ram)();
extern int (*A_u_t_o_registor_riscv_regfile)();
FILE* recordfile;
THREADLOCK recordfilelock;
FILE* recordfileGet()
{
threadlockLock(recordfilelock);
return recordfile;
}
void recordfileRelease()
{
threadlockUnlock(recordfilelock);
}
int main(int argc, char* argv[])
{
int i;
int width;
time_t starttime;
time_t lasttime;
IHDL4SEWaveOutput** vcdfile;
A_u_t_o_registor_digitled();
A_u_t_o_registor_riscv_core();
A_u_t_o_registor_riscv_ram();
A_u_t_o_registor_riscv_regfile();
recordfile = fopen("d:/gitwork/recordfile.txt", "w");
recordfilelock = threadlockCreate();
sim = hdl4sesimCreateSimulator();
topmodule = hdl4seCreate_main(NULL, "", "top");
objectCall1(sim, SetTopModule, topmodule);
objectCall1(sim, SetReset, 0);
#if RECORDVCD
vcdfile = hdl4sesimCreateVCDFile("riscv_v2.vcd");
objectCall2(vcdfile, AddSignal, "/top/core", "pc");
objectCall2(vcdfile, AddSignal, "/top/core", "instr");
objectCall2(vcdfile, AddSignal, "/top/core", "state");
objectCall2(vcdfile, AddSignal, "/top/core", "wRead");
objectCall2(vcdfile, AddSignal, "/top/core", "bReadData");
objectCall2(vcdfile, AddSignal, "/top/core", "wWrite");
objectCall2(vcdfile, AddSignal, "/top/core", "bWriteAddr");
objectCall2(vcdfile, AddSignal, "/top/core", "bWriteData");
objectCall2(vcdfile, AddSignal, "/top/regs", "x1");
objectCall2(vcdfile, AddSignal, "/top/regs", "x2");
objectCall2(vcdfile, AddSignal, "/top/regs", "x3");
objectCall2(vcdfile, AddSignal, "/top/regs", "x4");
objectCall2(vcdfile, AddSignal, "/top/regs", "x5");
objectCall2(vcdfile, AddSignal, "/top/regs", "x6");
objectCall2(vcdfile, AddSignal, "/top/regs", "x7");
objectCall2(vcdfile, AddSignal, "/top/regs", "x8");
objectCall2(vcdfile, AddSignal, "/top/regs", "x9");
objectCall2(vcdfile, AddSignal, "/top/regs", "x10");
objectCall2(vcdfile, AddSignal, "/top/regs", "x11");
objectCall2(vcdfile, AddSignal, "/top/regs", "x12");
objectCall2(vcdfile, AddSignal, "/top/regs", "x13");
objectCall2(vcdfile, AddSignal, "/top/regs", "x14");
objectCall2(vcdfile, AddSignal, "/top/regs", "x15");
objectCall2(vcdfile, AddSignal, "/top/regs", "x16");
objectCall2(vcdfile, AddSignal, "/top/regs", "x17");
objectCall2(vcdfile, AddSignal, "/top/regs", "x18");
objectCall2(vcdfile, AddSignal, "/top/regs", "x19");
objectCall2(vcdfile, AddSignal, "/top/regs", "x20");
objectCall2(vcdfile, AddSignal, "/top/regs", "x21");
objectCall2(vcdfile, AddSignal, "/top/regs", "x22");
objectCall2(vcdfile, AddSignal, "/top/regs", "x23");
objectCall2(vcdfile, AddSignal, "/top/regs", "x24");
objectCall2(vcdfile, AddSignal, "/top/regs", "x25");
objectCall2(vcdfile, AddSignal, "/top/regs", "x26");
objectCall2(vcdfile, AddSignal, "/top/regs", "x27");
objectCall2(vcdfile, AddSignal, "/top/regs", "x28");
objectCall2(vcdfile, AddSignal, "/top/regs", "x29");
objectCall2(vcdfile, AddSignal, "/top/regs", "x30");
objectCall2(vcdfile, AddSignal, "/top/regs", "x31");
objectCall1(vcdfile, SetTopModule, topmodule);
objectCall0(vcdfile, StartRecord);
#endif
objectPrintInfo(stdout, fprintf);
lasttime = starttime = time(NULL);
clocks = 0;
do {
objectCall0(sim, ClkTick);
#if RECORDVCD
objectCall1(vcdfile, ClkTick, clocks);
#endif
objectCall0(sim, Setup);
clocks++;
if (clocks == 4)
objectCall1(sim, SetReset, 1);
if ((clocks & 0xFFFF) == 0) {
time_t thistime = time(NULL);
printf("clocks: %lld, TSPD=%lfcps, LSPD=%lfcps\n",
clocks,
(double)clocks / (double)(thistime - starttime),
4096.0 * 16 / (double)(thistime - lasttime));
lasttime = time(NULL);
}
} while (running);
#if RECORDVCD
objectCall0(vcdfile, StopRecord);
objectRelease(vcdfile);
#endif
return 0;
}
examples/hdl4se_riscv/hdl4se_riscv_sim/riscv_sim_main_v2.c 0 → 100644
浏览文件 @ 55792653
/*
**HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
** derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Created by HDL4SE @ Wed Aug 25 16:02:24 2021
* Don't edit it.
*/
#include "stdlib.h"
#include "stdio.h"
#include "string.h"
#include "object.h"
#include "dlist.h"
#include "bignumber.h"
#include "hdl4secell.h"
#include "conststring.h"
#include "verilog_parsetree.h"
/* Module top */
#define M_ID(id) top##id
IDLIST
VID(wClk),
VID(nwReset),
VID(wRead_out),
VID(bReadAddr_out),
VID(regrddata),
VID(ram_dot_byteena), /* port:ram(ram8kb).byteena, 1 */
VID(bReadDataRam),
VID(bReadDataKey),
VID(wWrite),
VID(bWriteAddr),
VID(bWriteData),
VID(bWriteMask),
VID(wRead),
VID(bReadAddr),
VID(regno),
VID(regena),
VID(regwrdata),
VID(regwren),
VID(bReadData),
VID(ramaddr),
END_IDLIST
GEN_MODULE_DECLARE
END_GEN_MODULE_DECLARE
DEFINE_FUNC(top_gen_ram_dot_byteena, "bWriteMask, ") { /* port:ram(ram8kb).byteena, 1 */
vputs(ram_dot_byteena, ~(vgets(bWriteMask)));
} END_DEFINE_FUNC
DEFINE_FUNC(top_gen_bReadData, "bReadAddr_out, bReadDataKey, bReadDataRam, ") {
vputs(bReadData, (((vgets(bReadAddr_out)) & (0xffffff00)) == (0xf0000000))?(vgets(bReadDataKey)):((((vgets(bReadAddr_out)) & (0xffffc000)) == (0))?(vgets(bReadDataRam)):(0)));
} END_DEFINE_FUNC
DEFINE_FUNC(top_gen_ramaddr, "wWrite, bWriteAddr, bReadAddr, ") {
vputs(ramaddr, (vgets(wWrite))?((vget(bWriteAddr) >> 2) & 0x7ff):((vget(bReadAddr) >> 2) & 0x7ff));
} END_DEFINE_FUNC
GEN_MODULE_INIT
PORT_IN (wClk, 1);
PORT_IN (nwReset, 1);
WIRE(bReadData, 32);
WIRE(ramaddr, 11);
WIRE(wRead_out, 1);
WIRE(bReadAddr_out, 32);
WIRE(regrddata, 32);
WIRE(ram_dot_byteena, 1);
WIRE(bReadDataRam, 32);
WIRE(bReadDataKey, 32);
WIRE(wWrite, 1);
WIRE(bWriteAddr, 32);
WIRE(bWriteData, 32);
WIRE(bWriteMask, 4);
WIRE(wRead, 1);
WIRE(bReadAddr, 32);
WIRE(regno, 5);
WIRE(regena, 4);
WIRE(regwrdata, 32);
WIRE(regwren, 1);
CELL_INST("76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", /* hdl4se_reg */
"readcmd",
"32'h1",
"wClk, wRead, wRead_out");
CELL_INST("76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", /* hdl4se_reg */
"readaddr",
"32'h20",
"wClk, bReadAddr, bReadAddr_out");
CELL_INST("2E577C6B-2FF1-425E-90B3-947EB523B863", /* regfile */
"regs",
"",
"regno, regena, wClk, regwrdata, regwren, regrddata");
CELL_INST("EE3409B2-6D04-42B3-A44D-7F2444DDC00D", /* ram8kb */
"ram",
"",
"ramaddr, ram_dot_byteena, wClk, bWriteData, wWrite, bReadDataRam");
CELL_INST("2925e2cf-dd49-4155-b31d-41d48f0f98dc", /* digitled */
"led",
"",
"wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadDataKey");
CELL_INST("638E8BC3-B0E0-41DC-9EDD-D35A39FD8051", /* riscv_core */
"core",
"",
"wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData"
", regno, regena, regwrdata, regwren, regrddata");
GEN_FUNC("ram_dot_byteena", top_gen_ram_dot_byteena);
GEN_FUNC("bReadData", top_gen_bReadData);
GEN_FUNC("ramaddr", top_gen_ramaddr);
END_GEN_MODULE_INIT
#undef M_ID
IHDL4SEModuleVar* hdl4seCreate_main(IHDL4SEModuleVar * parent, const char* instanceparam, const char* name)
{
return TOP_MODULE(top);
}
examples/hdl4se_riscv/verilog/riscv_core.v
浏览文件 @ 55792653
......@@ -38,11 +38,17 @@
*)
module riscv_core(
input wClk, nwReset,
output wWrite,
output [31:0] bWriteAddr,
output [31:0] bWriteData,
output [3:0] bWriteMask,
output wRead,
output [31:0] bReadAddr,
input [31:0] bReadData);
output wWrite,
output [31:0] bWriteAddr,
output [31:0] bWriteData,
output [3:0] bWriteMask,
output wRead,
output [31:0] bReadAddr,
input [31:0] bReadData,
output [4:0] regno,
output [3:0] regena,
output [31:0] regwrdata,
output regwren,
input regrddata
);
endmodule
\ No newline at end of file
examples/hdl4se_riscv/verilog/riscv_sim.v
浏览文件 @ 55792653
......@@ -54,7 +54,7 @@ module top(input wClk, nwReset);
wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData;
wire [3:0] bWriteMask;
digitled led(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData);
digitled led(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData);
riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData);
endmodule
examples/hdl4se_riscv/verilog/riscv_sim_dump_v2.v 0 → 100644
浏览文件 @ 55792653
(*
HDL4SE = "LCOM",
CLSID = "638E8BC3-B0E0-41DC-9EDD-D35A39FD8051",
softmodule = "hdl4se"
*)
module riscv_core
(
input wClk,
input nwReset,
output wWrite,
output [32'h1f:32'h0] bWriteAddr,
output [32'h1f:32'h0] bWriteData,
output [32'h3:32'h0] bWriteMask,
output wRead,
output [32'h1f:32'h0] bReadAddr,
input [32'h1f:32'h0] bReadData,
output [32'h4:32'h0] regno,
output [32'h3:32'h0] regena,
output [32'h1f:32'h0] regwrdata,
output regwren,
input regrddata
)
;
endmodule
(*
HDL4SE = "LCOM",
CLSID = "2925e2cf-dd49-4155-b31d-41d48f0f98dc",
softmodule = "hdl4se"
*)
module digitled
(
input wClk,
input nwReset,
input wWrite,
input [32'h1f:32'h0] bWriteAddr,
input [32'h1f:32'h0] bWriteData,
input [32'h3:32'h0] bWriteMask,
input wRead,
input [32'h1f:32'h0] bReadAddr,
output [32'h1f:32'h0] bReadData
)
;
endmodule
(*
HDL4SE = "LCOM",
CLSID = "EE3409B2-6D04-42B3-A44D-7F2444DDC00D",
softmodule = "hdl4se"
*)
module ram8kb
(
input [32'ha:32'h0] address,
input [32'h3:32'h0] byteena,
input clock,
input [32'h1f:32'h0] data,
input wren,
output [32'h1f:32'h0] q
)
;
endmodule
(*
HDL4SE = "LCOM",
CLSID = "2E577C6B-2FF1-425E-90B3-947EB523B863",
softmodule = "hdl4se"
*)
module regfile
(
input [32'h4:32'h0] address,
input [32'h3:32'h0] byteena,
input clock,
input [32'h1f:32'h0] data,
input wren,
output [32'h1f:32'h0] q
)
;
endmodule
(*
HDL4SE = "LCOM",
CLSID = "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2",
softmodule = "hdl4se"
*)
module hdl4se_reg
#(
parameter WIDTH = 32'h8
)
(
input wClk,
input [(WIDTH-32'h1):32'h0] wirein,
output [(WIDTH-32'h1):32'h0] wireout
)
;
wire [(WIDTH-32'h1):32'h0] wirein;
always @(posedge wClk)
wireout <= wirein;
endmodule
module top
(
input wClk,
input nwReset
)
;
wire wWrite;
wire wRead;
wire [32'h1f:32'h0] bWriteAddr;
wire [32'h1f:32'h0] bWriteData;
wire [32'h1f:32'h0] bReadAddr;
wire [32'h1f:32'h0] bReadData;
wire [32'h1f:32'h0] bReadDataRam;
wire [32'h1f:32'h0] bReadDataKey;
wire [32'h3:32'h0] bWriteMask;
wire wRead_out;
wire [32'h1f:32'h0] bReadAddr_out;
wire [32'ha:32'h0] ramaddr;
wire [32'h4:32'h0] regno;
wire [32'h3:32'h0] regena;
wire [32'h1f:32'h0] regwrdata;
wire regwren;
wire [32'h1f:32'h0] regrddata;
assign bReadData = ((((bReadAddr_out&32'hffffff00)==32'hf0000000))?(bReadDataKey):(((((bReadAddr_out&32'hffffc000)==32'h0))?(bReadDataRam):(32'h0))));
assign ramaddr = ((wWrite)?(bWriteAddr [12:2] ):(bReadAddr [12:2] ));
hdl4se_reg #( 32'h1 ) readcmd( wClk, wRead, wRead_out );
hdl4se_reg #( 32'h20 ) readaddr( wClk, bReadAddr, bReadAddr_out );
regfile regs( regno, regena, wClk, regwrdata, regwren, regrddata
);
ram8kb ram( ramaddr, (~(bWriteMask)), wClk, bWriteData, wWrite, bReadDataRam
);
digitled led( wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask
, wRead, bReadAddr, bReadDataKey );
riscv_core core( wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask
, wRead, bReadAddr, bReadData, regno, regena
, regwrdata, regwren, regrddata );
endmodule
examples/hdl4se_riscv/verilog/riscv_sim_v2.v 0 → 100644
浏览文件 @ 55792653
/*
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
** derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/
/* riscv-sim_v2.v */
`include "riscv_core.v"
(*
HDL4SE="LCOM",
CLSID="2925e2cf-dd49-4155-b31d-41d48f0f98dc",
softmodule="hdl4se"
*)
module digitled(
input wClk, nwReset,
input wWrite,
input [31:0] bWriteAddr,
input [31:0] bWriteData,
input [3:0] bWriteMask,
input wRead,
input [31:0] bReadAddr,
output [31:0] bReadData);
endmodule
(*
HDL4SE="LCOM",
CLSID="EE3409B2-6D04-42B3-A44D-7F2444DDC00D",
softmodule="hdl4se"
*)
module ram8kb (
input [10:0] address,
input [3:0] byteena,
input clock,
input [31:0] data,
input wren,
output [31:0] q);
endmodule
(*
HDL4SE="LCOM",
CLSID="2E577C6B-2FF1-425E-90B3-947EB523B863",
softmodule="hdl4se"
*)
module regfile (
input [4:0] address,
input [3:0] byteena,
input clock,
input [31:0] data,
input wren,
output [31:0] q);
endmodule
(*
HDL4SE="LCOM",
CLSID="76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2",
softmodule="hdl4se"
*)
module hdl4se_reg
#(parameter WIDTH=8)
(
input wClk,
input [WIDTH-1:0] wirein,
output [WIDTH-1:0] wireout
);
wire [WIDTH-1:0] wirein;
reg [WIDTH-1:0] wireout;
always @(posedge wClk) wireout <= wirein;
endmodule
module top(input wClk, nwReset);
wire wWrite, wRead;
wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey;
wire [3:0] bWriteMask;
wire wRead_out;
wire [31:0] bReadAddr_out;
hdl4se_reg #(1) readcmd(wClk, wRead, wRead_out);
hdl4se_reg #(32) readaddr(wClk, bReadAddr, bReadAddr_out);
assign bReadData =
((bReadAddr_out & 32'hffffff00) == 32'hf0000000) ? bReadDataKey : (
((bReadAddr_out & 32'hffffc000) == 32'h00000000) ? bReadDataRam : (0)
);
wire [10:0] ramaddr;
assign ramaddr = wWrite?bWriteAddr[12:2]:bReadAddr[12:2];
wire [4:0] regno;
wire [3:0] regena;
wire [31:0] regwrdata;
wire regwren;
wire [31:0] regrddata;
regfile regs(regno, regena, wClk, regwrdata, regwren, regrddata);
ram8kb ram(ramaddr, ~bWriteMask, wClk, bWriteData, wWrite, bReadDataRam);
digitled led(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadDataKey);
riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData,
regno, regena, regwrdata, regwren, regrddata);
endmodule
hdl4secell/src/hdl4se_ram2p.c
浏览文件 @ 55792653
......@@ -84,7 +84,7 @@ MODULE_DECLARE(hdl4se_ram2p)
END_MODULE_DECLARE(hdl4se_ram2p)
DEFINE_FUNC(hdl4se_ram2p_do_Generate_ReadData, "bReadAddr_reg") {
unsigned int readaddr = VREAD_U32(bReadAddr_reg);
unsigned int readaddr = vget(bReadAddr_reg);
if (readaddr < pobj->wordcount) {
var dst = Var(bReadData);
unsigned int j;
......@@ -99,7 +99,7 @@ DEFINE_FUNC(hdl4se_ram2p_do_Store_bReadAddr, "bReadAddr") {
} END_DEFINE_FUNC
DEFINE_FUNC(hdl4se_ram2p_do_Generate_ReadData2, "bReadAddr2_reg") {
unsigned int readaddr = VREAD_U32(bReadAddr2_reg);
unsigned int readaddr = vget(bReadAddr2_reg);
if (readaddr < pobj->wordcount) {
var dst = Var(bReadData2);
unsigned int j;
......@@ -117,9 +117,9 @@ DEFINE_FUNC(hdl4se_ram2p_do_Store_bReadAddr2, "bReadAddr2") {
DEFINE_FUNC(hdl4se_ram2p_do_Generate_ClkTick, "") {
unsigned int write;
unsigned int addr;
write = VREAD_U32(wWrite);
write = vget(wWrite);
if (write) {
addr = VREAD_U32(bWriteAddr);
addr = vget(bWriteAddr);
if (addr < pobj->wordcount) {
unsigned int j;
var wd = Var(bWriteData);
......@@ -128,9 +128,9 @@ DEFINE_FUNC(hdl4se_ram2p_do_Generate_ClkTick, "") {
}
}
}
write = VREAD_U32(wWrite2);
write = vget(wWrite2);
if (write) {
addr = VREAD_U32(bWriteAddr2);
addr = vget(bWriteAddr2);
if (addr < pobj->wordcount) {
unsigned int j;
var wd = Var(bWriteData2);
......
parser/verilog_expr.c
浏览文件 @ 55792653
......@@ -1966,9 +1966,9 @@ const char * verilogparseGenExprStr(HOBJECT expr, HOBJECT module)
return hdl4se_parse_logbuf();
} else {
if (width <= 32)
sprintf(hdl4se_parse_logbuf(), "VREAD_S32(%s)", select->name->string);
sprintf(hdl4se_parse_logbuf(), "vgets(%s)", select->name->string);
else
sprintf(hdl4se_parse_logbuf(), "VREAD_U64(%s)", select->name->string);
sprintf(hdl4se_parse_logbuf(), "vget64(%s)", select->name->string);
return hdl4se_parse_logbuf();
}
}
......@@ -1978,9 +1978,9 @@ const char * verilogparseGenExprStr(HOBJECT expr, HOBJECT module)
sprintf(hdl4se_parse_logbuf(), "(pobj->%s >> (%s)) & 1", select->name->string, msb);
} else {
if (width <= 32)
sprintf(hdl4se_parse_logbuf(), "(VREAD_U32(%s) >> (%s)) & 1", select->name->string, msb);
sprintf(hdl4se_parse_logbuf(), "(vget(%s) >> (%s)) & 1", select->name->string, msb);
else
sprintf(hdl4se_parse_logbuf(), "(VREAD_U64(%s) >> (%s)) & 1", select->name->string, msb);
sprintf(hdl4se_parse_logbuf(), "(vget64(%s) >> (%s)) & 1", select->name->string, msb);
}
free(msb);
return hdl4se_parse_logbuf();
......@@ -2001,9 +2001,9 @@ const char * verilogparseGenExprStr(HOBJECT expr, HOBJECT module)
}
else {
if (width <= 32)
sprintf(hdl4se_parse_logbuf(), "(VREAD_U32(%s) >> %d) & 0x%x", select->name->string, v_lsb, (0xffffffff >> (32 - (v_msb - v_lsb + 1))));
sprintf(hdl4se_parse_logbuf(), "(vget(%s) >> %d) & 0x%x", select->name->string, v_lsb, (0xffffffff >> (32 - (v_msb - v_lsb + 1))));
else
sprintf(hdl4se_parse_logbuf(), "(VREAD_U64(%s) >> %d) & 0x%llxllu", select->name->string, v_lsb, (0xffffffffffffffffllu >> (64 - (v_msb - v_lsb + 1))));
sprintf(hdl4se_parse_logbuf(), "(vget64(%s) >> %d) & 0x%llxllu", select->name->string, v_lsb, (0xffffffffffffffffllu >> (64 - (v_msb - v_lsb + 1))));
}
}
else {
......@@ -2014,9 +2014,9 @@ const char * verilogparseGenExprStr(HOBJECT expr, HOBJECT module)
}
else {
if (width <= 32)
sprintf(hdl4se_parse_logbuf(), "(VREAD_U32(%s) >> (%s)) & (0xffffffff >> (32 - ((%s)-(%s) + 1))) ", select->name->string, lsb, msb, lsb);
sprintf(hdl4se_parse_logbuf(), "(vget(%s) >> (%s)) & (0xffffffff >> (32 - ((%s)-(%s) + 1))) ", select->name->string, lsb, msb, lsb);
else
sprintf(hdl4se_parse_logbuf(), "(VREAD_U64(%s) >> (%s)) & (0xffffffffffffffffllu >> (64 - ((%s)-(%s) + 1))) ", select->name->string, lsb, msb, lsb);
sprintf(hdl4se_parse_logbuf(), "(vget64(%s) >> (%s)) & (0xffffffffffffffffllu >> (64 - ((%s)-(%s) + 1))) ", select->name->string, lsb, msb, lsb);
}
free(msb);
free(lsb);
......
parser/verilog_module.c
浏览文件 @ 55792653
......@@ -736,11 +736,11 @@ static int verilogmodule_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJE
exprstr = verilogparseGenExprStr(connect->expr0, pobj);
if (exprstr != NULL) {
if (width <= 32)
fprintf(pFile, "\tVWRITE_S32(%s_dot_%s, %s);\n",
fprintf(pFile, "\tvputs(%s_dot_%s, %s);\n",
moduleinst->instname->string, port->name->string,
exprstr);
else
fprintf(pFile, "\tVWRITE_U64(%s_dot_%s, %s);\n",
fprintf(pFile, "\tvput64(%s_dot_%s, %s);\n",
moduleinst->instname->string, port->name->string,
exprstr);
}
......@@ -782,9 +782,9 @@ static int verilogmodule_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJE
exprstr = verilogparseGenExprStr(assignment->expr, pobj);
if (exprstr != NULL) {
if (width <= 32)
fprintf(pFile, "\tVWRITE_S32(%s, %s);\n", lvalue->name->string, exprstr);
fprintf(pFile, "\tvputs(%s, %s);\n", lvalue->name->string, exprstr);
else
fprintf(pFile, "\tVWRITE_U64(%s, %s);\n", lvalue->name->string, exprstr);
fprintf(pFile, "\tvput64(%s, %s);\n", lvalue->name->string, exprstr);
}
else {
exprstr = verilogparseGenExprStrVar(assignment->expr, pobj, "");
......
testparser/main.c
浏览文件 @ 55792653
......@@ -21,7 +21,7 @@ static char logbuf[64 * 1024];
#define GOOGLENET 0
#define TERRIS 0
#define COUNTER 0
#define RISCV 1
#define RISCV 2
#ifdef WIN32
#define WORKDIR "d:/gitwork"
......@@ -45,12 +45,17 @@ int main(int argc, char* argv[])
pCodeFile = fopen(WORKDIR"/hdl4se/examples/counter/src/counter_main.c", "w");
#endif
#if RISCV
#if RISCV == 1
objectCall2(p, SetFile, WORKDIR"/hdl4se/examples/hdl4se_riscv/verilog/riscv_sim.v", 0);
pDumpFile = fopen(WORKDIR"/hdl4se/examples/hdl4se_riscv/verilog/riscv_sim_dump.v", "w");
pCodeFile = fopen(WORKDIR"/hdl4se/examples/hdl4se_riscv/hdl4se_riscv_sim/riscv_sim_main.c", "w");
#endif
#if RISCV == 2
objectCall2(p, SetFile, WORKDIR"/hdl4se/examples/hdl4se_riscv/verilog/riscv_sim_v2.v", 0);
pDumpFile = fopen(WORKDIR"/hdl4se/examples/hdl4se_riscv/verilog/riscv_sim_dump_v2.v", "w");
pCodeFile = fopen(WORKDIR"/hdl4se/examples/hdl4se_riscv/hdl4se_riscv_sim/riscv_sim_main_v2.c", "w");
#endif
#if TERRIS
objectCall2(p, SetFile, WORKDIR"/hdl4se/examples/terris/verilog/terris_main.v", 0);
......
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