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提交 37264416 编写于 作者: 饶先宏's avatar 饶先宏
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202108280727

上级 c4750924
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examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_core_v2.c
浏览文件 @ 37264416
......@@ -70,16 +70,18 @@ IDLIST
VID(pc),
VID(instr),
VID(rs1),
VID(imm),
VID(rs2),
VID(write),
VID(writeaddr),
VID(writedata),
VID(writemask),
VID(readreg),
VID(state),
VID(imm),
VID(dstreg),
VID(dstvalue),
VID(ldaddr),
VID(divclk),
END_IDLIST
enum riscv_core_state {
......@@ -88,10 +90,12 @@ enum riscv_core_state {
RISCVSTATE_READ_INST,
RISCVSTATE_READ_RS1,
RISCVSTATE_READ_RS2,
RISCVSTATE_STORE_RS2,
RISCVSTATE_WRITE_RD,
RISCVSTATE_EXEC_INST,
RISCVSTATE_WAIT_LD,
RISCVSTATE_WAIT_ST,
RISCVSTATE_WAIT_DIV
};
MODULE_DECLARE(riscv_core)
......@@ -115,7 +119,7 @@ DEFINE_FUNC(riscv_core_wr_sig, "write, writeaddr, writedata, writemask") {
VAssign(bWriteMask, writemask);
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_core_read_sig, "state, pc, instr, bReadData, rs1") {
DEFINE_FUNC(riscv_core_read_sig, "state, pc, imm, instr, rs1") {
unsigned int state;
state = vget(state);
vput(wRead, 0);
......@@ -131,9 +135,8 @@ DEFINE_FUNC(riscv_core_read_sig, "state, pc, instr, bReadData, rs1") {
unsigned int imm;
unsigned int rs1;
unsigned int rdaddr;
imm = instr >> 20;
rs1 = vget(rs1);
imm = sign_expand(imm, 11);
imm = vget(imm);
rdaddr = rs1 + imm;
vput(wRead, 1);
vput(bReadAddr, rdaddr);
......@@ -141,7 +144,7 @@ DEFINE_FUNC(riscv_core_read_sig, "state, pc, instr, bReadData, rs1") {
}
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_core_gen_ldaddr, "state, pc, instr, rs1") {
DEFINE_FUNC(riscv_core_gen_ldaddr, "state, pc, instr, rs1, imm") {
unsigned int state;
state = vget(state);
if (state == RISCVSTATE_READ_INST) {
......@@ -155,9 +158,8 @@ DEFINE_FUNC(riscv_core_gen_ldaddr, "state, pc, instr, rs1") {
unsigned int imm;
unsigned int rs1;
unsigned int rdaddr;
imm = instr >> 20;
rs1 = vget(rs1);
imm = sign_expand(imm, 11);
imm = vget(imm);
rdaddr = rs1 + imm;
vput(ldaddr, rdaddr);
}
......@@ -386,7 +388,7 @@ DEFINE_FUNC(riscv_core_exec_inst, "") {
unsigned int pc = vget(pc);
unsigned int instr = vget(instr);
unsigned int rs1 = vget(rs1);
unsigned int rs2 = vget(regrddata);
unsigned int rs2 = vget(rs2);//vget(regrddata);
unsigned int opcode = instr & 0x7f;
if ( ((opcode & 0x3) != 3) || ( (opcode >> 2) & 0x7) == 0x7) {
printf("instruction format error, we support 32bit instruction only: pc=%08x: %x", pc, instr);
......@@ -412,7 +414,7 @@ DEFINE_FUNC(riscv_core_exec_inst, "") {
}
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_core_gen_dstreg, "state, instr, ldaddr, readreg, bReadData, pc, rs1, regrddata, imm") {
DEFINE_FUNC(riscv_core_gen_dstreg, "state, instr, ldaddr, readreg, bReadData, pc, rs1, rs2, imm") {
switch (vget(state)) {
case RISCVSTATE_INIT_REGX1: {
RISCV_SETDSTREG(1, 0x8c);
......@@ -488,7 +490,7 @@ DEFINE_FUNC(riscv_core_gen_dstreg, "state, instr, ldaddr, readreg, bReadData, pc
unsigned int pc = vget(pc);
unsigned int instr = vget(instr);
unsigned int rs1 = vget(rs1);
unsigned int rs2 = vget(regrddata);
unsigned int rs2 = vget(rs2);
unsigned int imm = vget(imm);
unsigned int opcode = instr & 0x7f;
unsigned int rd = (instr >> 7) & 0x1f;
......@@ -498,13 +500,8 @@ DEFINE_FUNC(riscv_core_gen_dstreg, "state, instr, ldaddr, readreg, bReadData, pc
case 0x05: RISCV_SETDSTREG(rd, imm + pc); break;
case 0x1b: RISCV_SETDSTREG(rd, pc + 4); break;
case 0x19: RISCV_SETDSTREG(rd, pc + 4); break;
case 0x18: RISCV_SETDSTREG(0, 0); break;
case 0x00: RISCV_SETDSTREG(0, 0); break;
case 0x08: RISCV_SETDSTREG(0, 0); break;
case 0x04: riscv_core_exec_alui_inst(pobj, pc, instr, rs1, rs2); break;
case 0x0c: riscv_core_exec_alu_inst(pobj, pc, instr, rs1, rs2); break;
case 0x03: RISCV_SETDSTREG(0, 0); break;
case 0x1c: RISCV_SETDSTREG(0, 0); break;
default: {
RISCV_SETDSTREG(0, 0);
}
......@@ -602,6 +599,9 @@ DEFINE_FUNC(riscv_core_gen_state, "state, instr, nwReset") {
vput(state, RISCVSTATE_READ_RS2);
}break;
case RISCVSTATE_READ_RS2: {
vput(state, RISCVSTATE_STORE_RS2);
}break;
case RISCVSTATE_STORE_RS2: {
vput(state, RISCVSTATE_EXEC_INST);
}break;
case RISCVSTATE_WRITE_RD: {
......@@ -610,12 +610,17 @@ DEFINE_FUNC(riscv_core_gen_state, "state, instr, nwReset") {
case RISCVSTATE_EXEC_INST: {
unsigned int instr = vget(instr);
unsigned int opcode = instr & 0x7f;
unsigned int func3 = (instr >> 12) & 0x7;
opcode >>= 2;
if (opcode == 0x00)
vput(state, RISCVSTATE_WAIT_LD);//ld
else if (opcode == 0x08)
else if (opcode == 0x08)
vput(state, RISCVSTATE_WAIT_ST);//st
else
else if (opcode == 0x0c && (instr & (1 << 15)) && (func3 & 4)) {
vput(state, RISCVSTATE_WAIT_DIV);
//divclk <= 11;
}
else
vput(state, RISCVSTATE_WRITE_RD);
}break;
case RISCVSTATE_WAIT_LD: {
......@@ -624,6 +629,10 @@ DEFINE_FUNC(riscv_core_gen_state, "state, instr, nwReset") {
case RISCVSTATE_WAIT_ST: {
vput(state, RISCVSTATE_READ_INST);
}break;
case RISCVSTATE_WAIT_DIV: {
if (vget(divclk) == 0)
vput(state, RISCVSTATE_WRITE_RD);
}break;
}
}
} END_DEFINE_FUNC
......@@ -705,6 +714,13 @@ DEFINE_FUNC(riscv_core_reg_gen_rs1, "state, regrddata") {
}
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_core_reg_gen_rs2, "state, regrddata") {
int state = vget(state);
if (state == RISCVSTATE_STORE_RS2) {
vput(rs2, vget(regrddata));
}
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_core_reg_gen_readreg, "state, instr") {
int state = vget(state);
if (state == RISCVSTATE_EXEC_INST) {
......@@ -727,7 +743,26 @@ DEFINE_FUNC(riscv_core_reg_gen_instr, "state, bReadData") {
}
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_core_reg_gen_pc, "nwReset, state, instr, pc, rs1, imm, regrddata") {
DEFINE_FUNC(riscv_core_reg_gen_divclk, "state, instr, divclk") {
int state = vget(state);
if (state == RISCVSTATE_EXEC_INST) {
unsigned int instr = vget(instr);
unsigned int opcode = instr & 0x7f;
unsigned int func3 = (instr >> 12) & 0x7;
opcode >>= 2;
if (opcode == 0x0c && (instr & (1 << 15)) && (func3 & 4)) {
vput(divclk, 11);
}
}
else if (state == RISCVSTATE_WAIT_DIV) {
if (vget(divclk) != 0) {
vput(divclk, vget(divclk) - 1);
}
}
} END_DEFINE_FUNC
DEFINE_FUNC(riscv_core_reg_gen_pc, "nwReset, state, instr, pc, rs1, rs2, imm") {
if (vget(nwReset) == 0) {
vput(pc, 0x74);
}
......@@ -746,7 +781,7 @@ DEFINE_FUNC(riscv_core_reg_gen_pc, "nwReset, state, instr, pc, rs1, imm, regrdda
case 0x19: vput(pc, rs1 + imm); break;
case 0x18: {
unsigned int func3;
unsigned int rs2 = vget(regrddata);
unsigned int rs2 = vget(rs2);
int cond;
func3 = (instr >> 12) & 0x7;
cond = 0;
......@@ -790,6 +825,8 @@ DEFINE_FUNC(riscv_core_clktick, "") {
}
} END_DEFINE_FUNC
MODULE_INIT(riscv_core)
PORT_IN(wClk, 1);
PORT_IN(nwReset, 1);
......@@ -808,6 +845,7 @@ MODULE_INIT(riscv_core)
GREG(pc, 32, riscv_core_reg_gen_pc);
GREG(instr, 32, riscv_core_reg_gen_instr);
GREG(rs1, 32, riscv_core_reg_gen_rs1);
GREG(rs2, 32, riscv_core_reg_gen_rs2);
GREG(write, 1, riscv_core_gen_write);
GREG(writeaddr, 32, riscv_core_gen_write);
GREG(writedata, 32, riscv_core_gen_write);
......@@ -818,6 +856,6 @@ MODULE_INIT(riscv_core)
GREG(dstreg, 5, riscv_core_gen_dstreg);
GREG(dstvalue, 32, riscv_core_gen_dstreg);
GREG(ldaddr, 2, riscv_core_gen_ldaddr);
GREG(divclk, 4, riscv_core_reg_gen_divclk);
CLKTICK_FUNC(riscv_core_clktick);
END_MODULE_INIT(riscv_core)
examples/hdl4se_riscv/verilog/riscv_core.v
浏览文件 @ 37264416
......@@ -101,6 +101,7 @@ module riscv_core(
wire [71:0] mulsu_result;
wire [31:0] div_result_r, mod_result_r, divs_result_r, mods_result_r;
wire [31:0] div_result, mod_result, divs_result, mods_result;
adder add(rs1, rs2, add_result);
suber sub(rs1, rs2, sub_result);
mult mul(rs1, rs2, mul_result);
......
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