202107020641 好像有个bug，编译器陷入死循环了

examples/terris/verilog/terris_main.v

@@ -278,4 +278,58 @@ module top(input wClk, nwReset);
   terrisdevice terrisui  (wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData);
   main         terrisctrl(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData);
 
-endmodule
\ No newline at end of file
+endmodule
+
+/* 以下代码测试编译器 */
+module dec2seg(input [3:0] dec, output [7:0] seg);
+wire [3:0] dec;
+reg [7:0] seg;
+always @(dec) 
+  case (dec)
+    4'd0:seg = 8'b00111111;
+    4'd1:seg = 8'b00000110;
+    4'd2:seg = 8'b01011011;
+    4'd3:seg = 8'b01001111;
+    4'd4:seg = 8'b01100110;
+    4'd5:seg = 8'b01101101;
+    4'd6:seg = 8'b01111101;
+    4'd7:seg = 8'b00000111;
+    4'd8:seg = 8'b01111111;
+    4'd9:seg = 8'b01101111;
+    default:seg = 8'b01111001;
+  endcase
+endmodule  
+
+module counter
+    #(parameter WIDTH=4, MAXVALUE=9, RESETVALUE=0)
+(input wClk, nwReset, wCounterIt, 
+output [WIDTH-1:0] bCouter, 
+output wCounterOverflow);
+
+/* WIDTH宽度的寄存器用来保存计数器的值 */
+reg [WIDTH-1:0] bCurrentCounter;
+/* 定义一个寄存器来表示计数器是否溢出 */
+reg wOverflow;
+wire [WIDTH-1:0] bCounter;
+wire wCounterOverflow;
+/* 输出线网直接连接在寄存器上 */
+assign bCounter = bCurrentCounter;
+assign wCounterOverflow = (bCurrentCounter == MAXVALUE) && wCounterIt;
+always @(posedge wClk) begin
+  if (~nwReset) begin /*复位处理*/
+  		bCurrentCounter <= RESETVALUE;
+        wOverflow <= 1'b0;
+  end else begin
+    /* 复位信号无效的情况，开始计数操作 */
+	if (wCounterIt) begin
+		if (bCurrentCounter == MAXVALUE) begin
+			bCurrentCounter <= RESETVALUE;
+            wOverflow <= 1'b1;
+        end else begin
+          bCurrentCounter <= bCurrentCounter + 1;
+          wOverflow <= 1'b0;
+        end
+    end /*wCounterIt*/
+  end /*nwReset*/
+end /*always*/
+endmodule

parser/verilog_assignment.c

@@ -136,16 +136,14 @@ static int assignment_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
 	pobj = (sAssignment *)objectThis(object);
 	output_attributes(pFile, opt, pobj);
 	if (pobj->data.assignmenttype == 0)
-		fprintf(pFile, "\tassign ");
-	else
-		fprintf(pFile, "\t");
+		fprintf(pFile, "assign ");
 	verilog_dump_node_list(pobj->data.hierarchical_identifier, pFile, opt, ".", 5);
 	if (pobj->data.assignmenttype == 0 || pobj->data.assignmenttype == 1)
 		fprintf(pFile, " = ");
 	else if (pobj->data.assignmenttype == 2)
 		fprintf(pFile, " <= ");
 	objectCall2(pobj->data.expr, dump, pFile, opt);
-	fprintf(pFile, ";\n");
+	fprintf(pFile, ";");
 	return 0;
 }
 

parser/verilog_caseitem.c

@@ -121,6 +121,12 @@ static int caseitem_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
 {
 	sCaseItem * pobj;
 	pobj = (sCaseItem *)objectThis(object);
+	if (dlistItemCount(pobj->data.expression_list) > 0)
+		verilog_dump_node_list(pobj->data.expression_list, pFile, opt, ",", 10000);
+	else
+		fprintf(pFile, "default");
+	fprintf(pFile, ": ");
+	objectCall2(pobj->data.statement, dump, pFile, opt);
 	return 0;
 }
 

parser/verilog_module.c

@@ -126,48 +126,50 @@ static int verilogmodule_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
     verilogmodule_verilognode_procheck(object, object, NULL);
     pModule = (sVerilogModule *)objectThis(object);
     if (dlistItemCount(pModule->data.attributes) > 0) {
-        fprintf(pFile, "(* \n  ");
-        verilog_dump_node_list(pModule->data.attributes, pFile, opt, ",\n  ", 10000);
+        fprintf(pFile, "\n(* \n\t");
+        verilog_dump_node_list(pModule->data.attributes, pFile, opt, ",\n\t", 10000);
         fprintf(pFile, "\n*)\n");
     }
-    fprintf(pFile, "module %s\n", conststringFromVar(pModule->data.name));
+    fprintf(pFile, "module %s\n\t", conststringFromVar(pModule->data.name));
     /*parameter*/
     if (dlistItemCount(pModule->data.module_parameters) > 0) {
-        fprintf(pFile, "#(\n  ");
-        verilog_dump_node_list(pModule->data.module_parameters, pFile, opt, ",\n  ", 10000);
-        fprintf(pFile, "\n)\n");
+        fprintf(pFile, "#(\n\t");
+        verilog_dump_node_list(pModule->data.module_parameters, pFile, opt, ",\n\t", 10000);
+        fprintf(pFile, "\n\t)\n\t");
     }
 
     /*ports*/
     if (dlistItemCount(pModule->data.module_ports) > 0) {
-        fprintf(pFile, "(\n  ");
-        verilog_dump_node_list(pModule->data.module_ports, pFile, opt, ",\n  ", 10000);
-        fprintf(pFile, "\n)\n");
+        fprintf(pFile, "(\n\t");
+        verilog_dump_node_list(pModule->data.module_ports, pFile, opt, ",\n\t", 10000);
+        fprintf(pFile, "\n\t)\n\t");
     }
 
-    fprintf(pFile, ";\n");
+    fprintf(pFile, ";\n\t");
 
     /*module items*/
 
-#define dump_module_items(item) \
+#define dump_module_items(item, gap) \
     if (dlistItemCount(pModule->data.item) > 0) { \
-        verilog_dump_node_list(pModule->data.item, pFile, opt, "", 10000); \
+        fprintf(pFile, gap); \
+        verilog_dump_node_list(pModule->data.item, pFile, opt, gap, 10000); \
     }
 
-    dump_module_items(net_declarations);
-    dump_module_items(reg_declarations);
-    dump_module_items(event_declarations);
-    dump_module_items(function_declarations);
-    dump_module_items(task_declarations);
-    dump_module_items(continuous_assignments);
-    dump_module_items(module_instantiations);
-    dump_module_items(initial_blocks);
+    dump_module_items(net_declarations, "\n\t");
+    dump_module_items(reg_declarations, "\n\t");
+    dump_module_items(event_declarations, "\n\t");
+    dump_module_items(function_declarations, "\n\t");
+    dump_module_items(task_declarations, "\n\t");
+    dump_module_items(continuous_assignments, "\n\t");
+    dump_module_items(module_instantiations, "\n\t");
+    dump_module_items(initial_blocks, "\n\t");
 
     if (dlistItemCount(pModule->data.always_blocks) > 0) {
-        verilog_dump_node_list(pModule->data.always_blocks, pFile, 1, "\n  ", 10000);
+        fprintf(pFile, "\n\t");
+        verilog_dump_node_list(pModule->data.always_blocks, pFile, 1, "\n\t", 10000);
     }
 
-    fprintf(pFile, "endmodule\n");
+    fprintf(pFile, "\nendmodule\n");
 	return 0;
 }
 

parser/verilog_moduleinst.c

@@ -146,7 +146,7 @@ static int moduleinst_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
 	sModuleInst * pobj;
 	pobj = (sModuleInst *)objectThis(object);
 	output_attributes(pFile, opt, pobj);
-	fprintf(pFile, "  %s", conststringFromVar(pobj->data.modulename));
+	fprintf(pFile, "%s", conststringFromVar(pobj->data.modulename));
 	if (dlistItemCount(pobj->data.parameter_value_assignment) > 0) {
 		fprintf(pFile, " #( ");
 		verilog_dump_node_list(pobj->data.parameter_value_assignment, pFile, opt, ", ", 5);
@@ -158,7 +158,7 @@ static int moduleinst_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
 		verilog_dump_node_list(pobj->data.port_connections, pFile, opt, ", ", 5);
 		fprintf(pFile, " )");
 	}
-	fprintf(pFile, ";\n");
+	fprintf(pFile, ";");
 	return 0;
 }
 

parser/verilog_statement.c

@@ -121,7 +121,7 @@ static int statement_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
 	sStatement * pobj;
 	pobj = (sStatement *)objectThis(object);
 	if (opt != 0) {
-		fprintf(pFile, "\talways ");
+		fprintf(pFile, "always ");
 	}
 	switch (pobj->data.timecontrol) {
 	case TIMECONTROL_NONE :
@@ -139,8 +139,47 @@ static int statement_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
 	}
 	switch (pobj->data.statementtype) {
 		case STATEMENT_NONBLOCKING_ASSIGNMENT :
+		case STATEMENT_BLOCKING_ASSIGNMENT:
 			objectCall2(pobj->data.assignment, dump, pFile, 0);
 			break;
+		case STATEMENT_CASE:
+			switch (pobj->data.case_type)
+			{
+			case CASETYPE_CASE:
+				fprintf(pFile, "\tcase (");
+				break;
+			case CASETYPE_CASEX:
+				fprintf(pFile, "\tcasex (");
+				break;
+			case CASETYPE_CASEZ:
+				fprintf(pFile, "\tcasez (");
+				break;
+			}
+			objectCall2(pobj->data.case_expression, dump, pFile, 0);
+			fprintf(pFile, ")\n\t\t");
+			verilog_dump_node_list(pobj->data.case_item_list, pFile, 0, "\n\t\t", 10000);
+			fprintf(pFile, "\n\tendcase\n");
+			break;
+		case STATEMENT_PAR:
+			fprintf(pFile, "\tfork\n\t\t");
+			verilog_dump_node_list(pobj->data.statement_list, pFile, 0, "\n\t\t", 10000);
+			fprintf(pFile, "\tjoin\n");
+			break;
+		case STATEMENT_SEQ:
+			fprintf(pFile, "\tbegin\n\t\t");
+			verilog_dump_node_list(pobj->data.statement_list, pFile, 0, "\n\t\t", 10000);
+			fprintf(pFile, "\tend\n");
+			break;
+		case STATEMENT_CONDITIONAL:
+			fprintf(pFile, "\tif (");
+			objectCall2(pobj->data.ifexpression, dump, pFile, 0);
+			fprintf(pFile, ")\n\t\t");
+			verilog_dump_node_list(pobj->data.iftrueblock, pFile, 0, "\n\t\t", 10000);
+			if (pobj->data.iffalseblock != NULL) {
+				fprintf(pFile, "\n\telse\n\t\t");
+				verilog_dump_node_list(pobj->data.iffalseblock, pFile, 0, "\n\t\t", 10000);
+			}
+			break;
 	}
 	return 0;
 }

parser/verilog_vardecl.c

@@ -177,7 +177,6 @@ static int vardecl_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
 	attribute_instance_list net_type drive_strength_option vectored_or_scalared_option signed_option
 		range_option delay3_option list_of_net
 	*/
-	fprintf(pFile, "  ");
 	if (dlistItemCount(pobj->data.attributes) > 0) {
 		fprintf(pFile, "(* ");
 		verilog_dump_node_list(pobj->data.attributes, pFile, opt, ", ", 5);
@@ -190,7 +189,7 @@ static int vardecl_verilognode_dump(HOBJECT object, FILE * pFile, int opt)
 		fprintf(pFile, " = ");
 		objectCall2(pobj->data.assignexpr, dump, pFile, opt);
 	}
-	fprintf(pFile, ";\n");
+	fprintf(pFile, ";");
 	return 0;
 }