hdl4se_macros.h

/*
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
**   this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
**   this list of conditions and the following disclaimer in the documentation
**   and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
**   derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/

/*
* hdl4se_macros.h
  修改记录：
	202107072033: rxh, initial version
*/

#ifndef __HDL4SE_MACROS_H
#define __HDL4SE_MACROS_H

#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASMLANGUAGE

enum port_direct {
	PORT_INPUT,
	PORT_OUTPUT,
	PORT_INOUT
};

typedef struct sModulePortInfo {
	int index;
	int portdirect;
	const char* name;
	int width;
	int isunsigned;
}ModulePortInfo;

#define H4S_PORT(module_name) static const ModulePortInfo module_name##_port_info_list[PORT_COUNT] = {
#define H4S_IN(index, name, width) {index, PORT_INPUT, #name, width, 1},
#define H4S_OUT(index, name, width) {index, PORT_OUTPUT, #name, width, 1},
#define H4S_IN_SIGNED(index, name, width) {index, PORT_INPUT, #name, width, 0},
#define H4S_OUT_SIGNED(index, name, width) {index, PORT_OUTPUT, #name, width, 0},
#define H4S_END_PORT };

#define MODULE_DATA_TYPE(module_name) sHDL4SE_##module_name

#define MODULE_DECLARE(module_name) \
struct _sHDL4SE_##module_name; \
typedef struct _sHDL4SE_##module_name sHDL4SE_##module_name; \
typedef int (*module_name##_func)(sHDL4SE_##module_name * pobj); \
typedef int (*module_name##_index_func)(sHDL4SE_##module_name * pobj, int index); \
struct _sHDL4SE_##module_name{ \
	OBJECT_HEADER \
	INTERFACE_DECLARE(IHDL4SEUnit) \
	HDL4SEUNIT_VARDECLARE \
	DLIST_VARDECLARE \
	\
	IHDL4SEModule **__parent; \
	char* __name; \
	int __datavalid; \
	char * __parameters[PARAM_COUNT + 1]; \
	const ModulePortInfo *__port_info_list; \
	int __port_count; \
	\
	IBigNumber** __inputdata; \
	int __port_datavalid[PORT_COUNT]; \
	IBigNumber** __port_data[PORT_COUNT];\
	IHDL4SEUnit** __input_unit[PORT_COUNT]; \
    module_name##_index_func __output_gen_func[PORT_COUNT]; \
	int           __input_index[PORT_COUNT]; \
	module_name##_func __setup_func; \
	module_name##_func __clktick_func;

#define END_MODULE_DECLARE(module_name) }; \
 \
OBJECT_FUNCDECLARE(module_name, MODULE_CLSID); \
HDL4SEUNIT_FUNCDECLARE(module_name, MODULE_CLSID, sHDL4SE_##module_name); \
DLIST_FUNCIMPL(module_name, clsid, sHDL4SE_##module_name); \
 \
OBJECT_FUNCIMPL(module_name, sHDL4SE_##module_name, MODULE_CLSID); \
 \
QUERYINTERFACE_BEGIN(module_name, MODULE_CLSID) \
QUERYINTERFACE_ITEM(IID_HDL4SEUNIT, IHDL4SEUnit, sHDL4SE_##module_name) \
QUERYINTERFACE_ITEM(IID_DLIST, IDList, sHDL4SE_##module_name) \
QUERYINTERFACE_END \
 \
static const char* module_name##ModuleInfo() \
{ \
	return MODULE_VERSION_STRING; \
}
 
#define MODULE_INIT(module_name) \
static int module_name##Create(const PARAMITEM* pParams, int paramcount, HOBJECT* pObject) \
{ \
	sHDL4SE_##module_name* pobj; \
	int __i; \
	pobj = (sHDL4SE_##module_name*)malloc(sizeof(sHDL4SE_##module_name)); \
	if (pobj == NULL) \
		return -1; \
	memset(pobj, 0, sizeof(sHDL4SE_##module_name)); \
	*pObject = 0; \
	HDL4SEUNIT_VARINIT(pobj, clsid); \
	INTERFACE_INIT(IHDL4SEUnit, pobj, module_name, hdl4se_unit); \
	DLIST_VARINIT(pobj, module_name); \
	\
	for (__i = 0; __i < PORT_COUNT; __i++) {\
		pobj->__input_unit[__i] = NULL; \
		pobj->__port_data[__i] = bigintegerCreate2( \
					module_name##_port_info_list[__i].width, \
					module_name##_port_info_list[__i].isunsigned \
				); \
	} \
	pobj->__inputdata = bigintegerCreate(64); \
	pobj->__name = NULL; \
	pobj->__parent = NULL; \
	pobj->__datavalid = 0; \
	pobj->__port_info_list = module_name##_port_info_list; \
	pobj->__port_count = PORT_COUNT; \
	for (__i = 0; __i < paramcount; __i++) { \
		if (pParams[__i].name == PARAMID_HDL4SE_UNIT_NAME) { \
			if (pobj->__name != NULL) \
				free(pobj->__name); \
			pobj->__name = strdup(pParams[__i].pvalue); \
		} \
		else if (pParams[__i].name == PARAMID_HDL4SE_UNIT_PARENT) { \
			pobj->__parent = (IHDL4SEModule**)pParams[__i].pvalue; \
		} \
		else if (pParams[__i].name == PARAMID_HDL4SE_UNIT_INSTANCE_PARAMETERS) { \
			hdl4se_split_string((const char*)pParams[__i].pvalue, pobj->__parameters, PARAM_COUNT, ','); \
		} \
	}

#define END_MODULE_INIT(module_name) \
	OBJECT_RETURN_GEN(module_name, pobj, pObject, MODULE_CLSID); \
	return EIID_OK; \
}

static int hdl4se_set_output_func(const ModulePortInfo* portlist, int portcount, const char* signal_list, void * func, void** function_list)
{
	char name[256];
	const char* inp = signal_list;
	char* namep = name;
	do {
		int ch = *inp;
		if (ch == '_' || (ch >= 'a' && ch <= 'z') || (ch >= 'A' && ch <= 'Z')) {
			*namep++ = ch;
		}
		else {
			if (namep != name || ch == '*') {
				if (ch >= '0' && ch <= '9') {
					*namep++ = ch;
				}
				else {
					/*find a token*/
					int i;
					*namep = 0;
					for (i = 0; i < portcount; i++) {
						if (portlist[i].portdirect == PORT_OUTPUT
							|| portlist[i].portdirect == PORT_INOUT) {
							if (ch == '*' || strcmp(name, portlist[i].name) == 0) {
								function_list[i] = func;
								break;
							}
						}
					}
					namep = name;
				}
			}
		}
		if (*inp == 0)
			break;
		inp++;
	} while (1);
	return 0;
}

#define GENOUTPUT_FUNC(signal_list, func)  hdl4se_set_output_func(pobj->__port_info_list, pobj->__port_count, signal_list, (void *)func, (void **)pobj->__output_gen_func)
#define SETUP_FUNC(func) pobj->__setup_func = func
#define CLKTICK_FUNC(func) pobj->__clktick_func = func

#define DEFINE_FUNC(module_name, funcname) \
static int funcname(sHDL4SE_##module_name* pobj) {

#define END_DEFINE_FUNC return 0; }

#define DEFINE_FUNC_INDEX(module_name, funcname) \
static int funcname(sHDL4SE_##module_name* pobj, int index) {

#define END_DEFINE_FUNC return 0; }


#define MODULE_DEINIT(module_name) \
static void module_name##Destroy(HOBJECT object) \
{ \
	sHDL4SE_##module_name* pobj; \
	int i; \
	pobj = (sHDL4SE_##module_name*)objectThis(object); \
	if (pobj->__name != NULL) \
		free(pobj->__name); \
	for (i = 0; i < PORT_COUNT; i++) { \
		objectRelease(pobj->__input_unit[i]); \
		objectRelease(pobj->__port_data[i]); \
	} \
	for (i = 0; i < PARAM_COUNT + 1; i++) { \
		if (pobj->__parameters[i] != NULL) \
			free(pobj->__parameters[i]); \
	} \
	objectRelease(pobj->__inputdata); \

#define END_MODULE_DEINIT(module_name) \
	memset(pobj, 0, sizeof(sHDL4SE_##module_name)); \
	free(pobj); \
} \
 \
static int module_name##Valid(HOBJECT object) \
{ \
	return 1; \
} \
 \
static int module_name##_hdl4se_unit_GetName(HOBJECT object, const char** pname) \
{ \
	sHDL4SE_##module_name* pobj; \
	pobj = (sHDL4SE_##module_name*)objectThis(object); \
	*pname = pobj->__name; \
	return 0; \
} \
\
static int module_name##_hdl4se_unit_ConnectInput(HOBJECT object, int index, HOBJECT from, int fromindex) \
{ \
	sHDL4SE_##module_name* pobj; \
	IHDL4SEUnit** unit = NULL; \
	pobj = (sHDL4SE_##module_name*)objectThis(object); \
	if (index < 0 || index >= pobj->__port_count) \
		return -1; \
	if (pobj->__port_info_list[index].portdirect == PORT_INPUT) { \
		if (0 == objectQueryInterface(from, IID_HDL4SEUNIT, (void**)&unit)) { \
			\
			objectRelease(pobj->__input_unit[index]); \
			pobj->__input_unit[index] = unit; \
			pobj->__input_index[index] = fromindex; \
		} \
	} \
	return 0; \
} \
 \
static int module_name##_hdl4se_unit_GetValue(HOBJECT object, int index, int width, IBigNumber ** value) \
{ \
	sHDL4SE_##module_name* pobj; \
	pobj = (sHDL4SE_##module_name*)objectThis(object); \
	if (index < 0 || index >= pobj->__port_count) \
		return -1; \
	if (pobj->__port_info_list[index].portdirect != PORT_OUTPUT) \
		return -2; \
	if (pobj->__port_datavalid[index] == 0) { \
		if (pobj->__output_gen_func[index] != NULL) \
			pobj->__output_gen_func[index](pobj, index); \
	} \
	if (width <= 0) { \
		objectCall1(value, SetUnsigned, pobj->__port_info_list[index].isunsigned); \
		objectCall1(value, SetWidth, pobj->__port_info_list[index].width); \
	} \
	objectCall1(value, Assign, pobj->__port_data[index]); \
	return 0; \
} \
 \
static int module_name##_hdl4se_unit_ClkTick(HOBJECT object) \
{ \
	sHDL4SE_##module_name* pobj; \
	pobj = (sHDL4SE_##module_name*)objectThis(object); \
	if (pobj->__clktick_func != NULL) \
		return pobj->__clktick_func(pobj); \
	return 0; \
} \
 \
static int module_name##_hdl4se_unit_Setup(HOBJECT object) \
{ \
	int i; \
	sHDL4SE_##module_name* pobj; \
	pobj = (sHDL4SE_##module_name*)objectThis(object); \
	if (pobj->__setup_func != 0) \
		pobj->__setup_func(pobj); \
	for (i = 0; i < pobj->__port_count; i++) { \
		pobj->__port_datavalid[i] = 0; \
	} \
	return 0; \
}


#define UpdatePortData(portindex) \
do { \
	if (portindex >= 0 && portindex < pobj->__port_count) { \
		if (pobj->__port_datavalid[portindex] == 0) { \
			if (pobj->__port_info_list[portindex].portdirect == PORT_INPUT) { \
				objectCall3(pobj->__input_unit[portindex], \
					GetValue, \
					pobj->__input_index[portindex], \
					pobj->__port_info_list[portindex].width, \
					pobj->__port_data[portindex]); \
				pobj->__port_datavalid[portindex] = 1; \
			} \
			else if (pobj->__port_info_list[portindex].portdirect == PORT_OUTPUT) { \
				if (pobj->__output_gen_func[portindex] != NULL) \
					pobj->__output_gen_func[portindex](pobj, portindex); \
				pobj->__port_datavalid[portindex] = 1; \
			} \
		} \

#define GetPortUint32(portindex, v) \
	UpdatePortData(portindex) \
		v = objectCall0(pobj->__port_data[portindex], ReadUint32); \
	} \
} while (0)

#define GetPortInt32(portindex, v) \
	UpdatePortData(portindex) \
		v = objectCall0(pobj->__port_data[portindex], ReadInt32); \
	} \
} while (0)

#define GetPortUint64(portindex, v) \
	UpdatePortData(portindex) \
		v = objectCall0(pobj->__port_data[portindex], ReadUint64); \
	} \
} while (0)

#define GetPortInt64(portindex, v) \
	UpdatePortData(portindex) \
		v = objectCall0(pobj->__port_data[portindex], ReadInt64); \
	} \
} while (0)

#define SetPortUint32(portindex, v) \
do { \
	objectCall1(pobj->__port_data[portindex], AssignUint32, v); \
	pobj->__port_datavalid[portindex] = 1; \
} while (0)

#define SetPortInt32(portindex, v) \
do { \
	objectCall1(pobj->__port_data[portindex], AssignInt32, v); \
	pobj->__port_datavalid[portindex] = 1; \
} while (0)

#define SetPortUint64(portindex, v) \
do { \
	objectCall1(pobj->__port_data[portindex], AssignUint64, v); \
	pobj->__port_datavalid[portindex] = 1; \
} while (0)

#define SetPortInt64(portindex, v) \
do { \
	objectCall1(pobj->__port_data[portindex], AssignInt64, v); \
	pobj->__port_datavalid[portindex] = 1; \
} while (0)

int hdl4se_split_string(const char * string, char ** substr, int substrcount, int gap);

#endif /* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif

#endif /* __HDL4SE_MACROS_H */