riscv_sim_dump_v3.v

(* 
	HDL4SE = "LCOM",
	CLSID = "638E8BC3-B0E0-41DC-9EDD-D35A39FD8051",
	softmodule = "hdl4se"
*)
module riscv_core
	(
	input  wClk,
	input  nwReset,
	output  wWrite,
	output  [32'h1f:32'h0]  bWriteAddr,
	output  [32'h1f:32'h0]  bWriteData,
	output  [32'h3:32'h0]  bWriteMask,
	output reg wRead,
	output reg [32'h1f:32'h0]  bReadAddr,
	input  [32'h1f:32'h0]  bReadData,
	output reg [32'h4:32'h0]  regno,
	output reg [32'h3:32'h0]  regena,
	output reg [32'h1f:32'h0]  regwrdata,
	output reg regwren,
	input  [32'h1f:32'h0]  regrddata,
	output reg [32'h4:32'h0]  regno2,
	output reg [32'h3:32'h0]  regena2,
	output reg [32'h1f:32'h0]  regwrdata2,
	output reg regwren2,
	input  [32'h1f:32'h0]  regrddata2
	)
	;
	
	wire [32'h4:32'h0]  opcode;
	wire [32'h4:32'h0]  rd;
	wire [32'h2:32'h0]  func3;
	wire [32'h1f:32'h0]  rs1;
	wire [32'h1f:32'h0]  rs2;
	wire [32'h1f:32'h0]  rs1_s;
	wire [32'h1f:32'h0]  rs2_s;
	wire [32'h1f:32'h0]  imm_s;
	wire [32'h1f:32'h0]  add_result;
	wire [32'h1f:32'h0]  sub_result;
	wire [32'h3f:32'h0]  mul_result;
	wire [32'h3f:32'h0]  muls_result;
	wire [32'h47:32'h0]  mulsu_result;
	wire [32'h1f:32'h0]  div_result_r;
	wire [32'h1f:32'h0]  mod_result_r;
	wire [32'h1f:32'h0]  divs_result_r;
	wire [32'h1f:32'h0]  mods_result_r;
	wire [32'h1f:32'h0]  div_result;
	wire [32'h1f:32'h0]  mod_result;
	wire [32'h1f:32'h0]  divs_result;
	wire [32'h1f:32'h0]  mods_result;
	assign wWrite = write;
	assign bWriteAddr = writeaddr;
	assign bWriteData = writedata;
	assign bWriteMask = writemask;
	assign div_result = div_result_r;
	assign divs_result = divs_result_r;
	assign mod_result = mod_result_r;
	assign mods_result = mods_result_r;
	assign opcode = instr [6:2] ;
	assign rd = instr [11:7] ;
	assign func3 = instr [14:12] ;
	assign rs1 = regrddata;
	assign rs2 = regrddata2;
	assign rs1_s = rs1;
	assign rs2_s = rs2;
	assign imm_s = imm;
	adder add( rs1, rs2, add_result );
	suber sub( rs1, rs2, sub_result );
	mult mul( rs1, rs2, mul_result );
	mult_s mul_s( rs1, rs2, muls_result );
	mulsu mul_su( rs1, {0,rs2}, mulsu_result );
	div div( wClk, rs2, rs1, div_result_r, mod_result_r );
	div_s divs( wClk, rs2, rs1, divs_result_r, mods_result_r );
	always @*
	case (func3)
		0: cond = (rs1==rs2);
		1: cond = (rs1!=rs2);
		4: cond = (rs1_s<rs2_s);
		5: cond = (rs1_s>=rs2_s);
		6: cond = (rs1<rs2);
		7: cond = (rs1>=rs2);
		default: cond = 1'b0;
	endcase
	
	always @(posedge wClk)
	if ((!(nwReset)))
		begin
			pc <= 32'h00000074;
		end
		else
		begin
			if ((state==4))
			begin
				case (opcode)
				5'h1b: pc <= (pc+imm);
				5'h19: pc <= (rs1+imm);
				5'h18: pc <= ((cond)?((pc+imm)):((pc+4)));
				default: pc <= (pc+4);
			endcase
			
			end
		end
	always @(posedge wClk)
	if ((state==3))
		instr <= bReadData;
	always @(posedge wClk)
	if ((state==4))
		if ((opcode==5'h00))
			readreg <= rd;
	always @(posedge wClk)
	if ((!(nwReset)))
		begin
			write <= 0;
		end
		else
		if ((state==4))
			begin
				write <= 0;
				if ((opcode==5'h08))
				begin
					writeaddr <= (rs1+imm);
					writemask <= 4'h0;
					writedata <= rs2;
					write <= 1'b1;
					case (func3)
					0: begin
						case (writeaddr)
						0: begin
							writemask <= 4'he;
							writedata <= rs2;
						end
						1: begin
							writemask <= 4'hd;
							writedata <= {rs2 [23:0] ,8'b0};
						end
						2: begin
							writemask <= 4'hb;
							writedata <= {rs2 [15:0] ,16'b0};
						end
						3: begin
							writemask <= 4'h7;
							writedata <= {rs2 [7:0] ,24'b0};
						end
					endcase
					
					end
					1: begin
						case (writeaddr)
						0: begin
							writemask <= 4'hc;
							writedata <= rs2;
						end
						1: begin
							writemask <= 4'hd;
							writedata <= {rs2 [23:0] ,8'b0};
						end
						2: begin
							writemask <= 4'hb;
							writedata <= {rs2 [15:0] ,16'b0};
						end
					endcase
					
					end
				endcase
				
				end
			end
			else
			begin
				write <= 0;
			end
	always @(posedge wClk)
	if ((!(nwReset)))
		begin
			state <= 0;
		end
		else
		begin
			case (state)
			0: state <= 1;
			1: state <= 2;
			2: state <= 3;
			3: state <= 4;
			5: state <= 2;
			4: begin
				if ((opcode==5'h00))
				state <= 6;
				else
				if ((opcode==5'h08))
					state <= 7;
					else
					if (((((opcode==5'h0c)&&instr [25] )&&func3 [2] )&&(rs2!=0)))
						begin
							state <= 8;
							divclk <= 11;
						end
						else
						state <= 5;
			end
			6: state <= 5;
			7: state <= 2;
			8: begin
				if ((divclk==0))
				state <= 5;
				else
				divclk <= (divclk-1);
			end
		endcase
		
		end
	always @(posedge wClk)
	if ((state==3))
		begin
			case (bReadData [6:2] )
			5'h0d: imm <= {bReadData [31:12] ,12'b0};
			5'h05: imm <= {bReadData [31:12] ,12'b0};
			5'h1b: imm <= {{12{bReadData [31] }{,bReadData [19:12] ,bReadData [20] ,bReadData [30:21] ,1'b0};
			5'h19: imm <= {{20{bReadData [31] }{,bReadData [31:20] };
			5'h18: imm <= {{20{bReadData [31] }{,bReadData [7] ,bReadData [30:25] ,bReadData [11:8] ,1'b0};
			5'h00: imm <= {{20{bReadData [31] }{,bReadData [31:20] };
			5'h08: imm <= {{20{bReadData [31] }{,bReadData [31:25] ,bReadData [11:7] };
			5'h04: imm <= {{20{bReadData [31] }{,bReadData [31:20] };
		endcase
		
		end
	always @*
	case (state)
		3: begin
			regno = bReadData [19:15] ;
			regwren = 0;
			regena = 0;
			regwrdata = 0;
			regno2 = bReadData [24:20] ;
			regwren2 = 0;
			regena2 = 0;
			regwrdata2 = 0;
		end
		5: begin
			regwren = (((dstreg!=0))?(1):(0));
			regno = dstreg;
			regena = 4'hf;
			regwrdata = dstvalue;
			regwren2 = (((dstreg!=0))?(1):(0));
			regno2 = dstreg;
			regena2 = 4'hf;
			regwrdata2 = dstvalue;
		end
		0: begin
			regwren = 1;
			regno = 1;
			regena = 4'hf;
			regwrdata = 32'h8c;
			regwren2 = 1;
			regno2 = 1;
			regena2 = 4'hf;
			regwrdata2 = 32'h8c;
		end
		1: begin
			regwren = 1;
			regno = 2;
			regena = 4'hf;
			regwrdata = ((32768*4)-16);
			regwren2 = 1;
			regno2 = 2;
			regena2 = 4'hf;
			regwrdata2 = ((32768*4)-16);
		end
		default: begin
			regwren = 0;
			regno = 0;
			regena = 0;
			regwrdata = 0;
			regwren2 = 0;
			regno2 = 0;
			regena2 = 0;
			regwrdata2 = 0;
		end
	endcase
	
	always @(posedge wClk)
	if ((state==2))
		begin
			ldaddr <= pc;
		end
		else
		if ((state==4))
			begin
				if ((opcode==5'h00))
				begin
					ldaddr <= (rs1+imm);
				end
			end
	always @(posedge wClk)
	case (state)
		6: begin
			dstreg <= readreg;
			case (func3)
			0: begin
				case (ldaddr)
				0: dstvalue <= {{24{bReadData [7] }{,bReadData [7:0] };
				1: dstvalue <= {{24{bReadData [15] }{,bReadData [15:8] };
				2: dstvalue <= {{24{bReadData [23] }{,bReadData [23:16] };
				3: dstvalue <= {{24{bReadData [31] }{,bReadData [31:24] };
			endcase
			
			end
			1: begin
				case (ldaddr)
				0: dstvalue <= {{16{bReadData [15] }{,bReadData [15:0] };
				1: dstvalue <= {{16{bReadData [23] }{,bReadData [23:8] };
				2: dstvalue <= {{16{bReadData [31] }{,bReadData [31:16] };
				3: dstvalue <= 32'hdeadbeef;
			endcase
			
			end
			2: dstvalue <= bReadData;
			4: begin
				case (ldaddr)
				0: dstvalue <= {24'b0,bReadData [7:0] };
				1: dstvalue <= {24'b0,bReadData [15:8] };
				2: dstvalue <= {24'b0,bReadData [23:16] };
				3: dstvalue <= {24'b0,bReadData [31:24] };
			endcase
			
			end
			5: begin
				case (ldaddr)
				0: dstvalue <= {16'b0,bReadData [15:0] };
				1: dstvalue <= {16'b0,bReadData [23:8] };
				2: dstvalue <= {16'b0,bReadData [31:16] };
				3: dstvalue <= 32'hdeadbeef;
			endcase
			
			end
		endcase
		
		end
		8: if ((divclk==0))
			begin
				dstreg <= 0;
				case (func3 [1:0] )
				0: begin
					dstreg <= rd;
					dstvalue <= divs_result;
				end
				1: begin
					dstreg <= rd;
					dstvalue <= div_result;
				end
				2: begin
					dstreg <= rd;
					dstvalue <= mods_result;
				end
				3: begin
					dstreg <= rd;
					dstvalue <= mod_result;
				end
			endcase
			
			end
		4: begin
			dstreg <= rd;
			case (opcode)
			5'h0d: begin
				dstvalue <= imm;
			end
			5'h05: begin
				dstvalue <= (imm+pc);
			end
			5'h1b: begin
				dstvalue <= (pc+4);
			end
			5'h19: begin
				dstvalue <= (pc+4);
			end
			5'h04: begin
				case (func3)
				0: dstvalue <= (rs1+imm);
				1: dstvalue <= (rs1<<imm [4:0] );
				2: dstvalue <= (((rs1_s<imm_s))?(1):(0));
				3: dstvalue <= (((rs1<imm))?(1):(0));
				4: dstvalue <= (rs1^imm);
				5: dstvalue <= ((instr [30] )?((rs1_s>>imm [4:0] )):((rs1>>imm [4:0] )));
				6: dstvalue <= (rs1|imm);
				7: dstvalue <= (rs1&imm);
				default: begin
					dstreg <= 0;
					dstvalue <= 0;
				end
			endcase
			
			end
			5'h0c: begin
				if (instr [25] )
				begin
					case (func3)
					0: begin
						dstvalue <= muls_result [31:0] ;
					end
					1: begin
						dstvalue <= muls_result [63:32] ;
					end
					2: begin
						dstvalue <= mulsu_result [63:32] ;
					end
					3: begin
						dstvalue <= mul_result [63:32] ;
					end
					4: begin
						if ((rs2==0))
						begin
							dstvalue <= 32'hffffffff;
						end
						else
						begin
							dstreg <= 0;
							dstvalue <= 0;
						end
					end
					5: begin
						if ((rs2==0))
						begin
							dstvalue <= 32'hffffffff;
						end
						else
						begin
							dstreg <= 0;
							dstvalue <= 0;
						end
					end
					6: begin
						if ((rs2==0))
						begin
							dstvalue <= rs1;
						end
						else
						begin
							dstreg <= 0;
							dstvalue <= 0;
						end
					end
					7: begin
						if ((rs2==0))
						begin
							dstvalue <= rs1;
						end
						else
						begin
							dstreg <= 0;
							dstvalue <= 0;
						end
					end
				endcase
				
				end
				else
				begin
					case (func3)
					0: begin
						if (instr [30] )
						dstvalue <= sub_result;
						else
						dstvalue <= add_result;
					end
					1: begin
						dstvalue <= (rs1<<rs2 [4:0] );
					end
					2: begin
						dstvalue <= (((rs1_s<rs2_s))?(1):(0));
					end
					3: begin
						dstvalue <= (((rs1<rs2))?(1):(0));
					end
					4: begin
						dstvalue <= (rs1^rs2);
					end
					5: begin
						if (instr [30] )
						dstvalue <= (rs1>>rs2 [4:0] );
						else
						dstvalue <= (rs1_s>>rs2 [4:0] );
					end
					6: begin
						dstvalue <= (rs1|rs2);
					end
					7: begin
						dstvalue <= (rs1&rs2);
					end
				endcase
				
				end
			end
			default: begin
				dstreg <= 0;
				dstvalue <= 0;
			end
		endcase
		
		end
	endcase
	
	always @*
	begin
		wRead = 0;
		bReadAddr = 0;
		if ((state==2))
		begin
			wRead = 1;
			bReadAddr = pc;
		end
		else
		if ((state==4))
			begin
				if ((opcode==5'h00))
				begin
					bReadAddr = (rs1+imm);
					wRead = 1;
				end
			end
	end
endmodule



(* 
	HDL4SE = "LCOM",
	CLSID = "2925e2cf-dd49-4155-b31d-41d48f0f98dc",
	softmodule = "hdl4se"
*)
module digitled
	(
	input  wClk,
	input  nwReset,
	input  wWrite,
	input  [32'h1f:32'h0]  bWriteAddr,
	input  [32'h1f:32'h0]  bWriteData,
	input  [32'h3:32'h0]  bWriteMask,
	input  wRead,
	input  [32'h1f:32'h0]  bReadAddr,
	output  [32'h1f:32'h0]  bReadData
	)
	;
	
endmodule



(* 
	HDL4SE = "LCOM",
	CLSID = "EE3409B2-6D04-42B3-A44D-7F2444DDC00D",
	softmodule = "hdl4se"
*)
module ram8kb
	(
	input  [32'h1d:32'h0]  address,
	input  [32'h3:32'h0]  byteena,
	input  clock,
	input  [32'h1f:32'h0]  data,
	input  wren,
	output  [32'h1f:32'h0]  q
	)
	;
	
endmodule



(* 
	HDL4SE = "LCOM",
	CLSID = "2E577C6B-2FF1-425E-90B3-947EB523B863",
	softmodule = "hdl4se"
*)
module regfile
	(
	input  [32'h4:32'h0]  address,
	input  [32'h3:32'h0]  byteena,
	input  clock,
	input  [32'h1f:32'h0]  data,
	input  wren,
	output  [32'h1f:32'h0]  q
	)
	;
	
endmodule



(* 
	HDL4SE = "LCOM",
	CLSID = "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2",
	softmodule = "hdl4se"
*)
module hdl4se_reg
	#(
	parameter WIDTH = 32'h8
	)
	(
	input  wClk,
	input  [(WIDTH-32'h1):32'h0]  wirein,
	output  [(WIDTH-32'h1):32'h0]  wireout
	)
	;
	
	wire [(WIDTH-32'h1):32'h0]  wirein;
	always @(posedge wClk)
	wireout <= wirein;
endmodule


module top
	(
	input  wClk,
	input  nwReset
	)
	;
	
	wire wWrite;
	wire wRead;
	wire [32'h1f:32'h0]  bWriteAddr;
	wire [32'h1f:32'h0]  bWriteData;
	wire [32'h1f:32'h0]  bReadAddr;
	wire [32'h1f:32'h0]  bReadData;
	wire [32'h1f:32'h0]  bReadDataRam;
	wire [32'h1f:32'h0]  bReadDataKey;
	wire [32'h3:32'h0]  bWriteMask;
	wire wRead_out;
	wire [32'h1f:32'h0]  bReadAddr_out;
	wire [32'h1d:32'h0]  ramaddr;
	wire [32'h4:32'h0]  regno;
	wire [32'h3:32'h0]  regena;
	wire [32'h1f:32'h0]  regwrdata;
	wire regwren;
	wire [32'h1f:32'h0]  regrddata;
	wire [32'h4:32'h0]  regno2;
	wire [32'h3:32'h0]  regena2;
	wire [32'h1f:32'h0]  regwrdata2;
	wire regwren2;
	wire [32'h1f:32'h0]  regrddata2;
	assign bReadData = ((((bReadAddr_out&32'hffffff00)==32'hf0000000))?(bReadDataKey):(((((bReadAddr_out&32'hff000000)==32'h0))?(bReadDataRam):(32'hffffffff))));
	assign ramaddr = ((wWrite)?(bWriteAddr [31:2] ):(bReadAddr [31:2] ));
	hdl4se_reg #( 32'h1 ) readcmd( wClk, wRead, wRead_out );
	hdl4se_reg #( 32'h20 ) readaddr( wClk, bReadAddr, bReadAddr_out );
	regfile regs( regno, regena, wClk, regwrdata, regwren, regrddata
   );
	regfile regs2( regno2, regena2, wClk, regwrdata2, regwren2, regrddata2
   );
	ram8kb ram( ramaddr, (~(bWriteMask)), wClk, bWriteData, ((((bWriteAddr&32'hff000000)==32'h0))?(wWrite):(0)), bReadDataRam
   );
	digitled led( wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask
  , wRead, bReadAddr, bReadDataKey );
	riscv_core core( wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask
  , wRead, bReadAddr, bReadData, regno, regena
  , regwrdata, regwren, regrddata, regno2, regena2
  , regwrdata2, regwren2, regrddata2 );
endmodule
module adder not found when declare instance add
module suber not found when declare instance sub
module mult not found when declare instance mul
module mult_s not found when declare instance mul_s
module mulsu not found when declare instance mul_su
module div not found when declare instance div
module div_s not found when declare instance divs