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riscv_core.vds 18.1 KB
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202109081321  
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#-----------------------------------------------------------
# Vivado v2021.1 (64-bit)
# SW Build 3247384 on Thu Jun 10 19:36:33 MDT 2021
# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
# Start of session at: Tue Sep  7 20:34:47 2021
# Process ID: 4436
# Current directory: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1
# Command line: vivado.exe -log riscv_core.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source riscv_core.tcl
# Log file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.vds
# Journal file: D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1\vivado.jou
#-----------------------------------------------------------
source riscv_core.tcl -notrace
Command: synth_design -top riscv_core -part xc7k70tfbv484-1
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k70t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k70t'
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 11312
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1134.922 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'riscv_core' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:60]
INFO: [Synth 8-6157] synthesizing module 'mul32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/alu/mul32.v:34]
INFO: [Synth 8-6155] done synthesizing module 'mul32' (1#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/alu/mul32.v:34]
WARNING: [Synth 8-689] width (32) of port connection 'wStart' does not match port width (1) of module 'mul32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:191]
INFO: [Synth 8-6157] synthesizing module 'div32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/alu/div32.v:34]
INFO: [Synth 8-6155] done synthesizing module 'div32' (2#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/alu/div32.v:34]
WARNING: [Synth 8-689] width (32) of port connection 'wStart' does not match port width (1) of module 'div32' [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:270]
INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:371]
INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:440]
INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:449]
INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:438]
INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:478]
INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:554]
INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:649]
INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:791]
INFO: [Synth 8-226] default block is never used [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:925]
INFO: [Synth 8-155] case statement is not full and has no default [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:788]
WARNING: [Synth 8-567] referenced signal 'csr_r' should be on the sensitivity list [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:777]
WARNING: [Synth 8-567] referenced signal 'imm_s' should be on the sensitivity list [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:777]
INFO: [Synth 8-6155] done synthesizing module 'riscv_core' (3#1) [D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core_v4.v:60]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1134.922 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1134.922 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k70tfbv484-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1134.922 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Device 21-403] Loading part xc7k70tfbv484-1
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'riscv_core'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 iSTATE4 |                             0000 |                             0000
                 iSTATE3 |                             0001 |                             0001
                 iSTATE0 |                             0010 |                             0011
                  iSTATE |                             0011 |                             0100
                 iSTATE9 |                             0100 |                             0101
                 iSTATE7 |                             0101 |                             0110
                 iSTATE6 |                             0110 |                             0111
                 iSTATE8 |                             0111 |                             1000
                 iSTATE5 |                             1000 |                             1001
                 iSTATE2 |                             1001 |                             1010
                 iSTATE1 |                             1010 |                             0010
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'riscv_core'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1134.922 ; gain = 0.000
---------------------------------------------------------------------------------
No constraint files found.
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   3 Input   64 Bit       Adders := 1     
	   2 Input   64 Bit       Adders := 1     
	   2 Input   32 Bit       Adders := 9     
	   3 Input   32 Bit       Adders := 1     
	   2 Input    6 Bit       Adders := 1     
+---XORs : 
	   2 Input     32 Bit         XORs := 2     
	   2 Input      1 Bit         XORs := 1     
+---Registers : 
	               64 Bit    Registers := 3     
	               32 Bit    Registers := 11    
	                6 Bit    Registers := 1     
	                5 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                1 Bit    Registers := 4     
+---Muxes : 
	   2 Input   64 Bit        Muxes := 4     
	   2 Input   32 Bit        Muxes := 30    
	  10 Input   32 Bit        Muxes := 1     
	   4 Input   32 Bit        Muxes := 12    
	   3 Input   32 Bit        Muxes := 2     
	   8 Input   32 Bit        Muxes := 2     
	   5 Input   32 Bit        Muxes := 2     
	   6 Input   32 Bit        Muxes := 1     
	   3 Input   24 Bit        Muxes := 1     
	   2 Input   24 Bit        Muxes := 2     
	   4 Input    8 Bit        Muxes := 1     
	   2 Input    5 Bit        Muxes := 7     
	   8 Input    5 Bit        Muxes := 1     
	   4 Input    5 Bit        Muxes := 1     
	   6 Input    5 Bit        Muxes := 1     
	   5 Input    5 Bit        Muxes := 2     
	   4 Input    4 Bit        Muxes := 1     
	   7 Input    4 Bit        Muxes := 1     
	   6 Input    4 Bit        Muxes := 1     
	   5 Input    4 Bit        Muxes := 1     
	   2 Input    4 Bit        Muxes := 9     
	  11 Input    4 Bit        Muxes := 1     
	   3 Input    4 Bit        Muxes := 1     
	   4 Input    3 Bit        Muxes := 1     
	   8 Input    2 Bit        Muxes := 1     
	   2 Input    2 Bit        Muxes := 3     
	   2 Input    1 Bit        Muxes := 26    
	   3 Input    1 Bit        Muxes := 6     
	   4 Input    1 Bit        Muxes := 3     
	   7 Input    1 Bit        Muxes := 2     
	  10 Input    1 Bit        Muxes := 1     
	   5 Input    1 Bit        Muxes := 2     
	  11 Input    1 Bit        Muxes := 1     
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
No constraint files found.
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1134.922 ; gain = 0.000
---------------------------------------------------------------------------------
No constraint files found.
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 1134.922 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1134.922 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+-------+------+
|      |Cell   |Count |
+------+-------+------+
|1     |BUFG   |     1|
|2     |CARRY4 |   166|
|3     |LUT1   |   200|
|4     |LUT2   |   242|
|5     |LUT3   |   211|
|6     |LUT4   |   494|
|7     |LUT5   |   313|
|8     |LUT6   |  1047|
|9     |MUXF7  |     3|
|10    |FDRE   |   571|
|11    |FDSE   |    29|
|12    |IBUF   |    98|
|13    |OBUF   |   186|
+------+-------+------+

Report Instance Areas: 
+------+---------+-------+------+
|      |Instance |Module |Cells |
+------+---------+-------+------+
|1     |top      |       |  3561|
|2     |  div    |div32  |   589|
|3     |  mul    |mul32  |   672|
+------+---------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 4 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000
Synthesis Optimization Complete : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1134.922 ; gain = 0.000
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1134.922 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 169 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1134.922 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Synth Design complete, checksum: e32a7290
INFO: [Common 17-83] Releasing license: Synthesis
30 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1134.922 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/gitwork/hdl4se/examples/hdl4se_riscv/z7/project_2/project_2.runs/synth_1/riscv_core.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file riscv_core_utilization_synth.rpt -pb riscv_core_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue Sep  7 20:35:12 2021...