main.cpp

/*
** HDL4SE: 软件Verilog综合仿真平台
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** LCOM: 轻量级组件对象模型
** Copyright (C) 2021-2021, raoxianhong<raoxianhong@163.net>
** All rights reserved.
**
** Redistribution and use in source and binary forms, with or without
** modification, are permitted provided that the following conditions are met:
**
** * Redistributions of source code must retain the above copyright notice,
**   this list of conditions and the following disclaimer.
** * Redistributions in binary form must reproduce the above copyright notice,
**   this list of conditions and the following disclaimer in the documentation
**   and/or other materials provided with the distribution.
** * The name of the author may be used to endorse or promote products
**   derived from this software without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
** ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
** INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
** CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
** ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
** THE POSSIBILITY OF SUCH DAMAGE.
*/

#include "stdlib.h"
#include "stdio.h"
#include "string.h"
#include "time.h"
#include "object.h"
#include "bignumber.h"
#include "hdl4secell.h"
#include "hdl4sesim.h"
#include "hdl4sevcdfile.h"
#include "terris.h"
#include "systemc.h"

IHDL4SESimulator** sim;
IHDL4SEUnit** topmodule; 
IHDL4SEUnit** gui;
unsigned long long clocks = 0;

static int running = 1;

#define VCDOUTPUT 1

extern "C" {
	int StopRunning()
{
	running = 0;
	return 0;
}


	IHDL4SEUnit** hdl4seCreate_main(IHDL4SEModule** parent, const char* instanceparam, const char* name);
	extern int (*A_u_t_o_registor_terrisctrl)();
	extern int (*A_u_t_o_registor_terrisctrl1)();
	extern int (*A_u_t_o_registor_terris_flushtodisp)();
	extern int (*A_u_t_o_registor_terris_blockwrite)();
	extern int (*A_u_t_o_registor_terris_canblocksetto)();
	extern int (*A_u_t_o_registor_terris_checkline)();
	extern int (*A_u_t_o_registor_terris_init)();
	extern int (*A_u_t_o_registor_terris_copylines)();
	extern int (*A_u_t_o_registor_terris_copylines)();
	extern int (*A_u_t_o_registor_terrisdevice)();
}

SC_MODULE(half_adder) {
	sc_in <bool>a, b;
	sc_out <bool> sum, carry;
	void prc_half_adder();

	SC_CTOR(half_adder) {
		SC_METHOD(prc_half_adder);
		sensitive << a << b;
	}
};

/*
struct signed_adder : ::sc_core::sc_module {
	sc_in <sc_int <4> >arb, tbe;
	sc_out <sc_int<5> > sum;
	void prc_signed_adder();

	typedef signed_adder SC_CURRENT_USER_MODULE;
	signed_adder(::sc_core::sc_module_name) {
		::sc_core::sc_process_handle prc_signed_adder_handle =
		sc_core::sc_get_curr_simcontext()->create_method_process(
		"prc_signed_adder",  false, SC_MAKE_FUNC_PTR( SC_CURRENT_USER_MODULE, prc_signed_adder ),
		this, 0 );
		sensitive << prc_signed_adder_handle;
		sensitive_pos << prc_signed_adder_handle;
		sensitive_neg << prc_signed_adder_handle;
		sensitive << arb << tbe;
	}
};
*/

void half_adder::prc_half_adder() {
	sum = a.read() ^ b.read();
	carry = a.read() & b.read();
	int aa = a.read();
	int bb = b.read();
	int ss = sum.read();
	int cc = carry.read();
	int dd = a.read();
}



int main(int argc, char* argv[])
{
	int i;
	int width;
	int resetwidth;
	int count, unitcount;
	IHDL4SEUnit** sim_unit;
	IHDL4SEWaveOutput** vcdfile;
	srand((unsigned int)time(NULL));
	resetwidth = 10 + rand() % 50;

	
	A_u_t_o_registor_terrisctrl();
	A_u_t_o_registor_terrisctrl1();
	A_u_t_o_registor_terris_flushtodisp();
	A_u_t_o_registor_terris_blockwrite();
	A_u_t_o_registor_terris_canblocksetto();
	A_u_t_o_registor_terris_checkline();
	A_u_t_o_registor_terris_init();
	A_u_t_o_registor_terris_copylines();
	A_u_t_o_registor_terrisdevice();
	sim = hdl4sesimCreateSimulator();
	topmodule = hdl4seCreate_main(NULL, "", "top");
	objectCall1(sim, SetTopModule, topmodule);
	objectCall1(sim, SetReset, 0);
	unitcount = 0;


	objectQueryInterface(sim, IID_HDL4SEUNIT, (void**) &sim_unit);
	objectPrintInfo(stdout, NULL);
#if VCDOUTPUT
	vcdfile = hdl4sesimCreateVCDFile("terris.vcd"); 
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl", "bWriteAddr");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl", "bWriteData");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/bCtrlState", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/wCtrlStateComplete", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/bCurBlockPos", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_curblock", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_nextblock", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_curposx", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_curposy", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_tick", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_speed", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/cur_key", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/outputx", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_curposx", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/outputy", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_curposy", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_testid", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/bResult", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_testx", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_testy", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_curposx", "out");
	objectCall2(vcdfile, AddSignal, "/top/terrisctrl/ctrl/wireout_curposy", "out");

	objectCall1(vcdfile, SetTopModule, topmodule);
	objectCall0(vcdfile, StartRecord);
#endif
	sc_get_curr_simcontext()->initialize();
	do {
		sc_time halfcycle(5, SC_NS);
		objectCall0(sim_unit, ClkTick);
#if VCDOUTPUT
		objectCall1(vcdfile, ClkTick, clocks);
#endif
		sc_get_curr_simcontext()->cycle(halfcycle);
		objectCall0(sim_unit, Setup);
		sc_get_curr_simcontext()->cycle(halfcycle);
		clocks++;
		if (clocks == resetwidth)
			objectCall1(sim, SetReset, 1);
	} while (running);
#if VCDOUTPUT
	objectCall0(vcdfile, StopRecord);
	objectRelease(vcdfile);
#endif
	return 0;
}